KR20210048590A - Semiconductor device - Google Patents

Abstract

It is an object to provide a semiconductor device having a low power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device having high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In a semiconductor device, a gate electrode layer (gate wiring layer) intersects a wiring layer electrically connected to a source electrode layer or a drain electrode layer with a gate insulating layer and an insulating layer covering the oxide semiconductor layer of the thin film transistor interposed therebetween. Accordingly, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layers can be reduced, so that low power consumption of the semiconductor device can be realized.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device containing an oxide semiconductor and a method of manufacturing the same.

In the present specification, a semiconductor device refers to an entire device that functions using semiconductor properties, and an electro-optical device, a semiconductor circuit and an electronic device are all semiconductor devices.

Recently, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of approximately several nm to several hundreds of nm) formed on a substrate having an insulating surface has been attracting attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development of thin film transistors to be used as switching elements in image display devices is being urged. Various metal oxides are used in a variety of applications. Indium oxide is a widely known material, and is used as a translucent electrode material required for liquid crystal displays and the like.

Some metal oxides have semiconductor properties. Examples of such metal oxides having semiconductor properties include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like. Thin film transistors in which a channel formation region is formed using such a metal oxide having semiconductor properties are known (Patent Document 1 and Patent Document 2).

As examples of electronic devices using thin film transistors, mobile devices such as cell phones or laptop computers may be provided. Power consumption, which affects the continuous operating time, is a serious problem for these mobile electronic devices. In addition, even for a television set having an increasing size, it is necessary to suppress an increase in power consumption due to an increase in size.

Japanese Laid-Open Patent Publication No. 2007-123861 Japanese Laid-Open Patent Publication No. 2007-096055

An object of the present invention is to provide a semiconductor device having a low power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

An object of the present invention is to provide a semiconductor device having high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

In a semiconductor device, a gate electrode layer (gate wiring layer) crosses a wiring layer electrically connected to the source electrode layer or the drain electrode layer, and an insulating layer and a gate insulating layer covering the oxide semiconductor layer of the thin film transistor are interposed therebetween. A stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer is not formed, except that the gate electrode layer of the thin film transistor partially overlaps the source electrode layer and the drain electrode layer on the oxide semiconductor layer.

Accordingly, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

One embodiment of the present invention is in contact with the oxide semiconductor layer on the gate electrode layer, the gate insulating layer on the gate electrode layer, the oxide semiconductor layer on the gate insulating layer, the source electrode layer and the drain electrode layer on the oxide semiconductor layer, and the source electrode layer and the drain electrode layer. A semiconductor device comprising an oxide insulating layer and a wiring layer electrically connected to a source or drain electrode layer on the oxide insulating layer. The opening is formed in the oxide insulating layer so as to reach the source or drain electrode layer, the wiring layer is in contact with the source or drain electrode layer at the opening, and the gate electrode layer and the wiring layer overlap each other with the gate insulating layer and the oxide semiconductor layer interposed therebetween.

The source and drain electrode layers are preferably as thin as 0.1 nm or more and 50 nm or less in thickness, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced.

It is preferred that the source and drain electrode layers are formed using a material containing a metal having high oxygen affinity. The metal with high oxygen affinity is preferably at least one material selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.

When heat treatment is performed while the oxide semiconductor layer and the metal layer having a high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density near the interface therebetween increases. A low resistance region is formed near the interface, so that the contact resistance between the oxide semiconductor layer and the source and drain electrode layers decreases.

Heat resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, even when heat treatment is performed after the formation of the source and drain electrode layers, the change or deterioration of the properties of the source and drain electrode layers can be prevented.

As a heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), or any of the above elements. An alloy containing as, an alloy film containing any combination of these elements, or a nitride containing any of the above elements as a component can be used. A conductive film in which a low-resistance conductive material such as aluminum (Al) or copper (Cu) is combined with the heat-resistant conductive material described above may be used.

The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a titanium oxide film (e.g., a titanium oxide film having a thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer For example, a structure in which a thickness of 1 nm or more and 20 nm or less) is provided may be used.

When the source and drain electrode layers are thin enough to transmit light, the source and drain electrode layers have light-transmitting properties.

The wiring layer is formed using a conductive film having a resistance lower than that of the source and drain electrode layers. In particular, the wiring layer may be formed to have a single layer or a laminated structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, scandium, or an alloy material containing any of these materials as a main component. have. In this embodiment, an aluminum film and a titanium film are used as the first wiring layer and the second wiring layer to form a laminated structure with the wiring layer.

In one embodiment of the present invention, a gate electrode layer is formed, a gate insulating layer is formed over the gate electrode layer, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is dehydrated or dehydrogenated, and thereafter, the atmosphere Is prevented from being exposed to the oxide semiconductor layer to prevent water or hydrogen from being mixed into the oxide semiconductor layer, source and drain electrode layers are formed on the oxide semiconductor layer, and a portion of the oxide semiconductor layer is in contact with the oxide semiconductor layer, the source and drain electrode layers An oxide insulating layer is formed, an opening is formed in the oxide insulating layer to the source or drain electrode layers, and the gate insulating layer and the oxide insulating layer and the gate electrode layer are partially in contact with the source or drain electrode layer and interposed therebetween. This is a method of manufacturing a semiconductor device in which an overlapping wiring layer is formed in an opening. The wiring layer is thinner than the source and drain electrode layers and has a lower resistance than the source and drain electrode layers.

With each of the above-described structures, at least one of the above-described objects can be achieved.

The oxide semiconductor layer is _{a thin film of InMO 3} (ZnO) _m (m>0). Using the thin film as an oxide semiconductor layer, a thin film transistor is formed. Note that M represents one or more metal elements selected from Ga, Fe, Ni, Mn and Co. For example, as M may be Ga, or may include the above-described metal elements other than Ga, for example, M may be Ga and Ni, or M may be Ga and Fe. In the oxide semiconductor described above, in addition to the metal element included as M, a transition metal element such as Fe or Ni or an oxide of a transition metal may be included as an impurity element. In this specification, an oxide semiconductor layer whose composition formula is InMO ₃ (ZnO) _m (m> 0) (at least Ga is included as M) is referred to as an In-Ga-Zn-O-based oxide semiconductor, and the thin film is In It is called -Ga-Zn-O non-single crystal film.

As other examples of the metal oxide applicable to the oxide semiconductor layer, any of the following metal oxides: In-Sn-O-based metal oxide, In-Sn-Zn-O-based metal oxide, In-Al-Zn-O-based metal Oxide, Sn-Ga-Zn-O type metal oxide, Al-Ga-Zn-O type metal oxide, Sn-Al-Zn-O type metal oxide, In-Zn-O type metal oxide, Sn-Zn-O type Metal oxides of metal oxides, Al-Zn-O-based metal oxides, In-O-based metal oxides, Sn-O-based metal oxides, and Zn-O-based metal oxides may be applied. Silicon oxide may be included in the oxide semiconductor layer formed using the metal oxide described above.

Dehydration or dehydrogenation is a heat treatment performed at 400°C or more and 750°C or less, preferably 425°C or more and less than the strain point of the substrate in an atmosphere of an inert gas such as nitrogen or a rare gas (such as argon or helium), and thus oxides Impurities such as moisture contained in the semiconductor layer are reduced. In addition, _{incorporation of water (H 2} O) may be prevented.

The heat treatment for dehydration or dehydrogenation is preferably carried out in a nitrogen atmosphere at _{a H 2 O concentration of 20 ppm or less.} Alternatively, the heat treatment may be carried out in an ultra-dry air atmosphere with _{a H 2 O concentration of 20 ppm or less.}

In heating treatment for dehydration or dehydrogenation, an instantaneous heating method such as a heating method using an electric furnace, a gas rapid thermal anneal (GRTA) method using a heated gas, or a lamp rapid thermal anneal (LRTA) method using a lamp light Etc. can be used.

Even when the TDS (Thermal Desorption Spectroscopy) measurement on the oxide semiconductor layer after dehydration or dehydrogenation is performed up to 450°C, the heat treatment conditions are set so that at least one of the two peaks of water appearing around 300°C is not detected. Therefore, even when the TDS measurement is performed up to 450°C on the thin film transistor including the dehydrated or dehydrogenated oxide semiconductor layer, the peak of water appearing around 300°C is not detected.

Thereafter, from the heating temperature (T) at which the oxide semiconductor layer is dehydrated or dehydrogenated to a temperature sufficiently low to prevent the incorporation of impurities such as water or hydrogen, specifically, to a temperature lower than the heating temperature (T) by 100°C. It becomes slow cooling. It is important that the same furnace used for dehydration or dehydrogenation is used without exposure to air, and incorporation of impurities such as water or hydrogenation is prevented. Dehydration or dehydrogenation is carried out to make the oxide semiconductor layer a low-resistance type layer, i.e., n-type (such as n ^- type or n ⁺ -type), and then, so that the oxide semiconductor layer becomes an i-type oxide semiconductor layer. Higher resistance. When a thin film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage of the thin film transistor is positive, and a so-called normally-off switching element can be obtained. It is desirable for a display device to form a channel with a threshold voltage that is a positive value as close to 0V as possible. If the threshold voltage value of the thin film transistor is negative, the thin film transistor tends to be a so-called normally-on TFT through which a current flows between the source electrode and the drain electrode even when the gate voltage is 0 V. In an active matrix display device, the electrical characteristics of the thin film transistors included in the circuit are important and affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage Vth is important. Even when the field effect mobility is high, if the threshold voltage value is high or a negative value, it is difficult to control the circuit. When the thin film transistor has a high threshold voltage value with a large absolute value, the thin film transistor cannot perform the switching function as a TFT when the transistor is driven at a low voltage, and may be a load. In the case of an n-channel thin film transistor, it is preferable that a channel is formed after a positive voltage is applied as the gate voltage, so that the drain current starts to flow. A transistor in which a channel is not formed when the driving voltage is not high, and a transistor in which a channel is formed even at a negative voltage and a drain current flows is not suitable as a thin film transistor used in a circuit.

The gas atmosphere reduced from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere in which the temperature increases to the heating temperature T. For example, dehydration or dehydrogenation in which the furnace is filled with high purity oxygen gas or N ₂ O gas, ultra-dry air (with a dew point of -40°C or less, preferably -60°C or less) without contacting the atmosphere. Slowly cooled in the same furnace as for the furnace.

It is formed by heat treatment for dehydration or dehydrogenation in order to reduce the moisture contained in the membrane, and slow cooling (with a dew point of -40°C or less, preferably -60°C or less) in an atmosphere that does not contain moisture. Alternatively, by using the oxide semiconductor film subjected to cooling), electrical properties of the thin film transistor can be improved, and mass productivity and high performance can be provided for the thin film transistor.

In this specification, heat treatment of nitrogen or a noble gas (such as argon or helium) in an inert gas atmosphere is referred to as heat treatment for dehydration or dehydrogenation. In this specification, dehydrogenation _{does not refer to only dehydration in the form of H 2} by heat treatment, and dehydration or dehydrogenation also refers to dehydration of H, OH, or the like for convenience.

In the case where the heat treatment is carried out under an inert gas atmosphere of nitrogen or a rare gas (such as argon or helium), the heat treatment makes the oxide semiconductor layer into an oxygen-deficient layer in order to reduce the resistance of the oxide semiconductor layer, so that the oxide semiconductor layer Becomes an n-type ( ^{such as n-} type) oxide semiconductor layer.

Further, a high resistance drain region (also referred to as a high resistance drain (HRD) region) overlapping with the drain electrode layer and having an oxygen deficiency type is formed. Further, a high resistance source region (also referred to as a high resistance source (HRS) region) overlapping with the source electrode layer and having an oxygen depletion type is formed.

Specifically, the carrier concentration in the high-resistance drain region is 1×10 ¹⁸ /cm ³ or more, and is at least higher than the carrier concentration in the channel formation region (less than ^{1×10 18} /cm ^{3 ).} The carrier concentration in the present specification refers to a value of the carrier concentration obtained by measuring the Hall effect at room temperature.

In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer becomes oxygen-excessive, has a higher resistance, i.e., becomes i-shaped, so that a channel formation region is formed. A treatment for bringing the dehydrated or dehydrogenated oxide semiconductor layer into an oxygen-excessive state, the following treatment: formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by a sputtering method (also referred to as sputtering); Heat treatment after the oxide insulating film is formed; After the oxide insulating film is formed, a cooling treatment or the like is performed in an oxygen atmosphere or ultra-dry air (having a dew point of -40°C or less, preferably -60°C or less) after heat treatment in an inert gas atmosphere.

In addition, for making at least a portion of the dehydrated or dehydrogenated oxide semiconductor layer (a portion overlapping with the gate electrode layer) as a channel formation region, the oxide semiconductor layer is selectively brought into an oxygen-excessive state, resulting in high resistance, that is, i-type Becomes. The channel formation region is formed by contacting the source and drain electrode layers formed using a metal electrode such as Ti on the dehydrated or dehydrogenated oxide semiconductor layer, and an exposed region that does not overlap the source and drain electrode layers is selectively oxygen-excessive. It can be formed in a way. When the exposed region is selectively in an oxygen-excessive state, a high resistance source region overlapping the source electrode layer and a high resistance drain region overlapping the drain electrode layer are formed to form a channel formation region between the high resistance source region and the high resistance drain region. . That is, the channel length of the channel formation region is self-matched with the source and drain electrode layers.

In this way, a semiconductor device including a thin film transistor having high electrical properties and high reliability can be provided.

By forming a high-resistance drain region in the oxide semiconductor layer overlapping the drain electrode layer, reliability can be improved when a driving circuit is formed. Specifically, by forming the high-resistance drain region, the conductivity can be changed stepwise from the drain electrode layer to the channel formation region through the high-resistance drain region. Therefore, in the case where the thin film transistor operates as a drain electrode layer connected to a wiring supplying a high power potential (VDD), the high resistance drain region functions as a buffer even when a high electric field is applied between the gate electrode layer and the drain electrode layer. And since the high electric field is not applied locally, the breakdown voltage of the thin film transistor can be improved.

Further, by forming the high resistance drain region and the high resistance source region in the oxide semiconductor layer overlapping the drain electrode layer and the source electrode layer, a reduction in leakage current in the channel formation region can be achieved when a driving circuit is formed. Specifically, by forming the high-resistance drain region, the leakage current between the drain electrode layer and the source electrode layer of the transistor is determined by the drain electrode layer, the high resistance drain region on the drain electrode layer side, the channel formation region, the high resistance source region on the source electrode layer side, and And flow in this order through the source electrode layer. In this case, in the channel formation region, the leakage current flowing from the high resistance drain region on the drain electrode layer side to the channel region can be concentrated near the interface between the high resistance gate insulating layer and the channel formation region when the transistor is turned off. Thus, the amount of leakage current in the back channel portion (a part of the surface of the channel formation region spaced apart from the gate electrode layer) can be reduced.

In addition, the high-resistance source region overlapping the source electrode layer and the high-resistance drain region overlapping the drain electrode layer, even depending on the width of the gate electrode layer, overlap each other with a portion of the gate electrode layer interposed therebetween, and the electric field near the end of the drain electrode layer. The strength of the can be reduced more efficiently.

Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source and drain electrode layers. It is preferable that the oxide conductive layer contains zinc oxide as a component and does not contain indium oxide. For example, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, and the like may be used. The oxide conductive layer also functions as a low resistance drain (LRD, also referred to as LRN (low resistance n-type conductivity)) region. Specifically, the carrier concentration in the low-resistance drain region is higher than the carrier concentration in the high-resistance drain region (HRD region), for example, in the range of 1×10 ²⁰ /cm ³ or more and 1×10 ²¹ /cm ³ or less. desirable. Providing an oxide conductive layer between the oxide semiconductor layer and the source and drain electrode layers can reduce the contact resistance and realize high-speed operation of the transistor. Accordingly, the frequency characteristics of the peripheral circuit (driving circuit) can be improved.

The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be formed continuously.

The first wiring and the second wiring described above may be formed using wiring formed by laminating the same material and metal material as the oxide conductive layer functioning as the LRN region or the LRD region. By laminating the metal and the oxide conductive layer, the coverage at a step such as a portion or an opening that overlaps with the lower layer wiring can be improved, so that wiring resistance can be lowered. In addition, it can be expected that a local increase in resistance of the wiring and disconnection of the wiring due to migration or the like can be prevented, so that a semiconductor device having high reliability can be provided.

Further, with regard to the connection between the first wiring and the second wiring described above, an oxide conductive layer may be provided therebetween, so that the increase in contact resistance due to the formation of insulating oxide on the metal surface at the connection portion (contact portion) is reduced. As it can be expected to be prevented, an oxide semiconductor device having high reliability can be provided.

Since the thin film transistor is easily destroyed by static electricity or the like, it is preferable that a protection circuit for protecting the thin film transistor included in the pixel portion, for the gate line or the source line, is provided on the same substrate as the substrate for the pixel portion. It is preferable that the protection circuit is formed using a nonlinear element using an oxide semiconductor layer.

In the present specification, ordinal numbers such as "first" and "second" are used for convenience, and do not indicate the order of steps or the order of stacking layers. In addition, ordinal numbers in the present specification do not indicate a specific name for specifying the present invention.

A thin film transistor using an oxide semiconductor layer can be used for an electronic device or an optical device. For example, a thin film transistor using an oxide semiconductor layer can be used as a liquid crystal display device, a light emitting device, a switching element for electronic paper, or the like.

The display device is not limited to, and insulated gate semiconductor devices for high power control, in particular, semiconductor devices referred to as power MOS devices can be fabricated. As an example of a power MOS device, a MOSFET, an IGBT, or the like can be provided.

As a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device having a small parasitic capacitance and low power consumption can be provided.

As a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device having high reliability can be provided.

1A1, 1A2, and 1B are diagrams illustrating semiconductor devices.
2A to 2F are diagrams illustrating a method of manufacturing a semiconductor device.
3A1, 3A2, and 3B are diagrams illustrating semiconductor devices.
4A to 4F are diagrams illustrating a method of manufacturing a semiconductor device.
5A to 5F are diagrams illustrating a method of manufacturing a semiconductor device.
6A and 6B are diagrams illustrating semiconductor devices.
7 is a diagram illustrating a semiconductor device.
8 is a diagram illustrating a semiconductor device.
9 is a diagram illustrating a semiconductor device.
10 is a diagram illustrating a semiconductor device.
11 is a diagram illustrating an equivalent circuit of a pixel of a semiconductor device.
12A to 12C are diagrams illustrating semiconductor devices.
13A and 13B are diagrams illustrating a semiconductor device.
14A to 14C are diagrams illustrating a semiconductor device.
15 is a diagram illustrating a semiconductor device.
16 is a diagram illustrating a semiconductor device.
17 is a diagram illustrating a semiconductor device.
18 is a diagram illustrating an equivalent circuit of a pixel of a semiconductor device.
19 is a diagram illustrating a semiconductor device.
20A and 20B are diagrams illustrating an electronic device.
21A and 21B are diagrams illustrating an electronic device.
22 is a diagram illustrating an electronic device.
23 is a diagram illustrating an electronic device.
24 is a diagram illustrating an electronic device.
25A to 25D are diagrams illustrating a multi-gradation mask.
26 is a diagram illustrating a result of a simulation.
27 is a diagram illustrating a result of a simulation.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, it is readily understood by those skilled in the art that the present invention is not limited to the description below, and that the forms and details disclosed herein may be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiment.

(Embodiment 1)

In Embodiment 1, an embodiment of a semiconductor device and a method of manufacturing a semiconductor device will be described with reference to Figs. 1A1 and 1A2, 1B, 2A to 2F, and Figs. 6A and 6B.

1A1 and 1A2 illustrate an example of a planar structure of a semiconductor device. 1B illustrates an example of a cross-sectional structure of a semiconductor device. The thin film transistor 410 shown in FIGS. 1A2 and 1B is a type of a bottom-gate structure called a channel etching type, and is also called an inverted staggered thin film transistor.

1A1 is a plan view of an intersection between a gate wiring layer (formed by the same step as the gate electrode layer) and a source wiring layer (formed by the same step as the wiring layer), and FIG. 1A2 is a plan view of a channel etching type thin film transistor 410, 1B is a cross-sectional view taken along lines C1-C2 and D1-D2 in FIGS. 1A1 and 1A2.

The thin film transistor 410, which is a channel etching type thin film transistor, has a gate electrode layer 411, a gate insulating layer 402, at least a channel formation region 413, and a high resistance source region 414a on a substrate 400 having an insulating surface. ), and an oxide semiconductor layer 412 including a high resistance drain region 414b, a source electrode layer 415a, and a drain electrode layer 415b. In addition, an oxide insulating layer 407 covering the thin film transistor 410 and in contact with the channel formation region 413 is provided, and a protective insulating layer 408 is provided thereon.

Openings (contact holes) reaching the source electrode layer 415a and the drain electrode layer 415b are formed in the oxide insulating layer 407 and the protective insulating layer 408. Wiring layers 417a and 418a are formed in one of the openings, and wiring layers 417b and 418b are formed in the other of the openings. At the intersection, the gate wiring layer 421 and the source wiring layers 422 and 423 are stacked with the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 interposed therebetween.

In this way, the gate electrode layer (gate wiring layer) intersects the wiring layer electrically connected to the source electrode layer or the drain electrode layer, the insulating layer covering the oxide semiconductor layer of the thin film transistor, and the gate insulating layer therebetween. A stacked structure of a gate electrode layer, a gate insulating layer, and a source or drain electrode layer is not formed, except that the gate electrode layer of the thin film transistor partially overlaps the source electrode layer and the drain electrode layer on the oxide semiconductor layer.

Accordingly, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Although the thin film transistor 410 is described as a single gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions may be formed if necessary.

Hereinafter, a step of forming the thin film transistor 410 on the substrate will be described with reference to FIGS. 2A to 2F.

First, a conductive film is formed on a substrate 400 having an insulating surface, and a first photolithography step is performed to form a gate electrode layer 411 and a gate wiring layer 421. The resist mask may be formed by an ink jet method. When the resist mask is formed by the inkjet method, a photomask is not used, which leads to a reduction in manufacturing cost.

There is no particular limitation on the substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance to withstand the heat treatment performed later. A glass substrate such as barium borosilicate glass or aluminoborosilicate glass may be used.

When the temperature of the heat treatment performed later is high, it is preferable that a substrate having a strain point of 730°C or higher is used as the glass substrate. As the material of the glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass or barium borosilicate glass is used. By containing a larger amount of barium oxide (BaO) than boric acid, the glass substrate is heat resistant and more practical. Therefore, it is desirable that the amount of BaO using a glass substrate containing BaO and B ₂ O ₃ is greater than the amount of B ₂ O _3.

Instead of the glass substrate described above, a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may also be used. Alternatively, crystallized glass or the like can be used.

An insulating film functioning as a base film may be provided between the substrate 400, the gate electrode layer 411, and the gate wiring layer 421. The underlying film has a function of preventing diffusion of impurity elements from the substrate 400, and is formed to have a single layer or a stacked structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. Can be.

The gate electrode layer 411 and the gate wiring layer 421 are single-layered using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material containing any of these materials as a main component. It may be formed to have a structure or a stacked structure.

Next, a gate insulating layer 402 is formed over the gate electrode layer 411 and the gate wiring layer 421.

The gate insulating layer 402 may be formed to have a single layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer or a stack thereof by a plasma CVD method, a sputtering method, or the like. For example, the silicon oxynitride layer may be formed using _{SiH 4} , oxygen and nitrogen as a film forming gas by a plasma CVD method. The thickness of the gate insulating layer 402 is 100 nm or more and 500 nm or less, and in the case of lamination, for example, a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less and 5 nm or more and 300 nm or less. A second gate insulating layer having a thickness is deposited.

In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed as the gate insulating layer 402 by the plasma CVD method.

Next, the oxide semiconductor layer 440 is formed on the gate insulating layer 402 to a thickness of 2 nm or more and 200 nm or less. After the oxide semiconductor film 440 is formed, it is preferable that the oxide semiconductor film 440 is as thin as 50 nm or less in order to maintain the amorphous state even when heat treatment for dehydration or dehydrogenation is performed. Due to the thickness of the oxide semiconductor film, crystallization of the oxide semiconductor film can be prevented when a heat treatment is performed after the formation of the oxide semiconductor layer.

Before the oxide semiconductor film 440 is formed by the sputtering method, it is preferable that dust on the surface of the gate insulating layer 402 is removed by reverse sputtering in which argon gas is introduced and plasma is generated. Reverse sputtering refers to a method in which a voltage is not applied to a target side, but an RF power source is used to apply a voltage to the substrate side in an argon atmosphere to generate plasma near the substrate to change the quality of the surface. Instead of an argon atmosphere, nitrogen, helium, or oxygen may be used.

The oxide semiconductor film 440 is an In-Ga-Zn-O-based non-single crystal film, or an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, and Sn-Ga-Zn- O-based oxide semiconductor film, Al-Ga-Zn-O-based oxide semiconductor film, Sn-Al-Zn-O-based oxide semiconductor film, In-Zn-O-based oxide semiconductor film, Sn-Zn-O-based oxide semiconductor film, It is formed using an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, an Sn-O-based oxide semiconductor film, or a Zn-O-based oxide semiconductor film.

In this embodiment, the oxide semiconductor film 440 is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. The cross-sectional view at this stage corresponds to FIG. 2A. In addition, the oxide semiconductor film 440 may be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. In the case of using the sputtering method, film formation is carried out using a target containing 2% by weight or more and 10% by weight or less of _{SiO 2, and SiO x} (X> 0), which inhibits crystallization, is deposited on the oxide semiconductor film 440. Included, and in this way, it is preferable that the oxide semiconductor film 440 can be prevented from crystallizing in a heat treatment for dehydration or dehydrogenation performed later.

In this embodiment, an oxide semiconductor target containing In, Ga, and Zn (In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:1 [mol%], In:Ga:Zn=1:1: 0.5 [atom%]) was used to form a film. Film formation conditions are set as follows, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is a mixed atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 20 sccm, and the oxygen flow ratio is 40%). It is preferable to use a pulsed direct current (DC) power source because dust can be reduced and the film thickness can be made uniform. An In-Ga-Zn-O-based non-single crystal film is formed with a thickness of 5 nm or more and 200 nm or less. In this embodiment, an In-Ga-Zn-O-based non-single crystal film having a thickness of 20 nm is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target as the oxide semiconductor film. Alternatively, as an oxide semiconductor target comprising In, Ga, and Zn, In:Ga:Zn=1:1:1[atom%], or In:Ga:Zn=1:1:2[atom%] A target having a composition ratio can be used.

Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulse manner. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

A multi-source sputtering apparatus can be used in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or films of plural kinds of materials can be formed in the same chamber simultaneously by electric discharge.

Alternatively, a sputtering device provided with a magnet system inside the chamber and used for the magnetron sputtering method, or a sputtering device used for the ECR sputtering method in which plasma generated using microwaves without using glow discharge is used may be used. I can.

In addition, as a film formation method using the sputtering method, a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted with each other during film formation to form a thin film of their compound, or a bias sputtering method in which a voltage is also applied to the substrate during film formation may be used. I can.

Next, the oxide semiconductor film 440 is processed into an island-shaped oxide semiconductor layer by a second photolithography step. Further, the resist mask for forming the island-like oxide semiconductor layer may be formed by an ink jet method. Since the photomask is not used when the resist mask is formed by the inkjet method, manufacturing cost can be reduced.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or more and 750°C or less, and preferably 400°C or more and less than the strain point of the substrate. In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after the oxide semiconductor layer is subjected to heat treatment at 450° C. for 1 hour in a nitrogen atmosphere, the oxide semiconductor layer is not exposed to the atmosphere, and the oxide Incorporation of water or hydrogen into the semiconductor layer is prevented. In this way, an oxide semiconductor layer 441 is obtained (see Fig. 2B).

An example of the mechanism of removal of water from the oxide semiconductor film was analyzed along the following reaction path (reaction of OH or H as well as water in the oxide semiconductor film). As the oxide semiconductor film, an In-Ga-Zn-O-based amorphous film is used.

In addition, the optimal molecular structure of the simulation model in the ground state was calculated using density functional theory (DFT). In DFT, the total energy is expressed as the sum of the potential energy, the electrostatic energy between electrons, the kinetic energy of the electrons, and the exchange correlation energy including all complex interactions between the electrons. In addition, in DFT, the exchange correlation interaction is approximated by a functional function of one electron potential expressed as an electron density (ie, a function of another function) to enable high-speed and high-precision calculations. In this embodiment, the blending functional B3LYP was used to define the weight of each parameter related to the exchange-correlated energy. In addition, as a basis function, LanL2DZ (a basis function obtained by adding a split valence basis system to the effective core potential of the Ne shell) is applied to the indium atom, gallium atom, and zinc atom, and 6-311 (for each valence orbital) is applied to the other atoms. The triple split ｖalence basis function using three shortening functions) is applied. By the basis functions, for example, in the case of a hydrogen atom, an orbital of 1s to 3s is considered, and in the case of an oxygen atom, an orbital of 1s to 4s and 2p to 4p is considered. Further, in order to improve the calculation precision, a p function and a d function are added to each of the hydrogen atom and the oxygen atom as a polarization basis system.

Gaussian 03 was used as a quantum chemistry calculation program. A high-performance computer (manufactured by SGI Japan, Ltd, Altix 4700) was used for the calculation.

It is assumed that heat treatment for dehydration or dehydrogenation causes -OH groups contained in the oxide semiconductor film to react with each other _{to generate H 2 O.} Thus, the mechanism of water generation and removal is interpreted as shown in FIG. 26. In FIG. 26, when Zn is bivalent and M is Zn, one MO bond is deleted in FIG. 26. In FIG.

In Fig. 26, M represents a metal atom, and is any one of the following three types: In, Ga, and Zn. In the starting state 1, -OH forms a coordination bond to bridge _{M 1} and M _2. In transition state 2, H of -OH is displaced to another -OH. In Intermediate 3, the resulting H ₂ O molecule forms a coordination bond with a metal atom. In end state 4, the H ₂ O molecule is desorbed and moves farther to infinity.

The following six combinations of (M ₁ -M ₂ ): 1, In-In; 2, Ga-Ga; 3, Zn-Zn; 4, In-Ga; 5, In-Zn; And 6, Ga-Zn. Simulations are run for all combinations. In this simulation, cluster calculation using a simulation model in which M'is replaced by H is used for simplicity of the simulation.

In the simulation, an energy diagram corresponding to the reaction path of FIG. 26 is obtained. Among the six combinations of (M ₁ -M ₂ ), simulation results of 1 and In-In are shown in FIG. 27.

It is found from Fig. 27 that the activation energy to generate water is 1.16 eV. By removal of the resulting water molecules, the membrane is destabilized by 1.58 eV.

When FIG. 27 is viewed from the opposite direction, such as a reaction from right to left, the reaction can be perceived as a reaction in which water enters the oxide semiconductor film. In this case, the activation energy when water coordinated to the metal is hydrolyzed to generate two OH groups is 0.47 eV.

Similarly, reaction pathways for different combinations of _{(M 1} -M _{2) are analyzed.} Table 1 shows the activation energies (Ea[eV]) of the water generation reaction in the cases (1 to 6).

[Table 1]

Activation energy Ea[eV] to generate water

From Table 1, it can be seen that the water formation reaction is likely to occur in 1, In-In or 4, In-Ga. In contrast, the formation reaction of water is unlikely to occur in 3, Zn-Zn. Therefore, it can be assumed that the reaction of generating water using a Zn atom is difficult to occur.

The heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be provided. For example, a rapid thermal anneal (RTA) device such as a gas rapid thermal anneal (GRTA) device or a lamp rapid thermal anneal (LRTA) device may be used. The LRTA device is a device that heats a target object by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas that does not react with the object to be treated by heat treatment such as nitrogen is used.

For example, as the first heat treatment, GRTA may be performed where the substrate is moved to an inert gas heated to a high temperature as high as 650°C to 700°C, heated for several minutes, and moved to the outside of the inert gas heated to a high temperature. have. GRTA enables high temperature heat treatment in a short time.

In the first heat treatment, it is preferable that water, hydrogen, or the like is contained as little as possible in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, nitrogen, or a rare gas such as helium, neon or argon, introduced into the heat treatment device has a purity of 6 N (99.9999%) or more, preferably 7 N (99.99999%) or more, i.e., an impurity concentration of 1 It is preferably set to ppm or less, preferably 0.1 ppm or less.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film may be microcrystalline so that it becomes a microcrystalline film or a polycrystalline film. For example, the oxide semiconductor layer may be microcrystallized to become an oxide semiconductor film having a degree of crystallization of 90% or more, or 80% or more. The oxide semiconductor layer may be an amorphous oxide semiconductor layer containing no crystal components depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. The oxide semiconductor layer may be an amorphous oxide semiconductor and may be an oxide semiconductor film in which a microcrystalline portion (having a particle diameter of 1 nm or more and 20 nm or less, and usually 2 nm or more and 4 nm or less) is mixed. When heat treatment is performed at a high temperature using RTA (eg, GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be formed on the surface side of the oxide semiconductor film. .

The first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film 440 before being processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus, and a photolithography step is performed.

The heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is performed at any of the following timings: after the formation of the oxide semiconductor layer, after the source electrode and the drain electrode are formed on the oxide semiconductor layer, and protection on the source electrode and drain electrode. It may be implemented after the insulating film is formed.

In addition, when a contact hole is formed in the gate insulating layer 402, the contact hole may be formed before or after dehydration or dehydrogenation of the oxide semiconductor layer 440.

The oxide semiconductor layer preferably contains In, more preferably In and Ga. In order to make the oxide semiconductor layer i-type (intrinsic), dehydration or dehydrogenation is effective.

The etching of the oxide semiconductor film is not limited to wet etching and may be dry etching.

As the etching gas for dry etching, a gas containing chlorine (chlorine-based plasticizing such as chlorine _{(Cl 2} ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CCl _{4 )) is preferably used.} .

Alternatively, a fluorine-containing gas (a fluorine-based gas such as carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ )); Hydrogen bromide (HBr), oxygen (O ₂ ); Gas to which a rare gas such as helium (He) or argon (Ar) is added to these gases may be used.

As the dry etching method, a parallel plate type RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method may be used. In order to etch into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted.

As an etchant used for wet etching, a solution of phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31% by weight hydrogen peroxide: 28% by weight aqueous ammonia: water = 5:2:2), and the like can be used. In addition, ITO07N (manufactured by KANTO CHEMICAL CO., INC) may be used.

The etchant used for wet etching is removed by cleaning together with the etched material. The waste liquid including the etchant and the etched material may be purified, and the material may be reused. A material such as indium contained in the oxide semiconductor layer may be recovered from the waste liquid after etching and may be reused, so that resources may be efficiently used and cost may be reduced.

In order to etch into the desired processing shape, the etching conditions (such as etchant, etching time, temperature) are appropriately adjusted depending on the material.

Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 441. Thereafter, a resist mask is formed by a third photolithography step, and after the metal conductive film is selectively etched to form the source electrode layer 415a and the drain electrode layer 415b, the resist mask is removed (see Fig. 2C).

Note that the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 441 is not removed by etching of the metal conductive film.

In this embodiment, a Ti film is used as a metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 441, and a hydrogen peroxide ammonia mixture (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etching solution. Is used.

The source and drain electrode layers are preferably as thin as 0.1 nm or more and 50 nm or less in thickness, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced.

The source and drain electrode layers are preferably formed using a material containing a metal having high oxygen affinity. The metal having high oxygen affinity is preferably at least one material selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.

When heat treatment is performed while the oxide semiconductor layer and the metal layer having high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, thereby increasing the carrier density near the interface. A low resistance region is formed near the interface to reduce the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.

A heat-resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, even when heat treatment is performed after the formation of the source and drain electrode layers, the change or deterioration of the characteristics of the source and drain electrode layers can be prevented.

As a heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), and any of the above elements An alloy containing as, an alloy film containing any combination of these elements, a nitride containing any of the above elements as a component, and the like can be used. A conductive film having heat resistance in which a low-resistance conductive material such as aluminum (Al) or copper (Cu) is combined with the heat-resistant conductive material described above may be used.

The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a titanium oxide film ( For example, a structure provided with a thickness of 1 nm or more and 20 nm or less) may be used.

When the source and drain electrode layers are thin enough to transmit light, the source and drain electrode layers have light-transmitting properties.

In the third photolithography step, only a part of the oxide semiconductor layer 441 may be etched, so that an oxide semiconductor layer having a groove portion (concave portion) may be formed. A resist mask for forming the source electrode layer 415a and the drain electrode layer 415b may be formed by an ink jet method. When the resist mask is formed by the inkjet method, the photomask is not used, which causes a reduction in manufacturing cost.

In order to reduce the number of photomasks and steps in the photolithography step, the etching step may be performed using a resist mask formed by a multi-gradation mask, which is a mask through which light is transmitted so as to have a plurality of intensities. The resist mask formed using the multi-gradation mask has a plurality of thicknesses, and the shape can be further changed by etching, and thus, the resist mask can be used in a plurality of etching steps for processing into different patterns. Thus, a resist mask corresponding to at least two types of different patterns can be formed by one multi-gradation mask. In this way, the number of exposure masks can be reduced, and the number of corresponding photolithography steps can also be reduced, so that simplification of the process can be realized.

Next, plasma treatment is performed using a gas such as _{N 2} O, N _{2, or Ar.} By this plasma treatment, adsorbed water and the like adhering to the exposed surface of the oxide semiconductor layer are removed. Plasma treatment may also be carried out using a mixed gas of oxygen and argon.

After the plasma treatment, an oxide insulating layer 407 that functions as a protective insulating film in contact with a part of the oxide semiconductor layer is formed without being exposed to air.

The oxide insulating layer 407 has a thickness of at least 1 nm, and may be appropriately formed by a method in which impurities such as water and hydrogen are mixed in the oxide insulating layer 407 as little as possible, such as a sputtering method. When hydrogen is included in the oxide insulating layer 407, intrusion of hydrogen into the oxide semiconductor layer or extraction of oxygen from the oxide semiconductor layer by hydrogen is caused, thereby lowering the resistance of the back channel of the oxide semiconductor layer (n- Type conductivity), a parasitic channel is formed. Therefore, it is important that the oxide insulating layer 407 contains as little hydrogen as possible, and a formation method in which as little hydrogen is used as possible is used.

In this embodiment, a 200 nm thick silicon oxide film is formed as the oxide insulating layer 407 by sputtering. The substrate temperature at the time of film formation is room temperature or more and 300°C or less, and in this embodiment, the temperature is 100°C. The silicon oxide film may be formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically argon) and oxygen by a sputtering method. As the target, a silicon oxide target or a silicon target may be used. For example, using a silicon target, a silicon oxide film may be formed by sputtering in an atmosphere containing oxygen and nitrogen. As the oxide insulating layer 407 formed in contact with the oxide semiconductor layer having a reduced resistance, an inorganic insulating film containing as little as possible impurities such ^{as moisture, hydrogen ions, and OH − and blocking their invasion from the outside is provided.} It may be used, and typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxide nitride film is used.

Next, a second heat treatment (at a temperature of 200°C or more and 400°C or less, for example, 250°C or more and 350°C or less) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. A second heat treatment is performed while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 407.

Through the above-described steps, after a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film to reduce the resistance, a part of the oxide semiconductor film is selectively brought into an oxygen-excess state. As a result, the channel formation region 413 overlapping the gate electrode layer 411 becomes I-type, and the high resistance overlaps the high resistance source region 414a and the drain electrode layer 415b overlapping the source electrode layer 415a. The drain region 414b is formed in a self-aligning manner. Through the above process, the thin film transistor 410 is formed.

Further, the heat treatment may be performed in the air at a temperature of 100°C or more and 200°C or less for a period of 1 hour or more and 30 hours or less. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heating treatment may be carried out at a fixed heating temperature, or alternatively, the following change in the heating temperature may be repeatedly carried out a plurality of times: the heating temperature is increased from room temperature to a temperature of 100° C. or more and 200° C. , Then, it is reduced to room temperature. Such heat treatment may be performed under reduced pressure before formation of the oxide insulating film. The reduced pressure allows the heat treatment to be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer, and thus, a normally off thin film transistor can be obtained. Accordingly, the reliability of the semiconductor device can be improved.

By forming a high resistance drain region 414b (and a high resistance source region 414a) in some(s) of the oxide semiconductor layer overlapping the drain electrode layer 415b (and the source electrode layer 415a), the reliability of the thin film transistor is improved. It can be improved. Specifically, by the formation of the high resistance drain region 414b, the conductivity can be gradually changed in this order from the drain electrode layer 415b to the high resistance drain region 414b and the channel formation region. Therefore, when the transistor operates as the drain electrode layer 415b connected to the wiring supplying the high power source potential (VDD), even if a high field is applied between the gate electrode layer 411 and the drain electrode layer 415b, the high resistance drain region is buffered. As a result, since a local high electric field is not applied to the transistor, the transistor can have an increased breakdown voltage.

The high-resistance source region or the high-resistance drain region may be formed over the entire film thickness direction in the oxide semiconductor when the oxide semiconductor layer is as thin as 15 nm or less, but when the oxide semiconductor layer is as thick as 30 nm or more and 50 nm or less. , A portion of the oxide semiconductor layer, that is, a region in contact with the source or drain electrode layers, and the vicinity thereof may have a reduced resistance, so that a high resistance source region or a high resistance drain region is formed, and the oxide semiconductor layer close to the gate insulating film The region can be of type I.

A protective insulating layer may be formed on the oxide insulating layer 407. For example, a silicon nitride film is formed by RF sputtering. The RF sputtering method is preferable as a method of forming a protective insulating layer due to its high mass productivity. The protective insulating layer is formed using an inorganic insulating film that contains as little as possible impurities such as moisture, hydrogen ions, and OH ^- and blocks them from entering from the outside, for example, a silicon nitride film, an aluminum nitride film , A silicon nitride oxide film, an aluminum oxide nitride film, and the like are used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer (see Fig. 2D).

Next, a fourth photolithography process is performed to form a resist mask, and etching is selectively performed to remove portions of the oxide insulating layer 407 and the protective insulating layer 408, and the source electrode layer 415a and Openings 442a and 442b reaching the drain electrode layer 415b are formed (see Fig. 2E).

A conductive layer stacked in the openings 442a and 442b so as to contact the source electrode layer 415a and the drain electrode layer 415b is formed by sputtering or vacuum evaporation, and a resist mask is formed by a fifth photolithography step. The stacked conductive layer is selectively etched to form wiring layers 417a, 417b, 418a and 418b and source wiring layers 422 and 423 at the intersections (see FIG. 2F).

The wiring layers 417a, 417b, 418a, and 418b are formed using a conductive film having resistances lower than those of the source and drain electrode layers. In particular, a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material containing any of these materials as a main component may be used to have a single-layer or laminated structure. In this embodiment, an aluminum film is used as each of the wiring layers 417a and 417b as the first wiring layer, and a titanium film is used as each of the wiring layers 418a and 418b as the second wiring layers.

A planarization insulating layer for planarization may be provided over the protective insulating layer 408. An example in which a planarization insulating layer is provided is shown in Fig. 6A. 6A, a planarization insulating layer 409 is formed on the protective insulating layer 408, and the wiring layers 417a, 417b, 418a, and 418b are an oxide insulating layer 407, a protective insulating layer 408, and planarization. It is formed in openings provided in the insulating layer 409. The source wiring layers 422 and 423 are formed on the planarization insulating layer 409. The provision of the planarization insulating layer 409 makes the gate wiring layer 421 and the source wiring layers 422 and 423 further away from each other, so that the parasitic capacitance can be further reduced.

The planarization insulating layer 409 may be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to these organic materials, it is possible to use a low dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. The planarization insulating layer 409 may be formed by laminating a plurality of insulating films formed using these materials.

The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may contain an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also contain a fluoro group.

There is no particular limitation on the method of forming the planarization insulating layer 409, depending on the material, sputtering method, spin coating method, dipping method, spray coating method, droplet discharge method (e.g., inkjet method, screen printing , Offset printing), a roll coating method, a curtain coating method, or a knife coating method, and the like may be used.

Alternatively, as shown in FIG. 6B, without providing a protective insulating layer, a wiring layer and a source wiring layer may be formed over the oxide insulating layer 407. In FIG. 6B, the source wiring layer 422 is provided over the oxide insulating layer 407, and the wiring layers 417a and 417b are provided in openings formed in the oxide insulating layer 407. As described above, the wiring layer may have a single layer structure.

In this way, a semiconductor device having a small parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

A semiconductor device having high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

(Embodiment 2)

In Embodiment 2, an example of a semiconductor device including a thin film transistor having a structure different from that of Embodiment 1 will be described later.

3A1 and 3A2 illustrate an example of a planar structure of a semiconductor device, and FIG. 3B illustrates an example of a cross section of the semiconductor device. The thin film transistor 450 shown in FIGS. 3A2 and 3B is a type of a bottom gate structure called a channel protection type (channel stop type), and is also called an inverse stagger type thin film transistor.

3A1 is a plan view of an intersection between a gate wiring layer (formed by the same step as the gate electrode layer) and a source wiring layer (formed by the same step as the wiring layer), and FIG. 3A2 is a plan view of the channel protection type thin film transistor 450, 3B is a cross-sectional view taken along lines C3-C4 and D3-D4 in FIGS. 3A1 and 3A2.

The thin film transistor 450, which is a channel-protected thin film transistor, has a gate electrode layer 451, a gate insulating layer 402, at least a channel formation region 453, and a high resistance source region 454a on a substrate 400 having an insulating surface. ), and an oxide semiconductor layer 452 including a high resistance drain region 454b, a source electrode layer 455a, and a drain electrode layer 455b. In addition, an oxide insulating layer 456 that covers the thin film transistor 450 and contacts the channel formation region 413 and functions as a channel protective layer is provided, and a protective insulating layer 408 is provided thereon.

In the protective insulating layer 408, openings (contact holes) reaching the source electrode layer 455a and the drain electrode layer 455b are formed. Wiring layers 457a and 458a are formed in one of the openings, and wiring layers 457b and 458b are formed in the other of the openings. At the intersection, the gate wiring layer 421 and the source wiring layers 422 and 423 are stacked with the gate insulating layer 402, the oxide insulating layer 459, and the protective insulating layer 408 interposed therebetween.

At the intersection, the oxide insulating layer 459 does not necessarily have to be provided, but the provision of the oxide insulating layer 459 makes the gate wiring layer 421 and the source wiring layers 422 and 423 further away from each other, and thus parasitic The dose can be further reduced.

The oxide insulating layers 456 and 459 may be formed by etching the oxide insulating layer, and may be formed by the same fabrication method and material as the oxide insulating layer 407 described in Embodiment 1. In this embodiment, an oxide insulating layer is formed by a sputtering method, and processed into oxide insulating layers 456 and 459 by a photolithography step.

In this way, the gate electrode layer (gate wiring layer) crosses the wiring layer electrically connected to the source electrode layer or the drain electrode layer, and a protective insulating layer and a gate insulating layer covering the thin film transistor are interposed therebetween. A stacked structure of a gate electrode layer, a gate insulating layer, and a source or drain electrode layer is not formed, except that the gate electrode layer of the thin film transistor partially overlaps the source electrode layer and the drain electrode layer on the oxide semiconductor layer.

Accordingly, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Although the thin film transistor 450 is described as a single gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions may be formed if necessary.

Hereinafter, a process of fabricating the thin film transistor 450 on the substrate will be described with reference to FIGS. 4A to 4F.

First, a conductive film is formed on a substrate 400 having an insulating surface, and a first photolithography process is performed to form a gate electrode layer 451 and a gate wiring layer 421. The resist mask may be formed by an ink jet method. When the resist mask is formed by the inkjet method, the photomask is not used, which causes a reduction in manufacturing cost.

The gate electrode layer 451 and the gate wiring layer 421 are made of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component. Thus, it may be formed to have a single layer structure or a stacked structure.

Next, a gate insulating layer 402 is formed over the gate electrode layer 451 and the gate wiring layer 421.

In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed as the gate insulating layer 402 by the plasma CVD method.

Next, on the gate insulating layer 402, an oxide semiconductor film with a thickness of 2 nm or more and 200 nm or less is formed, and then, the oxide semiconductor film is processed into an island-like oxide semiconductor layer by a second photolithography process. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or more and 750°C or less, and preferably 400°C or more and less than the strain point of the substrate. In this embodiment, the substrate is placed in an electric furnace, which is a kind of heat treatment apparatus, and after the oxide semiconductor layer is subjected to heat treatment at 450° C. for 1 hour in a nitrogen atmosphere, the oxide semiconductor layer is not exposed to the atmosphere. , Intrusion of water and hydrogen into the oxide semiconductor layer is prevented. In this way, an oxide semiconductor layer 441 is obtained (see Fig. 4A).

Next, plasma treatment is performed using a gas such as _{N 2} O, N _{2, or Ar.} By this plasma treatment, the adsorbed water adhering to the exposed surface of the oxide semiconductor layer is removed. Plasma treatment may also be carried out using a mixed gas of oxygen and argon.

Next, an oxide insulating layer is formed over the gate insulating layer 402 and the oxide semiconductor layer 441. Thereafter, a resist mask is formed by a third photolithography step, and after the oxide insulating layer is selectively etched to form the oxide insulating layer 456 and the oxide insulating layer 459, the resist mask is removed.

In this embodiment, a 200 nm thick oxide silicon layer is formed as the oxide insulating layer 456 and the oxide insulating layer 459 by sputtering. The substrate temperature at the time of film formation may be room temperature or more and 300°C or less, and in this embodiment, it is 100°C. The silicon oxide film can be formed by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. As the target, a silicon oxide target or a silicon target may be used. For example, using a silicon target, a silicon oxide film can be formed by a sputtering method in an oxygen and nitrogen atmosphere. As the oxide insulating layer 456 formed in contact with the oxide semiconductor layer whose resistance has been reduced, an inorganic insulating film containing as little as possible impurities such ^{as moisture, hydrogen ions or OH − and blocking their invasion from the outside may be used.} Alternatively, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxide nitride film is used as a representative example.

Next, the second heat treatment may be performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at a temperature of 200°C or more and 400°C or less, for example, at a temperature of 250°C or more and 350°C or less). For example, the 2nd heat treatment is performed for 1 hour at 250 degreeC in nitrogen atmosphere. A second heat treatment is performed while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 456.

In this embodiment, the oxide insulating layer 456 is provided and the partially exposed oxide semiconductor layer 441 is heat-treated under a nitrogen atmosphere or an inert gas atmosphere or under reduced pressure. By heat treatment under a nitrogen atmosphere or an inert gas atmosphere or under reduced pressure, the resistance of the exposed area of the oxide semiconductor layer 441 not covered by the oxide insulating layer 456 can be reduced. For example, the heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

By heat treatment for the oxide semiconductor layer 441 provided with the oxide insulating layer 456 in a nitrogen atmosphere, the resistance of the exposed area of the oxide semiconductor layer 441 is reduced (as shaded area and white area in Fig. 4B). An oxide semiconductor layer 452 comprising regions having different resistances (indicated) is formed.

Next, a metal conductive film is formed over the gate insulating layer 402, the oxide semiconductor layer 452, and the oxide insulating layer 456. Thereafter, a resist mask is formed by the fourth photolithography step, the metal conductive film is selectively etched to form the source electrode layer 455a and the drain electrode layer 455b, and then the resist mask is removed (see FIG. 4C). ).

The source electrode layer 455a and the drain electrode layer 455b are preferably as thin as 0.1 nm or more and 50 nm or less in thickness, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced.

It is preferable that the source electrode layer 455a and the drain electrode layer 455b are formed using a material containing a metal having high oxygen affinity. The metal having high oxygen affinity is preferably one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source electrode layer 455a and the drain electrode layer 455b.

When heat treatment is performed while the oxide semiconductor layer and the metal layer having high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density near the interface therebetween increases. Accordingly, a low resistance region is formed near the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.

A heat-resistant conductive material may be used in the source electrode layer 455a and the drain electrode layer 455b. By using a heat-resistant conductive material, change or deterioration of the characteristics of the source electrode layer 455a and the drain electrode layer 455b can be prevented even when heat treatment is performed after the formation of the source electrode layer 455a and the drain electrode layer 455b. .

As a heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), any of the above-described elements An alloy containing as a component, an alloy film containing any combination of these elements, a nitride containing any of the above elements as a component, and the like can be used. A conductive film having heat resistance in which a low-resistance conductive material such as aluminum (Al) or copper (Cu) is combined with the heat-resistant conductive material described above may be used.

The source electrode layer 455a and the drain electrode layer 455b may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a titanium oxide film (e.g., a titanium oxide film having a thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer For example, a structure provided with a thickness of 1 nm or more and 20 nm or less) may be used.

When the source electrode layer 455a and the drain electrode layer 455b are thin enough to transmit light, the source electrode layer 455a and the drain electrode layer 455b have light transmission properties.

Through the steps described above, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film to reduce the resistance, and after that, a part of the oxide semiconductor film is selectively brought into an oxygen excess state. As a result, the channel formation region 453 overlapping the gate electrode layer 451 becomes I-type, and the high resistance drain region overlaps the high resistance source region 454a and the drain electrode layer 455b ( 454b) is formed self-aligning. Through the above process, the thin film transistor 450 is formed.

Further, the heat treatment may be performed in the air at a temperature of 100°C or more and 200°C or less for 1 hour or more and 30 hours or less. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heat treatment may be carried out at a fixed heating temperature, alternatively, the following change in the heating temperature may be repeatedly carried out a plurality of times: the heating temperature is increased from room temperature to 100° C. or more and 200° C. After that, it is reduced to room temperature. Such heat treatment may be performed under reduced pressure before formation of the oxide insulating film. The reduced pressure can shorten the heat treatment time. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer, and thus, a normally off thin film transistor can be obtained. Accordingly, the reliability of the semiconductor device can be improved.

Reliability of a thin film transistor by forming a high resistance drain region 454b (and a high resistance source region 454a) in some(s) of the oxide semiconductor layer overlapping the drain electrode layer 455b (and the source electrode layer 455a) This can be improved. Specifically, by the formation of the high-resistance drain region 454b, the conductivity can be changed stepwise in this order from the drain electrode layer 455b to the high-resistance drain region 454b and the channel formation region. Therefore, when the transistor operates as the drain electrode layer 455b connected to the wiring supplying the high power source potential (VDD), the high resistance drain region is formed even when a high electric field is applied between the gate electrode layer 451 and the drain electrode layer 455b. The transistor can have an increased breakdown voltage because it acts as a buffer and no local high field is applied to the transistor.

A protective insulating layer 408 is formed over the source electrode layer 455a, the drain electrode layer 455b, the oxide insulating layer 456, and the oxide insulating layer 459. For example, a silicon nitride film is formed by RF sputtering. The RF sputtering method is preferable as a method of forming the protective insulating layer 408 due to its high mass productivity. The protective insulating layer 408 is formed using an inorganic insulating film that contains as little impurities as possible, such as moisture, hydrogen ions, or OH ^−, and blocks their intrusion from the outside, and is formed by using a silicon nitride film or an aluminum nitride film. , A silicon nitride oxide film, an aluminum oxide nitride film, and the like are used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film (see Fig. 4D).

An oxide insulating layer may be formed on the source electrode layer 455a, the drain electrode layer 455b, the oxide insulating layer 456, and the oxide insulating layer 459, and a protective insulating layer 408 is formed on the oxide insulating layer 408 It can also be stacked. As shown in FIG. 6A, a planarization insulating layer 409 may be provided. The provision of the planarization insulating layer 409 makes the gate wiring layer 421 and the source wiring layers 422 and 423 farther apart from each other, so that parasitic capacitance can be further reduced.

Next, a fifth photolithography step is performed to form a resist mask, and etching is selectively performed to remove a part of the protective insulating layer 408, and openings leading to the source electrode layer 455a and the drain electrode layer 455b Fields 467a and 467b are formed (see Fig. 4E).

A laminated conductive layer is formed in the openings 467a and 467b by sputtering or vacuum evaporation so as to contact the source electrode layer 455a and the drain electrode layer 455b, and a resist mask is formed by a sixth photolithography step. The stacked conductive layers are selectively etched to form the wiring layers 457a, 457b, 458a, and 458b and source wiring layers 422 and 423 at the intersections (see FIG. 4F).

The wiring layers 457a, 457b, 458a, and 458b are formed using conductive films having resistances lower than those of the source and drain electrode layers. In particular, a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material containing any of these materials as a main component may be used to have a single layer or laminated structure. . In this embodiment, an aluminum film is used as each of the wiring layers 457a and 457b as first wiring layers, and a titanium film is used as each of the wiring layers 458a and 458b as second wirings.

In this way, a semiconductor device having a small parasitic capacitance and a low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

A semiconductor device having high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

(Embodiment 3)

In Embodiment 3, another example different from Embodiment 1 in the manufacturing process of a semiconductor device including a thin film transistor is described with reference to Figs. 5A to 5F. 5A to 5 are the same as FIGS. 1A1, 1A2 and 1B and 2A to 2F, except that a part of the process is different, and thus, the same parts are denoted by the same reference numerals, and the same Detailed descriptions of the parts are omitted. In this embodiment, a mask layer formed using a multi-gradation mask is used in the photolithography step.

Since the mask layer formed using the multi-gradation mask has a plurality of film thicknesses, and the shape can be further deformed by performing the etching on the mask layer, the mask layer can be used in a plurality of etching steps processing different patterns. . Accordingly, a mask layer corresponding to at least two types of different patterns may be formed by one multi-gradation mask. Accordingly, the number of exposure masks can be reduced, and the number of photolithography steps can also be reduced accordingly, so that simplification of the process can be realized.

According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 481 are formed over the substrate 400 by a first photolithography step, and a gate insulating layer 402 is laminated thereon. An oxide semiconductor film is formed over the gate insulating layer 402. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target.

For dehydration or dehydrogenation, a substrate is placed in an electric furnace, which is a kind of heat treatment device, and a heat treatment is performed on the oxide semiconductor layer for 1 hour at 450° C. in a nitrogen atmosphere, after which the oxide semiconductor layer is placed in the atmosphere. It is not exposed, and water and hydrogen are prevented from entering the oxide semiconductor layer. In this way, the oxide semiconductor layer 465 is obtained.

Next, a metal conductive film 466 is formed on the oxide semiconductor film 465 by a sputtering method or a vacuum evaporation method (see Fig. 5A).

The metal conductive film 466 is a conductive film forming source and drain electrode layers. The source and drain electrode layers are preferably as small as 0.1 nm or more and 50 nm or less in thickness, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced.

It is preferable that the source and drain electrode layers are formed using a material containing a metal having high oxygen affinity. The metal with high oxygen affinity is preferably one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.

When heat treatment is performed while the oxide semiconductor layer and the metal layer having high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier concentration near the interface therebetween increases. The low resistance region is formed near the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.

Heat resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, change or deterioration of the characteristics of the source and drain electrode layers can be prevented even when heat treatment is performed after the formation of the source and drain electrode layers.

As a heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), and any of the above elements An alloy containing as, an alloy film containing any combination of these elements, or a nitride containing any of the above elements as a component can be used. A conductive film having heat resistance in which a low-resistance conductive material such as aluminum (Al) or copper (Cu) is combined with the heat-resistant conductive material described above may be used.

The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a titanium oxide film (e.g., a titanium oxide film having a thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer is provided between the oxide semiconductor layer and the titanium film. For example, a structure in which a thickness of 1 nm or more and 20 nm or less) is provided may be used.

When the source and drain electrode layers are thin enough to transmit light, the source and drain electrode layers have light-transmitting properties.

A second photolithography step is performed, and a resist mask 460 is formed over the oxide semiconductor film 465 and the metal conductive film 466.

In this embodiment, an example in which a high gradation mask is used for exposure to form the resist mask 460 is shown. A resist is formed to form a resist mask 460. As the resist, a positive type resist or a negative type resist can be used. In this embodiment, a positive resist is used. The resist may be formed by a spin coating method or may be selectively formed by an ink jet method. When the resist is selectively formed by the ink jet method, the resist can be prevented from being formed in an undesired portion, which causes a reduction in waste of material.

Next, the resist is irradiated with light using the multi-gradation mask 81 as an exposure mask, and the resist is exposed.

Here, exposure using the multi-gradation mask 81 will be described with reference to FIGS. 25A to 25D.

The multi-gradation mask makes it possible to form three exposure levels, an exposed portion, an intermediate exposed portion, and an unexposed portion, and the multi-gradation mask is a photomask through which light is transmitted so as to have a plurality of intensities. In one exposure and development process, a resist mask having regions of a plurality of thicknesses (typically, two types of thickness) can be formed. Therefore, by using a multi-gradation mask, the number of photomasks can be reduced.

Typical examples of the multi-gradation mask are the gray-tone mask 81a shown in Fig. 25A and the half-tone mask 81b shown in Fig. 25C.

As shown in Fig. 25A, the gray-tone mask 81a includes a light-transmitting substrate 83, a light-shielding portion 84 formed on the light-transmitting substrate 83, and a diffraction grating 85. The light transmittance at the light shielding portion 84 is 0%. The diffraction grating 85 has a slit-type, dot-type, or mesh-type light transmitting portion having an interval equal to or less than the resolution limit of light used for exposure, so that the light transmittance can be controlled. The diffraction grating 85 may be used in a slit type, dot type, or mesh type having periodic spacing, or a slit type, dot type, mesh type having aperiodic spacing.

As the light-transmitting substrate 83, a light-transmitting substrate such as a quartz substrate may be used. The light blocking portion 84 and the diffraction grating 85 may be formed using a light blocking material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 81a is irradiated with exposure light, as shown in FIG. 25B, the light transmittance 86 of the light-shielding portion 84 is 0%, and the light-shielding portion 84 and the diffraction grating 85 The light transmittance 86 in the region where) is not provided is 100%. The light transmittance 86 of the diffraction grating 85 can be controlled in a range of 10% to 70%. The light transmittance of the diffraction grating 85 can be controlled by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating.

As shown in Fig. 25C, the half-tone mask 81b includes a translucent substrate 83, and a translucent portion 87 and a light-shielding portion 88 formed on the translucent substrate. 87) can be formed using MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light blocking portion 88 may be formed using a light blocking material that absorbs light such as chromium or chromium oxide.

When the half-tone mask 81b is irradiated with exposure light, as shown in Fig. 25D, the light transmittance 89 of the light-shielding portion 88 is 0%, and the light-shielding portion 88 and the semi-transmissive portion 87 The light transmittance 89 in the region where) is not provided is 100%. The light transmittance 89 of the translucent portion 87 may be controlled in a range of 10% to 70%. The transmittance of light of the translucent portion 87 can be controlled by the material of the translucent portion 87.

After exposure using the multi-gradation mask, development is performed, so that a resist mask 460 having regions having different thicknesses can be formed as shown in FIG. 5B.

Next, a first etching step is performed using the resist mask 460, so that the oxide semiconductor film 465 and the metal conductive film 466 are etched in an island shape. As a result, the oxide semiconductor layer 461 and the metal conductive layer 462 may be formed (see FIG. 5B ).

Next, ashing is performed on the resist mask 460. As a result, the area (volume when considered in three dimensions) of the resist mask is reduced, and the thickness is reduced. Through this step, the resist (a region overlapping with a part of the gate electrode layer 481) of the resist mask having a small thickness is removed, so that the resist masks 463a and 463b separated from each other may be formed.

With the resist masks 463a and 463b, unnecessary portions are removed by etching to form a source electrode layer 485a and a drain electrode layer 485b (see Fig. 5C).

Each material and etching conditions of etching for the metal conductive layer 462 are appropriately adjusted so that the oxide semiconductor layer 461 is not removed.

In this embodiment, a Ti film is used as the metal conductive layer 462, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 461, and an ammonia peroxide solution (ammonia, water, hydrogen peroxide solution) is used as the etchant. Mixed solution) is used.

The etching of the metal conductive film and the oxide semiconductor film is not limited to wet etching and may be dry etching.

As the etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), or carbon tetrachloride (CCl ₄ )) is preferably used. .

Alternatively, a fluorine-containing gas (carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), a fluorine-based gas such as trifluoromethane (CHF ₃ )), hydrogen bromide (HBr) ), oxygen (O ₂ ), helium (He), or any of these gases to which a noble gas such as argon (Ar) is added may be used.

As the dry etching method, a parallel plate reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method may be used. In order to etch into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

As the etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid, ammonia peroxide mixture (31 wt% hydrogen peroxide solution: 28 wt% ammonia solution: water = 5:2:2), etc. can be used. . ITO07N (manufactured by KANTO CHEMICAL CO., LTD) may also be used.

The etchant used for wet etching is removed by cleaning together with the etched material. The etched material and the waste liquid containing the etchant may be purified, and the material may be reused. A material such as indium contained in the oxide semiconductor layer may be recovered or reused from the waste liquid after etching, thereby efficiently using resources and reducing cost.

Etching conditions (such as etchant, etching time, and temperature) are appropriately adjusted depending on the material to etch into the desired shape.

Next, the resist masks 463a and 463b are removed, and an oxide insulating layer 407 serving as a protective insulating film in contact with a part of the oxide semiconductor layer 461 is formed. In this embodiment, a 200 nm thick silicon oxide film is formed as the oxide insulating layer 407 by sputtering.

Next, the second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200°C or more and 400°C or less, for example, 250°C or more and 350°C or less). For example, the 2nd heat treatment is performed for 1 hour at 250 degreeC in nitrogen atmosphere. In the second heat treatment, heating is performed while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 407.

Through the above-described steps, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor layer to reduce the resistance, and after that, a part of the oxide semiconductor film is selectively brought into an oxygen-excess state. As a result, the channel formation region 483 overlapping the gate electrode layer 481 becomes I-type, and the high resistance drain region overlapping the high resistance source region 484a and the drain electrode layer 485b overlapping the source electrode layer 485a ( 484b) is formed by self-alignment. Through the above process, the thin film transistor 480 is formed.

Further, the heat treatment may be performed in the air at a temperature of 100°C or more and 200°C or less for 1 hour or more and 30 hours or less. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heating treatment may be carried out at a fixed heating temperature, or alternatively, the following change in the heating temperature may be repeatedly carried out a plurality of times: The heating temperature is increased from room temperature to a temperature of 100° C. or more and 200° C. or less. And then it is reduced to room temperature. Such heat treatment may be performed under reduced pressure before formation of the oxide insulating film. The reduced pressure makes it possible to shorten the heat treatment time. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer, and thus, a normally off thin film transistor can be obtained. Accordingly, the reliability of the semiconductor device can be improved.

Next, a protective insulating layer 408 is formed over the oxide insulating layer 407. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer (see Fig. 5D).

Next, a third photolithography step is performed to form a resist mask, and etching is selectively performed to remove portions of the oxide insulating layer 407 and the protective insulating layer 408, and the source electrode layer 485a and Openings 464a and 464b reaching the drain electrode layer 485b are formed (see Fig. 5(e)).

A laminated conductive layer is formed in the openings 464a and 464b by sputtering or vacuum evaporation so as to contact the source electrode layer 485a and the drain electrode layer 485b, and a resist mask is formed by a fourth photolithography process. The stacked conductive layer is selectively etched to form wiring layers 487a, 487b, 488a, and 488b, and source wiring layers 422 and 423 at the intersections (see Fig. 5(f)).

The wiring layers 487a, 487b, 488a, and 488b are formed using conductive films having a resistance lower than that of the source and drain electrode layers. In particular, the wiring layers are formed to have a single layer or a laminated structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material containing any of these materials as a main component. I can. In this embodiment, an aluminum film is used as each of the wiring layers 487a and 487b as first wiring layers, and a titanium film is used as each of the wiring layers 488a and 488b as second wiring layers.

In this way, a semiconductor device having a small parasitic capacitance and a low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

A semiconductor device having high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 4)

In Embodiment 4, an example in which the gate electrode layer of Embodiment 1 is formed using a light-transmitting conductive material is described with reference to FIG. 7. Accordingly, the same can be applied to the first embodiment, and descriptions of the same parts as the first embodiment and parts and steps having functions similar to those of the first embodiment are omitted. Fig. 7 is the same as Figs. 1A1, 1A2, 1B, and 2A to 2F, except that there is a difference in part of the process, and thus, the same parts are denoted by the same reference numerals, and the details of the same parts Description is omitted.

The thin film transistor 430 shown in FIG. 7 is a channel-etched thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 431, a gate insulating layer 402, at least a channel formation region 433, and It includes an oxide semiconductor layer 432 including a resistance source region 434a and a high resistance drain region 434b, a source electrode layer 435a, and a drain electrode layer 435b. Further, an oxide insulating layer 407 covering the thin film transistor 430 and in contact with the channel formation region 433 is provided, and a protective insulating layer 408 is provided thereon.

An opening (contact hole) reaching the source electrode layer 435a is formed in the oxide insulating layer 407 and the protective insulating layer 408. Wiring layers 437 and 438 are formed in the opening. At the intersection, the gate wiring layer 421 and the source wiring layers 422 and 423 are stacked with the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 interposed therebetween. As the opening reaching the source electrode layer 435a shown in FIG. 7 and wiring layers 437 and 438 formed in the opening, the opening and the wiring layer may be provided in a region that does not overlap with the oxide semiconductor layer 432.

In this way, the gate electrode layer (gate wiring layer) intersects the wiring layer electrically connected to the source electrode layer or the drain electrode layer, the insulating layer covering the oxide semiconductor layer of the thin film transistor, and the gate insulating layer therebetween. A stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer is not formed, except that the gate electrode layer of the thin film transistor partially overlaps the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.

Accordingly, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

A planarization insulating layer 409 is formed on the wiring layer 438, the source wiring layer 423, and the protective insulating layer 408, and a pixel electrode layer 427 is formed on the planarization insulating layer 409. The pixel electrode layer 427 is in contact with the wiring layer 438 through an opening formed in the planarization insulating layer 409, and the thin film transistor 430 is electrically connected to the pixel electrode layer 427 through the wiring layers 437 and 438. .

Each of the source electrode layer 435a and the drain electrode layer 435b can be formed as a light-transmitting conductive film by using a thin metal conductive film.

In addition, in FIG. 7, the gate electrode layer 431 of the thin film transistor 430 is also formed using a light-transmitting conductive film.

As the material of the gate electrode layer 431, a conductive material that transmits visible light may be used. For example, any of the following metal oxides: In-Sn-O-based metal oxide, In-Sn-Zn-O-based metal oxide, In-Al-Zn-O-based metal oxide, Sn-Ga-Zn-O-based Metal oxide, Al-Ga-Zn-O based metal oxide, Sn-Al-Zn-O based metal oxide, In-Zn-O based metal oxide, Sn-Zn-O based metal oxide, Al-Zn-O based metal Oxide, In-O-based metal oxide, Sn-O-based metal oxide, and Zn-O-based metal oxide may be used. Its thickness is appropriately set within the range of 50 nm or more and 300 nm or less. As a method of forming a metal oxide on the gate electrode layer 431, a sputtering method, a vacuum vapor deposition method (electron beam vapor deposition method, etc.), an arc discharge ion plating method, or a spray method is used. When the sputtering method is used, _{film formation is performed using a target containing 2% by weight or more and 10% by weight or less of SiO 2} , and SiOx (x> 0), which inhibits crystallization, is included in the translucent conductive film and is dehydrated in a later step. It is desirable to prevent crystallization during heat treatment for conversion or dehydrogenation.

In this way, the thin film transistor 430 can be formed as a translucent thin film transistor.

In a pixel provided with the thin film transistor 430, a pixel electrode layer 427, another electrode layer (such as a capacitor electrode layer), or a wiring layer (such as a capacitor wiring layer) is formed using a conductive film that transmits visible light, and has a high aperture ratio. The device is realized. Of course, it is preferable to use films that transmit visible light to form the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408.

In the present specification, a film that transmits visible light refers to a film having a thickness of 75% to 100% of visible light transmittance. In the case where the film has conductivity, the film is also referred to as a transparent conductive film. Further, a conductive film that is translucent to visible light may be used as a metal oxide applied to a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or another electrode layer or another wiring layer. Translucency to visible light means that the transmittance of visible light is 50% to 75%.

Since the thin film transistor 430 has light transmittance, the aperture ratio can be improved. Particularly, in a small liquid crystal display panel of 10 inches or less, a high aperture ratio can be achieved even when the size of the pixel is reduced to realize higher precision of display images, for example, by increasing the number of gate wirings. Further, by using a light-transmitting film for the constituent member of the thin film transistor 430, a high aperture ratio can be realized even when one pixel is divided into a plurality of sub-pixels in order to realize a wide viewing angle. That is, even when groups of high-density thin film transistors are arranged, a high aperture ratio can be maintained, and the display area can have a sufficient area. For example, in the case where one pixel includes 2 to 4 sub-pixels, since the thin film transistor has light-transmitting properties, the aperture ratio can be improved. Further, since the storage capacity may be formed using the same material by the same steps as the components of the thin film transistor, the storage capacity may have light transmission properties, whereby the aperture ratio may be further improved.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 5)

In Embodiment 5, an example different from Embodiment 1 in the manufacturing process of a thin film transistor is described with reference to FIG. 8. Fig. 8 is the same as Figs. 1A1, 1A2, 1B, and 2A to 2F, except that there is a difference in some of the processes, and thus, the same parts are denoted by the same reference numerals, and the same parts are Detailed description is omitted.

According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 471 are formed over the substrate 400, and a gate insulating layer 402 is stacked thereon.

Next, an oxide semiconductor film is formed and processed into an island-shaped oxide semiconductor layer by a photolithography process.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or more and 750°C or less, and preferably 425°C or more. When the temperature is 425°C or higher, the heat treatment time may be 1 hour or less, and when the temperature is less than 425°C, the heat treatment time is longer than 1 hour. In this embodiment, the substrate is placed in an electric furnace, which is a kind of heat treatment apparatus, and the heat treatment is performed on the oxide semiconductor layer under a nitrogen atmosphere, after which the oxide semiconductor layer is not exposed to the atmosphere, and water and hydrogen are Intrusion into the oxide semiconductor layer is prevented. In this way, an oxide semiconductor layer is obtained. Thereafter, high-purity oxygen gas, high-purity N ₂ O gas, or ultra-dry air (having a dew point of -40°C or less, preferably -60°C or less) is introduced into the same furnace and cooling is performed. It is preferable that water, hydrogen, or the like is contained as little as possible in the _{oxygen gas or N 2 O gas. Alternatively, the oxygen gas or N 2} O gas introduced into the heat treatment unit is of a purity of 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the impurity concentration in the _{oxygen gas or N 2 O gas).} Is set to 1 ppm or less, preferably 0.1 ppm or less).

Further, the heat treatment device is not limited to an electric furnace, and for example, a rapid thermal anneal (RTA) device such as a gas rapid thermal anneal (GRTA) device or a lamp rapid thermal anneal (LRTA) device may be used. The LRTA device is a device that heats a target object by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. . The LRTA apparatus may be provided with a device for heating not only a lamp but also an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. GRTA is a method of performing heat treatment using a hot gas. As the gas, a rare gas such as argon or an inert gas that does not react with the object to be processed by heat treatment such as nitrogen is used. The heat treatment may be performed at 600° C. to 750° C. for several minutes using the RTA method.

After the first heat treatment for dehydration or dehydrogenation, the heat treatment may be carried out _{in an oxygen gas or N 2} O gas atmosphere at a temperature of 200° C. or more and 400° C. or less, preferably 200° C. or more and 300° C. or less.

The first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film before being processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is taken out of the heating apparatus, and a photolithography step is performed.

Through the above process, the entire oxide semiconductor film becomes an oxygen-excessive state so that the entire oxide semiconductor film has a higher resistance, that is, becomes I-shaped. Accordingly, the oxide semiconductor layer 472 having an I-type conductivity as a whole is formed.

Next, a resist mask is formed on the oxide semiconductor layer 472 by a photolithography process, and is selectively etched to form the source electrode layer 475a and the drain electrode layer 475b, after which the oxide insulating layer 407 is formed. It is formed by sputtering.

Next, in order to reduce the variation in electrical properties of the thin film transistor, the heat treatment may be performed in an inert gas atmosphere or a nitrogen gas atmosphere (preferably at a temperature of 150°C or more and less than 350°C). For example, the heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

Further, the heat treatment may be performed in the air at a temperature of 100°C or more and 200°C or less for 1 hour or more and 30 hours or less. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heating treatment may be carried out at a fixed heating temperature, or alternatively, the following changes in the heat treatment may be repeatedly carried out a plurality of times: the heating temperature is from room temperature to a heating temperature of 100° C. or more and 200° C. or less. Increases, and then decreases to room temperature. Such heat treatment may be performed under reduced pressure before formation of the oxide insulating film. The reduced pressure allows the heating time to be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer, and thus, a normally off thin film transistor can be obtained. Accordingly, the reliability of the semiconductor device can be improved.

Next, a protective insulating layer 408 is formed over the oxide insulating layer 407.

Next, a photolithography step is performed to form a resist mask, and etching is selectively performed to remove portions of the oxide insulating layer 407 and the protective insulating layer 408, so that the source electrode layer 475a and the drain electrode layer Openings leading to 475b are formed.

A laminated conductive layer is formed in the openings by sputtering or vacuum evaporation to contact the source electrode layer 475a and the drain electrode layer 475b, and a resist mask is formed by a photolithography step. The stacked conductive layer is selectively etched to form wiring layers 477a, 477b, 478a, and 478b, and source wiring layers 422 and 423 at intersections (see FIG. 8).

In this way, as a semiconductor device including a thin film transistor using an oxide semiconductor layer, a semiconductor device having a small parasitic capacitance and low power consumption can be provided.

As a semiconductor device including a thin film transistor using an oxide semiconductor layer, a semiconductor device having high reliability can be provided.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 6)

In Embodiment 6, an example in which an oxide conductive layer functioning as source and drain regions in Embodiment 1 is provided between the oxide semiconductor layer and the source or drain electrode layers will be described with reference to FIG. 9. Accordingly, the same things as in Embodiment 1 can be applied, and descriptions of the same parts as in Embodiment 1 and similar parts and steps as in Embodiment 1 are omitted. 9 is the same as FIGS. 1A1, 1A2, 1B, and 2A to 2F, except that there is a difference in some of the processes, and thus, the same parts are denoted by the same reference numerals, and Detailed description is omitted.

The thin film transistor 469 shown in FIG. 9 is a channel-etched thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 411, a gate insulating layer 402, at least a channel formation region 413, and A resistance source region 414a, and an oxide semiconductor layer 412 including a high resistance drain region 414b, oxide conductive layers 416a and 416b, a source electrode layer 415a, and a drain electrode layer 415b. . Further, an oxide insulating layer 407 covering the thin film transistor 469 and in contact with the channel formation region 413 is provided, and a protective insulating layer 408 is provided thereon.

According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 411 are formed over the substrate 400, and a gate insulating layer 402 is stacked thereon. An oxide semiconductor film is formed over the gate insulating layer 402 to form a dehydrated or dehydrogenated oxide semiconductor layer.

Oxide conductive layers 416a and 416b are formed over the dehydrated or dehydrogenated oxide semiconductor layer. In this embodiment, an example in which the oxide conductive layers 416a and 416b are processed into an appropriate shape by the same photolithography step as the oxide semiconductor layer is described, but the oxide conductive layers 416a and 416b are It may be processed into an appropriate shape by the same photolithography step.

As a method of forming the oxide conductive layers 416a and 416b, a sputtering method, a vacuum evaporation method (electron beam evaporation method, etc.), an arc discharge ion plating method, or a spray method may be used. It is preferable that the material of each of the oxide conductive layers 416a and 416b contains zinc oxide as a component but does not contain indium oxide. As such a material for the oxide conductive layers 416a and 416b, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, gallium zinc oxide, or the like can be used. The thickness of each of the oxide conductive layers is appropriately set within a range of 50 nm or more and 300 nm or less. In the case of using the sputtering method, _{a target containing 2% by weight or more and 10% by weight or less of SiO 2} is used, and the oxide conductive film contains SiOx (x> 0), which inhibits crystallization, and is dehydrated in a later step. It is preferable to suppress crystallization during heat treatment for conversion or dehydrogenation.

In this embodiment, the oxide conductive layers 416a and 416b are formed as follows: processing into an appropriate shape is carried out by the same photolithography step as the oxide semiconductor layer, and etching is performed by the source electrode layer 415a and drain as a mask. It is implemented using the electrode layer 415b. The oxide conductive layers 416a and 416b including zinc oxide as a component can be easily etched with an alkaline solution such as a resist stripper.

The etching treatment for dividing the oxide conductive layer to form the channel region is performed by using the difference in the etching rate between the oxide semiconductor layer and the oxide conductive layer. The oxide conductive layer over the oxide semiconductor layer is selectively etched using a higher etch rate of the oxide conductive layer compared to the oxide semiconductor layer.

Accordingly, the resist mask used to form the source electrode layer 415a and the drain electrode layer 415b is preferably removed by an ashing step. In the case of etching using a stripper, the etching conditions (such as the type, concentration, and etching time of the etching solution) are appropriately adjusted so that the oxide conductive layers and the oxide semiconductor layer are not etched too much.

The oxide conductive layer 416b provided between the oxide semiconductor layer 412 and the drain electrode layer 415b formed using a metallic material is also referred to as a low resistance n-type conductivity (LRD) region. ). Similarly, the oxide conductive layer 416a provided between the oxide semiconductor layer 412 and the source electrode layer 415a formed using a metal material is a region that is a low resistance source (LRS) (low resistance n-type conductivity (LRN)). It also functions as a domain). With the configuration of an oxide semiconductor layer, a low-resistance drain region, and a drain electrode layer formed using a metal material, the breakdown voltage of the transistor can be further increased. Specifically, the carrier concentration in the low-resistance drain region is higher than the carrier concentration in the high-resistance drain region (HRD region), and is preferably in the range of 1×10 ²⁰ /cm ³ or more and 1×10 ²¹ /cm ³ or less.

When oxide conductive layers are provided as the source region and drain region between the oxide semiconductor layer and the source and drain electrode layers, the resistance of the source region and the drain region can be reduced, and high-speed operation of the transistor can be realized. It is effective to use an oxide conductive layer as the source and drain regions in order to improve the frequency characteristics of the peripheral circuit (driving circuit). This is because the contact between the metal electrode (eg Ti) and the oxide semiconductor layer can reduce the contact resistance compared to the contact between the metal electrode (eg Ti) and the oxide conductive layer.

In addition, there is a problem that molybdenum (Mo) used as a part of a wiring material (for example, Mo/Al/Mo) in a semiconductor device has a high contact resistance with an oxide semiconductor layer. This is because Mo is less susceptible to oxidation than Ti and has a weak effect of extracting oxygen from the oxide semiconductor layer, and the contact interface between Mo and the oxide semiconductor layer is not changed to have n-type conductivity. However, even in this case, the contact resistance can be reduced by interposing the oxide conductive layer between the oxide semiconductor layer and the source and drain electrode layers, and thus, the frequency characteristics of the peripheral circuit (driving circuit) can be improved.

The channel length of the thin film transistor is determined at the time of etching the oxide conductive layer, and thus the channel length can be further shortened. For example, the channel length L may be set to 0.1 μm or more and 2 μm or less, and in this way, the operation speed may be increased.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

In this way, a semiconductor device having a small parasitic capacitance and a low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

A semiconductor device having high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.

(Embodiment 7)

In Embodiment 7, Fig. 10 exemplifies an example in which the oxide semiconductor layer is surrounded by a nitride insulating film when viewed in its cross section. 10 is the same as FIGS. 1A1, 1A2, and 1B, except that there is a difference in the shape of the top surface and the position of the end of the oxide insulating layer, and the configuration of the gate insulating layer, and thus, the same parts are the same. Denoted by reference numerals, and detailed descriptions of the same parts are omitted.

The thin film transistor 410 shown in FIG. 10 is a channel-etched thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 411, a first gate insulating layer 492a formed using a nitride insulating film, and an oxide A second gate insulating layer 492b formed using an insulating film, an oxide semiconductor layer 412 including at least a channel formation region 413, a high resistance source region 414a, and a high resistance drain region 414b, and a source electrode layer 415a and a drain electrode layer 415b. Further, an oxide insulating layer 497b is provided that covers the thin film transistor 410 and contacts the channel formation region of the oxide semiconductor layer 412. A protective insulating layer 498 is provided over the oxide insulating layer 497b.

In the oxide insulating layer 497b and the protective insulating layer 498, openings (contact holes) reaching the source electrode layer 415a and the drain electrode layer 415b are formed. Wiring layers 417a and 418a are formed in one of the openings, and wiring layers 417b and 418b are formed in the other of the openings. At the intersection, the gate wiring layer 421 and the source wiring layers 422 and 423 are stacked with a gate insulating layer 402, an oxide insulating layer 497a, and a protective insulating layer 498 interposed therebetween.

In the thin film transistor 410 in this embodiment, the gate insulating layer has a stacked structure in which a nitride insulating film and an oxide insulating film are stacked on the side of the gate electrode layer. When forming the openings of the oxide insulating layer, the oxide insulating film of the second gate insulating layer is also selectively removed, exposing a part of the nitride insulating film.

As viewed from above, at least the oxide semiconductor layer 412 is inside the oxide insulating layer 497b and the second gate insulating layer 492b, and the oxide insulating layer 497b and the second gate insulating layer 492b are thin film transistors. It is desirable to cover.

Further, the protective insulating layer 498 formed by using the nitride insulating film is formed to cover the top and side surfaces of the oxide insulating layer 497b and to contact the nitride insulating film of the first gate insulating layer 492a.

Each of the protective insulating layer 498 and the first gate insulating layer 492a each formed using a nitride insulating film, contains as little impurities as possible such ^{as moisture, hydrogen ions, and OH −, and prevents invasion of impurities from the outside.} An inorganic insulating film to block is used, for example, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, and an aluminum oxynitride film obtained by a sputtering method or a plasma CVD method are used.

In this embodiment, as the protective insulating layer 498 formed using the nitride insulating film, a silicon nitride film having a thickness of 100 nm so as to cover the top and side surfaces of the oxide semiconductor layer 412 is provided by RF sputtering. Further, the protective insulating layer 498 contacts the first gate insulating layer 492a formed using a nitride insulating film.

With the structure illustrated in Fig. 10, intrusion of moisture from the outside can be prevented in the manufacturing process after the formation of the protective insulating layer 498 formed using the nitride insulating film. Further, even after the device is completed as a semiconductor device such as a liquid crystal display device, intrusion of moisture from the outside can be prevented for a long time, and thus, the long-term reliability of the device can be improved.

In this embodiment, one thin film transistor is surrounded by a nitride insulating film, but the present invention is not particularly limited, and a plurality of thin film transistors may be surrounded by a nitride insulating film, or a plurality of thin film transistors in the pixel portion are attached to the nitride insulating film. It may be enclosed collectively by. A region in which the protective insulating layer 498 and the first gate insulating layer 492a contact each other is formed to surround at least a pixel portion of the active matrix substrate.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 8)

In Embodiment 8, an example of manufacturing an active matrix light emitting display device using the thin film transistor according to any one of Embodiments 1 to 7 and the light emitting element using electroluminescence will be described.

Light-emitting elements using electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL device, by applying a voltage to a light emitting device, electrons and holes are injected from a pair of electrodes into a layer containing a light emitting organic compound, so that a current flows. By recombining the carriers (electrons and holes), the light-emitting organic compound is excited. The light-emitting organic compound emits light by returning from the excited state to the ground state. Due to this mechanism, this light-emitting element is referred to as a current-excited light-emitting element.

Inorganic EL elements are classified into distributed type inorganic EL elements and thin-film type inorganic EL elements according to their element configuration. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and its light emitting mechanism is a donor acceptor recombination type light emission using a donor level and an acceptor-level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers, the dielectric layers are also sandwiched between electrodes, and the light emitting mechanism of the thin-film inorganic EL element is localized light emission using internal electron transition of metal ions. In this embodiment, an organic EL element is used as a light emitting element for explanation.

11 illustrates an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device.

The configuration and operation of a pixel to which digital time grayscale driving can be applied will be described. In this embodiment, one pixel includes two n-channel transistors each including a channel formation region using an oxide semiconductor layer.

The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light emitting element 6404, and a capacitor 6403. The gate of the switching transistor 6401 is connected to the scan line 6406, the first electrode (one of the source electrode and the drain electrode) of the switching transistor 6401 is connected to the signal line 6405, and the first electrode of the switching transistor 6401 The second electrode (the other one of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The gate of the driving transistor 6402 is connected to the power line 6407 through the capacitor 6403, the first electrode of the driving transistor 6402 is connected to the power line 6407, and the second electrode of the driving transistor 6402 The electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6404. The common electrode 6508 is electrically connected to a common potential line provided on the same substrate.

The second electrode (common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power potential based on the high power potential set by the power supply line 6407. As the low power supply potential, for example, GND, 0 V, or the like may be used. A potential difference between the high-power potential and the low-power potential is applied to the light-emitting element 6404, and a current is supplied to the light-emitting element 6404 so that the light-emitting element 6404 emits light. In view of the above, each potential is set so that the potential difference between the high power source potential and the low power source potential is equal to or greater than the forward threshold voltage of the light emitting element 6404.

Also, the capacitor 6403 may be omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 may be formed between the channel region and the gate electrode.

In the case of the voltage input voltage driving method, a video signal is input to the gate of the driving transistor 6402, so that the driving transistor 6402 is in one of two states that are sufficiently turned on or turned off. That is, the driving transistor 6402 operates in a linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power line 6407 is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel configuration as in Fig. 11 can be used by changing the input signal.

In the case of performing analog grayscale driving, a voltage equal to or higher than (forward voltage of the light emitting element 6404 + Vth of the driving transistor 6402) is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to a voltage at which a desired luminance is obtained, and includes at least a forward threshold voltage. A video signal operating in the saturation region of the driving transistor 6402 is input, so that current may be supplied to the light emitting element 6404. In order to operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. When an analog video signal is used, it is possible to supply a current to the light emitting element 6404 according to the video signal and to perform analog gray scale driving.

The pixel configuration illustrated in FIG. 11 is not limited to this. For example, a switch, a resistive element, a capacitor, a transistor, or a logic circuit may be added to the pixel illustrated in FIG. 11.

Next, configurations of the light emitting device will be described with reference to FIGS. 12A to 12C. In this embodiment, the cross-sectional structure of the pixel will be described taking the n-channel driving TFT as an example. The driving TFTs 7001, 7011, and 7021 used for the semiconductor devices illustrated in FIGS. 12A, 12B and 12C may be fabricated in a manner similar to the thin film transistor described in Embodiment 4, and an oxide semiconductor layer Translucent thin film transistors each including.

In order to extract light from the light emitting element, at least one of the anode and the cathode transmits light. A thin film transistor and a light emitting device are formed on the substrate. Components of a light emitting device, comprising: a top emission structure in which light emission is extracted through a surface facing a substrate; A lower surface injection structure in which light emission is extracted through a surface on the substrate side; And a double-sided injection structure in which light emission is extracted through a surface facing the substrate and a surface on the side of the substrate. The pixel configuration shown in FIG. 11 can be applied to a light emitting device having any of these ejection structures.

A light-emitting element having a lower emission structure will be described with reference to FIG. 12A.

12A is a cross-sectional view of a pixel in the case where the driving TFT 7011 is n-type and light is emitted from the light emitting element 7012 to the first electrode 7013 side. In Fig. 12A, wiring layers 7018a and 7018b electrically connected to the drain electrode layer of the driving TFT 7011 are formed, and a planarization insulating layer 7036 is formed thereon. The wiring layer 7018b contacts the light-transmitting conductive film 7017 at an opening formed in the planarization insulating layer 7036, and electrically connects the driving TFT 7011 and the light-transmitting conductive film 7017. The first electrode 7013 of the light-emitting element 7012 is formed on the light-transmitting conductive film 7017, and the EL layer 7014 and the second electrode 7015 are stacked on the first electrode 7013 in this order.

As the light-transmitting conductive film 7017, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, Alternatively, a transparent conductive film such as a film of indium tin oxide to which silicon oxide is added may be used.

The first electrode 7013 of the light emitting device may be formed using various materials. For example, in the case where the first electrode 7013 is used as a cathode, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, and an alloy containing any of these (Mg: Ag, Al : Li, etc.), or a material having a low work function, such as a rare earth metal such as Yb or Er, is preferably used. In FIG. 12A, the thickness of the first electrode 7013 is a thickness capable of transmitting light (preferably, about 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm is used as the first electrode 7013.

Note that the light-transmitting conductive film and the aluminum film may be laminated and then selectively etched to form the light-transmitting conductive film 7017 and the first electrode 7013. In this case, the etching is preferably performed using the same mask.

The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. In particular, the partition wall 7019 is preferably formed so as to have an opening on the first electrode 7013 using a photosensitive resin material, and the sidewall of the opening is an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7019, the step of forming the resist mask may be omitted.

The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 may include at least a light emitting layer, may be formed as a single layer, or may be stacked in a plurality of layers. When the EL layer 7014 is formed as a plurality of layers, the EL layer 7014 has an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer on the first electrode 7013 functioning as a cathode in this order. It can also be formed by laminating with. It is not necessary to provide all of these layers.

The stacking order is not limited to the above, and on the first electrode 7013 functioning as an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order. However, considering power consumption, the first electrode 7013 functions as a cathode, and an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7013. Preferably, this is because an increase in voltage of the driving circuit portion can be suppressed and power consumption can be reduced.

As the second electrode 7015 formed over the EL layer 7014, various materials can be used. For example, when the second electrode 7015 is used as an anode, a material having a high work function such as ZrN, Ti, W, Ni, Pt, Cr, or a transparent conductive material such as ITO, IZO, or ZnO It is preferable to use. In addition, a light-shielding film 7016, for example, a light-shielding metal, a light-reflecting metal, or the like is provided on the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015, and a Ti film is used as the light shielding film 7016.

The light-emitting element 7012 corresponds to a region in which the EL layer 7014 includes a light-emitting layer sandwiched between the first electrode 7013 and the second electrode 7015. In the case of the element structure illustrated in Fig. 12A, light emitted from the light emitting element 7012 is emitted from the first electrode 7013 side as indicated by an arrow.

In the example shown in Fig. 12A, a light-transmitting conductive film is used as the gate electrode layer, and light emitted from the light-emitting element 7012 passes through the color filter layer 7033 to be emitted through the substrate.

The color filter layer 7033 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7033 is covered with an overcoat layer 7034, and is also covered with a protective insulating layer 7035. Although the overcoat layer 7034 having a thin thickness is shown in FIG. 12A, the overcoat layer 7034 has a function of flattening irregularities due to the color filter layer 7033.

A contact hole formed in the protective insulating layer 7035, the insulating layer 7032, and the insulating layer 7031 and reaching the drain electrode layer is provided so as to overlap the partition wall 7019.

Next, a light emitting device having a double-sided injection structure is described with reference to Fig. 12B.

In Fig. 12B, wiring layers 7028a and 7028b electrically connected to the drain electrode layer of the driving TFT 7021 are formed, and a planarization insulating layer 7046 is formed thereon. The wiring layer 7028b contacts the light-transmitting conductive film 7027 at an opening formed in the planarization insulating layer 7046, and electrically connects the driving TFT 7021 and the light-transmitting conductive film 7027. A first electrode 7023 of the light emitting element 7022 is formed on the light-transmitting conductive film 7027, and an EL layer 7024 and a second electrode 7025 are stacked in this order on the first electrode 7023.

As the light-transmitting conductive film 7027, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, Alternatively, a transparent conductive conductive film such as a film of indium tin oxide to which silicon oxide is added may be used.

The first electrode 7023 may be formed using various materials. For example, in the case where the first electrode 7023 is used as the cathode, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, an alloy containing any of these (Mg: Ag, Al: Li, etc.), or a material having a low work function, such as a rare earth metal such as Yb or Er, is preferably used. In this embodiment, the first electrode 7023 acts as a cathode, and the thickness of the first electrode 7023 is a thickness capable of transmitting light (preferably, about 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm is used as the cathode.

The light-transmitting conductive film and the aluminum film may be stacked, and then selectively etched, so that the light-transmitting conductive film 7027 and the first electrode 7023 may be formed. In this case, it is preferable that the etching can be carried out using the same mask.

The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable that the partition wall 7029 is formed so as to have an opening on the first electrode 7023 using a photosensitive resin material, and the sidewall of the opening is formed as an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7029, the step of forming a resist mask can be omitted.

The EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 may include at least a light emitting layer, may be formed as a single layer, or may be stacked in a plurality of layers. When the EL layer 7024 is formed as a plurality of layers, the EL layer 7024 has an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer on the first electrode 7023 serving as a cathode in this order. It can also be formed by laminating with. Not all of these layers need to be provided.

The stacking order is not limited to the above, and on the first electrode 7023 functioning as an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order. However, considering power consumption, due to low power consumption, the first electrode 7023 functions as a cathode, and an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are on the first electrode 7023. It is preferred that they are stacked in this order.

As the second electrode 7025 formed over the EL layer 7024, various materials can be used. For example, in the case where the second electrode 7025 is used as an anode, it is preferable to use a material having a high work function such as ITO, IZO, or ZnO. In this embodiment, an ITO film containing silicon oxide is used as the second electrode 7025 functioning as an anode.

The light-emitting element 7022 corresponds to a region in which the EL layer 7024 including the light-emitting layer is sandwiched between the first electrode 7023 and the second electrode 7025. In the case of the element structure illustrated in Fig. 12B, light emitted from the light emitting element 7022 is emitted from both the second electrode 7025 side and the first electrode 7023 side as indicated by arrows.

In the example shown in FIG. 12B, a light-transmitting conductive film is used as a gate electrode layer, a light-transmitting thin film is used as a source electrode layer and a drain electrode layer, and light emitted from the light-emitting element 7022 toward the first electrode 7023 is emitted through the substrate. It may pass through the color filter layer 7043.

The color filter layer 7043 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7043 is covered with an overcoat layer 7044, and also with a protective insulating layer 7045.

A contact hole formed in the protective insulating layer 7045, the insulating layer 7042, and the insulating layer 7041 and reaching the drain electrode layer is provided so as to overlap the partition wall 7029.

In the case where a light-emitting element having a double-sided emitting structure is used and full-color display is carried out on both display surfaces, the light from the second electrode 7025 side does not pass through the color filter layer 7043, and thus, another color filter layer is It is preferable that the provided sealing substrate is provided over the second electrode 7025.

Next, a light emitting device having a top emission structure will be described with reference to FIG. 12C.

12C is a cross-sectional view of a pixel in the case where the driving TFT 7001 is an n-channel TFT, and light is emitted from the light emitting element 7002 to the second electrode 7005. In Fig. 12C, wiring layers 7008a and 7008b electrically connected to the drain electrode layer of the driving TFT 7001 are formed, and a planarization insulating layer 7056 is formed thereon. The wiring layer 7008b contacts the first electrode 7003 of the light-emitting element 7002 at an opening formed in the planarization insulating layer 7056, and connects the driving TFT 7001 and the first electrode 7003 of the light-emitting element 7002. Connect electrically. An EL layer 7004 and a second electrode 7005 are stacked on the first electrode 7003 in this order.

In addition, the first electrode 7003 may be formed using various materials. For example, in the case where the first electrode 7003 is used as a cathode, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, an alloy containing any of these (Mg: Ag, Al: Li, etc.), or a material with a low work function, such as a rare earth metal such as Yb or Er, is preferably used.

The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable that the partition wall 7009 is formed of a photosensitive resin material and has an opening on the first electrode 7003 so that the sidewall of the opening becomes an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7009, the step of forming a resist mask may be omitted.

The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 may include at least a light emitting layer, may be formed as a single layer, or a plurality of layers may be stacked. When the EL layer 7004 is formed as a plurality of layers, the EL layer 7004 has an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer on the first electrode 7003 functioning as a cathode in this order. It can also be formed by laminating with. Not all of these layers need to be formed.

The stacking order is not limited to the above, and in the case where the first electrode 7003 functions as an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are in this order on the first electrode 7003. It can also be stacked.

In Fig. 12C, on the laminated film in which a Ti film, an aluminum film, and a Ti film are stacked in this order, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked in this order, and Mg:Ag A laminate of an alloy thin film and ITO is formed.

However, in the case where the driving TFT 7001 is an n-channel TFT, it is preferable that an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7003, which is This is because an increase in voltage in the driving circuit can be suppressed, and power consumption can be reduced.

The second electrode 7005 is formed using a light-transmitting conductive material, for example, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, and indium including titanium oxide. A light-transmitting conductive conductive film such as tin oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

The light-emitting element 7002 corresponds to a region in which the EL layer 7004 including the light-emitting layer is sandwiched between the first electrode 7003 and the second electrode 7005. In the case of the device structure illustrated in Fig. 12C, light emitted from the light-emitting element 7002 is emitted from the side of the second electrode 7005 as indicated by an arrow.

In Fig. 12C, the drain electrode layer of the TFT 7001 is an oxide insulating layer 7051, a protective insulating layer 7052, a planarizing insulating layer 7056, a planarizing insulating layer 7053, and a contact formed on the insulating layer 7055. It is electrically connected to the first electrode 7003 through the hole. The planarizing insulating layers 7036, 7046, 7053, and 7056 are formed using a resin material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to these resin materials, a low dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like can be used. Note that by laminating a plurality of insulating films formed of these materials, planarization insulating layers 7036, 7046, 7053, and 7056 may be formed. The method of forming the planarization insulating layers 7036, 7046, 7053, and 7056 is not particularly limited, and the planarization insulating layers 7036, 7046, 7053, and 7056 depend on the material, sputtering method, spin coating It can be formed by any method such as a method, a dipping method, a spray coating method, a droplet discharge method (ink jet method, screen printing, offset printing, etc.), a roll coating method, a curtain coating method, or a knife coating method.

A partition wall 7009 is provided to insulate the first electrode 7003 from the first electrode of a pixel adjacent to the first electrode 7003. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. In particular, the partition wall 7009 is preferably formed as an inclined surface having a continuous curvature by forming an opening on the first electrode 7003 using a photosensitive resin material. In the case where a photosensitive resin material is used for the partition wall 7009, the step of forming a resist mask may be omitted.

In the structure of FIG. 12C, when full-color display is performed, for example, the light-emitting element 7001 is used as a green light-emitting element, one of the neighboring light-emitting elements is used as a red light-emitting element, and the other is blue. It is used as a light-emitting element. Alternatively, a light-emitting display device capable of displaying a full color may be manufactured using four types of light-emitting elements including white elements in addition to three types of light-emitting elements.

In addition, alternatively, in the structure of FIG. 12C, all of the plurality of light-emitting elements arranged may be white light-emitting elements, and a sealing substrate having a color filter or the like may be arranged on the light-emitting element 7002, thereby providing full-color display. A capable light-emitting display device may be manufactured. A material exhibiting a single color such as white is formed, and by being combined with a color filter or a color conversion layer, full color display can be performed.

The steps and materials for forming the source electrode layer 415a and the drain electrode layer 415b described in Embodiment 1 can be applied to the source electrode layer and the drain electrode layer, respectively. The steps and materials of forming the wiring layers 417a and 418a or wiring layers 417b and 418b described in Embodiment 1 are arbitrary wiring layers 7018a and 7018b, wiring layers 7028a and 7028b, and wiring layers 7008a. And 7008b).

The source electrode layer and the drain electrode layer are preferably as thin as 0.1 nm or more and 50 nm or less, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced. Accordingly, a semiconductor device having low power consumption including a thin film transistor using an oxide semiconductor layer can be provided.

Of course, monochromatic light can be displayed. For example, the lighting system may be formed using white light emission, or an area color light emitting device may be formed using monochromatic light emission.

If necessary, an optical film such as a polarizing film including a circular polarizing plate may be provided.

Although the organic EL element is described as a light-emitting element in this embodiment, an inorganic EL element can also be provided as a light-emitting element.

An example in which a thin film transistor (driving TFT) for controlling driving of the light-emitting element is electrically connected to the light-emitting element is described, but a TFT for current control may be connected between the driving TFT and the light-emitting element.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 9)

In Embodiment 9, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) are described with reference to Figs. 13A and 13B. 13A is a plan view of a panel in which a thin film transistor and a light emitting device formed on a first substrate are sealed by a sealing material between the first substrate and the second substrate, and FIG. 13B is a cross-sectional view taken along line H-I of FIG. 13A.

A sealing material 4505 is provided to surround the pixel portion 4502 formed on the first substrate 4501, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b. Further, a second substrate 4506 is provided over the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b. Accordingly, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b are filled by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is sealed with (4507). In this way, it is preferable that the panel is packaged (enclosed) with a protective film (attachment film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and little degassing so that the panel is not exposed to outside air.

The pixel portion 4502, signal line driving circuits 4503a and 4503b, and scan line driving circuits 4504a and 4504b provided on the first substrate 4501 each include a plurality of thin film transistors. The thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are exemplified in FIG. 13B as an example.

A highly reliable thin film transistor including an oxide semiconductor layer described in Embodiments 1 to 7 can be used as the thin film transistor 4510 in a pixel. The thin film transistor 4509 in the driving circuit has a structure in which a conductive layer is provided so as to overlap with the channel formation region of the oxide semiconductor layer of the thin film transistor described in the first embodiment. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

A conductive layer 4540 is provided over the oxide insulating layer 4452 so as to overlap with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 in the driving circuit. Since the conductive layer 4540 is provided to overlap the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4509 by the BT test can be reduced. The potential of the conductive layer 4540 may be the same as or different from the potential of the gate electrode layer of the thin film transistor 4509, and the conductive layer 4540 may also function as a second gate electrode layer. The potential of the conductive layer 4540 may be GND or 0V, or the conductive layer 4540 may be in a floating state.

An oxide insulating layer 4452 covering the oxide semiconductor layer of the thin film transistor 4510 is formed. The source electrode layer or the drain electrode layer of the thin film transistor 4510 is electrically connected to the wiring layer 4550 at openings formed in the oxide insulating layer 4452 and insulating layer 4551 provided over the thin film transistor. The wiring layer 4550 is formed in contact with the first electrode 4517, and the thin film transistor 4510 is electrically connected to the first electrode 4517 through the wiring layer 4550.

The steps and materials for forming the source electrode layer or the drain electrode layer described in Embodiment 1 can be applied to the source electrode layer and the drain electrode layer. The steps and materials for forming the wiring layers 417a and 418a or the wiring layers 417b and 418b described in Embodiment 1 can be applied to the wiring layer 4550.

Each of the source electrode layer and the drain electrode layer is preferably as thin as 0.1 nm or more and 50 nm or less in thickness, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced. Accordingly, a semiconductor device having low power consumption including a thin film transistor using an oxide semiconductor layer can be provided.

The steps and materials for forming the oxide insulating layer 407 described in Embodiment 1 can be applied to the oxide insulating layer 4452.

A color filter layer 4545 is formed on the insulating layer 4451 so as to overlap the light emitting region of the light emitting element 4511.

Further, in order to reduce the surface irregularities of the color filter layer 4545, the color filter layer 4545 is covered with an overcoat layer 4453 serving as a planarizing insulating film.

Further, an insulating layer 4544 is formed over the overcoat layer 4453. The insulating layer 4544 may be formed in a manner similar to the method of forming the protective insulating layer 408 described in Embodiment 1, or, for example, a silicon nitride film may be formed by a sputtering method.

The first electrode 4517, which is a pixel electrode included in the light emitting element 4511, is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510 through a wiring layer 4550. The light-emitting element 4511 has a stacked structure of the first electrode 4517, the electroluminescent layer 4512, and the second electrode 4513, but there is no limitation on the configuration. The configuration of the light-emitting element 4511 can be appropriately changed depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. The partition wall 4520 is preferably formed using a photosensitive material to have an opening over the first electrode layer 4517 so that the sidewall of the opening is formed as an inclined surface having a continuous curvature.

The electroluminescent layer 4512 may be formed as a single layer or a plurality of stacked layers.

In order to prevent intrusion of oxygen, hydrogen, moisture, carbon dioxide, and the like into the light emitting element 4511, a protective film may be formed on the second electrode layer 4513 and the partition wall 4520. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, various signals and potentials are supplied from the FPCs 4518a and 4518b to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b, or the pixel portion 4502.

The connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light emitting element 4511, and the terminal electrode 4516 includes source and drain electrode layers included in the thin film transistor 4509. It is formed using the same conductive film.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518a through an anisotropic conductive film 4519.

The second substrate positioned in the direction in which light is extracted from the light emitting device 4511 needs to have light-transmitting properties. In this case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used for the second substrate 4506.

As the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curing resin or a heat curing resin may be used. For example, PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) may be used. For example, nitrogen is used as the filler.

In addition, if necessary, a polarizing plate, or a circular polarizing plate (including an elliptically polarizing plate), a retardation plate (λ/4 plate or λ/2 plate), or an optical film such as a color filter may be appropriately provided on the light emitting surface of the light emitting element. May be. In addition, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment may be performed in which reflected light is diffused by irregularities on the surface to reduce glare.

As driving circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film on an individually prepared substrate, signal line driving circuits 4503a and 4503b and scan line driving circuits 4504a and 4504b may be mounted. Alternatively, the signal line driving circuits or only a part thereof, or the scanning line driving circuits or only a part thereof may be separately formed and mounted. The present invention is not limited to the structure illustrated in FIGS. 13A and 13B.

Through the above process, a highly reliable light emitting display device (display panel) as a semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 10)

The appearance and cross section of a liquid crystal display panel as an embodiment of a semiconductor device will be described with reference to FIGS. 14A to 14C. 14A and 14B are plan views of a panel in which the thin film transistors 4010 and 4011 and the liquid crystal element 4013 are sealed with a sealing material 4005 between the first substrate 4001 and the second substrate 4006, respectively. 14B is a cross-sectional view taken along line M-N in FIG. 14A or 14C.

A sealing material 4005 is provided to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driving circuit 4004. Accordingly, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. A signal line driving circuit 4003 formed on an individually prepared substrate using a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on the first substrate 4001 in a region different from the region surrounded by the sealing material 4005.

A method of connecting individually formed driving circuits is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like may be used. 14A illustrates an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 14C illustrates an example of mounting the signal line driving circuit 4003 by the TAB method.

Each of the pixel portion 4002 and the scan line driving circuit 4004 provided on the first substrate 4001 includes a plurality of thin film transistors. 14B illustrates, as an example, a thin film transistor 4010 included in the pixel portion 4002 and a thin film transistor 4011 included in the scan line driving circuit 4004. On the thin film transistors 4010 and 4011, insulating layers 4041, 4042, 4020, and 4021 are provided.

As the thin film transistor 4011 included in the driving circuit and the thin film transistor 4010 included in the pixel, high reliability thin film transistors including the oxide semiconductor layer described in Embodiments 1 to 7 may be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A conductive layer 4040 is provided over the insulating layer 4021 so as to overlap with the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 in the driving circuit. Since the conductive layer 4040 is provided to overlap the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 by the BT test can be reduced. The potential of the conductive layer 4040 may be the same as or different from the potential of the gate electrode layer of the thin film transistor 4011, and the conductive layer 4040 may also function as a second gate electrode layer. The potential of the conductive layer 4040 may be GND or 0V, or the conductive layer 4040 may be in a floating state.

Further, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4010 through a wiring layer 4050. The counter electrode layer 4031 of the liquid crystal element 4013 is provided for the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap each other corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 that function as alignment layers, respectively, and insulating layers 4032 and 4033 are interposed therebetween to form a liquid crystal layer 4008. ) Is sandwiched between the pixel electrode layer 4030 and the counter electrode layer 4031.

A light-transmitting substrate may be used as the first substrate 4001 and the second substrate 4006, and glass, ceramics, or plastic may be used. As the plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Alternatively, spherical spacers may be used. Further, the counter electrode layer 4031 is electrically connected to a common potential line formed on the same substrate as the thin film transistor 4010. Using the common connection, the counter electrode layer 4031 and the common potential line can be electrically connected to each other by conductive particles arranged between a pair of substrates. The conductive particles are included in the sealing material 4005.

Alternatively, a liquid crystal exhibiting a blue phase in which an alignment layer is unnecessary may be used. The blue phase is one of the liquid crystal phases generated immediately before the cholesteric phase changes to the isotropic phase while the temperature of the cholesteric liquid crystal is increased. Since the blue phase only occurs in a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, has optical isotropy that makes alignment treatment unnecessary, and has a small viewing angle dependence.

The present invention can also be applied to transflective liquid crystal displays as well as transmissive liquid crystal displays.

A polarizing plate is provided on the outer surface (viewing side) of the substrate, and the colored layer and the electrode layer used for the display element are provided on the inner surface of the substrate, but the polarizing plate is also provided on the inner surface of the substrate. An example is illustrated. The laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and may be appropriately set depending on the material of the polarizing plate and the colored layer or the conditions of the manufacturing process. Further, a light shielding film functioning as a black matrix may be provided in addition to the display portion.

An insulating layer 4041 is formed to contact the respective oxide semiconductor layers of the thin film transistors 4011 and 4010. The material and method for forming the insulating layer 407 described in Embodiment 1 can be applied to the insulating layer 4041. In this embodiment, a silicon oxide film is formed as the insulating layer 4041 by sputtering using the first embodiment. A protective insulating layer 4042 is formed in contact with the insulating layer 4041. The protective insulating layer 4042 may be formed in a manner similar to the method of forming the protective insulating layer 408 described in Embodiment 1, and, for example, a silicon nitride film may be used. Further, in order to reduce the surface irregularities of the thin film transistor, the protective insulating layer 4042 is covered with an insulating layer 4021 serving as a planarizing insulating film.

The insulating layer 4021 is formed as a planarizing insulating film. As the insulating layer 4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy may be used. In addition to these organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like can be used. The insulating layer 4021 may be formed by laminating a plurality of insulating films formed using these materials.

The method of forming the insulating layer 4021 is not particularly limited, and the insulating layer 4021 depends on the material, and the sputtering method, spin coating method, dipping method, spray coating method, droplet discharge method (e.g. Method, screen printing, offset printing), roll coating method, curtain coating method, knife coating method, and the like. Since the firing step of the insulating layer 4021 functions as an annealing of the semiconductor layer, a semiconductor device can be efficiently fabricated.

Each of the pixel electrode layer 4030 and the counter electrode layer 4031 includes indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium tin. It may be formed using a light-transmitting conductive material such as oxide (hereinafter referred to as ITO), indium zinc oxide, and indium tin oxide to which silicon oxide is added.

A conductive composition including a conductive polymer (also referred to as a conductive polymer) may be used to form the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10000 Ω/□ or less and a light transmittance of 70% or more at a wavelength of 550 nm. In addition, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer may be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more types of these may be provided.

Various signals and potentials are supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, and the pixel portion 4002 through the FPC 4018.

The connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed with source and drain electrode layers of the thin film transistors 4010 and 4011. It is formed using the same conductive film.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

14A to 14C illustrate an example in which the signal line driving circuit 4003 is individually formed and mounted on the first substrate 4001, but the present invention is not limited to this structure. The scanning line driving circuit may be formed individually and then mounted, or a part of the signal line driving circuit or only a part of the scanning line driving circuit may be formed separately and then mounted.

For the liquid crystal display module, TN (twisted nematic) mode, IPS (in-plane-switching) mode, FFS (fringe field switching) mode, MVA (multi-domain vertical alignment) mode, PVA (patterned vertical alignment) mode, ASM A (axially symmetric aligned micro-cell) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, and the like may be used.

In addition, an example of a VA liquid crystal display device is described below.

VA liquid crystal display has a type in which the alignment of liquid crystal molecules of a liquid crystal display panel is controlled. In a VA liquid crystal display, liquid crystal molecules are aligned in a direction perpendicular to the panel surface when no voltage is applied. In this embodiment, in particular, pixels are divided into several regions (subpixels), and molecules are aligned in different directions in their respective regions. This is referred to as a multi-domain or multi-domain design. Hereinafter, a liquid crystal display device having a multi-domain design will be described.

15 and 16 each shows a pixel structure of a VA liquid crystal display panel. 16 is a plan view of the substrate 600. 15 shows a cross-sectional structure along the line Y-Z in FIG. 16. The following description is provided with reference to both drawings.

In this pixel structure, a plurality of pixel electrodes are provided in one pixel, and a TFT is connected to each pixel electrode. The plurality of TFTs are configured to be driven by different gate signals. That is, signals applied to individual pixel electrodes in the multi-domain pixels are controlled independently of each other.

The pixel electrode layer 624 is connected to the source or drain electrode layer 618 of the TFT 628 through the wiring 662 in the contact holes 623 and 660. In addition, the pixel electrode layer 626 is formed of the TFT 629 through the wiring 663 in the contact holes 627 and 661 formed in the insulating layer 622 provided to cover the insulating layer 620 and the insulating layer 620. It is connected to the source or drain electrode layer 619. The gate wiring 602 of the TFT 628 is separated from the gate wiring 603 of the TFT 629 so that different gate signals are supplied. On the other hand, the source or drain electrode layer 619 functioning as a data line is shared by the TFTs 628 and 629. As each of the TFTs 628 and 629, any thin film transistors described in Embodiments 1 to 7 can be suitably used.

The steps and materials for forming the source electrode layer 415a and the drain electrode layer 415b described in Embodiment 1 may be applied to the source or drain electrode layers 616, 618 and 619. The steps and materials for forming the wiring layers 417a and 418a or the wiring layers 417b and 418b described in Embodiment 1 can be applied to any of the wiring layers 662 and 663.

Each of the source electrode layer and the drain electrode layer is preferably as thin as 0.1 nm or more and 50 nm or less, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers is a thin conductive film, the parasitic capacitance formed with the gate electrode layer can be reduced. Accordingly, a semiconductor device having low power consumption including a thin film transistor using an oxide semiconductor layer can be provided.

Further, a capacitor wiring 690 is provided, and a gate insulating layer 606 is laminated thereon, which is used as a dielectric in a storage capacitor using a pixel electrode or a capacitor electrode electrically connected to the pixel electrode.

The shape of the pixel electrode layer 624 is different from the shape of the pixel electrode layer 626, and the pixel electrode layers are separated by a slit 625. The pixel electrode layer 626 is formed to surround the V-shaped pixel electrode layer 624. The timing of voltage application to the pixel electrode layers 624 and 626 is made to be different by the TFTs 628 and 629, so that the orientation of the liquid crystal is controlled. Fig. 18 shows an equivalent circuit of such a pixel configuration. The TFT 628 is connected to the gate wiring 602 and the TFT 629 is connected to the gate wiring 603. By supplying different gate signals to the gate wirings 602 and 603, the operation timing of the TFTs 628 and 629 may be different.

The counter substrate 601 is provided with a light shielding film 632, a second colored film 636, and a counter electrode layer 640. A planarization film 637, also referred to as an overcoat film, is formed between the second colored film 636 and the counter electrode layer 640 to prevent alignment disturbance of the liquid crystal. 17 shows the structure on the opposite substrate side. The counter electrode layer 640 is an electrode shared by a plurality of pixels and provided with slits 641. The slits 641 and the slits 625 on the side of the pixel electrode layers 624 and 626 are alternately arranged in a meshing manner, so that a gradient electric field is effectively generated and the alignment of the liquid crystal can be controlled. Therefore, the orientation of the liquid crystal can be changed depending on the position, so that the viewing angle is widened.

Further, the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap each other to form a first liquid crystal element. Further, the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640 overlap each other to form a second liquid crystal element. Also, a multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided for one pixel is used.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 11)

In Embodiment 11, an example of electronic paper is described as the semiconductor device of the embodiment of the present invention.

19 illustrates an active matrix electronic paper as an example of a semiconductor device to which the embodiment of the present invention is applied. As the thin film transistor 581 used in a semiconductor device, the thin film transistor described in any one of the first to seventh embodiments can be suitably used.

The electronic paper of FIG. 19 is an example of a display device using a twisting ball display system. In the twist ball display system, spherical particles colored in black and white are disposed between a first electrode layer and a second electrode layer, which are electrode layers used for a display element, and a first electrode layer and a second electrode layer are used to control the orientation of the spherical particles. It refers to a method in which a potential difference is generated between electrode layers and display is performed.

The thin film transistor 581 provided on the substrate 580 is a bottom gate thin film transistor, and its source or drain electrode layer is connected to the wiring layers 589a and 589b at the openings formed in the oxide insulating layer 583 and the protective insulating layer 584. It is electrically connected. The wiring layer 589b is provided in contact with the first electrode layer 587 at an opening formed in the insulating layer 585 provided over the wiring layer 589b. The thin film transistor 581 is electrically connected to the first electrode layer 587 through wiring layers 589a and 589b.

The steps and materials for forming the source electrode layer 415a and the drain electrode layer 415b described in Embodiment 1 may be applied to the source or drain electrode layer. The steps and materials of forming the wiring layers 417a and 418a or the wiring layers 417b and 418b described in Embodiment 1 can be applied to any of the wiring layers 589a and 589b.

Each of the source electrode layer and the drain electrode layer is preferably as thin as 0.1 nm or more and 50 nm or less, and a thinner film than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced. Accordingly, a semiconductor device having low power consumption including a thin film transistor using an oxide semiconductor device can be provided.

Spherical particles 589 are provided between the first electrode layer 587 and the second electrode layer 588. Each of the spherical particles includes a black region 590a, a white region 590b, and a cavity 594 filled with a liquid around the black region 590a and the white region 590b. The periphery of the spherical particles 589 is filled with a filler 595 such as a resin (see Fig. 19). In this embodiment, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 provided for the counter electrode 596 corresponds to the common electrode.

In addition, instead of a twist ball, an electrophoretic element can also be used. Microcapsules having a diameter of approximately 10 µm or more and 200 µm or less are used, enclosed in a transparent liquid, positively charged white fine particles and negatively charged black fine particles. In the microcapsules provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, so that white or black may be displayed. A display element using this principle is an electrophoretic display element, and is generally referred to as electronic paper. The electrophoretic display element has a higher reflectivity than the liquid crystal display element, so that an auxiliary light is unnecessary, power consumption is low, and the display portion can be recognized in a dim place. Also, even when power is not supplied to the display unit, the image displayed once can be maintained. Accordingly, even if a semiconductor device having a display function (also referred to as a display device or a semiconductor device having a display device) is far from the radio wave source, the displayed image can be stored.

Through this process, electronic paper that is highly reliable as a semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 12)

The semiconductor device disclosed in the present specification can be applied to various electronic devices (including entertainment devices). Examples of electronic devices are a television device (also referred to as a television or television receiver), a monitor such as a computer, a camera such as a digital camera or digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone, a mobile phone device). ), portable game consoles, portable information terminals, audio playback devices, and large game machines such as pachinko machines.

20A illustrates an example of the mobile phone 1100. The mobile phone 1100 is provided with a display unit 1102, an operation button 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like built in a housing 1101.

The display unit 1102 of the mobile phone 1100 illustrated in FIG. 20A is touched with a finger or the like, whereby information can be input to the mobile phone 1100. Further, an operation such as making a phone call or creating an e-mail can be performed by touching the display portion 1102 with a finger or the like.

Mainly, there are three screen modes of the display unit 1102. The first mode is a display mode mainly for displaying images. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-input mode in which two modes of a display mode and an input mode are combined.

For example, in the case of making a phone call or writing an e-mail, a text input mode in which text is mainly input is selected for the display unit 1102 so that text displayed on the screen may be input. In this case, it is preferable to display a keyboard or a number button on almost most of the screen of the display unit 1102.

When a detection device including a sensor for detecting a tilt such as a gyroscope or an acceleration sensor is provided in the mobile phone 1100, the display on the screen of the display unit 1102 is the direction of the mobile phone 1100 (the mobile phone 1100 ) Can be switched automatically by determining whether it is placed horizontally or vertically for landscape mode or portrait mode.

Screen modes are switched by touching the display portion 1102 or manipulating the operation button 1103 of the housing 1101. Alternatively, the screen modes may be switched depending on the type of image displayed on the display unit 1102. For example, when the signal of an image displayed on the display unit is a signal of moving picture data, the screen mode is switched to the display mode, and when the signal is the signal of text data, the screen mode is switched to the input mode.

In addition, in the input mode, while the signal detected by the optical sensor of the display unit 1102 is detected, when the input by the touch of the display unit 1102 is not performed for a certain period, the screen mode is changed from the input mode to the display mode. It can also be controlled to be switched.

The display portion 1102 may also function as an image sensor. For example, when the display unit 1102 is touched with a palm or a finger, a palm print, a fingerprint, or the like is captured, so that personal identification can be performed. In addition, by providing a backlight or a sensing light source emitting near-infrared light in the display unit, finger veins, palm veins, and the like can be captured.

In the display portion 1102, a plurality of thin film transistors described in Embodiment 1 are provided as switching elements of pixels.

20B illustrates another example of a mobile phone. The portable information terminal of which an example is illustrated in FIG. 20B may have a plurality of functions. For example, in addition to the telephone function, such a portable information terminal can have a function of processing various data by embedding a computer.

The portable information terminal illustrated in FIG. 20B includes a housing 1800 and a housing 1801. The housing 1800 is provided with a display panel 1802, a speaker 1803, a microphone 1804, a pointing device 1806, a camera lens 1807, an external connection terminal 1808, and the like. In the housing 1801, a keyboard 1810, an external memory slot 1811, and the like are provided. In addition, an antenna is built into the housing 1801.

A touch panel is provided on the display panel 1802. A plurality of operation keys 1805 displayed as images are illustrated by dotted lines in Fig. 20B.

Further, in addition to the above configuration, a non-contact IC chip, a small memory device, or the like may be incorporated.

The light emitting device of the present invention can be used for the display panel 1802, and the direction of the display is appropriately changed depending on the application mode. Further, the display device is provided with a camera lens 1807 on the same surface as the display panel 1802 to enable video telephony. The speaker 1803 and the microphone 1804 may be used not only for voice calls, but also for video calls, recording, and playback. In addition, the housings 1800 and 1801 in the unfolded state as illustrated in FIG. 20B can be slid, so that one overlaps the other, and thus, the size of the portable information terminal can be reduced, which is Make it suitable for carrying the terminal.

The external connection terminal 1808 can be connected to various types of cables such as an AC adapter and a USB cable, which enables charging and data communication with a personal computer or the like. Further, the recording medium can be inserted into the external memory slot 1811, so that a large amount of data can be stored and moved.

Further, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

21A illustrates an example of a television set 9600. In the television set 9600, a display portion 9603 is built into the housing 9601. The display unit 9603 may display images. In this embodiment, the housing 9601 is supported by a stand 9605.

The television set 9600 can be operated by an operation switch in the housing 9601 or a separate remote controller 9610. The channels and the volume can be controlled by an operation key 9609 provided for the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Further, the remote controller 9610 may be provided with a display unit 9607 that displays information output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. Using the receiver, general television broadcasts can be received. Further, when the display device is connected to the communication network by wire or wirelessly via a modem, information communication may be performed in one direction (from a sender to a receiver) or in two directions (between a sender and a receiver, or between a receiver).

In the display portion 9603, a plurality of thin film transistors described in Embodiment 1 are provided as switching elements of pixels.

21B illustrates an example of a digital photo frame. For example, in the digital photo frame 9700, the display portion 9703 is built into the housing 9701. The display unit 9703 may display various images. For example, the display unit 9703 can display image data captured by a digital camera or the like, and can function as a conventional photo frame.

In the display portion 9703, a plurality of thin film transistors described in Embodiment 1 are provided as switching elements of pixels.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection terminal (a USB terminal, a terminal that can be connected to various cables such as a USB cable, etc.), a recording medium insertion portion, and the like. These components may be provided on the side on which the display portion is provided, but it is preferable to provide them on the side or back side for the design of the digital photo frame 9700. For example, a memory storing data of an image taken with a digital camera is inserted into the recording medium insertion portion of a digital photo frame, so that the image data can be transferred, and then displayed on the display portion 9703. .

The digital photo frame 9700 may be configured to wirelessly transmit and receive data. A configuration that is transmitted wirelessly so that desired image data is displayed may be used.

Figure 22 is a portable entertainment device comprising two housings, the housing 9881 and the housing 991 are connected by a connection portion 9893 to which they can be folded. The display portion 9882 and the display portion 9883 are incorporated in the housing 9881 and the housing 991, respectively.

In the display portion 9883, a plurality of thin film transistors described in Embodiment 1 are provided as switching elements of pixels.

In addition, the portable entertainment device illustrated in FIG. 22 includes a speaker unit 9884, a recording medium insertion unit 9886, an LED lamp 9890, an input means (operation key 9885, a connection terminal 9887, a sensor 9888) (Force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetic, temperature, chemical, negative, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, hardness , Vibration, fragrance, or infrared measurement), and a microphone 9889. Of course, the configuration of the portable entertainment device is not limited to the above, and at least other configurations provided with the thin film transistor disclosed herein are The portable entertainment device may appropriately include other accessory equipment. The portable entertainment device illustrated in Fig. 22 reads programs or data stored in a recording medium and displays it on a display unit, and other portable entertainment devices and wireless devices can be used. It has a function of sharing information through communication. The function of the portable entertainment device illustrated in Fig. 22 is not limited to the above, and various functions may be provided.

24 is an example in which the light-emitting device formed according to the above embodiment is used as the indoor lighting device 3001. Since the area of the light emitting device described in Embodiment 4 or 5 may be increased, the light emitting device can be used as a lighting device having a large area. Further, the light emitting device illustrated in the above embodiment can be used as the desk lamp 3000. Note that luminaires include ceiling luminaires, desk lamps, wall-mounted luminaires, in-vehicle interior lighting, and guidance lights.

As described above, the thin film transistor described in any one of Embodiments 1 to 7 may be provided on display panels of such various electronic devices. An electronic device with high reliability can be provided by using a thin film transistor as a switching element of a display panel.

(Embodiment 13)

The semiconductor device disclosed in this specification can be applied as electronic paper. Electronic paper can be used for electronic devices in various fields as long as data can be displayed. For example, electronic paper may be applied to the display of various cards such as e-book readers (e-books), posters, advertisements in vehicles such as trains, or credit cards. An example of an electronic device is illustrated in FIG. 23.

23 illustrates an electronic book 2700. For example, the e-book 2700 includes two housings (a housing 2701 and a housing 2703). The housing 2701 and the housing 2703 are coupled to the hinge 2711, so that the e-book 2700 can be opened and closed by the hinge 2711 as an axis. With this structure, the e-book 2700 can operate like a paper book.

The display unit 2705 and the display unit 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display unit 2705 and the display unit 2707 may display one image or other images. In a configuration in which the display units display different images, for example, the right display unit (display unit 2705 in Fig. 23) can display text, and the left display unit (display unit 2707 in Fig. 23) can display images. I can.

23 illustrates an example in which an operation unit or the like is provided in the housing 2701. For example, the housing 2701 is provided with a power switch 2721, an operation key 2923, a speaker 2725, and the like. With the operation keys 2722, pages can be turned. Note that a keyboard, pointing device, etc. may also be provided on the surface of the housing on which the display portion is provided. In addition, external connection terminals (earphone terminals, USB terminals, terminals that can be connected to various cables such as AC adapters and USB cables, etc.), recording medium insertion portions, and the like may be provided on the rear or side surfaces of the housing. In addition, the electronic book 2700 may have a function such as an electronic dictionary.

The electronic book 2700 may have a configuration capable of transmitting and receiving data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

This embodiment can be implemented in appropriate combination with other embodiments.

This application is based on Japanese Patent Application No. 2009-214485 filed with the Japan Patent Office on September 16, 2009, the entire contents of which are incorporated herein by reference.

81: multi-gradation mask, 81a: gray-tone mask, 81b: half-tone mask, 83: light-transmitting substrate, 84: light-shielding portion, 85: diffraction grating, 86: light transmittance, 87: semi-transmissive portion, 88: light-shielding portion, 89: light transmittance, 400: substrate, 402: gate insulating layer, 403: protective insulating layer, 407: oxide insulating layer, 408: protective insulating layer, 409: planarizing insulating layer, 410: thin film transistor, 411: gate electrode layer, 412 : Oxide semiconductor layer, 413: channel formation region, 421: gate wiring layer, 422: source wiring layer, 423: source wiring layer, 427: pixel electrode layer, 430: thin film transistor, 431: gate electrode layer, 432: oxide semiconductor layer, 433: channel Reference numerals 437: wiring layer, 438: wiring layer, 440: oxide semiconductor film, 441: oxide semiconductor layer, 450: thin film transistor, 451: gate electrode layer, 452: oxide semiconductor layer, 453: channel formation region, 456: oxide insulating layer , 459: oxide insulating layer, 460: resist mask, 461: oxide semiconductor layer, 462: metal conductive layer, 465: oxide semiconductor film, 466: metal conductive film, 469: thin film transistor, 471: gate electrode layer, 472: oxide semiconductor Layer, 480: thin film transistor, 481: gate electrode layer, 483: channel formation region, 484a: high resistance source region, 484b: high resistance drain region, 485a: source electrode layer, 485b: drain electrode layer, 487a: wiring layer, 487b: wiring layer, 488a: wiring layer, 488b: wiring layer, 492a: gate insulating layer, 492b: gate insulating layer, 497a: oxide insulating layer, 497b: oxide insulating layer, 498: protective insulating layer, 580: substrate, 581: thin film transistor, 583: oxide Insulating layer, 584: protective insulating layer, 585: insulating layer, 587: first electrode layer, 588: second electrode layer, 589a: wiring layer, 589b: wiring layer, 590a: black region, 590b: white region, 594: cavity, 595: filler, 596: opposing substrate, 600: substrate, 601: opposing substrate, 602: gate wiring, 603: gate wiring, 606: gate insulating layer, 616: drain electrode layer, 618: drain electrode layer, 619: drain electrode layer, 620: insulating layer, 622: insulating layer, 623: contact hole, 624: pixel electrode layer, 625: slit, 626: pixel electrode layer, 627: contact hole, 628: TFT, 629: TFT, 632: light-shielding film, 636: colored film, 637: planarization film, 640: counter electrode layer, 641: slit, 650: liquid crystal layer, 660: contact hole, 661: contact hole , 662: wiring layer, 663: wiring layer, 690: capacity wiring, 1100: mobile phone, 1101: housing, 1102: display, 1103: operation button, 1104: external connection port, 1105: speaker, 1106: microphone, 1800: housing, 1801: housing, 1802: display panel, 1803: speaker, 1804: microphone, 1805: operation keys, 1806: pointing device, 1807: camera lens, 1808: external connection terminal, 1810: keyboard, 1811: external memory slot, 2700: E-book, 2701: housing, 2703: housing, 2705: display, 2707: display, 2711: hinge, 2721: power switch, 2723: operation key, 2725: speaker, 3000: desk lamp, 3001: lighting device, 4001: article 1 substrate, 4002: pixel portion, 4003: signal line driving circuit, 4004: scanning line driving circuit, 4005: sealing material, 4006: second substrate, 4008: liquid crystal layer, 4010: thin film transistor, 4011: thin film transistor, 4013: liquid crystal element, 4015: connection terminal electrode, 4016: single Self electrode, 4018: FPC, 4019: anisotropic conductive film, 4021: insulating layer, 4030: pixel electrode layer, 4031: counter electrode layer, 4032: insulating layer, 4040: conductive layer, 4041: insulating layer, 4042: protective insulating layer, 4050 : Wiring layer, 4501: first substrate, 4502: pixel portion, 4503a: signal line driving circuit, 4503b: signal line driving circuit, 4504a: scanning line driving circuit, 4504b: scanning line driving circuit, 4505: sealing material, 4506: second substrate, 4507: Filling material, 4509: thin film transistor, 4510: thin film transistor, 4511: light emitting element, 4512: electroluminescent layer, 4513: second electrode, 4515: connection terminal electrode, 4516: terminal electrode, 4517: first electrode, 4518a: FPC, 4518b : FPC, 4519: anisotropic conductive film, 4520: partition wall, 4540: conductive layer, 4542: oxide insulating layer, 4543: overcoat layer, 4544: insulating layer, 4545: color filter layer, 4550: wiring layer, 4551: insulating layer, 6400: Pixel, 6401: switching transistor, 6402: driving transistor, 6403: capacitance, 6404: light emitting element, 6405: signal line, 6406: scanning line, 6407: power line, 6408: common electrode, 7001: driving TFT, 7002: light emitting element, 7003 : First electrode, 7004: EL layer, 7005: second electrode, 7008a: wiring layer, 7008b: wiring layer, 7009: partition wall, 7011: driving TFT, 7012: light emitting element, 7013: first electrode, 7014: EL layer, 7015 : Second electrode, 7016: light-shielding film, 7017: conductive film, 7018a: wiring layer, 7018b: wiring layer, 7019: partition wall, 7021: driving TFT, 7022: light emitting element, 7023: first electrode, 7024: EL layer, 7025: agent 2 electrode, 7027: conductive film, 702 8a: wiring layer, 7028b: wiring layer, 7029: partition wall, 7031: insulating layer, 7032: insulating layer, 7033: color filter layer, 7034: overcoat layer, 7035: protective insulating layer, 7036: planarizing insulating layer, 7042: insulating layer, 7043 : Color filter layer, 7044: overcoat layer, 7045: protective insulation layer, 7046: planarization insulation layer, 7051: oxide insulation layer, 7052: protection insulation layer, 7053: planarization insulation layer, 7055: insulation layer, 7056: planarization insulation layer, 9600: TV set, 9601: housing, 9603: display, 9605: stand, 9607: display, 9609: operation keys, 9610: remote controller, 9700: digital photo frame, 9701: housing, 9703: display, 9881: housing, 9882 : Display part, 9883: display part, 9884: speaker part, 9885: operation key, 9886: recording medium insertion part, 9887: connection terminal, 9888: sensor, 9889: microphone, 9890: LED lamp, 9891: housing, 9893: connection part

Claims (9)

In a semiconductor device:
A first wiring layer over the substrate;
A nitride insulating layer over the first wiring layer;
An oxide insulating layer over the nitride insulating layer;
An oxide semiconductor layer over the oxide insulating layer, wherein the oxide semiconductor layer includes a channel formation region;
A first insulating layer over the oxide semiconductor layer;
A second wiring layer over the first insulating layer;
A second insulating layer over the second wiring layer;
A color filter layer over the second insulating layer;
A third insulating layer over the color filter layer; And
Including an electrode on the third insulating layer,
The channel formation region of the oxide semiconductor layer includes a crystal part,
The crystal part contains indium, gallium, and zinc,
The electrode overlaps with the first wiring layer, the nitride insulating layer, the oxide insulating layer, the oxide semiconductor layer, the second insulating layer, the color filter layer, and the third insulating layer,
The first wiring layer is a laminated structure and includes molybdenum, titanium, and copper,
The second wiring layer is a laminated structure and includes molybdenum, titanium, and copper,
The nitride insulating layer, the oxide insulating layer, and the first insulating layer are provided between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer. In a semiconductor device:
A first wiring layer on a substrate and in direct contact with the substrate;
A nitride insulating layer on the first wiring layer and in direct contact with the first wiring layer;
An oxide insulating layer over the nitride insulating layer and in direct contact with the nitride insulating layer;
An oxide semiconductor layer over the oxide insulating layer and in direct contact with the oxide insulating layer, the oxide semiconductor layer including a channel formation region;
A first insulating layer over the oxide semiconductor layer and in direct contact with the oxide semiconductor layer;
A second wiring layer over the first insulating layer and in direct contact with the first insulating layer;
A second insulating layer over the second wiring layer and in direct contact with the second wiring layer;
A color filter layer over the second insulating layer and in direct contact with the second insulating layer;
A third insulating layer on the color filter layer and in direct contact with the color filter layer; And
And an electrode on the third insulating layer and in direct contact with the third insulating layer,
The channel formation region of the oxide semiconductor layer includes a crystal part,
The crystal part contains indium, gallium, and zinc,
The electrode overlaps with the first wiring layer, the nitride insulating layer, the oxide insulating layer, the oxide semiconductor layer, the second insulating layer, the color filter layer, and the third insulating layer,
The first wiring layer is a laminated structure and includes molybdenum, titanium, and copper,
The second wiring layer is a laminated structure and includes molybdenum, titanium, and copper,
The nitride insulating layer, the oxide insulating layer, and the first insulating layer are provided between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer. The method according to claim 1 or 2,
The semiconductor device, wherein the carrier concentration in the channel formation region is ^{less than 1×10 18} /cm ^3. The method according to claim 1 or 2,
The semiconductor device, wherein the first insulating layer comprises silicon oxide. The method according to claim 1 or 2,
The semiconductor device, wherein the crystal portion has a particle diameter of 1 nm or more and 20 nm or less. The method according to claim 1 or 2,
The semiconductor device, wherein the crystal part is mixed with an amorphous structure. The method according to claim 1 or 2,
The semiconductor device, wherein the oxide semiconductor layer includes a concave portion. The method according to claim 1 or 2,
The semiconductor device, wherein the channel formation region of the oxide semiconductor layer is intrinsic. The method according to claim 1 or 2,
The semiconductor device, wherein the oxide semiconductor layer has a crystallinity of 80% or more.

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