JP2585118B2 - A method for manufacturing a thin film transistor - Google Patents

A method for manufacturing a thin film transistor

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JP2585118B2
JP2585118B2 JP2026824A JP2682490A JP2585118B2 JP 2585118 B2 JP2585118 B2 JP 2585118B2 JP 2026824 A JP2026824 A JP 2026824A JP 2682490 A JP2682490 A JP 2682490A JP 2585118 B2 JP2585118 B2 JP 2585118B2
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gate insulating
insulating film
thin film
film transistor
manufacturing
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JPH03231472A (en
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宏勇 張
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株式会社半導体エネルギー研究所
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【発明の詳細な説明】 「産業上の利用分野」 本発明は、液晶ディスプレー,イメージセンサー等に適用可能な薄膜トランジスタの作製方法に関する。 Description of the Invention The present "relates" invention, a liquid crystal display, relates to a method for manufacturing applicable TFT to the image sensor or the like.

「従来の技術」 最近、化学的気相法等によって、作製された非単結晶半導体薄膜を利用した薄膜トランジスタが注目されている。 "Background of the Invention" Recently, by chemical vapor phase method, a thin film transistor using a non-single-crystal semiconductor thin film produced has attracted attention.

この薄膜トランジスタは、絶縁性基板上に前述の如く化学的気相法等を用いて形成されるので、その作製雰囲気温度が最高で450℃程度と低温で形成でき、安価なソーダガラス,ホウケイ酸ガラス等を基板として用いることができる。 This thin film transistor, since it is formed by using the above as a chemical vapor phase method on an insulating substrate, can be formed in the order of manufacturing the ambient temperature is 450 ° C. at maximum and a low temperature, inexpensive soda glass, borosilicate glass or the like can be used as the substrate.

この薄膜トランジスタは電界効果型であり、いわゆる The thin film transistor is a field effect, the so-called
MOSFETと同様の機能を有しているが、前述の如く安価な絶縁性基板上に低温で形成でき、さらにその作製する最大面積は薄膜半導体を形成する装置の寸法にのみ限定されるもので、容易に大面積基板上にトランジスタを作製できるという利点を持っていた。 Has the MOSFET and similar functions, can be formed at low temperature on an inexpensive insulating substrate as described above, further largest area thereof to produce to be limited only to the dimensions of the apparatus for forming a thin film semiconductor, had the advantage of easily transistors on a large area substrate can be manufactured. このため多量の画素を持つマトリクス構造の液晶ディスプレーのスイッチング素子や一次元又は二次元のイメージセンサ等のスイッチング素子として極めて有望である。 Therefore it is very promising as a switching element of an image sensor such as a switching element and a one-dimensional or two-dimensional liquid crystal display of the matrix structure having a large amount of pixels.

また、この薄膜トランジスタを作製するにはすでに確立された技術であるフォトリソグラフィーが応用可能で、いわゆる微細加工が可能であり、IC等と同様に集積化を図ることも可能であった。 Also, possible photolithography fabricating the thin film transistor is already established technology applications are possible so-called micromachining, it was also possible to achieve an IC or the like as well as integration.

この従来より知られたTFTの代表的な構造を第2図に概略的に示す。 The representative structure of the conventionally known TFT is shown schematically in Figure 2.

(20)はガラスよりなる絶縁性基板であり、(21)は非単結晶半導体よりなる薄膜半導体、(22),(23)はソースドレイン領域で、(24),(25)はソースドレイン電極、(26)はゲイト絶縁膜で(27)はゲイト電極であります。 (20) is an insulating substrate made of glass, (21) a thin film semiconductor made of non-single-crystal semiconductor, (22), (23) in the source drain regions, (24), (25) a source drain electrode , (26) a gate insulating film (27) is located in the gate electrode.

このように構成された薄膜トランジスタはゲイト電極(27)に電圧を加えることにより、ソースドレイン(2 By applying a voltage to the thus configured thin-film transistor gate electrode (27), the source-drain (2
2),(23)間に流れる電流を調整するものであります。 2), it is proposed to adjust the current flowing between (23).

このような薄膜トランジスタに用いられるゲイト酸化膜は、半導体材料の直接熱酸化法,減圧または常圧下での熱CVD法等によって作製されていた。 Such a thin film transistor gate oxide film used in the direct thermal oxidation of the semiconductor material, have been produced by the thermal CVD method or the like in vacuum or atmospheric pressure.

この薄膜トランジスタの素子特性は、チャネルが形成される部分の半導体膜の膜質と、ゲイト絶縁膜の特性に大きく左右される。 Device characteristics of this thin film transistor, and the film quality of the semiconductor film in a portion where a channel is formed, highly dependent on the characteristics of the gate insulating film.

特に良好な膜質のゲイト絶縁膜を作製することが強く望まれていた。 It has been strongly desired to produce a particularly good film quality of the gate insulating film.

前述の方法により、作製されたゲイト絶縁膜を薄膜トランジスタに用いて良好な素子特性を得るためには、ゲイト絶縁膜の作製温度を600℃付近に設定する必要があり、そのため結晶化ガラス,石英ガラス等の非常に高価な基板材料を使用しなければならなかった。 By the method described above, the fabricated gate insulating film in order to obtain good element characteristics using the thin film transistor, it is necessary to set the fabrication temperature of the gate insulating film in the vicinity of 600 ° C., therefore crystallized glass, quartz glass We had to use very expensive substrate materials and the like. すなわち、 That is,
450℃程度の低温プロセスで作製でき、その結果安価な基板材料(ゾーダガラス等)を使用できる薄膜トランジスタの特徴をなくすものであった。 450 ° C. of about can be manufactured at a low temperature process, were those to eliminate the characteristics of the resulting thin film transistor which can use inexpensive substrate materials (Zodagarasu etc.).

また低温にてゲイト絶縁物を作製する方法として、プラズマCVD法やスパッタリング法が知られているが、いずれの方法においても、出発材料中に含まれ、かつ反応中にも存在する原子(例えばAr,Cl,F,N等)が、ゲイト絶縁膜中に多数取り込み膜中の固定電荷発生の原因となる。 As a method of producing a gate insulator at low temperatures, but the plasma CVD method or a sputtering method are known, in any of the methods contained in the starting material and atoms present in the reaction (for example, Ar , Cl, F, N, etc.), causing a large number of busy film fixed charge generation into the gate insulating film. さらに、反応中に存在する原子のイオン種が、薄膜トランジスタの活性層表面に衝突し、ゲイト絶縁膜と活性層との界面近傍に界面準位を形成し、いずれの場合も良好な薄膜トランジスタの特性を得るに至っていない。 Further, ion species of atoms present in the reaction is, collides with the surface of the active layer of the thin film transistor, the interface state is formed near the interface between the gate insulating film and the active layer, the characteristics of a good thin film transistors in any case not yet been obtained.

さらに、光CVD法によってゲイト絶縁膜を作製することが試みられており、熱酸化膜とほぼ同様レベルの2× Furthermore, a it is attempted to produce a gate insulating film by optical CVD method, 2 × substantially similar level as the thermal oxide film
10 10 eV -1 cm -2程度の界面準位密度が得られているが、膜作製に必要とする時間が長く(成膜速度が非常に遅い) Although 10 10 eV -1 cm -2 order of the interface state density is obtained, a long time required for film formation (film formation rate is very slow)
工業的な応用には不向きであった。 It was not suitable for industrial application.

「本発明の目的」 本発明は、従来の問題点を解決する方法であり、良好な特性の薄膜トランジスタを低温プロセスで作製する方法を提供するものであります。 The present invention, "object of the present invention" is a method to solve the conventional problems, and provides a method for manufacturing the thin film transistor with excellent characteristics at low temperature process.

「発明の構成」 本発明の構成は、薄膜トランジスタを作製する工程において、ゲイト絶縁膜の作製をスパッタリング法にて行ない、さらにスパッタリングに用いる気体における不活性ガスの割合を50%以下、すなわち酸化性ガスの方が不活性ガスより多い雰囲気下でスパッタリングを行ないゲイト絶縁膜を作製することを特徴とするものであります。 Configuration of the present invention, "Configuration of the invention", in the step of manufacturing the thin film transistor performs at the gate insulating film sputtering fabrication of, 50% or less the ratio of the inert gas in the gas to be used for further sputtering, i.e. oxidizing gas it is characterized in that the direction of to produce a gate insulating film subjected to sputtering under a greater atmosphere than inert gas.

本発明に用いられるスパッタリング法としては、RFスパッタ,直流スパッタ等いずれの方法も使用できるが、 The sputtering method used in the present invention, RF sputtering, but may be used any method DC sputtering,
スパッタリングターゲットが導電率の悪い酸化物,例えばSiO 2等の場合、安定した放電を持続するためにRFマグネトロンスパッタ法を用いることが好ましい。 Bad oxides sputtering target conductivity, for example, in the case of SiO 2 or the like, it is preferable to use an RF magnetron sputtering method to sustain a stable discharge.

また酸化性気体としては酸素,オゾン,亜酸化窒素等を挙げることができるが、特にオゾンや酸素を使用した場合、ゲイト絶縁膜中に取り込まれる不用な原子が存在しないので、非常に良好なゲイト絶縁膜を得ることができた。 The oxygen as the oxidizing gas, ozone, there may be mentioned nitrous oxide, etc., especially when using ozone or oxygen, so that unnecessary atoms incorporated into the gate insulating film is not present, very good gate It could be obtained insulating film.

またオゾンは、Oラジカルに分解されやすく、単位体積当りのOラジカル発生量が多く、成膜速度向上に寄与することができる。 The ozone is easily decomposed into O radical, can be O radical generation amount per unit volume is large, contributing to the deposition rate increased.

従来より行なわれてきたスパッタリング法によるゲイト絶縁膜の作製においては、不活性ガスであるArが酸素ガスより多く、通常は酸素が0〜10体積%程度で作製されていた。 In the production of the gate insulating film by has been done conventionally sputtering, Ar is an inert gas is more than oxygen gas, usually oxygen had been prepared at about 0-10% by volume. すなわち、従来から行なわれていたスパッタは、Arがターゲット材料をたたき成膜することが当然の如く考えられていた。 That is, sputtering has been performed conventionally, Ar were it is considered as a matter of course for forming striking target material. これはAr等の不活性ガスがターゲット材料をたたき出す確率(スパッタリングイールド) This probability of an inert gas such as Ar is knock the target material (sputtering yield)
が高い為であった。 Was because high. 本発明者らは、スパッタリング法によって作製されたゲイト絶縁膜の特性について鋭意検討した結果、ゲイト絶縁膜の性能を示す活性層とゲイト絶縁膜界面の界面準位、及びゲイト絶縁膜中の固定電荷の数を反映するフラットバンド電圧の理想値よりのズレが、スパッタリング時のArガスの割合に大きく依存することが判明した。 The present inventors have intensively studied a result the characteristics of the gate insulating film formed by sputtering, the interface state of the active layer and the gate insulating film interface showing the performance of the gate insulating film, and fixed charges in the gate insulating film deviation than the ideal value of the flat band voltage that reflects the number of, it has been found to depend largely on the ratio of the Ar gas during sputtering.

第3図に、気体に占めるArガスの割合と界面準位の関係を示す。 In Figure 3, it shows the relationship between the ratio and the interface state of the Ar gas to total gas. Arガス100%に比べ、Arガスの量を酸化性ガス(第3図では酸素)の量より少なく、50%以下とすると界面準位密度が約1/10程度に減っていることがわかり、Arガスの割合が20%以下の場合は、ほぼ一定の低い界面準位の値となっている。 Compared to Ar gas of 100% less than the amount of (oxygen in FIG. 3) the amount of the oxidizing gas of Ar gas, notice that the interface state density when 50% or less are reduced to about 1/10, If the proportion of Ar gas is 20% or less, and has a value of substantially constant, low interface state.

第4図にスパッタリング時の気体の占めるArガスの割合とフラットバンド電圧のズレ量との関係を示す。 It shows the relationship between the amount of deviation percentage and the flat band voltage of the Ar gas occupied by gas during sputtering in Figure 4.

フラットバンド電圧の理想電圧からのズレは、Arガスの割合に大きく依存し、Arガスの割合が20%以下の場合、ほぼ理想電圧に近い値となっている。 Deviation from the ideal voltage flat band voltage largely depends on the ratio of the Ar gas, when the ratio of Ar gas is 20% or less, and has a value close to approximately ideal voltage.

これらのことより、スパッタリングにより成膜時に反応雰囲気下に存在する活性化されたAr原子が、ゲイト絶縁膜の膜質に影響を与えており、できるだけAr原子の存在を減らしてスパッタリング成膜することが望ましいことが判明した。 From these things, the activated Ar atoms present under reaction atmosphere during deposition by sputtering, and affects the quality of the gate insulating film, be sputtering by reducing the presence of possible Ar atoms it has been found desirable.

その理由としては、Arイオン,または活性化されたAr The reason is that, Ar ions or activated Ar,
原子が、界面に衝突して界面での欠陥を形成し、更にゲイト絶縁膜に取り込まれて固定電荷発生の原因となっていることが考えられる。 Atoms, collide with the surface to form defects at the interface, it is considered that further causing the fixed charge generation incorporated in the gate insulating film.

また酸素原子は、Ar原子と比較して質量が軽いため、 The oxygen atoms, since the mass is lighter as compared with Ar atoms,
界面近傍に衝突しても、重大なダメージを界面付近に与えることはない。 Even if the collision in the vicinity of the interface, does not give a serious damage in the vicinity of the interface. さらに膜中には、主構成成分なので取り込まれても、固定電荷発生の原因となることはない。 The further film, be incorporated because the main component, does not cause the fixed charge generation.

また、スパッタリングに用いる材料は全て高純度のものが好ましい、例えば、スパッタリングターゲットは4N The material is preferably everything high purity for use in sputtering, for example, the sputtering target 4N
以上の合成石英または、LSIの基板に使用される程度に高純度のシリコン等が最も好ましい。 More synthetic quartz or high-purity silicon, such as the most preferred to the extent used in the substrate of the LSI.

即ち、ゲイト絶縁膜内に存在する不純物を極力少なくする必要がある。 That is, it is necessary to minimize the impurities present in the gate insulating film. 同様にスパッタリングに使用するガスも高純度(5N以上)の物を用い、不純物がゲイト絶縁膜中に混入することを極力さけた。 Similarly gases used a high purity (more than 5N) to be used for sputtering, impurities as much as possible avoid from being mixed into the gate insulating film.

以下に実施例により本発明を詳しく説明する。 The present invention will be described in detail by the following examples.

「実施例1」 第1図に本発明の薄膜トランジスタの作製工程を示す。 A manufacturing process of a thin film transistor of the present invention in FIG. 1, "Embodiment 1".

本実施例においては、基板材料として安価なソーダガラスを基板(1)として用いた。 In the present embodiment, using an inexpensive soda glass as the substrate material as the substrate (1). この基板(1)上に公知のプラズマCVD法により、I型の非単結晶半導体層(2)をアイランド状に形成し、第1図(A)の状態を得る。 The substrate (1) a known plasma CVD on, form I-type non-single-crystal semiconductor layer (2) into an island shape, and the state of FIG. 1 (A).

その作製条件は以下の通りであった。 The preparation conditions were as follows.

基板温度 350℃ 反応時圧力 0.06Torr Rfパワー(13.56MHz) 100W 使用ガス SiH 4膜厚 2000Å またアイランド状に形成する際本実施例ではメタルマスクを使用したが、公知のフォトリソグラフィー技術を使用しても良い。 While using the metal mask in this embodiment when forming at a substrate temperature of 350 ° C. The reaction pressure 0.06 Torr Rf power (13.56 MHz) 100W using gas SiH 4 film thickness 2000Å The island shape, using a known photolithography technique it may be.

次に、第1図(B)に示すようにエキシマレーザ光(3)を、非単結晶半導体(2)の素子領域付近に照射して結晶化し、粒径サイズの大きい多結晶状態、またはほぼ素子領域に等しいサイズの単結晶状態とする。 Next, FIG. 1 (B) in an excimer laser beam to indicate (3), and crystallized by irradiating near the element region of the non-single-crystal semiconductor (2), of particle size sizes larger polycrystalline state or nearly, a single crystal state of the size equal to the element region. この時のエキシマレーザ光の照射条件を以下に示す。 Shows the irradiation condition of the excimer laser beam at this time is shown below.

レーザ光波長 284nm(KrF) 照射エネルギー量 200mJ/cm 2ショット数 10 光パルス巾 30ns 次に、公知のプラズマCVD法により、N型の非単結晶半導体層を全面に形成した後、公知のフォトリソグラフィー技術により、ソース,ドレイン領域(4),(5) Laser light wavelength 284 nm (KrF) irradiation energy amount 200 mJ / cm 2 Shot Number 10 optical pulse width 30ns Next, by a known plasma CVD method to form a non-single-crystal semiconductor layer of N-type on the entire surface, known photolithography the techniques, the source, drain region (4), (5)
を残すようにパターニングし、第1図(C)の状態を得た。 Patterned to leave, to obtain a state of FIG. 1 (C).

このN型非単結晶半導体層の作製条件を以下に示す。 A manufacturing condition of the N-type non-single-crystal semiconductor layer below.

基板温度 250℃ 反応時圧力 0.05Torr Rfパワー(13.56MHz) 150W 使用ガス SiH 4 +PH 3 +H 2膜厚 500Å このN型非単結晶半導体としては、多量のH 2ガスに希釈し、かつRfパワーを高くに微結晶化させ、電気抵抗の低い膜を使用した。 The time the substrate temperature of 250 ° C. The reaction pressure 0.05 Torr Rf power (13.56 MHz) 150 W using gas SiH 4 + PH 3 + H 2 film thickness 500Å this N-type non-single-crystal semiconductor, and diluted in a large amount of H 2 gas, and the Rf power high to produce microcrystals was used a low electrical resistance film.

次にRfスパッタリング法により、ゲイト絶縁膜(6) The next Rf sputtering, a gate insulating film (6)
を700Å形成し、その後ソースドレインのコンタクト用穴(7),(8)をフォトリソグラフィー技術により形成し、第1図(D)の状態を得た。 Was 700Å formed, a contact hole for subsequent source-drain (7), formed by a photolithography technique (8), obtaining the state of FIG. 1 (D).

このゲイト絶縁膜の作製条件を以下に示す。 A manufacturing condition of the gate insulating film below.

ターゲット SiO 2 99.99% 反応ガス O 2 100% 反応圧力 0.5Pa Rfパワー 500W 基板温度 100℃ 基板ターゲット間距離 150mm このゲイト絶縁膜の特性を以下に示す。 Target SiO 2 99.99% reactive gas O 2 100% reaction pressure 0.5 Pa Rf power 500W substrate temperature 100 ° C. substrate-target distance 150mm The properties of the gate insulating film below.

1/10HFエッチング速度 67nm/min 絶縁耐圧 9.1MV/cm 界面準位 2.5×10 10 eV -1 cm -2次に、ゲイト電極(9),ソース電極(10),ドレイン(11)電極をAlにより形成し、薄膜トランジスタを完成させた。 1 / 10HF etch rate 67 nm / min withstand voltage 9.1MV / cm interface state 2.5 × 10 10 eV -1 cm -2 Next, a gate electrode (9), a source electrode (10), a drain (11) electrodes by Al formed, thereby completing the thin film transistor.

このような薄膜トランジスタのスレショルド電圧(Vt Threshold voltage of such a thin film transistor (Vt
h)は1V以下とすることができ、Ar100%で形成された同様の素子のVthが1V以下にはならなかった。 h) may be a less than 1V, Vth of similar elements made of Ar 100% had to the below 1V.

また、ゲイト電圧を一定時間かけ続けた後のVthの変化率は、熱酸化によって形成されたゲイト絶縁膜の変化率とほぼ同様であり、1000時間後にわずか0.3程度しか変化しておらず、ゲイト絶縁膜(6)と非単結晶半導体(2)界面及び、ゲイト絶縁膜中に局在順位がほとんど形成されていないことがわかる。 Further, the rate of change of Vth after continuously applied a gate voltage a predetermined time is substantially the same as the rate of change of the gate insulating film formed by thermal oxidation, not only only 0.3 degree change after 1000 hours, the gate insulating film (6) and the non-single-crystal semiconductor (2) surface and, it can be seen that localized rank into the gate insulating film is not almost formed.

また、この本発明の薄膜トランジスタの移動度は100c Also, mobility of the thin film transistor of the present invention 100c
m 2 /V・Sが得られた。 m 2 / V · S was obtained.

本実施例においては、ゲイト絶縁膜形成時のArガスの割合を0としたが、約20%以下の割合でArガスが存在する条件下でゲイト絶縁膜を作製するなら薄膜トランジスタの特性上特に問題は生じなかった。 In this embodiment, the ratio of the Ar gas during the gate insulating film formed was 0, TFT characteristics particular problem of if under the conditions of Ar gas is present in a proportion of about 20% or less to produce a gate insulating film It did not occur.

ただし、Arの割合を0とした方がより特性のよい薄膜トランジスタを得ることができた。 However, it was possible to better to zero the proportion of Ar to obtain a good thin film transistor more properties.

またArガスを20%以下の割合で混合する場合には、ターゲットと基板との距離をArガス0%で作製する場合より長くすることができ、ほぼ同様の膜質のゲイト絶縁膜を得ることが可能である。 Also in case of mixing Ar gas at a rate of 20% or less, the distance between the target and the substrate can be longer than the case of manufacturing with 0% Ar gas, to obtain a gate insulating film of substantially the same quality possible it is.

さらにArガス20%以下の割合で混合して形成したゲイト絶縁膜に対し、エキシマレーザ光を照射し、フラッシュアニールを施し、膜中に取り込れたArを除去し、膜中の固定電荷の発生原因を取り除くことも可能であった。 To further gate insulating film formed by mixing at a ratio of less 20% Ar gas, it is irradiated with excimer laser light, subjected to flash annealing to remove Ar was Captures in the film, in the film fixed charge it was also possible to remove the cause.

この時、エキシマレーザ光より膜に与えるエネルギー量を多くし、ゲイト絶縁膜のアニールと同時にその下の半導体層の結晶化を行なうこともでき、作製工程数を減らす上で非常に有効な手段であった。 In this case, by increasing the amount of energy applied to the film than the excimer laser light can also be carried out the crystallization annealing at the same time as the semiconductor layer underlying the gate insulating film, a very effective means in reducing the number of manufacturing steps there were.

本実施例において、薄膜トランジスタを作製するプロセスに使用した真空装置の排気手段としては全てオイル等の排気系からの逆拡散のないターボ分子ポンプを使用し、ゲイト絶縁膜及びその他の半導体層の膜特性に影響を及ぼさないようにした。 In the present embodiment, the film characteristics of the despread without using turbo molecular pump, a gate insulating film and the other semiconductor layer from all the evacuation unit exhaust system such as an oil of a vacuum apparatus used in the process for manufacturing the thin film transistor It was in order not to affect.

「効果」 本発明方法により、低温プロセスのみで非常に特性の良い薄膜トランジスタを容易に形成することができた。 By the method of the present invention "effective", it was possible to easily form a good thin film transistor very characteristic only by a low temperature process.

またゲイト絶縁膜中に存在する固定電荷の原因を減らすことができたので、長期的な使用において特性変化の少ない信頼性の良い薄膜トランジスタを提供することが可能となった。 Since it was possible to reduce the causes of fixed charges existing in the gate insulating film, it becomes possible to provide a long-term good TFT less reliable characteristic change in use.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図は本発明の作製工程を示す。 Figure 1 shows a manufacturing process of the present invention. 第2図は一般的な薄膜トランジスタの概略図を示す。 Figure 2 shows a schematic view of a general thin film transistor. 第3図はゲイト絶縁膜作製時におけるArガスの割合と界面準位密度の関係を示す。 Figure 3 shows the relationship between the ratio and the interface state density of Ar gas during the gate insulating film formation. 第4図はゲイト絶縁膜作製時におけるArガスの割合とフラットバンド電圧のズレ量との関係を示す。 Figure 4 shows the relationship between shift amount of the proportion and the flat band voltage of the Ar gas during the gate insulating film formation.

Claims (1)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】薄膜トランジスタを作製する工程において、ゲイト絶縁膜の作製を酸化性気体と不活性気体との混合気体であって、不活性気体が20体積%以下の割合で含まれる雰囲気下において、スパッタリング法によって形成されることを特徴とする薄膜トランジスタの作製方法。 1. A process for manufacturing the thin film transistor, a mixed gas of an oxidizing gas and an inert gas produce the gate insulating film, in an atmosphere inert gas is contained in a proportion of 20 vol% or less, a method for manufacturing a thin film transistor characterized in that it is formed by sputtering.
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JP2026824A JP2585118B2 (en) 1990-02-06 1990-02-06 A method for manufacturing a thin film transistor
EP19910101533 EP0445535B1 (en) 1990-02-06 1991-02-05 Method of forming an oxide film
DE1991607101 DE69107101D1 (en) 1990-02-06 1991-02-05 A method for manufacturing an oxide film.
DE1991607101 DE69107101T2 (en) 1990-02-06 1991-02-05 A method for manufacturing an oxide film.
KR91001992A KR950010282B1 (en) 1990-02-06 1991-02-06 Method of forming an oxide film
US07/966,607 US6586346B1 (en) 1990-02-06 1992-10-26 Method of forming an oxide film
US10/459,430 US6960812B2 (en) 1990-02-06 2003-06-12 Method of forming an oxide film
US11/229,651 US7301211B2 (en) 1990-02-06 2005-09-20 Method of forming an oxide film

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