US20110062433A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
US20110062433A1
US20110062433A1 US12/880,259 US88025910A US2011062433A1 US 20110062433 A1 US20110062433 A1 US 20110062433A1 US 88025910 A US88025910 A US 88025910A US 2011062433 A1 US2011062433 A1 US 2011062433A1
Authority
US
United States
Prior art keywords
layer
insulating layer
oxide
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/880,259
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2009-214485 priority Critical
Priority to JP2009214485 priority
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAZAKI, SHUNPEI
Publication of US20110062433A1 publication Critical patent/US20110062433A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Description

    TECHNICAL FIELD
  • The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.
  • In this specification, a semiconductor device means any device which can function by utilizing semiconductor characteristics; an electrooptical device, a semiconductor circuit, and an electronic appliance are all semiconductor devices.
  • BACKGROUND ART
  • In recent years, a technique for forming a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of about several nanometers to several hundred nanometers) formed over a substrate having an insulating surface has attracted attention. Thin film transistors are applied to a wide range of electronic devices such as ICs or electrooptical devices, and particularly, prompt development of thin film transistors that are to be used as switching elements in image display devices is being pushed. Various metal oxides are used for a variety of applications. Indium oxide is a well-known material and is used as a transparent electrode material which is necessary for liquid crystal displays and the like.
  • Some metal oxides have semiconductor characteristics. Examples of such metal oxides having semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like. Thin film transistors in which a channel formation region is formed using such metal oxides having semiconductor characteristics are known (see Patent Documents 1 and 2).
  • As examples of electronic devices using thin film transistors, mobile devices such as mobile phones or laptop computers can be given. Power consumption that affects the continuous operation time is a serious concern for such a mobile electronic device. Further, also for a television set which has grown in size, it is necessary to suppress the increase of power consumption by the increase in size.
  • REFERENCE Patent Document 1
  • Japanese Published Patent Application No. 2007-123861
  • Patent Document 2
  • Japanese Published Patent Application No. 2007-096055
  • DISCLOSURE OF INVENTION
  • It is an object of the present invention to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • It is an object of the present invention to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • In a semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers an oxide semiconductor layer of a thin film transistor and a gate insulating layer interposed therebetween. Except that the gate electrode layer of the thin film transistor partly overlaps the source and drain electrode layers over the oxide semiconductor layer, a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer is not formed.
  • Accordingly, the parasitic capacitance formed by the stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.
  • One embodiment of the present invention is a semiconductor device which includes: a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, a source and drain electrode layers over the oxide semiconductor layer, an oxide insulating layer over the source and drain electrode layers, which is in contact with the oxide semiconductor layer, and a wiring layer over the oxide insulating layer, which is electrically connected to the source or drain electrode layer. An opening is formed in the oxide insulating layer so as to reach the source or drain electrode layer, the wiring layer is in contact with the source or drain electrode layer in the opening, and the gate electrode layer and the wiring layer overlap each other with the gate insulating layer and the oxide semiconductor layer interposed therebetween.
  • It is preferable that the source and drain electrode layers are as thin as a thickness greater than or equal to 0.1 nm and less than or equal to 50 nm; a film which is thinner than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced.
  • It is preferable that the source and drain electrode layers are formed using a material including a metal with high oxygen affinity. It is preferable that the metal with high oxygen affinity be one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.
  • When thermal treatment is performed while the oxide semiconductor layer and the metal layer with high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, so that the carrier density in the vicinity of the interface therebetween is increased. A low-resistance region is formed in the vicinity of the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.
  • A heat-resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, the change of properties or degradation of the source and drain electrode layers can be prevented even when thermal treatment is performed after the formation of the source and drain electrode layers.
  • As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including any of the above elements as its component, an alloy film including a combination of any of these elements, a nitride including any of the above elements as its component, or the like can be used. A conductive film in which a low-resistant conductive material such as aluminum (Al) or copper (Cu) is combined with the above-described heat-resistant conductive material may be used.
  • The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a structure in which a titanium oxide film (for example, having a thickness greater than or equal to 1 nm and less than or equal to 20 nm) is provided between a titanium film (for example, having a thickness greater than or equal to 0.1 nm and less than or equal to 5 nm) and an oxide insulating layer may be employed.
  • When the source and drain electrode layers are as thin as light is transmitted, the source and drain electrode layers have light-transmitting properties.
  • The wiring layer is formed using a conductive film having a resistance lower than that of the source and drain electrode layers. In particular, the wiring layer can be formed to have a single-layer or stacked-layer structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material which contains any of these materials as its main component. In this embodiment, an aluminum film and a titanium film are used as a first wiring layer and a second wiring layer to form a stacked-layer structure as the wiring layer.
  • One embodiment of the present invention is a method for manufacturing a semiconductor device, in which a gate electrode layer is formed, a gate insulating layer is formed over the gate electrode layer, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is subjected to dehydration or dehydrogenation and then is prevented from being exposed to air so that entry of water or hydrogen is prevented, a source and drain electrode layers are formed over the oxide semiconductor layer, an oxide insulating layer which is in contact with part of the oxide semiconductor layer is formed over the oxide semiconductor layer and the source and drain electrode layers, an opening which reaches the source or drain electrode layer is formed in the oxide insulating layer, and a wiring layer which is in contact with the source or drain electrode layer and partly overlaps the gate electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween is formed in the opening. The wiring layer is thinner than the source and drain electrode layers and has lower resistance than the same.
  • With each of the above-described structures, at least one of the above-described objects can be achieved.
  • The oxide semiconductor layer is a thin film of InMO3(ZnO)m (m>0). A thin film transistor is formed using the thin film as an oxide semiconductor layer. Note that M denotes one or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M may be Ga or may include the above-described metal element in addition to Ga, for example, M may be Ga and Ni or M may be Ga and Fe. In the above-described oxide semiconductor, a transition metal element such as Fe or Ni or an oxide of the transition metal may be included as an impurity element in addition to the metal element included as M. In this specification, an oxide semiconductor layer whose composition formula is represented as InMO3(ZnO)m (m>0) where at least Ga is included as M is referred to as an In—Ga—Zn—O-based oxide semiconductor, and a thin film thereof is also referred to as an In—Ga—Zn—O-based non-single-crystal film.
  • As other examples of the metal oxide applicable to the oxide semiconductor layer, any of the following metal oxides can be applied: an In—Sn—O-based metal oxide; an In—Sn—Zn—O-based metal oxide; an In—Al—Zn—O-based metal oxide; a Sn—Ga—Zn—O-based metal oxide; an Al—Ga—Zn—O-based metal oxide; a Sn—Al—Zn—O-based metal oxide; an In—Zn—O-based metal oxide; a Sn—Zn—O-based metal oxide; an Al—Zn—O-based metal oxide; an In—O-based metal oxide; a Sn—O-based metal oxide; and a Zn—O-based metal oxide. Silicon oxide may be included in the oxide semiconductor layer formed using the above-described metal oxide.
  • The dehydration or dehydrogenation is heat treatment performed in an atmosphere of an inert gas such as nitrogen or a rare gas (such as argon or helium) at a temperature greater than or equal to 400° C. and less than or equal to 750° C., preferably greater than or equal to 425° C. and less than the strain point of a substrate, so that impurities such as moisture included in the oxide semiconductor layer are reduced. Further, entrance of water (H2O) can be prevented.
  • The thermal treatment for dehydration or dehydrogenation is preferably performed in a nitrogen atmosphere with an H2O concentration of 20 ppm or lower. Alternatively, the thermal treatment may be performed in ultra-dry air with an H2O concentration of 20 ppm or lower.
  • For the heat treatment for dehydration or dehydrogenation, a heating method using an electric furnace, a rapid heating method such as a gas rapid thermal anneal (GRTA) method using a heated gas or a lamp rapid thermal anneal (LRTA) method using lamp light, or the like can be used.
  • The thermal treatment condition is set such that at least one of two peaks of water, which appears at around 300° C. is not detected even when TDS (Thermal Desorption Spectroscopy) measurement is performed on the oxide semiconductor layer after being dehydrated or dehydrogenated, to 450° C. Therefore, even when TDS measurement is performed on a thin film transistor including the dehydrated or dehydrogenated oxide semiconductor layer to 450° C., the peak of water which appears at around 300° C. is not detected.
  • After that, slow cooling is performed from the heat temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated to a temperature low enough to prevent entry of impurities such as water or hydrogen, specifically to a temperature which is lower than the heating temperature T by 100° C. It is important that the same furnace used for the dehydration or dehydrogenation is used without exposure to air and entry of impurities such as water or hydrogen is prevented. The dehydration or dehydrogenation is performed to make an oxide semiconductor layer a less-resistive type layer, that is, an n-type (such as n- or n+-type) layer, and after that, the oxide semiconductor layer is made to be a high-resistive so as to be an i-type oxide semiconductor layer. In the case where a thin film transistor is manufactured using such an oxide semiconductor layer, the threshold voltage of the thin film transistor is positive and a so-called normally-off switching element can be obtained. It is preferable for a display device that a channel be formed with a threshold voltage that is a positive value as close to 0 V as possible. If the threshold voltage of the thin film transistor is negative, the thin film transistor tends to be a so-called normally-on TFT, in which current flows between the source electrode and the drain electrode even when the gate voltage is 0 V. In an active-matrix display device, electric characteristics of thin film transistors included in a circuit are important and affect the performance of the display device. Among the electric characteristics of thin film transistors, in particular, a threshold voltage (Vth) is important. When the threshold voltage value is high or a negative value even when the field effect mobility is high, it is difficult to control the circuit. When a thin film transistor has a high threshold voltage value with a large absolute value, the thin film transistor cannot perform switching function as a TFT and may be a load when the transistor is driven at a low voltage. In the case of an n-channel thin film transistor, it is preferable that a channel is formed and drain current begins to flow after a positive voltage is applied as a gate voltage. A transistor in which a channel is not formed unless the driving voltage is high and a transistor in which a channel is formed and drain current flows even at a negative voltage are unsuitable as thin film transistors used in a circuit.
  • A gas atmosphere in which the temperature is decreased from the heat temperature T may be switched to a gas atmosphere different from that in which the temperature is increased to the heat temperature T. For example, the slow cooling is performed in the same furnace as the furnace for the dehydration or dehydrogenation, which is filled with a high-purity oxygen gas or N2O gas, or an ultra-dry air (with a dew point of −40° C. or less, preferably −60° C. or less) without exposure to air.
  • Using the oxide semiconductor film, which is formed by the heat treatment for dehydration or dehydrogenation so as to reduce moisture contained in the film and then the slow cooling (or cooling) in an atmosphere (with a dew point of −40° C. or less, preferably −60° C. or less) in which moisture is not contained, the electric characteristics of the thin film transistor is improved and mass productivity and high performance can be provided for the thin film transistor.
  • In this specification, heat treatment in an inert gas atmosphere of nitrogen or a rare gas (such as argon or helium) is referred to as heat treatment for dehydration or dehydrogenation. In this specification, dehydrogenation does not refer to only elimination in the form of H2 by the heat treatment, and dehydration or dehydrogenation also refers to elimination of H, OH, and the like for convenience.
  • In the case where the heat treatment is performed in the inert gas atmosphere of nitrogen or a rare gas (such as argon or helium), the heat treatment makes an oxide semiconductor layer an oxygen-depleted type layer to reduce the resistance thereof, so that the oxide semiconductor layer is turned into an n-type (such as n-type) oxide semiconductor layer.
  • Further, a high-resistance drain region (also referred to as an HRD region) which overlaps the drain electrode layer and is an oxygen-depleted type is formed. In addition, a high-resistance source region (also referred to as an HRS region) which overlaps the source electrode layer and is an oxygen-depleted type is formed.
  • Specifically, the carrier concentration of the high-resistance drain region is greater than or equal to 1×1018/cm3 and is at least higher than the carrier concentration of the channel formation region (less than 1×1018/cm3). The carrier concentration in this specification refers to a value of carrier concentration obtained by Hall effect measurement at room temperature.
  • Further, at least part of the dehydrated or dehydrogenated oxide semiconductor layer is made into an oxygen-excess state to have higher resistance, i.e., to be an i-type, so that the channel formation region is formed. As the treatment for making the dehydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state, the following treatment is performed: deposition of an oxide insulating film which is in contact with the dehydrated or dehydrogenated oxide semiconductor layer by a sputtering method (also referred to as sputtering); heat treatment after the deposition of the oxide insulating film; heat treatment in an atmosphere including oxygen after the deposition of the oxide insulating film; or cooling treatment in an oxygen atmosphere or ultra-dry air (having a dew point of −40° C. or lower, preferably −60° C. or lower) after the heat treatment in an inert gas atmosphere, after the deposition of the oxide insulating film; or the like.
  • Further, in order to make at least part of the dehydrated or dehydrogenated oxide semiconductor layer (a portion overlapping the gate electrode layer) the channel formation region, the oxide semiconductor layer is selectively made into an oxygen-excess state, thereby being high-resistance, that is, an i-type. The channel formation region can be formed in such a manner that a source and drain electrode layers formed using a metal electrode of Ti or the like are formed on and in contact with the dehydrated or dehydrogenated oxide semiconductor layer and an exposed region that does not overlap the source and the drain electrode layers is selectively made into an oxygen-excess state. In the case where the exposed region is selectively made into an oxygen-excess state, a high-resistance source region which overlaps the source electrode layer and a high-resistance drain region which overlaps the drain electrode layer are formed, by which the channel formation region is formed between the high-resistance source region and the high-resistance drain region. That is, the channel length of the channel formation region is self-aligned with the source and drain electrode layers.
  • In this manner, a semiconductor device including a thin film transistor having high electrical characteristics and high reliability can be provided.
  • By forming the high-resistance drain region in the oxide semiconductor layer overlapping the drain electrode layer, the reliability can be improved in the case where a driver circuit is formed. Specifically, by forming the high-resistance drain region, the conductivity can vary stepwise from the drain electrode layer to the channel formation region through the high-resistance drain region. Therefore, in the case where the thin film transistor operates with the drain electrode layer connected to a wiring for supplying a high power supply potential VDD, the high-resistance drain region serves as a buffer and a high electric field is not applied locally even if a high electric field is applied between the gate electrode layer and the drain electrode layer, so that the withstand voltage of the thin film transistor can be improved.
  • In addition, by forming the high-resistance drain region and the high-resistance source region in the oxide semiconductor layer overlapping the drain electrode layer and the source electrode layer, reduction in leakage current can be achieved in the channel formation region in the case where the driver circuit is formed. Specifically, by forming the high-resistance drain region, leakage current between the drain electrode layer and the source electrode layer of the transistor flows through the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the high-resistance source region on the source electrode layer side, and the source electrode layer in this order. In that case, in the channel formation region, leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region can be concentrated on the vicinity of the interface between the channel formation region and the gate insulating layer which has high resistance when the transistor is off; thus, the amount of leakage current in a back channel portion (part of a surface of the channel formation region, which is apart from the gate electrode layer) can be reduced.
  • Further, the high-resistance source region which overlaps the source electrode layer and the high-resistance drain region which overlaps the drain electrode layer, although depending on the width of the gate electrode layer, overlap each other with part of the gate electrode layer and the gate insulating layer interposed therebetween, and the intensity of the electric field in the vicinity of an end portion of the drain electrode layer can be reduced more effectively.
  • Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source and drain electrode layers. It is preferable that the oxide conductive layer contains zinc oxide as a component and do not contain indium oxide. For example, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, gallium zinc oxide, or the like can be used. The oxide conductive layer also functions as a low-resistance drain (LRD, also referred to as an LRN (low-resistance n-type conductivity)) region. Specifically, the carrier concentration of the low-resistance drain region is higher than that of the high-resistance drain region (HRD region), and is preferably in the range of 1×1020/cm3 to 1×1021/cm3 inclusive, for example. Provision of the oxide conductive layer between the oxide semiconductor layer and the source and drain electrode layers can reduce the contact resistance and realize higher speed operation of the transistor. Accordingly, frequency characteristics of a peripheral circuit (a driver circuit) can be improved.
  • The oxide conductive layer and the metal layer for forming the source and drain electrode layers can be formed successively.
  • The above-described first wiring and second wiring may be formed using a wiring that is formed by stacking a metal material and the same material as that of the oxide conductive layer which functions as an LRN region or an LRD region. By stacking the metal and the oxide conductive layer, coverage at the step such as a portion for overlapping a lower wiring or an opening can be improved; thus, wiring resistance can be lowered. Furthermore, the local increase in resistance of a wiring due to migration or the like and disconnection of a wiring can be expected to be prevented; accordingly, a semiconductor device having high reliability can be provided.
  • Also with respect to the above-described connection between the first wirings and the second wirings, an oxide conductive layer may be provided therebetween, by which increase in the contact resistance due to formation of an insulating oxide on a metal surface in the connection portion (contact portion) can be expected to be prevented; accordingly, a semiconductor device having high reliability can be provided.
  • Since a thin film transistor is easily broken due to static electricity or the like, it is preferable that a protection circuit for protecting a thin film transistor included in a pixel portion be provided for a gate line or a source line, over the same substrate as a substrate for the pixel portion. It is preferable that the protection circuit be formed using a nonlinear element using an oxide semiconductor layer.
  • Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps or the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the present invention.
  • Thin film transistors using oxide semiconductor layers can be used for electronic devices or optical devices. For example, a thin film transistor using an oxide semiconductor layer can be used as a switching element of a liquid crystal display device, a light-emitting device, an electronic paper, or the like.
  • Without being limited to display devices, insulated-gate semiconductor devices for high power control, particularly a semiconductor device called a power MOS device can be manufactured. As examples of the power MOS device, a MOSFET, an IGBT, and the like can be given.
  • A semiconductor device with less parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • A semiconductor device with high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIGS. 1A1 and 1A2 and FIG. 1B illustrate a semiconductor device.
  • FIGS. 2A to 2F illustrate a method for manufacturing a semiconductor device.
  • FIGS. 3A1 and 3A2 and FIG. 3B illustrate a semiconductor device.
  • FIGS. 4A to 4F illustrate a method for manufacturing a semiconductor device.
  • FIGS. 5A to 5F illustrate a method for manufacturing a semiconductor device.
  • FIGS. 6A and 6B illustrate semiconductor devices.
  • FIG. 7 illustrates a semiconductor device.
  • FIG. 8 illustrates a semiconductor device.
  • FIG. 9 illustrates a semiconductor device.
  • FIG. 10 illustrates a semiconductor device.
  • FIG. 11 illustrates an equivalent circuit of a pixel of a semiconductor device.
  • FIGS. 12A to 12C illustrate semiconductor devices.
  • FIGS. 13A and 13B illustrate a semiconductor device.
  • FIGS. 14A to 14C each illustrate a semiconductor device.
  • FIG. 15 illustrates a semiconductor device.
  • FIG. 16 illustrates a semiconductor device.
  • FIG. 17 illustrates a semiconductor device.
  • FIG. 18 illustrates an equivalent circuit of a pixel of a semiconductor device.
  • FIG. 19 illustrates a semiconductor device.
  • FIGS. 20A and 20B illustrate electronic appliances.
  • FIGS. 21A and 21B illustrate electronic appliances.
  • FIG. 22 illustrates an electronic appliance.
  • FIG. 23 illustrates an electronic appliance.
  • FIG. 24 illustrates electronic appliances.
  • FIGS. 25A to 25D illustrate multi-tone masks.
  • FIG. 26 illustrates results of simulation.
  • FIG. 27 illustrates results of simulation.
  • BEST MODE FOR CARRYING OUT THE INVENTION
  • Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to description of the embodiments.
  • Embodiment 1
  • In Embodiment 1, one embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A1 and 1A2 and FIG. 1B, FIGS. 2A to 2F, and FIGS. 6A and 6B.
  • FIGS. 1A1 and 1A2 illustrate an example of a plane surface structure of a semiconductor device, and FIG. 1B illustrates an example of a cross-sectional structure of the same. A thin film transistor 410 shown in FIGS. 1A2 and 1B is a kind of bottom-gate structure called a channel-etched type and is also called an inverted staggered thin film transistor.
  • FIG. 1A1 is a plane view of an intersection between a gate wiring layer (formed by the same step as a gate electrode layer) and a source wiring layer (formed by the same step as a wiring layer); FIG. 1A2 is a plane view of the channel-etched thin film transistor 410; and FIG. 1B is a cross-sectional view along line C1-C2 and line D1-D2 in FIGS. 1A1 and 1A2.
  • The thin film transistor 410, which is a channel-etched thin film transistor, includes a gate electrode layer 411, a gate insulating layer 402, an oxide semiconductor layer 412 including at least a channel formation region 413, a high-resistance source region 414 a, and a high-resistance drain region 414 b, a source electrode layer 415 a, and a drain electrode layer 415 b over a substrate 400 having an insulating surface. Further, an oxide insulating layer 407 which covers the thin film transistor 410 and is in contact with the channel formation region 413 is provided, and a protective insulating layer 408 is provided thereover.
  • Openings (Contact holes) are formed to reach the source electrode layer 415 a and the drain electrode layer 415 b, in the oxide insulating layer 407 and the protective insulating layer 408. Wiring layers 417 a and 418 a are formed in one of the openings and wiring layers 417 b and 418 b are formed in the other of the openings. In the intersection, a gate wiring layer 421 and source wiring layers 422 and 423 are stacked with the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 interposed therebetween.
  • In this manner, the gate electrode layer (gate wiring layer) intersects with the wiring layer which is electrically connected to the source electrode layer or the drain electrode layer, with the insulating layer which covers the oxide semiconductor layer of the thin film transistor and the gate insulating layer interposed therebetween. Except that the gate electrode layer of the thin film transistor partly overlaps the source and drain electrode layers over the oxide semiconductor layer, a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer is not formed.
  • Accordingly, the parasitic capacitance formed by the stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.
  • Although the thin film transistor 410 is described as a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • A process for forming the thin film transistor 410 over a substrate is described below with reference to FIGS. 2A to 2F.
  • First, a conductive film is formed over the substrate 400 having an insulating surface, and a first photolithography step is performed thereon, so that the gate electrode layer 411 and the gate wiring layer 421 are formed. A resist mask may be formed by an inkjet method. A photomask is not used when the resist mask is formed by an inkjet method, which results in reducing manufacturing costs.
  • There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance to withstand heat treatment performed later. A glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like can be used.
  • When the temperature of the heat treatment performed later is high, it is preferable that a substrate having a strain point of 730° C. or higher be used as the glass substrate. As a material of the glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. By containing a larger amount of barium oxide (BaO) than that of boric acid, a glass substrate is heat-resistant and of more practical use. Therefore, it is preferable to use a glass substrate containing BaO and B2O3 such that the amount of BaO is larger than that of B2O3.
  • Instead of the glass substrate described above, a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as well. Alternatively, crystallized glass or the like may be used.
  • An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411 and the gate wiring layer 421. The base film has a function of preventing diffusion of an impurity element from the substrate 400, and can be formed to have a single-layer or stacked-layer structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
  • The gate electrode layer 411 and the gate wiring layer 421 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • Next, the gate insulating layer 402 is formed over the gate electrode layer 411 and the gate wiring layer 421.
  • The gate insulating layer 402 can be formed to have a single layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer or a stacked layer thereof by a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed using SiH4, oxygen, and nitrogen as deposition gases by a plasma CVD method. The thickness of the gate insulating layer 402 is greater than or equal to 100 nm and less than or equal to 500 nm; in the case of a stacked layer, a first gate insulating layer having a thickness greater than or equal to 50 nm and less than or equal to 200 nm and a second gate insulating layer having a thickness greater than or equal to 5 nm and less than or equal to 300 nm are stacked.
  • In this embodiment, a silicon nitride layer having a thickness less than or equal to 200 nm is formed as the gate insulating layer 402 by a plasma CVD method.
  • Next, an oxide semiconductor film 440 is formed to a thickness greater than or equal to 2 nm and less than or equal to 200 nm over the gate insulating layer 402. It is preferable that the oxide semiconductor film 440 be as thin as a thickness greater than or equal to 50 nm so as to keep an amorphous state even when heat treatment for dehydration or dehydrogenation is performed after the oxide semiconductor film 440 is formed. Owing to the thickness of the oxide semiconductor film, the oxide semiconductor film can be prevented from being crystallized when heat treatment is performed after the formation of the oxide semiconductor layer.
  • Before the oxide semiconductor film 440 is formed by a sputtering method, it is preferable that dust on a surface of the gate insulating layer 402 be removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which, without application of voltage to a target side, an RF power source is used for application of voltage to a substrate side in an argon atmosphere to generate plasma in the vicinity of the substrate to change the qualities of the surface. Instead of an argon atmosphere, nitrogen, helium, oxygen, or the like may be used.
  • The oxide semiconductor film 440 is formed using an In—Ga—Zn—O-based non-single-crystal film; or an In—Sn—Zn—O-based oxide semiconductor film, an In—Al—Zn—O-based oxide semiconductor film, a Sn—Ga—Zn—O-based oxide semiconductor film, an Al—Ga—Zn—O-based oxide semiconductor film, a Sn—Al—Zn—O-based oxide semiconductor film, an In—Zn—O-based oxide semiconductor film, a Sn—Zn—O-based oxide semiconductor film, an Al—Zn—O-based oxide semiconductor film, an In—O-based oxide semiconductor film, a Sn—O-based oxide semiconductor film, or a Zn—O-based oxide semiconductor film.
  • In this embodiment, the oxide semiconductor film 440 is formed by a sputtering method with the use of an In—Ga—Zn—O-based oxide semiconductor target. A cross-sectional view of this stage corresponds to FIG. 2A. Further, the oxide semiconductor film 440 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. In the case of using a sputtering method, it is preferable that deposition is performed with the use of a target containing SiO2 at greater than or equal to 2 wt % and less than or equal to 10 wt %, so that SiOx (x>0) which hinders crystallization is contained in the oxide semiconductor film 440; in this way, the oxide semiconductor film 440 can be prevented from being crystallized in heat treatment for dehydration or dehydrogenation performed later.
  • In this embodiment, film deposition is performed using an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O3:ZnO=1:1:1 [mol %] and In:Ga:Zn=1:1:0.5 [at %]). The deposition condition is set as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, the direct current (DC) power supply is 0.5 kW, and the atmosphere is a mixed atmosphere of argon and oxygen (argon:oxygen=30 sccm:20 sccm and the oxygen flow rate is 40%). It is preferable to use a pulsed direct current (DC) power supply because dust can be reduced and the film thickness can be uniform. The In—Ga—Zn—O-based non-single-crystal film is formed to a thickness of greater than or equal to 5 nm and less than or equal to 200 nm. In this embodiment, as the oxide semiconductor film, an In—Ga—Zn—O-based non-single-crystal film with a thickness of 20 nm is formed using an In—Ga—Zn—O-based oxide semiconductor target by a sputtering method. Alternatively, as an oxide semiconductor target containing In, Ga, and Zn, a target having such composition ratio that In:Ga:Zn=1:1:1 [at %] or In:Ga:Zn=1:1:2 [at %] can be used.
  • Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used for a sputtering power supply, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is used mainly in the case of forming an insulating film, and a DC sputtering method is used mainly in the case of forming a metal film.
  • A multi-source sputtering apparatus in which a plurality of targets of different materials can be set can be used. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.
  • Alternatively, a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, or a sputtering apparatus used for an ECR sputtering method in which plasma generated with the use of microwaves is used without using glow discharge can be used.
  • Further, as a deposition method using a sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, or a bias sputtering method in which a voltage is also applied to a substrate during deposition can be used.
  • Next, the oxide semiconductor film 440 is processed into an island-shaped oxide semiconductor layer by a second photolithography step. A resist mask for forming the island-shaped semiconductor layer may be formed by an inkjet method. A photomask is not used when the resist mask is formed by an inkjet method, which results in reducing manufacturing costs.
  • Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, the substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then water and hydrogen are prevented from entering the oxide semiconductor layer with the oxide semiconductor layer not exposed to air. In this manner, the oxide semiconductor layer 441 is obtained (see FIG. 2B).
  • An example of a mechanism of water elimination in an oxide semiconductor film was analyzed along the reaction pathway below (reaction of not only water but also OH or H in the oxide semiconductor film). As the oxide semiconductor film, an In—Ga—Zn—O-based amorphous film was used.
  • In addition, the optimal molecular structure of the simulation model in the ground state was calculated using the density functional theory (DFT). In the DFT, the total energy is represented as the sum of potential energy, electrostatic energy between electrons, electronic kinetic energy, and exchange-correlation energy including all the complicated interactions between electrons. Also in the DFT, an exchange-correlation interaction is approximated by a functional (that is, a function of another function) of one electron potential represented in terms of electron density to enable high-speed and highly-accurate calculations. In this embodiment, B3LYP which was a hybrid functional was used to specify the weight of each parameter related to exchange-correlation energy. In addition, as a basis function, LanL2DZ (a basis function in which a split valence basis is added to the effective core potential of the Ne shell) was applied to indium atoms, gallium atoms, and zinc atoms, and 6-311 (a basis function of a triple-split valence basis set using three contraction functions for each valence orbital) was applied to the other atoms. By the above basis functions, for example, orbits of 1s to 3s are considered in the case of hydrogen atoms while orbits of 1s to 4s and 2p to 4p are considered in the case of oxygen atoms. Furthermore, to improve calculation accuracy, the p function and the d function as polarization basis sets were added to hydrogen atoms and oxygen atoms, respectively.
  • Gaussian 03 was used as a quantum chemistry computational program. A high performance computer (manufactured by SGI Japan, Ltd., Altix 4700) was used for the calculations.
  • It is assumed that heat treatment for dehydration or dehydrogenation causes —OH groups included in the oxide semiconductor film to react with each other and thus to generate H2O. Therefore, the mechanism of generation and elimination of water was analyzed as shown in FIG. 26. In FIG. 26, since Zn is divalent, in the case where M is Zn, one M-O bond is deleted in FIG. 26.
  • In FIG. 26, M represents a metal atom and is any of the following three kinds: In, Ga, and Zn. At the starting state 1, —OH forms a coordinate bond to cross-link M1 to M2. At the transition state 2, H of the —OH is dislocated to the other —OH. At the intermediate 3, the generated H2O molecule forms a coordinate bond with the metal atom. At the end state 4, the H2O molecule is detached and moves away to infinity.
  • There are the following six combinations of (M1-M2): 1, In—In; 2, Ga—Ga; 3, Zn—Zn; 4, In—Ga; 5, In—Zn; and 6, Ga—Zn. Simulation was performed for all the combinations. In this simulation, cluster computing was employed using a simulation model in which M′ is replaced with H for simplifying the simulation.
  • In the simulation, the energy diagram corresponding to the reaction pathway in FIG. 26 was obtained. Of the six combinations of (M1-M2), a simulation result of 1, (In—In) is shown in FIG. 27.
  • It was found from FIG. 27 that the activation energy for generating water was 1.16 eV. By elimination of the generated water molecule, the film is destabilized by 1.58 eV.
  • When looking at FIG. 27 in the opposite direction as a reaction from the right to the left, the reaction can be perceived as a reaction in which water enters the oxide semiconductor film. In that case, the activation energy at the time when water coordinated to the metal is hydrolyzed to produce two OH groups is 0.47 eV.
  • Similarly, the reaction pathways for the other combinations of (M1-M2) were analyzed. The activation energies (Ea [eV]) in the generation reaction of water in the cases 1 to 6 are shown in Table 1.
  • TABLE 1 the activation energy for generating water Ea [eV] 1 2 3 4 5 6 M1-M2 In—In Ga—Ga Zn—Zn In—Ga In—Zn Ga—Zn Ea 1.16 1.25 2.01 1.14 1.35 1.4
  • It can be seen from Table 1 that the generation reaction of water is more likely to be caused in the cases 1, (In—In) and 4, (In—Ga). On the contrary, the generation reaction of water is less likely to be caused in the case 3, (Zn—Zn). Accordingly, it can be assumed that the generation reaction of water using Zn atoms is less likely to be caused.
  • The heat treatment apparatus is not limited to the electric furnace, an apparatus for heating an object by thermal conduction or thermal radiation from a heating element such as a resistance heating element may be provided. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used.
  • For example, as the first heat treatment, GRTA by which the substrate is moved into an inert gas heated to a high temperature as high as 650° C. to 700° C., heated for several minutes, and moved out of the inert gas heated to the high temperature may be performed. GRTA enables high-temperature heat treatment by a short period of time.
  • In the first heat treatment, it is preferable that water, hydrogen, and the like be included as less as possible in nitrogen or the rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or the rare gas such as helium, neon, or argon introduced into the heat treatment apparatus have a purity of 6N (99.9999%) or more, more preferably 7N (99.99999%) or more, that is, the impurity concentration be set to 1 ppm or less, more preferably 0.1 ppm or less.
  • Further, the oxide semiconductor film may be crystallized to be a micro crystal film or a polycrystalline film depending on the condition of the first heat treatment or a material of the oxide semiconductor layer. For example, the oxide semiconductor layer may be crystallized to be a microcrystalline oxide semiconductor layer having a degree of crystallization of 90% or more, or 80% or more. The oxide semiconductor layer may become an amorphous oxide semiconductor layer containing no crystalline component depending on the condition of the first heat treatment or a material of the oxide semiconductor layer. The oxide semiconductor layer may become an oxide semiconductor film in which a microcrystalline portion (with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) is mixed into an amorphous oxide semiconductor. A needle-like crystal in a longitudinal direction (the film-thickness direction) may be generated on the surface side of the oxide semiconductor film in the case where heat treatment at a high temperature is performed using RTA (e.g., GRTA or LRTA).
  • The first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 440 before it is processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heat apparatus and a photolithography step is performed thereon.
  • The heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode and a drain electrode are formed over the oxide semiconductor layer; and after a protective insulating film is formed over the source electrode and the drain electrode.
  • Further, in the case where a contact hole is formed in the gate insulating layer 402, the formation of the contact hole may be performed before or after the dehydration or dehydrogenation of the oxide semiconductor film 440.
  • The oxide semiconductor layer preferably includes In, more preferably In and Ga. In order to make an oxide semiconductor layer i-type (intrinsic), dehydration or dehydrogenation is effective.
  • The etching of the oxide semiconductor film may be dry etching, without being limited to wet etching.
  • As an etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)) is preferably used.
  • Alternatively, a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used.
  • As a dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch into a desired shape, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.
  • As an etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide mixture (hydrogen peroxide water at 31 wt %: ammonia water at 28 wt %: water=5:2:2), or the like can be used. ITO07N (produced by KANTO CHEMICAL CO., INC.) may be used.
  • The etchant used in the wet etching is removed together with the material which is etched off, by cleaning. The waste liquid including the etchant and the material etched off may be purified and the material may be reused. A material such as indium included in the oxide semiconductor layer may be collected from the waste liquid after the etching and reused, thereby efficiently using resources and reducing the cost.
  • The etching conditions (such as an etchant, etching time, and temperature) are adjusted as appropriate depending on the material in order to etch into an appropriate shape.
  • Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 441. After that, a resist mask is formed by a third photolithography step, the metal conductive film is selectively etched to form the source electrode layer 415 a and the drain electrode layer 415 b, and then, the resist mask is removed (see FIG. 2C).
  • Note that each material and etching conditions are adjusted as appropriate so that the oxide semiconductor layer 441 is not removed by the etching of the metal conductive film.
  • In this embodiment, a Ti film is used as the metal conductive film, and an In—Ga—Zn—O-based oxide is used for the oxide semiconductor layer 441; and an ammonia hydrogen peroxide mixture (a mixed solution of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • It is preferable that the source and drain electrode layers are as thin as a thickness greater than or equal to 0.1 nm and less than or equal to 50 nm; a film which is thinner than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced.
  • It is preferable that the source and drain electrode layers are formed using a material including a metal with high oxygen affinity. It is preferable that the metal with high oxygen affinity be one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.
  • When thermal treatment is performed while the oxide semiconductor layer and the metal layer with high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, so that the carrier density in the vicinity of the interface therebetween is increased. A low-resistance region is formed in the vicinity of the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.
  • A heat-resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, the change of properties or degradation of the source and drain electrode layers can be prevented even when thermal treatment is performed after the formation of the source and drain electrode layers.
  • As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including any of the above elements as its component, an alloy film including a combination of any of these elements, a nitride including any of the above elements as its component, or the like can be used. A conductive film having heat resistance in which a low-resistant conductive material such as aluminum (Al) or copper (Cu) is combined with the above-described heat-resistant conductive material may be used.
  • The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a structure in which a titanium oxide film (for example, having a thickness greater than or equal to 1 nm and less than or equal to 20 nm) is provided between a titanium film (for example, having a thickness greater than or equal to 0.1 nm and less than or equal to 5 nm) and an oxide insulating layer may be employed.
  • When the source and drain electrode layers are as thin as light is transmitted, the source and drain electrode layers have light-transmitting properties.
  • In the third photolithography step, only part of the oxide semiconductor layer 441 may be etched off, whereby an oxide semiconductor layer having a groove (a depressed portion) may be formed. A resist mask for forming the source electrode layer 415 a and the drain electrode layer 415 b may be formed by an ink jet method. A photomask is not used when the resist mask is formed by an inkjet method, which results in reducing manufacturing costs.
  • In order to reduce the number of photomasks and steps in the photolithography step, the etching step may be performed using a resist mask formed by a multi-tone mask that is a mask through which light is transmitted to have a plurality of intensities. A resist mask formed with the use of a multi-tone mask has a plurality of thicknesses and further can be changed in shape by etching; therefore, the resist mask can be used in a plurality of etching steps for processing into different patterns. Therefore, a resist mask corresponding at least two kinds of different patterns can be formed by one multi-tone mask. In this manner, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced, whereby simplification of a process can be realized.
  • Next, plasma treatment is performed thereon, using a gas such as N2O, N2, or Ar. By this plasma treatment, absorbed water and the like attached to an exposed surface of the oxide semiconductor layer are removed. Plasma treatment may be performed using a mixture gas of oxygen and argon as well.
  • After the plasma treatment, the oxide insulating layer 407 which functions as a protective insulating film which is in contact with part of the oxide semiconductor layer is formed without exposure to air.
  • The oxide insulating layer 407 has a thickness of at least 1 nm and can be formed by a method by which impurities such as water and hydrogen are mixed into the oxide insulating layer 407 as less as possible such as a sputtering method, as appropriate. When hydrogen is contained in the oxide insulating layer 407, entry of the hydrogen to the oxide semiconductor layer or extraction of oxygen in the oxide semiconductor layer by the hydrogen is caused, thereby making the resistance of the backchannel of the oxide semiconductor layer low (to have an n-type conductivity), so that a parasitic channel is formed. Therefore, it is important that a formation method in which hydrogen is used as less as possible is employed such that the oxide insulating layer 407 contains hydrogen as less as possible.
  • In this embodiment, a 200-nm-thick silicon oxide film is deposited as the oxide insulating layer 407 by a sputtering method. The substrate temperature in the film deposition may be greater than or equal to room temperature and less than or equal to 300° C.; in this embodiment, the temperature is 100° C. The silicon oxide film can be deposited by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere including a rare gas (typically argon) and oxygen. A silicon oxide target or a silicon target can be used as a target. For example, with use of a silicon target, a silicon oxide film can be formed by a sputtering method in an atmosphere including oxygen and nitrogen. As the oxide insulating layer 407 formed in contact with the oxide semiconductor layer whose resistance is reduced, an inorganic insulating film that includes impurities such as moisture, a hydrogen ion, and OH as less as possible and blocks entry of these from the outside may be used; typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.
  • Next, second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (at a temperature higher than or equal to 200° C. and lower than or equal to 400° C., for example a temperature higher than or equal to 250° C. and lower than or equal to 350° C.). For example, the second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment performs heating while part (a channel formation region) of the oxide semiconductor layer is in contact with the oxide insulating layer 407.
  • Through the above-described steps, the heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film to reduce the resistance, and then, part of the oxide semiconductor film is selectively made into an oxygen-excess state. As a result, the channel formation region 413 overlapping the gate electrode layer 411 becomes I-type, and the high-resistance source region 414 a which overlaps the source electrode layer 415 a and the high-resistance drain region 414 b which overlaps the drain electrode layer 415 b are formed in a self-aligned manner. Through the above process, the thin film transistor 410 is formed.
  • Further, heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 200° C. for a period longer than or equal to one hour and shorter than or equal to 30 hours in air. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature; alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature higher than or equal to 100° C. and lower than or equal to 200° C. and then decreased to room temperature. This heat treatment may be performed before the formation of the oxide insulating film under a reduced pressure. The reduced pressure enables the heat treatment time to be short. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, a normally-off thin film transistor can be obtained. Therefore, reliability of the semiconductor device can be improved.
  • By the formation of the high-resistance drain region 414 b (and the high-resistance source region 414 a) in part(s) of the oxide semiconductor layer, which overlaps/overlap the drain electrode layer 415 b (and the source electrode layer 415 a), reliability of the thin film transistor can be improved. Specifically, by the formation of the high-resistance drain region 414 b, the conductivity can be gradually changed from the drain electrode layer 415 b to the high-resistance drain region 414 b and the channel formation region in this order. Thus, when the transistor operates with the drain electrode layer 415 b connected to a wiring that supplies a high power supply potential VDD, the transistor can have increased withstand voltage because the high-resistance drain region serves as a buffer even when a high electric field is applied between the gate electrode layer 411 and the drain electrode layer 415 b so that a localized high electric field is not applied to the transistor.
  • The high-resistance source region and the high-resistance drain region may be formed at all depths in the film thickness direction in the oxide semiconductor layer in the case where the oxide semiconductor layer is as thin as 15 nm or less; whereas in the case where the oxide semiconductor layer is as thick as a thickness greater than or equal to 30 nm and less than or equal to 50 nm, parts of the oxide semiconductor layer, that is, regions of the oxide semiconductor layer, which are in contact with the source and drain electrode layers and the vicinity thereof may be reduced in the resistance, so that the high-resistance source region and the high-resistance drain region are formed and a region of the oxide semiconductor layer, near the gate insulating layer can be made to be I-type.
  • A protective insulating layer may be formed over the oxide insulating layer 407. For example, a silicon nitride film is formed by an RF sputtering method. An RF sputtering method is preferable as the formation method of the protective insulating layer because of high productivity. The protective insulating layer is formed using an inorganic insulating film which includes impurities such as moisture, a hydrogen ion, and OH as less as possible and blocks entry of these from the outside; for example, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer (see FIG. 2D).
  • Next, a fourth photolithography step is performed to form a resist mask, and etching is selectively performed to remove parts of the oxide insulating layer 407 and the protective insulating layer 408, so that openings 442 a and 442 b reaching the source electrode layer 415 a and the drain electrode layer 415 b are formed (see FIG. 2E).
  • A stacked-layer conductive layer is formed in the openings 442 a and 442 b so as to be in contact with the source electrode layer 415 a and the drain electrode layer 415 b by a sputtering method or a vacuum evaporation method, and a resist mask is formed by a fifth photolithography step. The stacked-layer conductive layer is selectively etched to form the wiring layers 417 a, 417 b, 418 a, and 418 b, and the source wiring layers 422 and 423 in the intersection (see FIG. 2F).
  • The wiring layers 417 a, 417 b, 418 a, and 418 b are formed using conductive films having resistances lower than that of the source and drain electrode layers. In particular, the wiring layers can be formed to have a single-layer or stacked-layer structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material which contains any of these materials as its main component. In this embodiment, an aluminum film is used as each of the wiring layers 417 a and 417 b which are first wiring layers and a titanium film is used as each of the wiring layers 418 a and 418 b which are second wiring layers.
  • A planarization insulating layer for planarization may be provided over the protective insulating layer 408. An example in which a planarization insulating layer is provided is shown in FIG. 6A. In FIG. 6A, a planarization insulating layer 409 is formed over the protective insulating layer 408, and the wiring layers 417 a, 417 b, 418 a, and 418 b are formed in the openings provided in the oxide insulating layer 407, the protective insulating layer 408, and the planarization insulating layer 409. The source wiring layers 422 and 423 are formed over the planarization insulating layer 409. The provision of the planarization insulating layer 409 further distances the gate wiring layer 421 and the source wiring layers 422 and 423 from each other, by which the parasitic capacitance can be further decreased.
  • The planarization insulating layer 409 can be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. The planarization insulating layer 409 may be formed by stacking a plurality of insulating films formed using these materials.
  • The siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include as a substituent an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. The organic group may include a fluoro group.
  • There is no particular limitation on the method for forming the planarization insulating layer 409, and any of the following can be used depending on a material thereof: a sputtering method, a spin coating method, a dipping method, a spray coating method, or a droplet discharging method (e.g., an inkjet method, screen printing, or offset printing), a roll coating method, a curtain coating method, or a knife coating method, and the like.
  • Alternatively, as shown in FIG. 6B, the wiring layer and the source wiring layer may be formed over the oxide insulating layer 407 without providing a protective insulating layer. In FIG. 6B, the source wiring layer 422 is provided over the oxide insulating layer 407, and the wiring layers 417 a and 417 b are provided in openings formed in the oxide insulating layer 407. As described above, the wiring layer may have a single-layer structure.
  • In this manner, a semiconductor device with less parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • A semiconductor device with high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • Embodiment 2
  • In Embodiment 2, an example of a semiconductor device including a thin film transistor having a structure different from that of Embodiment 1 will be described below.
  • FIGS. 3A1 and 3A2 illustrate an example of a plane surface structure of a semiconductor device, and FIG. 3B illustrates an example of a cross-sectional structure of the same. A thin film transistor 450 shown in FIGS. 3A2 and 3B is a kind of bottom-gate structure called a channel-protective type (channel-stop type) and is also called an inverted staggered thin film transistor.
  • FIG. 3A1 is a plane view of an intersection between a gate wiring layer (formed by the same step as a gate electrode layer) and a source wiring layer (formed by the same step as a wiring layer); FIG. 3A2 is a plane view of the channel-protective type thin film transistor 450; and FIG. 3B is a cross-sectional view along line C3-C4 and line D3-D4 in FIGS. 3A1 and 3A2.
  • The thin film transistor 450, which is a channel-protective type thin film transistor, includes a gate electrode layer 451, a gate insulating layer 402, an oxide semiconductor layer 452 including at least a channel formation region 453, a high-resistance source region 454 a, and a high-resistance drain region 454 b, a source electrode layer 455 a, and a drain electrode layer 455 b over a substrate 400 having an insulating surface. Further, an oxide insulating layer 456 which covers the thin film transistor 450, is in contact with the channel formation region 413, and functions as a channel protective layer is provided, and a protective insulating layer 408 is provided thereover.
  • Openings (Contact holes) are formed to reach the source electrode layer 455 a and the drain electrode layer 455 b, in the protective insulating layer 408. Wiring layers 457 a and 458 a are formed in one of the openings and wiring layers 457 b and 458 b are formed in the other of the openings. In the intersection, a gate wiring layer 421 and source wiring layers 422 and 423 are stacked with the gate insulating layer 402, an oxide insulating layer 459, and the protective insulating layer 408 interposed therebetween.
  • The oxide insulating layer 459 is not necessarily provided in the intersection; however, the provision of the oxide insulating layer 459 further distances the gate wiring layer 421 and the source wiring layers 422 and 423 from each other, by which the parasitic capacitance can be further decreased.
  • The oxide insulating layers 456 and 459 can be formed by etching an oxide insulating layer, and can be formed by a manufacturing method and a material which are the same as those of the oxide insulating layer 407 described in Embodiment 1. In this embodiment, the oxide insulating layer is formed by a sputtering method and is processed into the oxide insulating layers 456 and 459 by a photolithography step.
  • In this manner, the gate electrode layer (gate wiring layer) intersects with the wiring layer which is electrically connected to the source electrode layer or the drain electrode layer, with the protective insulating layer which covers the thin film transistor and the gate insulating layer interposed therebetween. Except that the gate electrode layer of the thin film transistor partly overlaps the source and drain electrode layers over the oxide semiconductor layer, a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer is not formed.
  • Accordingly, the parasitic capacitance formed by the stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.
  • Although the thin film transistor 450 is described as a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • A process for forming the thin film transistor 450 over a substrate is described below with reference to FIGS. 4A to 4F.
  • First, a conductive film is formed over the substrate 400 having an insulating surface, and a first photolithography step is performed thereon, so that the gate electrode layer 451 and the gate wiring layer 421 are formed. A resist mask may be formed by an inkjet method. A photomask is not used when the resist mask is formed by an inkjet method, which results in reducing manufacturing costs.
  • The gate electrode layer 451 and the gate wiring layer 421 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • Next, the gate insulating layer 402 is formed over the gate electrode layer 451 and the gate wiring layer 421.
  • In this embodiment, a silicon nitride layer having a thickness of less than or equal to 200 nm is formed as the gate insulating layer 402 by a plasma CVD method.
  • Next, an oxide semiconductor film is formed to a thickness greater than or equal to 2 nm and less than or equal to 200 nm over the gate insulating layer 402, and then, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by a second photolithography step. In this embodiment, the oxide semiconductor film is formed by a sputtering method with the use of an In—Ga—Zn—O-based oxide semiconductor target.
  • Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, the substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then water and hydrogen are prevented from entering the oxide semiconductor layer with the oxide semiconductor layer not exposed to air. In this manner, an oxide semiconductor layer 441 is obtained (see FIG. 4A).
  • Next, plasma treatment is performed thereon, using a gas such as N2O, N2, or Ar. By this plasma treatment, absorbed water and the like attached to an exposed surface of the oxide semiconductor layer are removed. Plasma treatment may be performed using a mixture gas of oxygen and argon as well.
  • Next, an oxide insulating layer is formed over the gate insulating layer 402 and the oxide semiconductor layer 441. After that, a resist mask is formed by a third photolithography step, the oxide insulating layer is selectively etched to form the oxide insulating layer 456 and the oxide insulating layer 459, and then, the resist mask is removed.
  • In this embodiment, a 200-nm-thick silicon oxide film is deposited as each of the oxide insulating layer 456 and the oxide insulating layer 459 by a sputtering method. The substrate temperature in the film deposition may be greater than or equal to room temperature and less than or equal to 300° C.; in this embodiment, the temperature is 100° C. The silicon oxide film can be deposited by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere including a rare gas (typically argon) and oxygen. A silicon oxide target or a silicon target can be used as a target. For example, with use of a silicon target, a silicon oxide film can be formed by a sputtering method in an atmosphere including oxygen and nitrogen. As the oxide insulating layer 456 formed in contact with the oxide semiconductor layer whose resistance is reduced, an inorganic insulating film that includes impurities such as moisture, a hydrogen ion, and OH as less as possible and blocks entry of these from the outside may be used; typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.
  • Next, second heat treatment may be performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at a temperature higher than or equal to 200° C. and lower than or equal to 400° C., for example a temperature higher than or equal to 250° C. and lower than or equal to 350° C.). For example, the second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment performs heating while part (a channel formation region) of the oxide semiconductor layer is in contact with the oxide insulating layer 456.
  • In this embodiment, the oxide semiconductor layer 441 which is provided with the oxide insulating layer 456 and is partly exposed is further subjected to heat treatment in a nitrogen atmosphere or an inert gas atmosphere or under a reduced pressure. By the heat treatment in a nitrogen atmosphere or an inert gas atmosphere or under a reduced pressure, the resistance of the exposed region of the oxide semiconductor layer 441, which is not covered by the oxide insulating layer 456 can be reduced. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.
  • With the heat treatment on the oxide semiconductor layer 441 provided with the oxide insulating layer 456 in a nitrogen atmosphere, the resistance of the exposed region of the oxide semiconductor layer 441 is reduced, so that an oxide semiconductor layer 452 including regions with different resistances (indicated as a shaded region and a white region in FIG. 4B) is formed.
  • Next, a metal conductive film is formed over the gate insulating layer 402, the oxide semiconductor layer 452 m and the oxide insulating layer 456. After that, a resist mask is formed by a fourth photolithography step, the metal conductive film is selectively etched to form the source electrode layer 455 a and the drain electrode layer 455 b, and then, the resist mask is removed (see FIG. 4C).
  • It is preferable that the source electrode layer 455 a and the drain electrode layer 455 b are as thin as a thickness greater than or equal to 0.1 nm and less than or equal to 50 nm; a film which is thinner than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced.
  • It is preferable that the source electrode layer 455 a and the drain electrode layer 455 b are formed using a material including a metal with a high oxygen affinity. It is preferable that the metal with a high oxygen affinity be one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source electrode layer 455 a and the drain electrode layer 455 b.
  • When thermal treatment is performed while the oxide semiconductor layer and the metal layer with a high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, so that the carrier density in the vicinity of the interface therebetween is increased. Therefore, a low-resistance region is formed in the vicinity of the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.
  • A heat-resistant conductive material may be used in the source electrode layer 455 a and the drain electrode layer 455 b. By using the heat-resistant conductive material, the change of properties or degradation of the source electrode layer 455 a and the drain electrode layer 455 b can be prevented even when thermal treatment is performed after the formation of the source electrode layer 455 a and the drain electrode layer 455 b.
  • As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including any of the above elements as its component, an alloy film including a combination of any of these elements, a nitride including any of the above elements as its component, or the like can be used. A conductive film having heat resistance in which a low-resistant conductive material such as aluminum (Al) or copper (Cu) is combined with the above-described heat-resistant conductive material may be used.
  • The source electrode layer 455 a and the drain electrode layer 455 b may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a structure in which a titanium oxide film (for example, having a thickness greater than or equal to 1 nm and less than or equal to 20 nm) is provided between a titanium film (for example, having a thickness greater than or equal to 0.1 nm and less than or equal to 5 nm) and an oxide insulating layer may be employed.
  • When the source electrode layer 455 a and the drain electrode layer 455 b are as thin as light is transmitted, the source electrode layer 455 a and the drain electrode layer 455 b have light-transmitting properties.
  • Through the above-described steps, the heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film to reduce the resistance, and then, part of the oxide semiconductor film is selectively made into an oxygen-excess state. As a result, the channel formation region 453 overlapping the gate electrode layer 451 becomes I-type, and the high-resistance source region 454 a which overlaps the source electrode layer 455 a and the high-resistance drain region 454 b which overlaps the drain electrode layer 455 b are formed in a self-aligned manner. Through the above process, the thin film transistor 450 is formed.
  • Further, heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 200° C. for a period longer than or equal to one hour and shorter than or equal to 30 hours in air. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature; alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature higher than or equal to 100° C. and lower than or equal to 200° C. and then decreased to room temperature. This heat treatment may be performed before the formation of the oxide insulating film under a reduced pressure. The reduced pressure enables the heat treatment time to be short. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, a normally-off thin film transistor can be obtained. Therefore, reliability of the semiconductor device can be improved.
  • By the formation of the high-resistance drain region 454 b (and the high-resistance source region 454 a) in part(s) of the oxide semiconductor layer, which overlaps/overlap the drain electrode layer 455 b (and the source electrode layer 455 a), reliability of the thin film transistor can be improved. Specifically, by the formation of the high-resistance drain region 454 b, the conductivity can be gradually changed from the drain electrode layer 455 b to the high-resistance drain region 454 b and the channel formation region in this order. Thus, when the transistor operates with the drain electrode layer 455 b connected to a wiring that supplies a high power supply potential VDD, the transistor can have increased withstand voltage because the high-resistance drain region serves as a buffer even when a high electric field is applied between the gate electrode layer 451 and the drain electrode layer 455 b so that a localized high electric field is not applied to the transistor.
  • The protective insulating layer 408 is formed over the source electrode layer 455 a, the drain electrode layer 455 b, the oxide insulating layer 456, and the oxide insulating layer 459. For example, a silicon nitride film is formed by an RF sputtering method. An RF sputtering method is preferable as the formation method of the protective insulating layer 408 because of high productivity. The protective insulating layer 408 is formed using an inorganic insulating film which includes impurities such as moisture, a hydrogen ion, and OH as less as possible and blocks entry of these from the outside; for example, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film (see FIG. 4D).
  • An oxide insulating layer may be formed over the source electrode layer 455 a, the drain electrode layer 455 b, the oxide insulating layer 456, and the oxide insulating layer 459, and the protective insulating layer 408 may be stacked over the oxide insulating layer 408. A planarization insulating layer 409 as shown in FIG. 6A may be provided. The provision of the planarization insulating layer 409 further distances the gate wiring layer 421 and the source wiring layers 422 and 423 from each other, by which the parasitic capacitance can be further decreased.
  • Next, a fifth photolithography step is performed to form a resist mask, and etching is selectively performed to remove parts of the protective insulating layer 408, so that openings 467 a and 467 b reaching the source electrode layer 455 a and the drain electrode layer 455 b are formed (see FIG. 4E).
  • A stacked-layer conductive layer is formed in the openings 467 a and 467 b so as to be in contact with the source electrode layer 455 a and the drain electrode layer 455 b by a sputtering method or a vacuum evaporation method, and a resist mask is formed by a sixth photolithography step. The stacked-layer conductive layer is selectively etched to form the wiring layers 457 a, 457 b, 458 a, and 458 b, and the source wiring layers 422 and 423 in the intersection (see FIG. 4F).
  • The wiring layers 457 a, 457 b, 458 a, and 458 b are formed using conductive films having resistances lower than that of the source and drain electrode layers. In particular, the wiring layers can be formed to have a single-layer or stacked-layer structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material which contains any of these materials as its main component. In this embodiment, an aluminum film is used as each of the wiring layers 457 a and 457 b which are first wiring layers and a titanium film is used as each of the wiring layers 458 a and 458 b which are second wiring layers.
  • In this manner, a semiconductor device with less parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • A semiconductor device with high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • Embodiment 3
  • In Embodiment 3, another example which is different from Embodiment 1 in the manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. 5A to 5F. FIGS. 5A to 5F are the same as FIGS. 1A1, 1A2, and FIG. 1B and FIGS. 2A to 2F except that there is a difference in part of the process; therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted. In this embodiment, a mask layer formed using a multi-tone mask is used in a photolithography step.
  • Since a mask layer formed with the use of a multi-tone mask has a plurality of film thicknesses and further can be changed in shape by performing etching on the mask layer, the mask layer can be used in a plurality of etching steps for processing into different patterns. Therefore, a mask layer corresponding at least two kinds of different patterns can be formed by one multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of photolithography steps can be also reduced accordingly, whereby simplification of a process can be realized.
  • In accordance with Embodiment 1, a gate wiring layer 421 and a gate electrode layer 481 are formed over a substrate 400 by a first photolithography step, and a gate insulating layer 402 is stacked thereover. An oxide semiconductor film is formed over the gate insulating layer 402. In this embodiment, the oxide semiconductor film is formed by a sputtering method with the use of an In—Ga—Zn—O-based oxide semiconductor target.
  • The substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour in order for dehydration or dehydrogenation, and then water and hydrogen are prevented from entering the oxide semiconductor layer with the oxide semiconductor layer not exposed to air. In this manner, an oxide semiconductor film 465 is obtained
  • Next, a metal conductive film 466 is formed over the oxide semiconductor film 465 by a sputtering method or a vacuum evaporation method (see FIG. 5A).
  • The metal conductive film 466 is a conductive film which forms a source and drain electrode layers. It is preferable that the source and drain electrode layers are as thin as a thickness greater than or equal to 0.1 nm and less than or equal to 50 nm; a film which is thinner than the wiring layer is used. Since each of the source and drain electrode layers are thin conductive films, the parasitic capacitance formed with the gate electrode layer can be reduced.
  • It is preferable that the source and drain electrode layers are formed using a material including a metal with a high oxygen affinity. It is preferable that the metal with a high oxygen affinity be one or more materials selected from titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as each of the source and drain electrode layers.
  • When thermal treatment is performed while the oxide semiconductor layer and the metal layer with a high oxygen affinity are in contact with each other, oxygen atoms move from the oxide semiconductor layer to the metal layer, so that the carrier density in the vicinity of the interface therebetween is increased. A low-resistance region is formed in the vicinity of the interface therebetween, thereby reducing the contact resistance between the oxide semiconductor layer and the source and drain electrode layers.
  • A heat-resistant conductive material may be used in the source and drain electrode layers. By using the heat-resistant conductive material, the change of properties or degradation of the source and drain electrode layers can be prevented even when thermal treatment is performed after the formation of the source and drain electrode layers.
  • As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including any of the above elements as its component, an alloy film including a combination of any of these elements, a nitride including any of the above elements as its component, or the like can be used. A conductive film having heat resistance in which a low-resistant conductive material such as aluminum (Al) or copper (Cu) is combined with the above-described heat-resistant conductive material may be used.
  • The source and drain electrode layers may include a metal oxide layer. For example, a structure in which a titanium oxide film is provided between an oxide semiconductor layer and a titanium film, or a structure in which a titanium oxide film (for example, having a thickness greater than or equal to 1 nm and less than or equal to 20 nm) is provided between a titanium film (for example, having a thickness greater than or equal to 0.1 nm and less than or equal to 5 nm) and an oxide insulating layer may be employed.
  • When the source and drain electrode layers are as thin as light is transmitted, the source and drain electrode layers have light-transmitting properties.
  • A second photolithography step is performed, so that a resist mask 460 is formed over the oxide semiconductor film 465 and the metal conductive film 466.
  • In this embodiment, an example is shown in which a high-tone mask is used for light exposure to form the resist mask 460. A resist is formed in order to form the resist mask 460. As the resist, a positive type resist or a negative type resist can be used. In this embodiment, a positive type resist is used. The resist may be formed by a spin coating method or may be selectively formed by an inkjet method. When the resist is selectively formed by an inkjet method, a resist can be prevented from being formed in an unintended portion, which results in reducing waste of the material.
  • Next, the resist is irradiated with light with the use of a multi-tone mask 81 as a light-exposure mask, so that the resist is exposed to light.
  • Here, light exposure using the multi-tone mask 81 is described with reference to FIGS. 25A to 25D.
  • A multi-tone mask enables three levels of light exposure to form an exposed portion, a half-exposed portion, and an unexposed portion: a multi-tone mask is a photomask through which light is transmitted to have a plurality of intensities. With one-time light exposure and development process, a resist mask with regions of plural thicknesses (typically, two kinds of thicknesses) can be formed. Accordingly, by using a multi-tone mask, the number of photomasks can be reduced.
  • Typical examples of the multi-tone mask are a gray-tone mask 81 a shown in FIG. 25A and a half-tone mask 81 b shown in FIG. 25C.
  • As shown in FIG. 25A, the gray-tone mask 81 a includes a light-transmitting substrate 83, and a light-blocking portion 84 and a diffraction grating 85 that are formed on the light-transmitting substrate 83. The light transmittance of the light-blocking portion 84 is 0%. The diffraction grating 85 has a light-transmitting portion in a slit form, a dot form, a mesh form, or the like with intervals that are less than or equal to the resolution limit of light used for the exposure, whereby the light transmittance can be controlled. The diffraction grating 85 can be in a slit form, a dot form, or a mesh form with regular intervals; or in a slit form, a dot form, or a mesh form with irregular intervals.
  • As the light-transmitting substrate 83, a light-transmitting substrate such as a quartz substrate can be used. The light-blocking portion 84 and the diffraction grating 85 can be formed using a light-blocking material that absorbs light, such as chromium or chromium oxide.
  • When the gray-tone mask 81 a is irradiated with light for exposure, a light transmittance 86 of the light-blocking portion 84 is 0% and the light transmittance 86 of a region where none of the light-blocking portion 84 and the diffraction grating 85 are provided is 100% as shown in FIG. 25B. The light transmittance 86 of the diffraction grating 85 can be controlled in the range of 10% to 70%. The light transmittance of the diffraction grating 85 can be controlled by adjusting the interval or pitch of slits, dots, or meshes of the diffraction grating.
  • As shown in FIG. 25C, the half-tone mask 81 b includes a light-transmitting substrate 83, and a semi-light-transmitting portion 87 and a light-blocking portion 88 that are formed on the light-transmitting substrate 83. The semi-light-transmitting portion 87 can be formed using MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-blocking portion 88 can be formed using a light-blocking material that absorbs light, such as chromium or chromium oxide.
  • When the half-tone mask 81 b is irradiated with light for exposure, a light transmittance 89 of the light-blocking portion 88 is 0% and the light transmittance 89 of a region where none of the light-blocking portion 88 and the semi-light-transmitting portion 87 are provided is 100% as shown in FIG. 25D. The light transmittance 89 of the semi-light-transmitting portion 87 can be controlled in the range of 10% to 70%. The light transmittance of the semi-light-transmitting portion 87 can be controlled by a material of the semi-light-transmitting portion 87.
  • After the light exposure using the multi-tone mask, development is carried out, whereby the resist mask 460 with regions having different thicknesses can be formed as shown in FIG. 5B.
  • Next, a first etching step is performed using the resist mask 460, so that the oxide semiconductor film 465 and the metal conductive film 466 are etched into island shapes. As a result, an oxide semiconductor layer 461 and a metal conductive layer 462 can be formed (see FIG. 5B).
  • Next, ashing is performed on the resist mask 460. Consequently, the area (the volume when considering three dimensions) of the resist mask is reduced and the thickness is reduced. Through this step, the resist of the resist mask in a region with a small thickness (a region overlapping with part of the gate electrode layer 481) is removed, so that resist masks 463 a and 436 b which are separated from each other can be formed.
  • With the resist masks 463 a and 436 b, an unnecessary portion is removed by etching, so that a source electrode layer 485 a and a drain electrode layer 485 b are formed (see FIG. 5C).
  • Each material and etching conditions of the etching on the metal conductive layer 462 are adjusted as appropriate such that the oxide semiconductor layer 461 is not removed by the etching.
  • In this embodiment, a Ti film is used as the metal conductive layer 462; an In—Ga—Zn—O-based oxide is used for the oxide semiconductor layer 461; and an ammonia hydrogen peroxide solution (a mixed solution of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • The etching of the metal conductive film and the oxide semiconductor film may be dry etching, without being limited to wet etching.
  • As an etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)) is preferably used.
  • Alternatively, the following can be used: a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like.
  • As a dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch into a desired shape, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.
  • As an etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide mixture (hydrogen peroxide water at 31 wt %: ammonia water at 28 wt %: water=5:2:2), or the like can be used. ITO07N (produced by KANTO CHEMICAL CO., INC.) may be used.
  • The etchant used in the wet etching is removed together with the material which is etched off, by cleaning. The waste liquid including the etchant and the material etched off may be purified and the material may be reused. A material such as indium included in the oxide semiconductor layer may be collected from the waste liquid after the etching and reused, thereby efficiently using resources and reducing the cost.
  • The etching conditions (such as an etchant, etching time, and temperature) are adjusted as appropriate depending on the material in order to etch into an appropriate shape.
  • Next, the resist masks 463 a and 436 b are removed, and an oxide insulating layer 407 which functions as a protective insulating film which is in contact with part of the oxide semiconductor layer 461 is formed. In this embodiment, a 200-nm-thick silicon oxide film is deposited as the oxide insulating layer 407 by a sputtering method.
  • Next, second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at a temperature higher than or equal to 200° C. and lower than or equal to 400° C., for example a temperature higher than or equal to 250° C. and lower than or equal to 350° C.). For example, the second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment performs heating while part (a channel formation region) of the oxide semiconductor layer is in contact with the oxide insulating layer 407.
  • Through the above-described steps, the heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film to reduce the resistance, and then, part of the oxide semiconductor film is selectively made into an oxygen-excess state. As a result, a channel formation region 483 overlapping the gate electrode layer 481 becomes I-type, and a high-resistance source region 484 a which overlaps the source electrode layer 485 a and a high-resistance drain region 484 b which overlaps the drain electrode layer 485 b are formed in a self-aligned manner. Through the above process, a thin film transistor 480 is formed.
  • Further, heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 200° C. for a period longer than or equal to one hour and shorter than or equal to 30 hours in air. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature; alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature higher than or equal to 100° C. and lower than or equal to 200° C. and then decreased to room temperature. This heat treatment may be performed before the formation of the oxide insulating film under a reduced pressure. The reduced pressure enables the heat treatment time to be short. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, a normally-off thin film transistor can be obtained. Therefore, reliability of the semiconductor device can be improved.
  • Next, a protective insulating layer 408 is formed over the oxide insulating layer 407. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer (see FIG. 5D).
  • Next, a third photolithography step is performed to form a resist mask, and etching is selectively performed to remove parts of the oxide insulating layer 407 and the protective insulating layer 408, so that openings 464 a and 464 b reaching the source electrode layer 485 a and the drain electrode layer 485 b are formed (see FIG. 5E).
  • A stacked-layer conductive layer is formed in the openings 464 a and 464 b so as to be in contact with the source electrode layer 485 a and the drain electrode layer 485 b by a sputtering method or a vacuum evaporation method, and a resist mask is formed by a fourth photolithography step. The stacked-layer conductive layer is selectively etched to form wiring layers 487 a, 487 b, 488 a, and 488 b, and source wiring layers 422 and 423 in the intersection (see FIG. 5F).
  • The wiring layers 487 a, 487 b, 488 a, and 488 b are formed using conductive films having resistances lower than that of the source and drain electrode layers. In particular, the wiring layers can be formed to have a single-layer or stacked-layer structure using a metal material such as aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, or scandium, or an alloy material which contains any of these materials as its main component. In this embodiment, an aluminum film is used as each of the wiring layers 487 a and 487 b which are first wiring layers and a titanium film is used as each of the wiring layers 488 a and 488 b which are second wiring layers.
  • In this manner, a semiconductor device with less parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • A semiconductor device with high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • This embodiment can be implemented combining with another embodiment as appropriate.
  • Embodiment 4
  • In Embodiment 4, an example in which a gate electrode layer is formed using a light-transmitting conductive material in Embodiment 1 will be described with reference to FIG. 7. Therefore, the same as Embodiment 1 can be applied, and the description of the same portions as Embodiment 1 and portions and steps having similar functions to Embodiment 1 are omitted. FIG. 7 is the same as FIGS. 1A1, 1A2, and FIG. 1B and FIGS. 2A to 2F except that there is a difference in part of the process; therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted.
  • A thin film transistor 430 shown in FIG. 7 is a channel-etched thin film transistor, and includes a gate electrode layer 431, a gate insulating layer 402, an oxide semiconductor layer 432 including at least a channel formation region 433, a high-resistance source region 434 a, and a high-resistance drain region 434 b, a source electrode layer 435 a, and a drain electrode layer 435 b over a substrate 400 having an insulating surface. Further, an oxide insulating layer 407 which covers the thin film transistor 430 and is in contact with the channel formation region 433 is provided, and a protective insulating layer 408 is provided thereover.
  • An opening (a contact hole) is formed to reach the source electrode layer 435 a, in the oxide insulating layer 407 and the protective insulating layer 408. Wiring layers 437 and 438 are formed in the opening. In the intersection, a gate wiring layer 421 and source wiring layers 422 and 423 are stacked with the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 interposed therebetween. As the opening reaching the source electrode layer 435 a and the wiring layers 437 and 438 formed in the opening shown in FIG. 7, the opening and the wiring layer may be provided in a region which does not overlap the oxide semiconductor layer 432.
  • In this manner, the gate electrode layer (gate wiring layer) intersects with the wiring layer which is electrically connected to the source electrode layer or the drain electrode layer, with the insulating layer which covers the oxide semiconductor layer of the thin film transistor and the gate insulating layer interposed therebetween. Except that the gate electrode layer of the thin film transistor partly overlaps the source and drain electrode layers over the oxide semiconductor layer, a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer is not formed.
  • Accordingly, the parasitic capacitance formed by the stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.
  • A planarization insulating layer 409 is provided over the wiring layer 438, the source wiring layer 423, and the protective insulating layer 408, and a pixel electrode layer 427 is provided over the planarization insulating layer 409. The pixel electrode layer 427 is in contact with the wiring layer 438 through the opening formed in the planarization insulating layer 409, and the thin film transistor 430 is electrically connected to the pixel electrode layer 427 through the wiring layers 437 and 438.
  • The source electrode layer 435 a and the drain electrode layer 435 b each can be formed as a light-transmitting conductive film by using a thin metal conductive film.
  • Further, in FIG. 7, the gate electrode layer 431 in the thin film transistor 430 is also formed using a light-transmitting conductive film.
  • As a material of the gate electrode layer 431, a conductive material that transmits visible light can be used. For example, any of the following metal oxides can be used: an In—Sn—O-based metal oxide; an In—Sn—Zn—O-based metal oxide; an In—Al—Zn—O-based metal oxide; a Sn—Ga—Zn—O-based metal oxide; an Al—Ga—Zn—O-based metal oxide; a Sn—Al—Zn—O-based metal oxide; an In—Zn—O-based metal oxide; a Sn—Zn—O-based metal oxide; an Al—Zn—O-based metal oxide; an In—O-based metal oxide; a Sn—O-based metal oxide; and a Zn—O-based metal oxide. The thickness thereof is set in the range of greater than or equal to 50 nm and less than or equal to 300 nm as appropriate. As a deposition method of the metal oxide used for the gate electrode layer 431, a sputtering method, a vacuum evaporation method (an electron beam evaporation method or the like), an arc discharge ion plating method, or a spray method is used. When a sputtering method is employed, it is preferable that deposition be performed using a target containing SiO2 at 2 wt % to 10 wt % both inclusive and SiOx (x>0) which inhibits crystallization be contained in the light-transmitting conductive film so as to prevent crystallization at the time of heat treatment for dehydration or dehydrogenation in a later step.
  • In this manner, the thin film transistor 430 can be formed as a light-transmitting thin film transistor.
  • In a pixel provided with the thin film transistor 430, the pixel electrode layer 427, another electrode layer (such as a capacitor electrode layer), or a wiring layer (such as a capacitor wiring layer) is formed using a conductive film that transmits visible light, so that a display device having a high aperture ratio is realized. Needless to say, it is preferable to use films that transmit visible light to form the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408.
  • In this specification, a film that transmits visible light means a film having a thickness at which the transmittance of visible light is 75% to 100%. In the case where the film has conductivity, the film is also referred to as a transparent conductive film. Further, a conductive film that is semi-transparent to visible light may be used as a metal oxide applied to the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, or another electrode layer or another wiring layer. Semi-transparency to visible light means that the transmittance of visible light is 50% to 75%.
  • Since the thin film transistor 430 has light-transmitting properties, the aperture ratio can be improved. Particularly for small liquid crystal display panels of 10 inches or smaller, a high aperture ratio can be achieved even when the size of a pixel is decreased in order to realize higher definition of display images by increasing the number of gate wirings, for example. Further, by using a light-transmitting film for a component in the thin film transistor 430, a high aperture ratio can be achieved even when one pixel is divided into a plurality of sub-pixels in order to realize a wide viewing angle. That is, a high aperture ratio can be maintained even when a group of high-density thin film transistors is arranged, and the display region can have a sufficient area. For example, in the case where one pixel includes two to four sub-pixels, the aperture ratio can be improved because the thin film transistor has light-transmitting properties. Further, a storage capacitor may be formed using the same material by the same step as the component in the thin film transistor so that the storage capacitor can have light-transmitting properties, by which the aperture ratio can be further improved.
  • This embodiment can be implemented combining with another embodiment as appropriate.
  • Embodiment 5
  • In Embodiment 5, an example which is different from Embodiment 1 in the manufacturing process of a thin film transistor will be described with reference to FIG. 8. FIG. 8 is the same as FIGS. 1A1, 1A2, and FIG. 1B and FIGS. 2A to 2F except that there is a difference in part of the process; therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted.
  • In accordance with Embodiment 1, a gate wiring layer 421 and a gate electrode layer 471 are formed over a substrate 400, and a gate insulating layer 402 is stacked thereover.
  • Next, an oxide semiconductor film is formed, and is processed into an island-shaped oxide semiconductor layer by a photolithography step.
  • Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 425° C. Note that in the case where the temperature is 425° C. or higher, the heat treatment time may be one hour or less, whereas in the case where the temperature is lower than 425° C., the heat treatment time is longer than one hour. In this embodiment, the substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere, and then water and hydrogen are prevented from entering the oxide semiconductor layer with the oxide semiconductor layer not exposed to air. In this manner, an oxide semiconductor layer is obtained. After that, a high-purity oxygen gas, a high-purity N2O gas, or an ultra-dry air (with a dew point of −40° C. or less, preferably −60° C. or less) is introduced into the same furnace and cooling is performed. It is preferable that water, hydrogen, and the like be included as less as possible in the oxygen gas or the N2O gas. Alternatively, it is preferable that the oxygen gas or the N2O gas introduced into the heat treatment apparatus have a purity of 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (that is, the impurity concentration in the oxygen gas or the N2O gas be set to 1 ppm or less, more preferably 0.1 ppm or less).
  • The heat treatment apparatus is not limited to the electric furnace, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used, for example. An LRTA apparatus is an apparatus for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The LRTA apparatus may be provided with a device that heats an object to be processed by heat conduction or heat radiation from not only a lamp but also a heater such as a resistance heater. A GRTA is a method for performing heat treatment using a high-temperature gas. As the gas, an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used. Heat treatment may be performed at 600° C. to 750° C. for several minutes using an RTA method.
  • After the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at a temperature higher than or equal to 200° C. and lower than or equal to 400° C., preferably at a temperature higher than or equal to 200° C. and lower than or equal to 300° C., in an oxygen gas atmosphere or a N2O gas atmosphere.
  • The first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heat apparatus and a photolithography step is performed thereon.
  • Through the above process, the whole oxide semiconductor film is made into an oxygen-excess state to have higher resistance, that is, become an I-type oxide semiconductor film. Accordingly, an oxide semiconductor layer 472 whose entire region has I-type conductivity is formed.
  • Next, a resist mask is formed by a photolithography step over the oxide semiconductor layer 472, and is selectively etched to form a source electrode layer 475 a and a drain electrode layer 475 b, and then, an oxide insulating layer 407 is formed by a sputtering method.
  • Next, in order to reduce variation in electric characteristics of the thin film transistor, heat treatment may be performed in an inert gas atmosphere or a nitrogen gas atmosphere (preferably at a temperature higher than or equal to 150° C. and lower than 350° C.). For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.
  • Further, heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 200° C. for a period longer than or equal to one hour and shorter than or equal to 30 hours in air. In this embodiment, the heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature; alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature higher than or equal to 100° C. and lower than or equal to 200° C. and then decreased to room temperature. This heat treatment may be performed before the formation of the oxide insulating film under a reduced pressure. The reduced pressure enables the heat treatment time to be short. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, a normally-off thin film transistor can be obtained. Therefore, reliability of the semiconductor device can be improved.
  • Next, a protective insulating layer 408 is formed over the oxide insulating layer 407.
  • Next, a photolithography step is performed to form a resist mask, and etching is selectively performed to remove parts of the oxide insulating layer 407 and the protective insulating layer 408, so that openings reaching the source electrode layer 475 a and the drain electrode layer 475 b are formed.
  • A stacked-layer conductive layer is formed in the openings so as to be in contact with the source electrode layer 475 a and the drain electrode layer 475 b by a sputtering method or a vacuum evaporation method, and a resist mask is formed by a photolithography step. The stacked-layer conductive layer is selectively etched to form wiring layers 477 a, 477 b, 478 a, and 478 b, and source wiring layers 422 and 423 in the intersection (see FIG. 8).
  • In this manner, a semiconductor device with less parasitic capacitance and low power consumption can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • A semiconductor device with high reliability can be provided as a semiconductor device including a thin film transistor using an oxide semiconductor layer.
  • This embodiment can be implemented combining with another embodiment as appropriate.
  • Embodiment 6
  • In Embodiment 6, an example in which oxide conductive layers serving as a source and drain regions are provided between an oxide semiconductor layer and a source and drain electrode layers in Embodiment 1 will be described with reference to FIG. 9. Therefore, the same as Embodiment 1 can be applied, and the description of the same portions as Embodiment 1 and portions and steps having similar functions to Embodiment 1 are omitted. FIG. 9 is the same as FIGS. 1A1, 1A2, and FIG. 1B and FIGS. 2A to 2F except that there is a difference in part of the process; therefore, the same portions are denoted by the same reference numerals, and detailed description of the same portions is omitted.
  • A thin film transistor 469 shown in FIG. 9 is a channel-etched thin film transistor, and includes a gate electrode layer 411, a gate insulating layer 402, an oxide semiconductor layer 412 including at least a channel formation region 413, a high-resistance source region 414 a, and a high-resistance drain region 414 b, oxide conductive layers 416 a and 416 b, a source electrode layer 415 a, and a drain electrode layer 415 b over a substrate 400 having an insulating surface. Further, an oxide insulating layer 407 which covers the thin film transistor 469 and is in contact with the channel formation region 413 is provided, and a protective insulating layer 408 is provided thereover.
  • In accordance with Embodiment 1, a gate wiring layer 421 and the gate electrode layer 411 are formed over the substrate 400, and the gate insulating layer 402 is stacked thereover. An oxide semiconductor film is formed over the gate insulating layer 402 to form an oxide semiconductor layer which is dehydrated or dehydrogenated.
  • The oxide conductive layers 416 a and 416 b are formed over the dehydrated or dehydrogenated oxide semiconductor layer. Described in this embodiment is an example in which the oxide conductive layers 416 a and 416 b is processed into appropriate shapes by the same photolithography step as the oxide semiconductor layer; however, the oxide conductive layers 416 a and 416 b may be processed into the appropriate shapes by the same photolithography step as the source electrode layer and the drain electrode layer.
  • As the formation method of the oxide conductive layers 416 a and 416 b, a sputteri