JPS60198861A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS60198861A JPS60198861A JP59055518A JP5551884A JPS60198861A JP S60198861 A JPS60198861 A JP S60198861A JP 59055518 A JP59055518 A JP 59055518A JP 5551884 A JP5551884 A JP 5551884A JP S60198861 A JPS60198861 A JP S60198861A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- film transistor
- transparent
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 229910000314 transition metal oxide Inorganic materials 0.000 claims abstract description 9
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical group O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- ZNOKGRXACCSDPY-UHFFFAOYSA-N tungsten trioxide Chemical compound O=[W](=O)=O ZNOKGRXACCSDPY-UHFFFAOYSA-N 0.000 description 4
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
Abstract
Description
【発明の詳細な説明】
(11発明の技術分野
本発明は薄膜トランジスタ、詳しくはオン電流が大でメ
モリ機能をもち、透明であるなどの特徴を具備した素子
に関する。DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a thin film transistor, and more particularly, to an element having characteristics such as a large on-current, a memory function, and transparency.
・(2)技術の背景
例えば液晶表示装置の駆動のためにはアモルファス・シ
リコン(a−3i)の半導体層で作った薄膜トランジス
タ(TPT)が用いられているが、最近エレクトロクロ
ミック表示装置(EC[l)が開発されそれの駆動用T
PTの研究が進められている。・(2) Technology background For example, thin film transistors (TPT) made of amorphous silicon (a-3i) semiconductor layers are used to drive liquid crystal display devices, but recently electrochromic display devices (EC [ l) was developed and its driving T
Research on PT is underway.
(3)従来技術と問題点
ECOを駆動するTPTについて三つの問題点があるこ
とが判明した。第一に、ECDの消費電流はLC口のそ
れに比べ3桁も大なるオーダーのものである。第二に、
TPTは表示装置に用いるものであるから透明でなけれ
ばならない。第三にECUのためのTFTがメモリ機能
をもつものであれば、表示装置の各ラインに対しアドレ
スだけを与えておき、それをメモリし、後で装置の全ラ
インに着色電圧を印加することが可能になる。(3) Prior art and problems It has been found that there are three problems with the TPT that drives the ECO. First, the current consumption of the ECD is three orders of magnitude larger than that of the LC port. Secondly,
Since TPT is used for display devices, it must be transparent. Third, if the TFT for the ECU has a memory function, it is possible to give only an address to each line of the display device, store it in memory, and later apply coloring voltage to all lines of the device. becomes possible.
なお、これらの問題点はECD用のTPTに限定される
ものではない。Note that these problems are not limited to TPT for ECD.
従来のTPTには、半導体層としてa −S t %多
結晶シリコン(poly−3t ) 、セレン化カドミ
ウムCdSe。Conventional TPT includes a-St% polycrystalline silicon (poly-3T) and cadmium selenide CdSe as semiconductor layers.
テルル(Te)などを用いたものがある。このうち、a
−5tはモビリティ(移動度)が小さくオン電流が小で
あり、poly−3iはオン電流は大であるが、製造方
法が複雑であり、CdSeは移動度は満足すべきもので
あるが、橙色に着色しており、Teはオン・オフ比が小
である、などの問題がある。Some use tellurium (Te) or the like. Of these, a
-5t has low mobility and low on-current, poly-3i has high on-current but has a complicated manufacturing method, and CdSe has satisfactory mobility but has an orange color. Te has problems such as being colored and having a small on/off ratio.
上記の材料を半導体層として用いるTPTはいずれもメ
モリ性がなく、更に透明度を要求される表示装置の分野
においては、上記材料の半導体層はいずれも不透明であ
るので、応用範囲が限られるという問題があった。None of the TPTs that use the above materials as semiconductor layers have memory properties, and furthermore, in the field of display devices that require transparency, the semiconductor layers of the above materials are opaque, which limits the scope of their application. was there.
(4)発明の目的
本発明の上記従来の問題に鑑み、オン電流が大で、メモ
リ性をもち、透明であるなどの長所をもったTPTを提
供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a TPT having advantages such as a large on-current, a memory property, and transparency.
(5)発明の構成
そしてこの目的は本発明によれば、遷移金属酸化物を半
導体層として用いたことを特徴とする薄膜トランジスタ
を提供することによって達成される。(5) Structure of the Invention According to the present invention, this object is achieved by providing a thin film transistor characterized in that a transition metal oxide is used as a semiconductor layer.
(6)発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明者は、遷移金属酸化物においては、製膜方法によ
り、キャリア濃度、モビリティ膜の透明度、更に膜内で
の可動イオンの可逆的な移動などを広範囲に制御可能で
あることを利用し、オン電流が大でメモリ性をもち、透
明であるなどの特徴をもったTPTを開発した。The present inventor took advantage of the fact that in transition metal oxides, the carrier concentration, the transparency of the mobility film, and the reversible movement of mobile ions within the film can be controlled over a wide range by the film forming method. We have developed TPT with features such as high on-current, memory properties, and transparency.
より具体的に説明すると、オン電流を大にするには移動
度が高いほどよいのであるが、遷移金属酸化物の1つで
ある酸化タングステンWO3−xは一般に移動度が0.
1であるものの、作り方により酸素を減らしてその移動
度を40のオーダーに高めることは可能である。To explain more specifically, higher mobility is better in order to increase the on-current, but tungsten oxide WO3-x, which is one of the transition metal oxides, generally has a mobility of 0.
1, but it is possible to increase the mobility to the order of 40 by reducing oxygen depending on the manufacturing method.
−03が透明であることは知られているから、それを半
導体層として用いるTPTは表示装置において有益であ
る。Since -03 is known to be transparent, TPT using it as a semiconductor layer is useful in display devices.
メモリ性についていうと、電極と接続する同3の界面に
は空乏層が作られ、この中のプロトンが電極に加えられ
る電圧が十のときは界面から遠ざかって空乏層を拡げ、
電極に−の電圧が印加されるとプロトンが界面に吸い寄
せられて空乏層が薄くなることが確かめられた。Regarding memory properties, a depletion layer is created at the interface between the two electrodes, and when the voltage applied to the electrode is 0, protons move away from the interface and expand the depletion layer.
It was confirmed that when a negative voltage is applied to the electrode, protons are attracted to the interface and the depletion layer becomes thinner.
第1図に本発明の第1の実施例が、そのla)には平面
図で示され、またその(blには(alにおいて点線で
囲んだ1画素の断面図が示される。図示の例においては
、半導体層に遷移金属酸化物すなわら酸化タングステン
(WO3)を、絶縁体には二酸化シリコン(5i02)
を用いた。図において、1は基板、2はゲート、3は5
i02膜、4は間3の半導体層、5はソース電極、6は
ドレイン電極、7は5i02膜を示す。A first embodiment of the present invention is shown in FIG. In this method, a transition metal oxide such as tungsten oxide (WO3) is used as the semiconductor layer, and silicon dioxide (5i02) is used as the insulator.
was used. In the figure, 1 is the substrate, 2 is the gate, 3 is 5
4 is a semiconductor layer between 3, 5 is a source electrode, 6 is a drain electrode, and 7 is a 5i02 film.
WO3膜4は、蒸着、スパッタリング、イオンブレーテ
ィング、化学気相成長法(CVD法)などの製膜法によ
り、膜中の酸素の量、結晶性が広範囲に制御可能であり
、キャリア濃度、モビリティの制御も容易である。例え
ば、リアクティブ・スパッタリング法を用いると、キャ
リア・モビリティは1〜30cII12/ν・Sのよう
に大幅に変化する。The amount of oxygen and crystallinity of the WO3 film 4 can be controlled over a wide range by film-forming methods such as vapor deposition, sputtering, ion blating, and chemical vapor deposition (CVD), and the carrier concentration and mobility can be controlled over a wide range. It is also easy to control. For example, when using a reactive sputtering method, the carrier mobility varies significantly from 1 to 30cII12/ν·S.
例えば、抵抗率50Ωcan、膜厚1μmのWO3を用
い、ゲート幅10μm1ゲート長さ300#mのTPT
を作ると、オン状態でのソース・ドレイン間の抵抗はR
= 2 X 10’Ωとなり、l0VO印加電圧に対し
て0.5mAの電流が流れる。この電流は、従来のa−
5t半導体層を用いたTPTに比して約2桁高い。For example, using WO3 with a resistivity of 50Ωcan and a film thickness of 1μm, TPT with a gate width of 10μm and a gate length of 300#m.
, the resistance between the source and drain in the on state is R
= 2 x 10'Ω, and a current of 0.5 mA flows with respect to the applied voltage of 10 VO. This current is similar to the conventional a-
This is about two orders of magnitude higher than TPT using a 5t semiconductor layer.
−〇3は透明であるため、ゲート、ドレイン、ソース電
極にインジウム酸化tJiHro)などの透明電極を用
いると、透明なTPTとなり表示応用に適する。-〇3 is transparent, so if transparent electrodes such as indium oxide (tJiHro) are used for the gate, drain, and source electrodes, it becomes a transparent TPT and is suitable for display applications.
゛W03薄膜では、前記した如く外部からの電場によっ
てプロトンを移動させることができ、膜内でのドナーの
位置、空乏層の幅をゲート電圧で制御し、電圧を切った
後も一定期間これを維持させ、メモリ性をもたせること
ができる。゛In the W03 thin film, protons can be moved by an external electric field as described above, and the position of the donor within the film and the width of the depletion layer are controlled by the gate voltage, and this continues for a certain period of time even after the voltage is turned off. It can be maintained and have memory properties.
第1図の実施例の製造方法について説明すると、基板l
上にゲート形成のための金属層を形成し、それをパクー
ニングしてゲート2を作り、次いで全面に5i02膜3
をCVO、蒸着またはスパッタリング法で堆積し、何0
3膜4をスパッタリングにより形成し、ソース電極5、
ドレイン電極6を形成し、次にレジストをリフト・オフ
してドレイン電極6の上だけのらぬように5iOz膜7
を形成する。To explain the manufacturing method of the embodiment shown in FIG.
A metal layer for gate formation is formed on top, and the gate 2 is formed by patterning it, and then a 5i02 film 3 is formed on the entire surface.
Deposited by CVO, evaporation or sputtering method,
3 film 4 is formed by sputtering, source electrode 5,
A drain electrode 6 is formed, and then the resist is lifted off and a 5iOz film 7 is formed so as not to cover only the drain electrode 6.
form.
本発明の第2の実施例は第2図(alには平面図で示さ
れ、またその(b)には1画素の断面図が示される。こ
の実施例においては、ゲート電極、ソース電極をくし型
に形成配置し、ギヤ・ノブの長さを大にして電流を更に
かせぐことができる。The second embodiment of the present invention is shown in FIG. 2(al) as a plan view, and FIG. It is arranged in a comb shape, and the length of the gear knob can be increased to generate more current.
(7ン発明の効果
以上詳細に説明した如く本発明によれば、遷移金属酸化
物をTPTの半導体層に適用することにより、オン電流
が大きく、メモリ性をもち、透明なTPTが提供される
。なお上記の例は遷移金属酸化物に−03を、また絶縁
物にSiO2を用いたが、本発明の適用範囲はその場合
に限られるものでない。(7) Effects of the Invention As described in detail above, according to the present invention, by applying a transition metal oxide to the semiconductor layer of the TPT, a transparent TPT with a large on-current and memory properties is provided. Although -03 was used as the transition metal oxide and SiO2 was used as the insulator in the above example, the scope of application of the present invention is not limited to that case.
第1図(alは本発明の第1の実施例の平面図、同図1
b)は前記実施例の1画素の断面図、第2図+alは本
発明の第2の実施例の平面図、同図1blはその実施例
の1画素の断面図である。
1一基板、2−ゲート電極、3−5iO2膜、4−−−
No a膜、5−ソース電極、6−・−ドレイン電極
、7−5iO2j!i!
第1図
第2図
/FIG. 1 (al is a plan view of the first embodiment of the present invention, FIG.
b) is a sectional view of one pixel of the embodiment, FIG. 2+al is a plan view of the second embodiment of the present invention, and FIG. 1bl is a sectional view of one pixel of the embodiment. 1-substrate, 2-gate electrode, 3-5iO2 film, 4----
No a film, 5-source electrode, 6-.-drain electrode, 7-5iO2j! i! Figure 1 Figure 2/
Claims (1)
徴とする薄膜トランジスタ。 (2)前記半導体層が酸化タングステンであることを特
徴とする特許請求の範囲第1項記載の薄膜トランジスタ
。 (3)前記半導体に生じる空乏層の幅をゲート電圧によ
り制御し、その時の空乏層幅をゲート電圧を取り去った
後も一定時間保持させる構成としたことを特徴とする特
許請求の範囲第1項記載の薄膜トランジスタ。 (4)前記半導体層が透明であることを特徴とする特許
請求の範囲第1項記載の薄1漠トランジスタ。[Claims] (11) A thin film transistor characterized in that a transition metal oxide is used as a semiconductor layer. (2) A thin film transistor according to claim 1, characterized in that the semiconductor layer is tungsten oxide. Thin film transistor. (3) The width of the depletion layer generated in the semiconductor is controlled by a gate voltage, and the width of the depletion layer at that time is maintained for a certain period of time even after the gate voltage is removed. The thin film transistor according to claim 1. (4) The thin film transistor according to claim 1, wherein the semiconductor layer is transparent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59055518A JPS60198861A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59055518A JPS60198861A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60198861A true JPS60198861A (en) | 1985-10-08 |
Family
ID=13000918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59055518A Pending JPS60198861A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60198861A (en) |
Cited By (1534)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0236526A1 (en) * | 1986-03-12 | 1987-09-16 | Itt Industries, Inc. | Optical field effect transistor |
FR2601801A1 (en) * | 1986-07-16 | 1988-01-22 | Morin Francois | ACTIVE MATRIX DISPLAY SCREEN USING HYDROGENIC AMORPHOUS SILICON CARBIDE AND METHOD OF MANUFACTURING THE SAME |
US5744864A (en) * | 1995-08-03 | 1998-04-28 | U.S. Philips Corporation | Semiconductor device having a transparent switching element |
US7333072B2 (en) * | 2003-03-24 | 2008-02-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film integrated circuit device |
KR20100088565A (en) | 2009-01-30 | 2010-08-09 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
KR20100090208A (en) | 2009-02-05 | 2010-08-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Transistor and method for manufacturing the transistor |
KR20100090641A (en) | 2009-02-06 | 2010-08-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of manufacturing the semiconductor device |
KR20100092882A (en) | 2009-02-13 | 2010-08-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device including a transistor, and manufacturing method of the semiconductor device |
KR20100092885A (en) | 2009-02-13 | 2010-08-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Transistor, semiconductor device including the transistor, and manufacturing method of the transistor and the semiconductor device |
KR20100097053A (en) | 2009-02-25 | 2010-09-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
KR20100100636A (en) | 2009-03-06 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
KR20100103414A (en) | 2009-03-13 | 2010-09-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the semiconductor device |
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