JP4332545B2 - Field effect transistor and manufacturing method thereof - Google Patents

Field effect transistor and manufacturing method thereof Download PDF

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JP4332545B2
JP4332545B2 JP2006250902A JP2006250902A JP4332545B2 JP 4332545 B2 JP4332545 B2 JP 4332545B2 JP 2006250902 A JP2006250902 A JP 2006250902A JP 2006250902 A JP2006250902 A JP 2006250902A JP 4332545 B2 JP4332545 B2 JP 4332545B2
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oxide semiconductor
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達哉 岩崎
享 林
文徳 遠藤
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キヤノン株式会社
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Description

本発明は、酸化物膜を半導体層として有する電界効果型トランジスタとその製造方法、及び表示装置に関するものである。 The present invention is a field effect transistor and manufacturing method thereof including an oxide film as a semiconductor layer, and to a display device.

近年、ZnOを主成分として用いた透明伝導性酸化物多結晶薄膜をチャネル層に用いた薄膜トランジスタ(TFT)の開発が活発に行われている(特許文献1)。 Recently, the development of thin film transistor using a transparent conductive oxide polycrystalline thin film using ZnO as the main component in the channel layer (TFT) have been actively (Patent Document 1).

上記薄膜は、低温で成膜でき、かつ可視光に透明であるため、プラスチック板やフィルムなどの基板上にフレキシブルな透明TFTを形成することが可能であるとされている。 The thin film can be formed at low temperature and is transparent to visible light, it is that it is possible to form a flexible transparent TFT on a substrate such as a plastic plate or a film.

しかし、ZnOを主成分とする化合物は室温で安定なアモルファス相を形成することができず、多結晶相になるために、多結晶粒子界面の散乱により、電子移動度を大きくすることが困難である。 However, compounds mainly composed of ZnO can not form a stable amorphous phase at room temperature, to become a polycrystalline phase, due to scattering of polycrystalline grain boundaries, it is difficult to increase the electron mobility is there. また多結晶粒子の形状や相互接続が成膜方法により大きく異なるため、TFT素子の特性がばらついてしまう。 Also the shape and interconnection of polycrystalline grains are significantly different by a film forming method causes fluctuations in characteristics of the TFT element.

最近では、In−Ga−Zn−O系のアモルファス酸化物を用いた薄膜トランジスタが報告されている(非特許文献1)。 Recently, thin film transistor using an In-Ga-Zn-O based amorphous oxide has been reported (Non-Patent Document 1). このトランジスタは、室温でプラスチックやガラス基板への作成が可能である。 This transistor can be formed on a plastic or glass substrate at room temperature. さらには、電界効果移動度が6乃至9程度でノーマリーオフ型のトランジスタ特性が得られている。 Furthermore, the field-effect mobility normally-off type transistor characteristics in the order of 6 to 9 is obtained. また、可視光に対して透明であるという特徴を有している。 Also has a characteristic of being transparent to visible light.
特開2002−76356号公報 JP 2002-76356 JP

本発明者らが、アモルファスIn−Ga−Zn−O系をはじめとする酸化物を用いた薄膜トランジスタを検討したところ、どのような組成や製造条件で作製するかにもよるが、TFTのトランジスタ特性にばらつきが生じる場合があった。 The present inventors have, was investigated thin film transistor using an oxide including an amorphous In-Ga-Zn-O-based, depending on whether manufactured in any composition and production conditions, the transistor characteristics of the TFT there are cases where variations in.

このトランジスタ特性のばらつきは、例えばディスプレイの画素回路などに用いる場合に、駆動対象となる有機LEDや液晶などの動作のばらつきの原因となる。 Variations in transistor characteristics, for example, in the case of using such a pixel circuit of the display causes variations in the operation of such an organic LED or a liquid crystal to be driven.

このばらつきの要因のひとつとして、ソース、ドレイン電極とチャネルの間に生じる寄生抵抗があげられる。 One of the factors of this variation, the source parasitic resistance between the drain electrode and the channel and the like. そこで、本発明の目的は、この寄生抵抗に起因するTFTトランジスタの特性ばらつきの低減を図ることを目的とする。 An object of the present invention aims to reduce the characteristic variation of the TFT transistor due to the parasitic resistance.

本発明の電界効果型トランジスタの製造方法は、水素又は重水素を含有するソース電極及びドレイン電極を形成する工程と、水素又は重水素を添加すると電気抵抗値が低下する酸化物半導体層を形成する工程と、前記ソース電極及びドレイン電極から前記酸化物半導体層に水素又は重水素を拡散させる工程とを備えたことを特徴とする電界効果型トランジスタの製造方法である。 Method of manufacturing a field effect transistor of the present invention forms a step of forming a source electrode and a drain electrode containing hydrogen or deuterium, the addition of hydrogen or deuterium oxide semiconductor layer whose electric resistance value decreases a step, a method for manufacturing a field effect transistor characterized by comprising a step of diffusing hydrogen or deuterium into the oxide semiconductor layer from the source electrode and the drain electrode.

また、本発明の電界効果型トランジスタは、半導体層は水素又は重水素を添加すると電気抵抗値が低下する酸化物半導体層からなり、 The field effect transistor of the present invention, the semiconductor layer is an oxide semiconductor layer whose electric resistance value decreases when the addition of hydrogen or deuterium,
前記酸化物半導体層中のソース電極及びドレイン電極に接する領域における水素又は重水素の濃度が、前記酸化物半導体層中の水素又は重水素の平均濃度に比べて大きく、かつ、前記水素又は重水素の濃度が0.1atm%乃至10atm%であることを特徴とする電界効果型トランジスタである。 The concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode of the oxide semiconductor layer is, rather large in comparison with the average concentration of hydrogen or deuterium of the oxide semiconductor layer, and the hydrogen or the heavy a field effect transistor, wherein the concentration of hydrogen is 0.1 atm% to 10 atm%.

また、本発明の表示装置は、 本願発明に係る電界効果型トランジスタと、表示素子とを含み、前記電界効果型トランジスタのソース又はドレイン電極が前記表示素子の電極に接続されている表示装置である。 The display device of the present invention, a field effect transistor according to the present invention, and a display device, or the source of the field effect transistor is a display device and a drain electrode connected to the electrode of the display element .

本発明の電界効果型トランジスタの製造方法によれば、ソース電極及びドレイン電極に含まれている水素又は重水素が酸化物半導体層中に拡散し、酸化物半導体層中のソース電極及びドレイン電極に接する領域における抵抗を低抵抗化することができる。 According to the manufacturing method of the field effect transistor of the present invention, hydrogen or deuterium is diffused into the oxide semiconductor layer is included in the source electrode and the drain electrode, a source electrode and a drain electrode in the oxide semiconductor layer it can be reduce the resistance of the resistance in the region in contact. これにより、ソース電極及びドレイン電極と酸化物半導体層との間に生じる寄生抵抗を低減することができ、優れた安定性を有する電界効果型トランジスタを実現できる。 This makes it possible to reduce the parasitic resistance between the source electrode and the drain electrode oxide semiconductor layer can be realized field effect transistors having excellent stability.

図1(a)、(b)に本発明の電界効果型トランジスタの構成例を示す。 FIG. 1 (a), shows a configuration example of a field effect transistor of the present invention (b). 図1(a)はトップゲート構造の例、図1(b)はボトムゲート構造の例である。 Example of FIG. 1 (a) top-gate structure, FIG. 1 (b) is an example of a bottom-gate structure.
図2にトップゲート型の電界効果型トランジスタの製造方法を示す。 Showing a method for manufacturing the field effect transistor having a top gate type in Figure 2.

(水素含有電極形成) (Hydrogen-containing electrode formed)
まず、図2(a)に示すような基板10に、後にソース電極11及びドレイン電極12を形成するための電極層17を形成する(図2(b))。 First, the substrate 10 as shown in FIG. 2 (a), after forming the electrode layer 17 for forming the source electrode 11 and drain electrode 12 (Figure 2 (b)). 当該層17の形成には、スパッタ法、パルスレーザー蒸着法(PLD法)、電子ビーム蒸着法、化学気層蒸着法(CVD法)等を用いることができる。 The formation of the layer 17, sputtering, pulsed laser deposition (PLD) method, an electron beam deposition method, a chemical vapor deposition (CVD), or the like can be used.
基板10には、ガラス基板、プラスチック基板、プラスチックフィルムなどを用いることができる。 The substrate 10 may be a glass substrate, a plastic substrate, or a plastic film.

電極材料は、良好な電気伝導性を有するものであれば特にこだわらない。 Electrode material is not particularly particular about as long as it has good electrical conductivity. 例えばIn :Sn、ZnOなどの酸化物導電体や、Pt、Au、Ni、Alなどの金属電極材料を用いることができる。 For example In 2 O 3: Sn, may be used or an oxide conductor such as ZnO, Pt, Au, Ni, a metal electrode material such as Al.

水素又は重水素は、後にソース電極11及びドレイン電極12を形成するための電極層17を形成した後に水素イオン注入することで添加することができる(図2(b))。 Hydrogen or deuterium can be added by hydrogen ion implantation after the formation of the electrode layer 17 for forming the source electrode 11 and drain electrode 12 after (Figure 2 (b)).

別の水素又は重水素の添加方法としては、成膜時に水素ガス又は重水素ガスを導入しながら、電極層17を形成する方法や、電極層17を形成後に水素プラズマ処理をする方法等がある。 The method of adding another hydrogen or deuterium, while introducing hydrogen gas or heavy hydrogen gas during deposition, and a method of forming an electrode layer 17, and a method of the hydrogen plasma treatment after forming the electrode layer 17 .

イオン注入法においては、H+イオン、H−イオン、D+イオン(重水素イオン)、H +イオン(水素分子イオン)などを用いることができる。 In the ion implantation, H + ions, H- ions, D + ions (deuterium ion), H 2 + ions (hydrogen molecular ion), or the like can be used.

水素プラズマ処理は、例えば平行平板型のプラズマCVD装置あるいはRIEタイプのプラズマエッチング装置を用いておこなうことができる。 Hydrogen plasma treatment can be performed using, for example, a parallel plate type plasma CVD apparatus or RIE type plasma etching apparatus.

ソース電極及びドレイン電極に添加する水素又は重水素の濃度は、1×10 19乃至1×10 22 (1/cm )程度である。 The concentration of hydrogen or deuterium is added to the source electrode and the drain electrode is about 1 × 10 19 to 1 × 10 22 (1 / cm 3).
水素濃度の測定は、SIMS(2次イオン質量分析)にて評価することができる。 Measurement of hydrogen concentration can be evaluated by SIMS (2 ion mass spectrometry).

次に、図2(c)に示すように、フォトリソグラフィー法等を用いてソース電極11及びドレイン電極12のパターンを形成する。 Next, as shown in FIG. 2 (c), to form a pattern of the source electrode 11 and the drain electrode 12 by photolithography or the like.

水素イオンの注入は、ソース電極11及びドレイン電極12のパターン形成前に限るものではなく、ソース電極11及びドレイン電極12のパターンを形成した後に水素イオン注入してもよい。 Implantation of hydrogen ions is not limited to the previous patterning of the source electrode 11 and drain electrode 12 may be a hydrogen ion implantation after forming the pattern of the source electrode 11 and the drain electrode 12.

(酸化物半導体層) (Oxide semiconductor layer)
次に、図2(d)に示すように、パターニングされたソース電極11及びドレイン電極12を有する基板上に酸化物膜からなる酸化物半導体層13を形成する。 Next, as shown in FIG. 2 (d), to form the oxide semiconductor layer 13 made of an oxide film on a substrate having a patterned source electrode 11 and drain electrode 12 were.

酸化物半導体層13の作製には、スパッタ法、パルスレーザー蒸着法(PLD法)、電子ビーム蒸着法、化学気層蒸着法(CVD法)等を用いることができる。 The manufacturing an oxide semiconductor layer 13, a sputtering method, a pulse laser deposition (PLD) method, an electron beam deposition method, a chemical vapor deposition (CVD), or the like can be used.

酸化物半導体材料は、半導体特性を有する酸化物材料で、水素又は重水素を添加すると抵抗値が下がる材料であれば特にこだわらない。 Oxide semiconductor material, an oxide material having semiconductor properties, not particularly particular about as long as the material whose resistance decreases with the addition of hydrogen or deuterium. 例えばInやZn系の酸化物が挙げられる。 For example, oxides of In and Zn systems. また、酸化物半導体層はアモルファスの酸化物からなることがこのましい。 The oxide semiconductor layer is preferably made of an amorphous oxide.

さらには、酸化物半導体材料としては、InとGaとZnを含有したアモルファス酸化物からなることが、特に、好ましい。 Furthermore, as the oxide semiconductor material, made of an amorphous oxide containing In, Ga, and Zn it is particularly preferred.

図3は、膜厚がおよそ500nmのInGaZnO 薄膜に、水素をイオン注入した際の、イオン注入量に対する電気伝導率の変化を示している。 3, the InGaZnO 4 thin film having a film thickness of approximately 500 nm, hydrogen at the time of ion implantation, shows a change in electrical conductivity for the ion implantation amount. 横軸は、単位面積あたりの水素イオンの注入量の対数表示、縦軸は抵抗率の対数表示である。 The horizontal axis, the injection amount of the logarithm of the hydrogen ion per unit area, and the vertical axis indicates the logarithm representation of resistivity. このように、アモルファス酸化物膜に水素を導入することで電気伝導度を大きくすることができる。 In this way, it is possible to increase the electrical conductivity by introducing hydrogen in the amorphous oxide film.

(ゲート絶縁層) (Gate insulating layer)
次に、図2(e)に示すように、酸化物半導体層13上にゲート絶縁層14を形成する。 Next, as shown in FIG. 2 (e), a gate insulating layer 14 on the oxide semiconductor layer 13. ゲート絶縁層14の作製には、スパッタ法、パルスレーザー蒸着法(PLD法)、電子ビーム蒸着法、化学気層蒸着法(CVD法)等を用いることができる。 The production of the gate insulating layer 14, a sputtering method, a pulse laser deposition (PLD) method, an electron beam deposition method, a chemical vapor deposition (CVD), or the like can be used.

ゲート絶縁材料としては、良好な絶縁特性を有するものであれば特にこだわらない。 The gate insulating material, not particularly particular about as long as it has good insulating properties. 例えばAl 、Y 、又はHfO の1種、又はそれらの化合物を少なくとも2種以上含む混晶化合物を用いることができる。 For example Al 2 O 3, Y 2 O 3, or HfO 2 of one kind, or these compounds can be used mixed crystal compound containing at least two kinds.

(ゲート電極) (Gate electrode)
次に、図2(f)に示すように、ゲート絶縁層14上にゲート電極15を形成する。 Next, as shown in FIG. 2 (f), to form a gate electrode 15 on the gate insulating layer 14. ゲート電極15の作製には、スパッタ法、パルスレーザー蒸着法(PLD法)、電子ビーム蒸着法、化学気層蒸着法(CVD法)等を用いることができる。 The production of the gate electrode 15, a sputtering method, a pulse laser deposition (PLD) method, an electron beam deposition method, a chemical vapor deposition (CVD), or the like can be used.

電極材料は、良好な電気伝導性を有するものであれば特にこだわらない。 Electrode material is not particularly particular about as long as it has good electrical conductivity. 例えばIn :Sn、ZnOなどの酸化物導電体や、Pt、Au、Ni、Alなどの金属電極材料を用いることができる。 For example In 2 O 3: Sn, may be used or an oxide conductor such as ZnO, Pt, Au, Ni, a metal electrode material such as Al.

ゲート電極15はフォトリソグラフィー法を用いてパターンを形成する。 The gate electrode 15 to form a pattern by photolithography. パターンを形成する位置は、ソース電極11とドレイン電極12の位置関係を考慮し、トランジスタ特性を得られる位置であればよい。 Position for forming a pattern, taking into consideration the positional relationship between the source electrode 11 and the drain electrode 12, may be a position obtained transistor characteristics.

(拡散処理) (Diffusion process)
次に、ソース電極11及びドレイン電極12に含まれる水素又は重水素を酸化物半導体層13中に拡散させる。 Then, to diffuse the hydrogen or deuterium contained in the source electrode 11 and drain electrode 12 in the oxide semiconductor layer 13.

拡散する際は、酸化物半導体層中のソース電極及びドレイン電極と接する領域における水素又は重水素の濃度が、酸化物半導体層中の水素又は重水素の平均濃度に比べて大きくなればよい。 When diffusion is the concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer may if greater than the average concentration of hydrogen or deuterium in the oxide semiconductor layer.

酸化物半導体層中のソース電極及びドレイン電極と接する領域における水素又は重水素の濃度、及び酸化物半導体層中の水素又は重水素の平均濃度は、SIMSを用いて酸化物半導体層の深さ方向の組成を分析することで求めることができる。 The concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer, and the average concentration of hydrogen or deuterium in the oxide semiconductor layer, the depth direction of the oxide semiconductor layer by SIMS it can be determined by analyzing the composition of the.

ここで、酸化物半導体層中のソース電極及びドレイン電極と接する領域とは、酸化物半導体層中におけるソース電極及びドレイン電極との界面付近のことである。 Here, the area in contact with the source electrode and the drain electrode in the oxide semiconductor layer, is that in the vicinity of the interface between the source electrode and the drain electrode in the oxide semiconductor layer. ただし、半導体特性に悪影響を及ぼさない場合は、酸化物半導体層中のソース電極及びドレイン電極と接する領域に限定することなく、ソース電極及びドレイン電極と対向するゲート絶縁層側へ水素を拡散させてもよい。 However, if that does not adversely affect the semiconductor characteristics is not limited to the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer, thereby diffusing hydrogen into the gate insulating layer side facing the source electrode and the drain electrode it may be.

また、水素又は重水素の拡散の程度は、最低限ソース電極11及びドレイン電極12と酸化物半導体層13の寄生抵抗を低減する程度であればよいが、半導体特性に悪影響を及ぼさない程度であればそれ以上の量を拡散させてもよい。 The degree of diffusion of hydrogen or deuterium, may as long as to reduce the parasitic resistance of the minimum source electrode 11 and drain electrode 12 and the oxide semiconductor layer 13, there to the extent that does not adversely affect the semiconductor properties if any further amounts may be diffused.

また、電気特性に悪影響を及ぼさない程度であれば、ソース電極11及びドレイン電極12中に水素が残留してもよい。 Further, as long as that the electrical characteristics do not adversely affect the hydrogen it may remain in the source electrode 11 and drain electrode 12.

拡散には、ランプ加熱やレーザアニールなどのアニール処理を用いる。 The diffusion, using an annealing process, such as lamp heating or laser annealing. 水素又は重水素の拡散度合いは、アニール温度とアニール時間に依存する。 Degree of diffusion of hydrogen or deuterium depends on the annealing temperature and annealing time.

拡散処理をするタイミングは、水素又は重水素を含有するソース電極11及びドレイン電極12上に酸化物半導体層13を形成した後であればいつでもよい。 Timing of the diffusion process may at any time after the formation of the oxide semiconductor layer 13 on the source electrode 11 and drain electrode 12 containing hydrogen or deuterium.

また、酸化物半導体層13形成時に基板温度を加熱しながら成膜することで、水素又は重水素を酸化物半導体13層中へと拡散することもできる。 Further, by forming while heating the substrate temperature during the oxide semiconductor layer 13 formed, it is also possible to diffuse into the oxide semiconductor 13 layers in hydrogen or deuterium.

また、ソース電極11及びドレイン電極12中に水素を多量に添加することで、アニール温度を低温化することができ、さらにはアニール処理をおこなうことなく室温程度でも酸化物半導体層13中に水素を拡散することができる。 Further, by addition of a large amount of hydrogen in the source electrode 11 and drain electrode 12 can be a low temperature of the annealing temperature, further hydrogen in the oxide semiconductor layer 13 at about room temperature without performing an annealing treatment it can diffuse.

プラスチック基板やフィルム基板などを用いる場合は、水素添加量を多めにし、アニール温度を比較的低めにするとよい。 When using a plastic substrate or a film substrate, and the generous hydrogen addition amount may be relatively low annealing temperature.

酸化物半導体層中のソース電極及びドレイン電極に接する領域での水素イオン濃度は、0.1atm%乃至10atm%、好ましくは0.5atm%乃至5atm%である。 Hydrogen ion concentration in the area in contact with the source electrode and the drain electrode in the oxide semiconductor layer, 0.1 atm% to 10 atm%, preferably from 0.5 atm% to 5 atm%. 水素イオン濃度が0.1atm%以下では酸化物半導体の抵抗値が十分に低下しない。 The resistance of the oxide semiconductor in the hydrogen ion concentration is less 0.1 atm% is not reduced sufficiently. また、水素イオン濃度が10atm%以上では、酸化物半導体の抵抗値が低下しすぎる。 The hydrogen ion concentration is more than 10 atm%, the resistance value of the oxide semiconductor is too low.

(電界効果型トランジスタ) (Field-effect transistor)
図1(a)、(b)に示す電界効果型トランジスタにおいて、10は基板、11はソース電極、12はドレイン電極、13は酸化物半導体層、14はゲート絶縁膜、15はゲート電極である。 In the field effect transistor shown in FIG. 1 (a), (b), 10 is a substrate, a source electrode 11, 12 drain electrode, 13 is an oxide semiconductor layer, 14 denotes a gate insulating film, 15 is a gate electrode . それぞれの構成要素の特徴は、上で説明したとおりである。 Characteristics of each component are as described above.

また、酸化物半導体層中のソース電極及びドレイン電極に接する領域における水素又は重水素の濃度とは、酸化物半導体層13中におけるソース電極11との界面付近、及び酸化物半導体層13中におけるドレイン電極12との界面付近、それぞれにおける水素又は重水素の濃度のことである。 Further, the concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer, the drain in the vicinity of the interface, and the oxide semiconductor layer 13 between the source electrode 11 in the oxide semiconductor layer 13 near the interface with the electrode 12, is that the concentration of hydrogen or deuterium in each.

酸化物半導体層中のソース電極及びドレイン電極に接する領域における水素又は重水素の濃度は、酸化物半導体層中の水素又は重水素の平均濃度に比べて大きな値となる。 The concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer becomes a larger value than the average concentration of hydrogen or deuterium in the oxide semiconductor layer. つまり、寄生抵抗の原因となる酸化物半導体層と電極との界面付近において、水素又は重水素の濃度が大きくなることにより寄生抵抗が低減する。 That is, in the vicinity of the interface between the oxide semiconductor layer and the electrode which causes parasitic resistance, parasitic resistance is reduced by the concentration of hydrogen or deuterium increases.

酸化物半導体層中のソース電極及びドレイン電極と接する領域における水素又は重水素の濃度、及び酸化物半導体層中の水素又は重水素の平均濃度は、SIMSを用いて酸化物半導体層の深さ方向の組成を分析することで求めることができる。 The concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode in the oxide semiconductor layer, and the average concentration of hydrogen or deuterium in the oxide semiconductor layer, the depth direction of the oxide semiconductor layer by SIMS it can be determined by analyzing the composition of the. 水素又は重水素を拡散する領域は、酸化物半導体層中のソース電極及びドレイン電極と接する領域で足りるが、半導体特性に悪影響を与えないようであれば、ソース・ドレイン電極と対向するゲート絶縁層側へ水素を拡散させてもよい。 Region for diffusing hydrogen or deuterium is sufficient in a region in contact with the source electrode and the drain electrode in the oxide semiconductor layer, as long as not adversely affect the semiconductor characteristics, source and drain electrode facing the gate insulating layer hydrogen to the side may be diffused. また、水素又は重水素の拡散の程度は、最低限ソース電極11及びドレイン電極12と酸化物半導体層13の寄生抵抗を低減する程度であればよいが、半導体特性に悪影響を及ぼさない程度であればそれ以上の量を拡散させてもよい。 The degree of diffusion of hydrogen or deuterium, may as long as to reduce the parasitic resistance of the minimum source electrode 11 and drain electrode 12 and the oxide semiconductor layer 13, there to the extent that does not adversely affect the semiconductor properties if any further amounts may be diffused.

(表示装置) (Display device)
上記電界効果型トランジスタの出力端子であるドレインに、有機又は無機のエレクトロルミネッセンス(EL)素子、液晶素子等の表示素子の電極に接続することで表示装置を構成することができる。 A drain which is an output terminal of the field effect transistor, it is possible to construct a display device by connecting an organic or inorganic electroluminescent (EL) device, the electrode of the display element such as a liquid crystal element. 以下に表示装置の断面図を用いて具体的な表示装置構成の例を説明する。 Illustrating an example of a specific display apparatus configuration using a cross-sectional view of a display device below.

たとえば図9に示すように、基体111上に、酸化物膜(チャネル層)112と、ソース電極113と、ドレイン電極114とゲート絶縁膜115と、ゲート電極116から構成される電界効果型トランジスタを形成する。 For example, as shown in FIG. 9, on a substrate 111, an oxide film (channel layer) 112, a source electrode 113, a drain electrode 114 and the gate insulating film 115, a field-effect transistor composed of a gate electrode 116 Form. そして、ドレイン電極114に、層間絶縁膜117を介して電極118が接続されており、電極118は発光層119と接し、さらに発光層119が電極120と接している。 Then, the drain electrode 114 are electrodes 118 via an interlayer insulating film 117 is connected, the electrode 118 is in contact with the light-emitting layer 119, and further the light emitting layer 119 is in contact with the electrode 120. かかる構成により、発光層119に注入する電流を、ソース電極113からドレイン電極114に酸化物膜112に形成されるチャネルを介して流れる電流値によって制御することが可能となる。 With this configuration, the current injected into the light emitting layer 119, can be controlled by a current value flowing through the channel formed in the oxide film 112 from the source electrode 113 to the drain electrode 114. したがってこれを電界効果型トランジスタのゲート電極116の電圧によって制御することができる。 Thus this can be controlled by the voltage of the gate electrode 116 of the field effect transistor. ここで、電極118、発光層119、電極120は無機もしくは有機のエレクトロルミネッセンス素子を構成する。 Here, the electrode 118, light emitting layer 119, the electrode 120 constitute the electroluminescent device of the inorganic or organic.

あるいは、図10に示すように、ドレイン電極114が延長されて電極118を兼ねており、これを高抵抗膜121、122に挟まれた液晶セルや電気泳動型粒子セル123へ電圧を印加する電極118とする構成を取ることができる。 Alternatively, as shown in FIG. 10, the drain electrode 114 also serves as the electrode 118 is extended, the electrode for applying a voltage to it to the liquid crystal cell or electrophoretic particle cell 123 sandwiched between high resistance films 121 and 122 it is possible to take a configuration in which the 118. 液晶セルや電気泳動型粒子セル123、高抵抗層121及び122、電極118、電極120は表示素子を構成する。 A liquid crystal cell or electrophoretic particle cell 123, the high resistance layer 121 and 122, the electrode 118, the electrode 120 constitute display elements. これら表示素子に印加する電圧を、ソース電極113からドレイン電極114に非晶質酸化物半導体膜112に形成されるチャネルを介して流れる電流値によって制御することが可能となる。 The voltage applied to these display elements can be controlled by a current value flowing through the channel formed in the amorphous oxide semiconductor film 112 from the source electrode 113 to the drain electrode 114. したがってこれをTFTのゲート電極116の電圧によって制御することができる。 Thus this can be controlled by the voltage of the gate electrode 116 of the TFT. ここで表示素子の表示媒体が流体と粒子を絶縁性被膜中に封止したカプセルであるなら、高抵抗膜121、122は不要である。 If a capsule display medium of the display element is sealed fluid and particles in the insulating film where the high-resistance films 121 and 122 are unnecessary.

上記電界効果型トランジスタの出力端子であるドレインに、有機又は無機のエレクトロルミネッセンス(EL)素子、液晶素子等の表示素子の電極に接続することで表示装置を構成することができる。 A drain which is an output terminal of the field effect transistor, it is possible to construct a display device by connecting an organic or inorganic electroluminescent (EL) device, the electrode of the display element such as a liquid crystal element.

EL素子(ここでは有機EL素子)と電界効果型トランジスタを含む画素を二次元状に配置した表示装置について図11を用いて説明する。 The display device in which pixels arranged in a two-dimensional shape that includes an EL element and a field effect transistor (organic EL element in this case) will be described with reference to FIG. 11.

図11において、181は有機EL層184を駆動するトランジスタであり、182は画素を選択するトランジスタである。 11, 181 is a transistor for driving the organic EL layer 184, 182 is a transistor for selecting a pixel. また、コンデンサ183は選択された状態を保持するためのものであり、共通電極線187とトランジスタ182のソース部分との間に電荷を蓄え、トランジスタ181のゲートの信号を保持している。 The capacitor 183 is for holding the selected state, an electric charge is charged between the source portion of the common electrode line 187 and the transistor 182, holding the gate signal of the transistor 181. 画素選択は走査電極線185と信号電極線186により決定される。 Pixel selection is determined by scanning electrode lines 185 and the signal electrode line 186.

より具体的に説明すると、画像信号がドライバ回路(不図示)から走査電極185を通してゲート電極へパルス信号で印加される。 To be more specific, the image signal is applied as a pulse signal to the gate electrode through the scanning electrode 185 from the driver circuit (not shown). それと同時に、別のドライバ回路(不図示)から信号電極186を通してやはりパスル信号でトランジスタ182へと印加されて画素が選択される。 At the same time, a pixel is selected is applied to the transistor 182 again Pasuru signal through the signal electrode 186 from another driver circuit (not shown). そのときトランジスタ182がONとなり信号電極線186とトランジスタ182のソースの間にあるコンデンサ183に電荷が蓄積される。 Then the transistor 182 charges the capacitor 183 located between the source of the turned ON signal electrode line 186 and the transistor 182 are accumulated. これによりトランジスタ181のゲート電圧が所望の電圧に保持されトランジスタ181はONになる。 Thus the gate voltage of the transistor 181 is maintained at a desired voltage transistor 181 is turned ON. この状態は次の信号を受け取るまで保持される。 This state is held until a next signal is received. トランジスタ181がONである状態の間、有機EL層184には電圧、電流が供給され続け発光が維持されることになる。 During state transistor 181 is ON, the voltage, so that the emission current are continuously fed is maintained in the organic EL layer 184.

この図11の例では1画素にトランジスタ2ヶコンデンサー1ヶの構成であるが、性能を向上させるために更に多くのトランジスタ等を組み込んでも構わない。 In the example of FIG. 11 is two transistors and one capacitor structure in one pixel, but may incorporate more transistors or the like in order to improve the performance.

図2に、トップゲート型の電界効果型トランジスタの作製例を示す。 Figure 2 illustrates the production of a field effect transistor having a top gate type.
まず、図2(a)に示すガラス基板10(コーニング社製1737)上に、図2(b)に示すように後にソース電極及びドレイン電極を形成するための電極層17をスパッタ法により形成する。 First, on a glass substrate 10 shown in FIG. 2 (a) (Corning 1737), to form an electrode layer 17 for forming a source electrode and a drain electrode later as shown in FIG. 2 (b) by a sputtering method . 電極材料にはITO(Indium Tin Oxide)を用い、膜厚は50nmとする。 The electrode material used ITO (Indium Tin Oxide), the film thickness is set to 50nm.

次に、イオン注入法によりITO電極中に水素を添加する。 Next, hydrogen is added into the ITO electrode by ion implantation. 注入イオンはH を使用し、注入エネルギーは5keV、水素イオン照射量は1×10 16 (1/cm )とする。 Implanted ions using H 2, the implantation energy is 5 keV, hydrogen ion dose is set to 1 × 10 16 (1 / cm 2). このイオン注入条件での水素濃度は1×10 21 (1/cm )程度と見積もられる。 The hydrogen concentration in the ion implantation condition is estimated to be 1 × 10 21 (1 / cm 3) degree.

その後、図2(c)に示すように、フォトリソグラフィー技術とエッチング技術とを用いて電極をパターニングし、ソース電極11及びドレイン電極12とする。 Thereafter, as shown in FIG. 2 (c), an electrode is patterned by a photolithography technique and an etching technique, and the source electrode 11 and the drain electrode 12.

次に、図2(d)に示すように、ソース電極11及びドレイン電極12を有するガラス基板上にIn−Zn−Ga−O系アモルファス酸化物半導体層13を50nm形成する。 Next, as shown in FIG. 2 (d), an In-Zn-Ga-O-based amorphous oxide semiconductor layer 13 on a glass substrate having a source electrode 11 and drain electrode 12 to 50nm formed. 当該酸化物半導体層は、RFスパッタ装置を用いて基板温度は室温(25℃)で形成する。 The oxide semiconductor layer, the substrate temperature by using an RF sputtering apparatus to form at room temperature (25 ° C.). ターゲットは3インチサイズのIn ・ZnO組成を有する多結晶焼結体を用い、投入RFパワーは200Wとする。 Target using a polycrystalline sintered body having a In 2 O 3 · ZnO composition 3-inch size, the applied RF power was 200 W. 成膜時の雰囲気は、全圧0.5Paであり、その際のガス流量はAr:O =95:5である。 Atmosphere during film formation, the total pressure 0.5 Pa, the gas flow rate at that time is Ar: O 2 = 95: 5.
次に、図2(e)及び(f)に示すように、ゲート絶縁層14とゲート電極15を形成する。 Next, as shown in FIG. 2 (e) and (f), a gate insulating layer 14 and the gate electrode 15.

ゲート絶縁層材料にはSiO を用い、スパッタ法により150nm堆積させる。 The SiO 2 used for the gate insulating layer material, is 150nm by sputtering. また、フォトリソグラフィー法とリフトオフ法により、ゲート絶縁層14をパターニング形成する。 Further, by photolithography and a lift-off method, the gate insulating layer 14 patterned.

ゲート電極材料にはAuを用い、電子ビーム蒸着法により30nm堆積させる。 Using Au for the gate electrode material, it is 30nm deposited by electron beam evaporation. また、フォトリソグラフィー法とリフトオフ法により、ゲート電極15をパターニング形成する。 Further, by photolithography and a lift-off method, the gate electrode 15 patterned.

次に、電気炉を用いて大気圧で150℃、20分間アニール処理をし、水素を酸化物半導体膜中に拡散させる。 Then, 0.99 ° C. at atmospheric pressure in an electric furnace, a 20 min annealing, to diffuse the hydrogen into the oxide semiconductor film.

本実施例により作製した電界効果型トランジスタは、ヒステリシス特性、均一性、高速動作性等に関して良好な特性を実現できる。 Field effect transistor manufactured according to this embodiment, the hysteresis characteristics, uniformity, excellent characteristics with regard to high-speed operability, and the like can be realized.

(比較例1) (Comparative Example 1)
水素を含む電極から酸化物半導体膜中へ水素を拡散させることで、酸化物半導体と電極との寄生抵抗が低下することを以下の比較例で説明する。 By diffusing hydrogen from the electrode containing the hydrogen to the oxide semiconductor film, the parasitic resistance between the oxide semiconductor and the electrode are described in the following comparative example a decrease.

ガラス基板(コーニング社製1737)上にITO電極をスパッタ法により125nm成膜する。 The ITO electrode on a glass substrate (Corning Corporation product 1737) is 125nm formed by sputtering.

次に、イオン注入法によりITO電極中に水素を添加する。 Next, hydrogen is added into the ITO electrode by ion implantation. 注入イオンはH を使用し、注入エネルギーは5keV、水素イオン照射量は1×10 16 (1/cm )とする。 Implanted ions using H 2, the implantation energy is 5 keV, hydrogen ion dose is set to 1 × 10 16 (1 / cm 2). このイオン注入条件での水素濃度は1×10 21 (1/cm )程度と見積もられる。 The hydrogen concentration in the ion implantation condition is estimated to be 1 × 10 21 (1 / cm 3) degree.

次に、水素イオンを含むITO電極上に、In−Zn−Ga−O系アモルファス酸化物半導体層を50nm形成する。 Next, on the ITO electrode containing hydrogen ions to 50nm form an In-Zn-Ga-O-based amorphous oxide semiconductor layer. 当該酸化物半導体膜は、RFスパッタ装置を用いて基板温度は室温(25℃)で形成する。 The oxide semiconductor film, the substrate temperature by using an RF sputtering apparatus to form at room temperature (25 ° C.). ターゲットは3インチサイズのIn ・ZnO組成を有する多結晶焼結体を用い、投入RFパワーは200Wとする。 Target using a polycrystalline sintered body having a In 2 O 3 · ZnO composition 3-inch size, the applied RF power was 200 W. 成膜時の雰囲気は、全圧0.5Paであり、その際のガス流量はAr:O =95:5である。 Atmosphere during film formation, the total pressure 0.5 Pa, the gas flow rate at that time is Ar: O 2 = 95: 5.

次に、電気炉を用いて各サンプルを大気圧でそれぞれ150℃、300℃で20分間アニール処理をし、水素を酸化物半導体膜中に拡散させる。 Then, 0.99 ° C. respectively each sample using an electric furnace at atmospheric pressure, then for 20 minutes annealing at 300 ° C., thereby diffusing hydrogen into the oxide semiconductor film.

次に、φ300μmのマスクを用いて、上部電極を電子ビーム蒸着法により30nm堆積させる。 Next, using a mask Fai300myuemu, the upper electrode is 30nm deposited by electron beam evaporation.

このようにして得られたサンプルの寄生抵抗を比較するために、I−V特性を測定し抵抗値を求める。 To compare the parasitic resistance of the samples obtained in this way, we obtain the resistance value was measured the I-V characteristic. 当該サンプルのアニール温度と抵抗値との関係を図6に示す。 The relationship between the sample of the annealing temperature and the resistance value shown in FIG. また比較例として、水素を含まない電極に接する酸化物半導体層を形成した複数のサンプルを作製し、一つは室温(25℃)に置き、他はそれぞれ150℃及び300℃でアニールした後、各サンプルの寄生抵抗の値を測定した。 In addition, as a comparative example, to prepare a plurality of samples forming the oxide semiconductor layer in contact with the electrode containing no hydrogen, one placed at room temperature (25 ° C.), after others were annealed at 0.99 ° C. and 300 ° C., respectively, the value of the parasitic resistance of each sample was measured. 当該結果を図7に示す。 The results shown in FIG. それぞれのグラフの抵抗値は、室温(25℃)での値を1として規格化している。 The resistance of each graph are normalized values ​​at room temperature (25 ° C.) as a 1. 水素を含む電極の場合は、アニール温度が室温、150℃、300℃になるにしたがい寄生抵抗の値は低下する。 For electrode containing hydrogen, the annealing temperature is room temperature, 0.99 ° C., the value of parasitic resistance in accordance becomes 300 ° C. is reduced. これに対して、水素を含まない電極の場合は、アニール温度が、室温、150℃、300℃と変化させても寄生抵抗の低下は確認できなかった。 In contrast, in the case of electrodes containing no hydrogen, annealing temperature, room temperature, reduction in the parasitic resistance even 0.99 ° C., it is changed from 300 ° C. was not confirmed.

図8に、上述した方法で作製した素子のSIMSによる水素濃度の測定結果を示す。 Figure 8 shows the results of measurement of the hydrogen concentration by SIMS of device produced by the method described above. 図8の(a)は水素を含まない電極を用いた場合のデータ、(b)は水素を含む電極を用いた場合のデータ(アニール温度は150℃)である。 (A) data for the case of using the electrode containing no hydrogen in FIG. 8, a (b) data in the case of using the electrode containing hydrogen (annealing temperature 0.99 ° C.). 図8の横軸(深さ)の0乃至50nmが酸化物半導体であり、それより深い部分は電極である。 0 to 50nm on the horizontal axis (depth) of FIG. 8 is an oxide semiconductor, deeper than is electrode. この結果から、(a)よりも(b)のほうが酸化物半導体層中において水素を多く含むことが確認できた。 This result was confirmed to contain much hydrogen in the oxide semiconductor layer is more also (b) from (a). これにより、電極に水素を含む電極を用い150℃でアニールすると、酸化物半導体膜中に水素が拡散することが確認できた。 Thus, when annealed at 0.99 ° C. using an electrode containing hydrogen electrode, hydrogen is confirmed to be diffused into the oxide semiconductor film.

図4にトップゲート型の電界効果型トランジスタの作製例を示す。 It illustrates the production of a field effect transistor having a top gate type in FIG.
まず、図4(a)に示すガラス基板10(コーニング社製1737)上に、図4(b)に示すように、後にソース電極及びドレイン電極を形成するための電極層17をスパッタ法により形成する。 First, formed on a glass substrate 10 (Corning 1737), as shown in FIG. 4 (b), an electrode layer 17 for forming a source electrode and a drain electrode later by a sputtering method as shown in FIGS. 4 (a) to. 電極は、ガラス基板10上にTiを5nm成膜した後、Pt電極を50nm成膜する。 Electrodes, after 5nm film of Ti on the glass substrate 10, for 50nm deposited Pt electrode.

Ptをスパッタする際は、H ガスとArガスの流量比が3%程度となるように、Arガスおよび水素ガスを導入する。 When sputtering the Pt, as in the flow rate ratio of the H 2 gas and Ar gas is about 3%, introducing the Ar gas and hydrogen gas.

その後、図4(c)に示すように、フォトリソグラフィー技術とエッチング技術とを用いて電極をパターニングし、ソース電極10及びドレイン電極12とする。 Thereafter, as shown in FIG. 4 (c), an electrode is patterned by a photolithography technique and an etching technique, and the source electrode 10 and the drain electrode 12.

次に、図4(d)に示すように、ソース電極11及びドレイン電極12を有するガラス基板上にIn−Zn−Ga−O系アモルファス酸化物半導体層13を50nm形成する。 Next, as shown in FIG. 4 (d), an In-Zn-Ga-O-based amorphous oxide semiconductor layer 13 on a glass substrate having a source electrode 11 and drain electrode 12 to 50nm formed. 酸化物半導体膜は、RFスパッタ装置を用いて基板温度は室温(25℃)で形成する。 The oxide semiconductor film, the substrate temperature by using an RF sputtering apparatus to form at room temperature (25 ° C.). ターゲットは3インチサイズのIn ・ZnO組成を有する多結晶焼結体を用い、投入RFパワーは200Wとする。 Target using a polycrystalline sintered body having a In 2 O 3 · ZnO composition 3-inch size, the applied RF power was 200 W. 成膜時の雰囲気は、全圧0.5Paであり、その際のガス流量はAr:O =95:5である。 Atmosphere during film formation, the total pressure 0.5 Pa, the gas flow rate at that time is Ar: O 2 = 95: 5.

次に、図4(e)及び(f)に示すように、ゲート絶縁層とゲート電極を形成する。 Next, as shown in FIG. 4 (e) and (f), a gate insulating layer and the gate electrode.
ゲート絶縁層材料にはSiO を用い、スパッタ法により150nm堆積させる。 The SiO 2 used for the gate insulating layer material, is 150nm by sputtering. また、フォトリソグラフィー法とリフトオフ法により、ゲート絶縁層14をパターニング形成する。 Further, by photolithography and a lift-off method, the gate insulating layer 14 patterned.

ゲート電極材料にはAuを用い、電子ビーム蒸着法により30nm堆積させる。 Using Au for the gate electrode material, it is 30nm deposited by electron beam evaporation. また、フォトリソグラフィー法とリフトオフ法により、ゲート電極15をパターニング形成する。 Further, by photolithography and a lift-off method, the gate electrode 15 patterned.

次に、図4(g)に示すように、基板裏側からレーザー16を照射し、ソース電極11及びドレイン電極12部分を加熱して、水素を酸化物半導体層13中に拡散させる。 Next, as shown in FIG. 4 (g), the laser 16 is irradiated from the back side of the substrate, and heating the source electrode 11 and drain electrode 12 partially, to diffuse into the oxide semiconductor layer 13 of hydrogen.

レーザーには、XeClエキシマレーザー(波長308nm)を用い、エネルギー出力は500mJ/パルスで、パルス幅は100nsとする。 The laser using XeCl excimer laser (wavelength 308 nm), the energy output is 500 mJ / pulse, the pulse width is set to 100 ns.

レーザーにはこれ以外にKrFエキシマレーザー(波長248nm)、ArFエキシマレーザー(波長193nm)、XeFエキシマレーザー(波長353nm)などを用いることができる。 KrF excimer laser thereto except laser (wavelength 248 nm), ArF excimer laser (wavelength 193 nm), etc. can be used XeF excimer laser (wavelength 353 nm).

本実施例により作製した電界効果型トランジスタは、ヒステリシス特性、均一性、高速動作性等に関して良好な特性を実現できる。 Field effect transistor manufactured according to this embodiment, the hysteresis characteristics, uniformity, excellent characteristics with regard to high-speed operability, and the like can be realized.

図5にボトムゲート型の電界効果型トランジスタの作製例を示す。 It illustrates the production of a field effect transistor having a bottom gate type in FIG.
まず、図5(a)に示すような基板10(コーニング社製1737)上に、フォトリソグラフィー技術とエッチング技術を用いてゲート電極15をパターニング形成する(図5(b))。 First, on the substrate 10 as shown in FIG. 5 (a) (Corning 1737), the gate electrode 15 is patterned by photolithography and etching (Figure 5 (b)). 電極はガラス基板10上にスパッタ法を用いてTi(5nm)、Pt(50nm)の順に形成する。 Electrodes are formed in order of Ti by sputtering on the glass substrate 10 (5nm), Pt (50nm).

次に、図5(c)に示すように、フォトリソグラフィー技術とエッチング技術を用いて、ゲート絶縁膜14をパターニング形成する。 Next, as shown in FIG. 5 (c), by using photolithography and etching techniques, the gate insulating film 14 patterned. ゲート絶縁膜14はスパッタ法を用いて150nmのSiO 膜を成膜する。 The gate insulating film 14 is a SiO 2 film of 150nm by sputtering.

さらに、図5(d)に示すように、フォトリソグラフィー技術とエッチング技術を用いて、酸化物半導体膜13をパターニング形成する。 Furthermore, as shown in FIG. 5 (d), by using a photolithography technique and an etching technique, patterning the oxide semiconductor film 13. 酸化物半導体膜13には、50nmのIn−Zn−Ga−O系アモルファス酸化物半導体材料を用いる。 The oxide semiconductor film 13, using 50nm of In-Zn-Ga-O type amorphous oxide semiconductor material.

酸化物半導体膜は、RFスパッタ装置を用いて基板温度は室温(25℃)で形成する。 The oxide semiconductor film, the substrate temperature by using an RF sputtering apparatus to form at room temperature (25 ° C.). ターゲットは3インチサイズのIn ・ZnO組成を有する多結晶焼結体を用い、投入RFパワーは200Wとする。 Target using a polycrystalline sintered body having a In 2 O 3 · ZnO composition 3-inch size, the applied RF power was 200 W. 成膜時の雰囲気は、全圧0.5Paであり、その際のガス流量はAr:O =95:5である。 Atmosphere during film formation, the total pressure 0.5 Pa, the gas flow rate at that time is Ar: O 2 = 95: 5.

次に、図5(e)に示すように、フォトリソグラフィー技術とエッチング技術を用いて、ドレイン電極とソース電極を形成する。 Next, as shown in FIG. 5 (e), using photolithography and etching techniques to form the drain and source electrodes. ドレイン電極とソース電極にはTi(5nm)とPt(50nm)を用いる。 The drain and source electrodes using Pt (50 nm) and Ti (5 nm). 電極形成にはスパッタ法を用いる。 The electrode formation by sputtering. 電極形成時に電極材料中へ水素を添加するために、スパッタする際はH ガスとArガスの流量比が3%程度となるように、Arガスおよび水素ガスを導入する。 To add hydrogen to the electrode material at the time of electrode formation, when sputtering as the flow rate ratio of the H 2 gas and Ar gas is about 3%, introducing the Ar gas and hydrogen gas.

次に、電気炉を用いて大気圧で150℃、20分間アニール処理をし、水素を酸化物半導体膜中に拡散させる。 Then, 0.99 ° C. at atmospheric pressure in an electric furnace, a 20 min annealing, to diffuse the hydrogen into the oxide semiconductor film.

本実施例により作製した電界効果型トランジスタは、ヒステリシス特性、均一性、高速動作性等に関して良好な特性を実現できる。 Field effect transistor manufactured according to this embodiment, the hysteresis characteristics, uniformity, excellent characteristics with regard to high-speed operability, and the like can be realized.

本実施例ではトップゲート型のTFTを用いた表示装置について説明する。 In this embodiment a description will be given of a display device using a top-gate type of a TFT. TFTの製造工程は上記実施例1または2と同様である。 Manufacturing process of the TFT is the same as Example 1 or 2. 上記TFTにおいて、ドレイン電極をなすITO膜の島の短辺を100μmまで延長し、延長された90μmの部分を残し、ソース電極およびゲート電極への配線を確保した上で、TFTを絶縁層で被覆する。 In the TFT, a short side of the island of the ITO film constituting the drain electrode is extended to 100 [mu] m, leaving a portion of the extended 90 [mu] m, while securing the wiring to the source electrode and the gate electrode, the TFT is covered with an insulating layer to. この上にポリイミド膜を塗布し、ラビング工程を施す。 A polyimide film is applied onto, subjected to a rubbing process.

一方で、同じくプラスチック基板上にITO膜とポリイミド膜を形成し、ラビング工程を施したものを用意し、上記TFTを形成した基板と5μmの空隙を空けて対向させ、ここにネマチック液晶を注入する。 On the other hand, also to form an ITO film and a polyimide film on a plastic substrate, prepared that has been subjected to a rubbing process, it is opposed at a gap between the substrate and 5μm formed with the TFT, wherein the injecting a nematic liquid crystal . さらにこの構造体の両側に一対の偏光板を設ける。 Further, a pair of polarizing plates on both sides of the structure. ここで、TFTのソース電極に電圧を印加し、ゲート電極の印加電圧を変化させると、ドレイン電極から延長されたITO膜の島の一部である30μm×90μmの領域のみ、光透過率が変化する。 Here, a voltage is applied to the source electrode of the TFT, when changing the voltage applied to the gate electrode, only the region of 30 [mu] m × 90 [mu] m which is a part of the island of the ITO film extended from the drain electrode, light transmittance changes to. またその透過率は、TFTがオン状態となるゲート電圧の下ではソース−ドレイン間電圧によっても連続的に変化させることができる。 The transmittance thereof is under the gate voltage where the TFT is turned on source - can also be continuously changed by the drain voltage. このようにして、図9に対応した、液晶セルを表示素子とする表示装置を作成する。 In this manner, corresponding to FIG. 9, to create a display device to display elements of the liquid crystal cell.

本実施例において、TFTを形成する基板として白色のプラスチック基板を用い、TFTの各電極を金に置き換え、ポリイミド膜と偏光板を廃する構成とする。 In this example, a white plastic substrate is used as the substrate for forming the TFT, replace each electrode of the TFT in gold, a configuration in which the waste a polyimide film and the polarizing plate. そして、白色と透明のプラスチック基板の空隙に粒子と流体を絶縁性皮膜にて被覆したカプセルを充填させる構成とする。 Then, a configuration of filling the capsule particles and the fluid in the gap white and transparent plastic substrates was coated with an insulating coating. この構成の表示装置の場合、本TFTによって延長されたドレイン電極と上部のITO膜間の電圧が制御され、よってカプセル内の粒子が上下に移動する。 For the display device of this configuration, the voltage between the extended drain electrode and the top of the ITO film by the TFT is controlled, the particles in the capsule moves up and down. それによって、透明基板側から見た延長されたドレイン電極領域の反射率を制御することで表示を行うことができる。 Thereby, it is possible to perform display by controlling the reflectivity of the extended drain electrode region seen from the transparent substrate side.

また、本実施例において、TFTを複数隣接して形成して、たとえば、通常の4トランジスタ1キャパシタ構成の電流制御回路を構成し、その最終段トランジスタのひとつを図6のTFTとして、EL素子を駆動することもできる。 Further, in this embodiment, be formed by a plurality adjacent TFT, for example, constitute a current control circuit of the conventional four-transistor one-capacitor configuration, one of the final stage transistor as TFT of FIG. 6, the EL element it is also possible to drive. たとえば、上述のITO膜をドレイン電極とするTFTを用いる。 For example, using a TFT having a drain electrode of ITO film described above. そして、ドレイン電極から延長されたITO膜の島の一部である30μm×90μmの領域に電荷注入層と発光層からなる有機エレクトロルミネッセンス素子を形成する。 Then, an organic electroluminescence element in the region of 30 [mu] m × 90 [mu] m which is a part of the island of the ITO film extended from the drain electrode a light emitting layer and a charge injection layer. こうして、EL素子を用いる表示装置を形成することができる。 Thus, it is possible to form a display device using an EL element.

実施例4の表示素子とTFTとを二次元に配列させる。 Aligning the display device and the TFT of Example 4 in two dimensions. たとえば、実施例4の液晶セルやEL素子等の表示素子と、TFTとを含めて約30μm×115μmの面積を占める画素を、短辺方向に40μmピッチ、長辺方向に120μmピッチでそれぞれ7425×1790個方形配列する。 For example, a display element such as a liquid crystal cell or an EL device of Example 4, a pixel that occupies an area of ​​about 30 [mu] m × 115 .mu.m including a TFT, 40 [mu] m pitch in the short side direction, respectively 7425 × at 120μm pitch in the long side direction 1790 or be square array. そして、長辺方向に7425個のTFTのゲート電極を貫くゲート配線を1790本、1790個のTFTのソース電極が非晶質酸化物半導体膜の島から5μmはみ出した部分を短辺方向に貫く信号配線を7425本設ける。 Then, 1790 present a gate wiring through the gate electrode of the 7425 pieces of TFT in the long side direction, 1790 pieces of signal source electrode of the TFT through the 5μm surplus part from the island of the amorphous oxide semiconductor film in the short side direction wiring the 7425 this provision. そして、それぞれをゲートドライバ回路、ソースドライバ回路に接続する。 Then, to connect the respective gate driver circuit and a source driver circuit. さらに液晶表示素子の場合、液晶表示素子と同サイズで位置を合わせRGBが長辺方向に反復するカラーフィルタを表面に設ければ、約211ppiでA4サイズのアクティブマトリクス型カラー画像表示装置を構成することができる。 Further, in the case of the liquid crystal display device, by providing the color filter RGB align the liquid crystal display device of the same size is repeated in the long side direction to the surface, constituting the active matrix color image display apparatus of A4 size approximately 211ppi be able to.

また、EL素子においても、ひとつのEL素子に含まれる2TFTのうち第一TFTのゲート電極をゲート線に配線し、第二TFTのソース電極を信号線に配線し、さらに、EL素子の発光波長を長辺方向にRGBで反復させる。 Also in the EL element, the gate electrode of the first TFT of the 2TFT included in one EL device is wired to the gate line, and route the source electrode of the second TFT to the signal line, further, the emission wavelength of the EL element the is repeated in RGB in the long side direction. こうすることで、同じ解像度の発光型カラー画像表示装置を構成することができる。 Thereby, it is possible to construct a light emission type color image display device of the same resolution.

ここで、アクティブマトリクスを駆動するドライバ回路は、画素のTFTと同じ本発明のTFTを用いて構成しても良いし、既存のICチップを用いても良い。 Here, the driver circuit for driving the active matrix may be formed by using the TFT of the same invention as the TFT of the pixel, may be used existing IC chip.

本発明に係る電界効果型トランジスタは、LCDや有機ELディスプレイのスイッチング素子として応用することができる。 Field effect transistor according to the present invention can be applied as a switching element of an LCD or organic EL display. また、プラスチックフィルムをはじめとするフレキシブル素材に低温で形成することが可能であり、フレキシブル・ディスプレイをはじめ、ICカードやIDタグなどに幅広く応用できる。 Further, it is possible to form at a low temperature flexible materials including plastic films, including flexible display, can be widely applied such as IC cards and ID tags.

本発明の電界効果型トランジスタの構成例を示す断面図である。 A configuration example of a field effect transistor of the present invention is a cross-sectional view illustrating. 本発明の電界効果型トランジスタの作製方法を示す図である。 It is a diagram illustrating a method for fabricating the field-effect transistor of the present invention. 水素を添加した際のIn−Ga−Zn−O系アモルファス酸化物膜の抵抗率変化を示す図である。 Is a diagram showing changes in resistivity of the In-Ga-Zn-O-based amorphous oxide film when hydrogen was added. 本発明の電界効果型トランジスタの作製方法を示す図である。 It is a diagram illustrating a method for fabricating the field-effect transistor of the present invention. 本発明の電界効果型トランジスタの作製方法を示す図である。 It is a diagram illustrating a method for fabricating the field-effect transistor of the present invention. In−Ga−Zn−O系アモルファス酸化物膜の寄生抵抗の変化を示す図である。 Is a graph showing changes in parasitic resistance of In-Ga-Zn-O-based amorphous oxide film. In−Ga−Zn−O系アモルファス酸化物膜の寄生抵抗の変化を示す図である。 Is a graph showing changes in parasitic resistance of In-Ga-Zn-O-based amorphous oxide film. In−Ga−Zn−O系アモルファス酸化物膜と電極のSIMS測定結果を示す図である。 It is a graph showing the SIMS measurement results of the In-Ga-Zn-O-based amorphous oxide film and the electrode. 本発明に係る表示装置の一例の断面図である。 It is a cross-sectional view of an example of a display device according to the present invention. 本発明に係る表示装置の他の例の断面図である。 It is a cross-sectional view of another example of a display device according to the present invention. 有機EL素子と薄膜トランジスタを含む画素を二次元に配列した表示装置の構成を示す図である。 Pixels including an organic EL element and a thin film transistor is a diagram showing a configuration of a display device arranged in two dimensions.

符号の説明 DESCRIPTION OF SYMBOLS

10 基板 11 ソース電極 12 ドレイン電極 13 酸化物半導体層 14 ゲート絶縁膜 15 ゲート電極 16 レーザー 17 後にソース電極及びドレイン電極を形成するための電極層 10 substrate 11 source electrode 12 drain electrode 13 oxide electrode layer for forming a source electrode and a drain electrode after the semiconductor layer 14 a gate insulating film 15 gate electrode 16 Laser 17

Claims (16)

  1. 電界効果型トランジスタの製造方法において、 The method of manufacturing a field effect transistor,
    水素又は重水素を含有するソース電極及びドレイン電極を形成する工程と、 Forming a source electrode and a drain electrode containing hydrogen or deuterium,
    水素又は重水素を添加すると電気抵抗値が低下する酸化物半導体層を形成する工程と、前記ソース電極及びドレイン電極から前記酸化物半導体層に水素又は重水素を拡散させる工程とを備えたことを特徴とする電界効果型トランジスタの製造方法。 Forming an oxide semiconductor layer whose electric resistance value decreases when the addition of hydrogen or deuterium, further comprising the step of diffusing hydrogen or deuterium into the oxide semiconductor layer from the source electrode and the drain electrode method of manufacturing a field effect transistor, characterized.
  2. 前記水素又は重水素を含有するソース電極及びドレイン電極を形成する工程は、 Forming a source electrode and a drain electrode containing hydrogen or deuterium,
    ガスを含む雰囲気中でソース電極及びドレイン電極を形成する工程、又はH Oガスを含む雰囲気中でソース電極及びドレイン電極を形成する工程、又はソース電極及びドレイン電極の形成後に水素プラズマ処理する工程、又はソース電極及びドレイン電極の形成後に加速された水素イオンをこれらの電極に照射する工程であることを特徴とする請求項1に記載の電界効果型トランジスタの製造方法。 Forming source and drain electrodes in an atmosphere containing H 2 gas, or H 2 O process gas to form a source electrode and a drain electrode in an atmosphere containing, or source electrode and the hydrogen plasma treatment after the formation of the drain electrode method for producing a field effect transistor according to claim 1, step, or accelerated hydrogen ions after the formation of the source electrode and the drain electrode, characterized in that a step of irradiating these electrodes.
  3. 前記ソース電極及びドレイン電極から前記酸化物半導体層に水素又は重水素を拡散させる工程により拡散される水素イオン濃度は、前記酸化物半導体層中のソース電極及びドレイン電極に接する領域において0.1atm%乃至10atm%であることを特徴とする請求項1又は2に記載の電界効果トランジスタの製造方法。 The source electrode and the hydrogen ion concentration is diffused by a process from the drain electrode to diffuse the hydrogen or deuterium to the oxide semiconductor layer, 0.1 atm% in the area in contact with the source electrode and the drain electrode of the oxide semiconductor layer method of manufacturing a field effect transistor according to claim 1 or 2, characterized in that to a 10 atm%.
  4. 前記ソース電極及びドレイン電極から前記酸化物半導体層に水素又は重水素を拡散させる工程により拡散される水素イオン濃度は、前記酸化物半導体層中のソース電極及びドレイン電極に接する領域において0.5atm%乃至5atm%であることを特徴とする請求項1又は2に記載の電界効果トランジスタの製造方法。 The source electrode and the hydrogen ion concentration is diffused by a process from the drain electrode to diffuse the hydrogen or deuterium to the oxide semiconductor layer, 0.5 atm% in the area in contact with the source electrode and the drain electrode of the oxide semiconductor layer method of manufacturing a field effect transistor according to claim 1 or 2, characterized in that to a 5 atm%.
  5. 前記ソース電極及びドレイン電極から前記酸化物半導体層に水素又は重水素を拡散させる工程は、アニール処理であることを特徴とする請求項1乃至4のいずれか1項記載の電界効果型トランジスタの製造方法。 Step of diffusing hydrogen or deuterium into the oxide semiconductor layer from the source electrode and the drain electrode, manufacturing a field effect transistor of any one of claims 1 to 4, characterized in that it is annealed Method.
  6. 前記酸化物半導体層はInとGaとZnを含有したアモルファス酸化物材料で形成されていることを特徴とする請求項1乃至5のいずれか1項に記載の電界効果型トランジスタの製造方法。 Production method of the oxide semiconductor layer is a field-effect transistor according to any one of claims 1 to 5, characterized in that it is formed in the amorphous oxide material containing In, Ga, and Zn.
  7. 前記ソース電極又はドレイン電極が酸化物導電体であることを特徴とする請求項1乃至6のいずれか1項に記載の電界効果型トランジスタの製造方法。 Method for producing a field effect transistor according to any one of claims 1 to 6, wherein the source electrode or the drain electrode is an oxide conductor.
  8. 前記ソース電極又はドレイン電極が金属電極であることを特徴とする請求項1乃至6のいずれか1項に記載の電界効果型トランジスタの製造方法。 Method for producing a field effect transistor according to any one of claims 1 to 6, wherein the source electrode or the drain electrode is a metal electrode.
  9. 電界効果型トランジスタにおいて、 In the field-effect transistor,
    半導体層は水素又は重水素を添加すると電気抵抗値が低下する酸化物半導体層からなり、 The semiconductor layer is an oxide semiconductor layer whose electric resistance value decreases when the addition of hydrogen or deuterium,
    前記酸化物半導体層中のソース電極及びドレイン電極に接する領域における水素又は重水素の濃度が、前記酸化物半導体層中の水素又は重水素の平均濃度に比べて大きく、かつ、前記水素又は重水素の濃度が0.1atm%乃至10atm%であることを特徴とする電界効果型トランジスタ。 The concentration of hydrogen or deuterium in the region in contact with the source electrode and the drain electrode of the oxide semiconductor layer is, rather large in comparison with the average concentration of hydrogen or deuterium of the oxide semiconductor layer, and the hydrogen or the heavy field effect transistor, wherein the concentration of hydrogen is 0.1 atm% to 10 atm%.
  10. 前記酸化物半導体層中のソース電極及びドレイン電極に接する領域における水素又は重水素は、前記ソース電極又はドレイン電極から前記酸化物半導体層中に拡散した水素又は重水素であることを特徴とする請求項9に記載の電界効果型トランジスタ。 The hydrogen or deuterium in the region in contact with the source electrode and the drain electrode of the oxide semiconductor layer is claims, characterized in that from the source electrode or the drain electrode is diffused hydrogen or deuterium in the oxide semiconductor layer the field effect transistor according to claim 9.
  11. 前記酸化物半導体層中のソース電極及びドレイン電極に接する領域での水素イオン濃度は、0.5atm%乃至5atm%であることを特徴とする請求項9又は10に記載の電界効果型トランジスタ。 The hydrogen ion concentration in the area in contact with the source electrode and the drain electrode of the oxide semiconductor layer in a field effect transistor according to claim 9 or 10, characterized in that it is 0.5 atm% to 5 atm%.
  12. 前記酸化物半導体層はInとGaとZnを含有したアモルファス酸化物材料からなることを特徴とする請求項又は11のいずれか1項に記載の電界効果型トランジスタ。 The oxide semiconductor layer is a field-effect transistor according to any one of claims 9 or 11, characterized in that an amorphous oxide material containing In, Ga, and Zn.
  13. 求項乃至12のいずれか1項に記載の電界効果型トランジスタと、表示素子とを含み、前記電界効果型トランジスタのソース又はドレイン電極が前記表示素子の電極に接続されている表示装置。 A field effect transistor according to any one of Motomeko 9-12, and a display device, the source or display device and a drain electrode connected to the electrode of the display element of the field-effect transistor.
  14. 前記表示素子がエレクトロルミネッセンス素子である、請求項13に記載の表示装置。 Wherein the display element is an electroluminescence element display device according to claim 13.
  15. 前記表示素子が液晶セルである、請求項13に記載の表示装置。 The display element is a liquid crystal cell, display device according to claim 13.
  16. 基板上に前記表示素子及び前記電界効果型トランジスタが二次元的に複数配されている請求項13乃至15のいずれか1項に記載の表示装置。 Display device according to any one of claims 13 to 15 wherein the display device and the field effect transistor on the substrate is two-dimensionally a plurality arranged.
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