JP2008235871A - Method for forming thin film transistor and display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-priced/stable display element by simplifying the formation process of a thin film transistor using an oxide semiconductor and a method for forming the same. <P>SOLUTION: The method for forming a thin film transistor where a gate electrode 4 is formed on a substrate 1 that includes a step that forms the electrode 4, a step that forms a metal oxide layer 7 so as to cover the electrode 4, a step that forms a source electrode 6 and a drain electrode 5, and a step that converts a part of the layer 7 into a channel region by performing thermal processing on a region that is to be a channel region of the layer 7 in an inert gas. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for forming a thin film transistor and a display device, and more particularly, to a method for forming a thin film transistor using an oxide semiconductor for a channel layer and a display device.

  In recent years, development of a thin film transistor (TFT) using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component in a channel layer has been actively performed (Patent Document 1).

  Since the thin film can be formed at a low temperature and is transparent to visible light, it is said that a flexible transparent TFT can be formed on a substrate such as a plastic plate or a film.

  Patent Document 2 and Non-Patent Document 1 disclose a technique in which a transparent amorphous oxide semiconductor film (a-IGZO) made of indium, gallium, zinc, and oxygen is used for a TFT channel layer.

Furthermore, it is shown that it is possible to form a flexible and transparent TFT having a good field effect mobility of 6-9 cm ² V ⁻¹ s ⁻¹ on a substrate such as a polyethylene terephthalate (PET) film at room temperature. Yes.

Furthermore, Non-Patent Document 2 describes that SiON is used for an insulating layer and an element isolation region of a thin film transistor using a-IZGO as a channel layer of a TFT.
JP 2002-76356 A International Publication WO2005 / 088726A1 Pamphlet Nature, 488, 432, (2004) Figure 7 on page 73 of the Nikkei Microdevice February 2006 issue

  In general, TFTs including amorphous silicon thin film transistors (TFTs) are formed by a number of microfabrication processes. Simplification of the microfabrication process is important for manufacturing a TFT that operates stably at a low cost.

  When a transparent semiconductor film made of zinc and oxygen as described in Patent Document 1, Patent Document 2 and Non-Patent Document 1 is used for the channel region of the TFT, there are the following problems.

  That is, the conductive transparent oxide channel region is formed using a photolithography method and dry etching or wet etching.

  Dry etching is usually performed using an expensive vacuum apparatus, which causes an increase in manufacturing cost. Wet etching is effective for cost reduction.

  However, in wet etching, there is a case where the element size is restricted such as a decrease in fine processing accuracy and moisture adsorption to the channel region due to the wet process, or a throughput is reduced such as addition of a drying process.

  Accordingly, an object of the present invention is to provide a low-cost and stable display element and a method for forming the same by simplifying a process for forming a thin film transistor using an oxide semiconductor.

  As a means for solving the above problems, the present invention provides a method for forming a thin film transistor in which a gate electrode is formed on a substrate, a step of forming the gate electrode, and a metal oxide layer so as to cover the gate electrode. And forming a source electrode and a drain electrode, and changing the part of the metal oxide layer into a channel region by heat treatment in an inert gas.

  According to the present invention, the metal oxide layer for forming the high resistance region and the channel region is formed by a single film formation process. For example, a high-resistance metal oxide layer is formed, and a part of the high-resistance layer is subjected to heat treatment to locally reduce the resistance. Then, the low resistance region is used as a channel region. As a result, the high resistance region and the channel region can be formed using a metal oxide layer formed by the same film formation process. In this way, a part of the metal oxide layer (high resistance layer) is locally altered to form a high resistance region and a region functioning as a channel layer (channel region). The region etching process can be omitted.

  By using the oxide semiconductor TFT and the formation method, it is possible to provide an electronic element including a thin film TFT which is stable at low cost.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

  The thin film transistor of the embodiment of the present invention is characterized in that the high resistance region and the channel region are formed of the same metal oxide layer.

  In addition, the present invention provides a high resistance region and a channel with the same amorphous oxide layer by locally changing the characteristics of the metal oxide material by performing a specific heat treatment on the specific metal oxide material described below. A region is formed.

  In the present invention, “a part of the metal oxide layer is changed into a channel region” means an electrical characteristic that functions as a channel layer of a semiconductor device by changing at least a part of the metal oxide layer by heat treatment. To change to.

  FIG. 8 is a flowchart illustrating a manufacturing process of a thin film transistor which is one embodiment of the present invention.

  A method for forming a thin film transistor in which a gate electrode is formed over a substrate will be described along the steps.

(Step of forming gate electrode: S11)
This process is designed by calculating the gate electrode material, the gate electrode width, and the gate electrode film thickness in advance in consideration of the voltage drop or the amount of heat that rises according to the size of the substrate to be used and its purpose. A desired gate electrode is formed by vacuum deposition or sputtering, and is formed through a photolithography process (also referred to as a photolithography process).

(Step of forming a metal oxide layer: S12)
In this step, after forming a desired gate electrode, a metal oxide layer is formed so as to cover the gate electrode. A high-resistance film that can be used as a gate insulating film is formed by a sputtering method or the like. In this step, patterning by a photolithography process can be omitted.

(Step of forming source and drain electrodes: S13)
This step is a step of patterning the source electrode and the drain electrode with a metal or the like at a desired position by a photolithography process or the like.

(Step of changing a part of the metal oxide layer into a channel region: S14)
This step is one of the important steps of the present invention. By heat-treating in an inert gas, a part of the metal oxide layer (high resistance layer) is locally altered, so that a high resistance region and a channel are formed. This is a step of forming a region functioning as a layer (channel region). Further, this process can be repeated a plurality of times to obtain a desired channel region.

  Through the above steps, the thin film transistor of the present invention is formed.

  FIG. 9 is a flowchart showing a manufacturing process of a thin film transistor having a process of separately providing a gate insulating film, which is another embodiment of the present invention.

  Each step shown in FIG. 9 will be described in the same manner as the step diagram of FIG.

(Step of forming gate electrode on substrate: S21)
This process takes into account the voltage drop or the amount of heat that rises in advance in accordance with the size of the substrate used when forming the gate electrode on the substrate and the purpose thereof, and the gate electrode material, gate electrode width, gate electrode The film thickness is calculated and designed. A desired gate electrode is formed by vacuum deposition or sputtering, and is formed through a photolithography process.

(Step of forming a gate insulating film: S22)
This process must be formed so as to cover the gate electrode and have at least film quality, film thickness, and gate electrode coverage so that the gate leakage current does not adversely affect the operation of the thin film transistor.

(Step of forming a metal oxide layer: S23)
In this step, a metal oxide layer is formed after the gate insulating film is formed, and a high-resistance film that can also be used as the gate insulating film is formed into a thin film by sputtering or the like. Here, a thin film can be formed because it does not necessarily have a function as a gate insulating film. In this step, patterning by a photolithography process can be omitted.

(Step of forming source and drain electrodes: S24)
This step is a step of patterning the source electrode and the drain electrode with a metal or the like at a desired position by a photolithography process or the like.

(Step of changing a part of the metal oxide layer into a channel region: S25)
This step is one of the important steps of the present invention. By heat-treating in an inert gas, a part of the metal oxide layer (high resistance layer) is locally altered, so that a high resistance region and a channel are formed. This is a step of forming a region functioning as a layer (channel region). Further, this process can be repeated a plurality of times to obtain a desired channel region. Through the above steps, the thin film transistor of the present invention is formed.

  For the high resistance region and the channel region of the thin film transistor of the embodiment of the present invention, an oxide containing Zn and In is preferably used.

The high resistance region includes Zn and at least one of In, Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge, and has a resistance value of 10 ⁸ Ω · cm or more. It is preferable to use a product.

Furthermore, it is preferable to use an amorphous oxide having a resistance value of 10 ¹⁰ Ω · cm or more.

  An electronic element including the thin film transistor of this embodiment can be used as a driving transistor of a display device.

  In that case, the distance between the source and drain electrodes of adjacent TFTs assumed from the 200 dpi pixel size is about 10 μm, and the TFT width in the pixel is about 100 μm.

  Assuming that the high resistance region that electrically isolates the elements has a film thickness of 50 nm, the leakage current is estimated using the resistivity of the region (also referred to as an inter-element separation film) as a variable as shown in FIG.

In order to use as an organic EL driving TFT, the leak current is required to be 10 ⁻¹¹ A or less, and thus the high resistance region (inter-element separation film) needs a film resistivity of 10 ¹⁰ Ω · cm or more as described above. It becomes.

  Next, the case where the amorphous oxide semiconductor of the present invention functions as a high resistance region (high resistance layer) will be further described.

  In a polycrystalline conductive transparent oxide containing ZnO as a main component, oxygen defects are likely to occur and a large number of carrier electrons are generated. In addition, since the crystal grain boundary part exists, the resistivity is smaller than the above-described value, and it is difficult to obtain the high resistance region of the present invention.

In the present invention, an element (specifically, Ga) that suppresses generation of carrier electrons in an oxide semiconductor and makes the oxide easily form an amorphous structure is added. Thus, an oxide film (high resistance layer) having a high resistivity of 10 ¹⁰ Ω · cm or more sufficient to function as an element isolation region can be obtained.

The electrical characteristics held in the high resistance region of the present invention are preferably 10 ⁸ Ω · cm or more and 10 ¹⁰ Ω · cm or less. When the resistance is higher than 10 ¹⁰ Ω · cm, it is difficult to form a channel layer after annealing. On the other hand, when it is 10 ⁸ Ω · cm or less, the leakage current increases, and the function as an element isolation region (an element isolation film) deteriorates.

  On the other hand, the channel region of the present invention changes the electrical characteristics of the semiconductor so as to function as a channel layer by performing heat treatment on the high resistance region (high resistance layer).

The electrical characteristics required for the channel region of the present invention are preferably 10 ¹ Ω · cm or more and 10 ⁷ Ω · cm or less. If the range is exceeded, the characteristics of the TFT are degraded. In the present invention, the following heat treatment (annealing) is performed in order to change the high resistance region so as to function as a channel region.

That is, a pressure (for example, 1.1 × 10 ^{5 to} 1.0 × 10 ⁻³ Pa) selected from the range of vacuum to atmospheric pressure, an inert gas (N 2, Ar, He, Ne, Kr, Xe, etc.) atmosphere Among them, heat treatment is performed for several tens of seconds to several tens of minutes in a temperature range of 150 ° C to 250 ° C.

  In the present invention, it is important that the channel region after the heat treatment (annealing) is maintained in an amorphous state. For example, the channel region may crystallize if the temperature range of the heat treatment (annealing) is different from the range of the present invention. When the channel region is crystallized in this way, the resistance may be lowered more than necessary and the characteristics as a channel may be deteriorated or the channel may not function.

  Moreover, the following method is mentioned as a concrete method of changing the resistivity of a metal oxide layer (film | membrane) locally in this invention (it changes to a channel area | region).

  Using a metal or material (ITO, IZO, etc.) whose band gap is smaller than that of the oxide insulator layer for the source electrode or drain electrode, UV lamp, visible light lamp, infrared lamp, near infrared lamp, far infrared lamp, or visible light Irradiate a laser or the like. By doing so, since the source electrode or the drain electrode is selectively heated, the resistance of the region in contact with the electrode can be locally reduced. In this case as well, it is important that the amorphous state of the region where the heat treatment (annealing) is performed is maintained before and after the heat treatment as in the above case.

  Further, a metal is used for the source electrode or the drain electrode, and the oxide semiconductor is irradiated with an ultraviolet laser or an excimer laser. The electrode made of the metal reflects an ultraviolet laser or an excimer laser (it is difficult to absorb).

  Therefore, by doing in this way, the region between the source electrode and the drain electrode can be locally reduced in resistance and used as a channel region. In this case as well, it is important that the amorphous state of the region where the heat treatment (annealing) is performed is maintained before and after the heat treatment as in the above case.

  In the case of using a top gate type TFT, a source electrode and a drain electrode are formed on the substrate. Next, a high-resistance metal oxide layer that can also be used as a gate insulating film is formed over the source electrode and the drain electrode, and a gate electrode is formed at a desired position.

  Heat treatment (annealing) similar to the above can be performed by irradiating the vicinity of the source and drain electrodes in the inert gas from the back side of the substrate using the light source. By this heat treatment, a high resistance region and a region functioning as a channel layer (channel region) can be formed.

  Also in this case, it is important that the amorphous state in the region where the heat treatment (annealing) is performed is maintained before and after the heat treatment.

  Also in the top gate type TFT, a source electrode and a drain electrode are formed on a substrate, a gate insulating film is formed on the source electrode and the drain electrode, and then a high resistance metal oxide that can be used as a gate insulating film. A physical layer is formed.

  Thereafter, a thin film transistor can be formed by forming a gate electrode at a desired position and performing heat treatment.

  In this case, the high-resistance metal oxide layer does not necessarily have a function as a gate insulating film, and thus can be formed with a thickness that can form a region (channel region) functioning as a channel layer after annealing.

  In the present invention, when an amorphous oxide containing In, Zn, and O is used as the high resistance region and the channel region, the amorphous oxide film can be formed at room temperature. Can be formed at room temperature.

  In addition to a metal substrate and a glass substrate, a plastic substrate or a plastic film can be used as the substrate.

(First embodiment: Inverted stagger type TFT)
FIG. 1 is a cross-sectional view showing a configuration of a bottom-gate thin film transistor as the thin film transistor of the first embodiment of the present invention.

A gate electrode 4 is provided on the substrate 1, and a high resistance oxide layer 7 as a metal oxide layer having a high resistivity of 10 ¹⁰ Ω · cm or more is provided thereon.

  As the electrode material for providing the source electrode 6 and the drain electrode 5 thereon, for example, at least one layer made of a metal selected from Mo, Ti, W, Al, or an alloy of the metal can be used. Specifically, a three-layer structure (Mo / W / Mo, Mo / Al / Mo, Ti / Al / Ti, Ti /) in which a conductor made of a relatively low resistance metal is sandwiched between upper and lower conductors. Mo / Ti, MoW / Al / MoW, etc.).

  Thereafter, the high resistance oxide layer shown in FIG. 3 is annealed at a desired temperature on the basis of the change in resistivity when the high resistance oxide layer is heat-treated in Ar gas (hereinafter referred to as annealing). The channel region 2 is provided by reducing the resistance of the portion.

At that time, it is desirable that the semiconductor region has a resistance value of 10 ³ Ω · cm to 10 ⁷ Ω · cm. By taking this resistance value, a field effect mobility of 1 cm ² / Vs or higher can be obtained. Here, a channel region was formed by locally irradiating the region adjacent to the source electrode and the drain electrode by irradiating with a visible light lamp in an Ar gas atmosphere at atmospheric pressure for 10 minutes.

  Thus, an inverted staggered bottom-gate thin film transistor in which the element isolation region and the oxide semiconductor region are integrally formed can be formed without using the etching process of the semiconductor region.

  In this way, the throughput during production is increased by eliminating the etching process of the semiconductor region. Further, since there is no physical interface associated with the formation of the semiconductor layer and the gate insulating film, the interface state is reduced, and the hysteresis can be improved and the long-term stability can be improved.

  Amorphous can be confirmed by the fact that a clear diffraction peak is not detected when X-ray diffraction is performed on the thin film to be measured at a low incident angle of about 0.5 degrees. The fact that a clear diffraction peak is not detected means that a halo pattern is observed.

  Note that in this embodiment, when the above-described materials are used for the element isolation region and the oxide semiconductor region of the field effect transistor, it is excluded that the element isolation region and the oxide semiconductor region include a constituent material in a microcrystalline state. It is not a thing.

Second Embodiment: Inverted Staggered TFT
FIG. 2 is a cross-sectional view showing a configuration of a bottom-gate thin film transistor as the thin film transistor according to the second embodiment of the present invention.

A gate electrode 4 is provided on the substrate 1, a gate insulating film 3, and a high resistance oxide layer 7 as a metal oxide layer showing a high resistivity of 10 ¹⁰ Ω · cm or more is provided thereon.

  A source electrode 6 and a drain electrode 5 are provided thereon.

Then, based on the change in resistivity when the high resistance oxide layer shown in FIG. 3 is annealed in an inert gas, a part of the high resistance oxide layer is reduced in resistance by annealing at a desired temperature. Thus, the channel region 2 is provided. He gas is used as an inert gas used for annealing. At that time, it is desirable that the semiconductor region has a resistance value of 10 ³ Ω · cm to 10 ⁷ Ω · cm. By taking this resistance value, a field effect mobility of 1 cm ² / Vs or more can be obtained. Here, the channel region was formed by locally irradiating the region adjacent to the source electrode and the drain electrode by irradiating with a near-infrared lamp at atmospheric pressure in a He gas atmosphere for 15 minutes.

  Thus, an inverted staggered bottom-gate thin film transistor in which the element isolation region and the oxide semiconductor region are integrally formed can be formed without using the etching process of the semiconductor region.

  Amorphous can be confirmed by the fact that a clear diffraction peak is not detected when X-ray diffraction is performed on a thin film to be measured at a low incident angle of about 0.5 degrees. The fact that a clear diffraction peak is not detected means that a halo pattern is observed.

  Note that in this embodiment, when the above-described materials are used for the element isolation region and the oxide semiconductor region of the field effect transistor, it is excluded that the element isolation region and the oxide semiconductor region include a constituent material in a microcrystalline state. Not what you want.

(Third embodiment: display device)
Next, a display device can be formed by connecting a drain which is an output terminal of the thin film transistor to an electrode of a display element such as an organic or inorganic electroluminescence (EL) element or a liquid crystal element.

  An example of a specific display device configuration will be described below with reference to the drawing of the display device.

  FIG. 4 is a cross-sectional view showing an example in which an electroluminescence element as a display element is used.

  For example, as shown in FIG. 4, after forming the gate electrode 416 and the gate insulating film 415 on the base 411, a high resistance oxide layer 421 having a high resistivity is formed.

  Further, after forming the source electrode 413 and the drain electrode 414, annealing is performed in an inert gas, whereby a part of the high-resistance oxide layer 421 is reduced in resistance to form a channel region 412 and a TFT is formed.

  An electrode 418 is connected to the drain electrode 414 through an interlayer insulating film 417. A light emitting layer 419 is stacked on the electrode 418, and an electrode 420 is stacked on the light emitting layer 419.

  With such a structure, a current injected into the light emitting layer 419 can be controlled by a current value flowing from the source electrode 413 to the drain electrode 414 through the channel region 412.

  Therefore, this can be controlled by the voltage at the gate 416 of the TFT. Here, the electrode 418, the light emitting layer 419, and the electrode 420 constitute an inorganic or organic electroluminescence element.

  FIG. 5 is a cross-sectional view showing an example using a liquid crystal cell as a display element.

  As shown in FIG. 5, the drain electrode 514 is extended to serve as the electrode 518, and the electrode 518 applies a voltage to the liquid crystal cell or the electrophoretic particle cell 523 sandwiched between the high resistance films 522 and 524. You can take a configuration to do.

  The liquid crystal cell, the electrophoretic particle cell 523, the high resistance regions 522 and 524, the electrode 518, and the electrode 520 constitute a display element.

  The voltage applied to these display elements can be controlled by the value of current flowing from the source electrode 513 to the drain electrode 514 through the channel region 512.

  Therefore, this can be controlled by the voltage of the gate electrode 516 of the TFT. Here, if the display medium of the display element is a capsule in which a fluid and particles are sealed in an insulating film, the high resistance films 522 and 524 are unnecessary.

  In the above two examples, an example in which a pair of electrodes for driving the display element is provided in parallel with the base body is illustrated, but this embodiment is not necessarily limited to this configuration.

  For example, as long as the connection between the drain electrode, which is the output terminal of the TFT, and the display element are topologically the same, either electrode or both electrodes may be provided perpendicular to the substrate.

  Furthermore, in the above two examples, only one TFT connected to the display element is shown, but the present invention is not necessarily limited to this configuration.

  For example, the TFT shown in the figure may be connected to another TFT, and the TFT in the figure may be the final stage of the circuit using these TFTs.

  Here, when a pair of electrodes for driving the display element is provided in parallel with the substrate and the display element is a reflective display element such as an electroluminescence element or a reflective liquid crystal element, the following is necessary. That is to make one of the pair of electrodes transparent to the emission wavelength or the wavelength of the reflected light. In the case of a transmissive display element such as a transmissive liquid crystal element, both electrodes need to be transparent to transmitted light.

  Furthermore, in the TFT of this embodiment, it is possible to make all the constituents transparent, thereby forming a transparent display element.

  Further, such a display element can be provided on a low heat-resistant substrate such as a lightweight, flexible and transparent resin plastic substrate.

  FIG. 6 is a circuit diagram illustrating a circuit of a display device in which pixels including an electroluminescent element (here, an organic electroluminescent element) and a thin film transistor are two-dimensionally arranged.

  In FIG. 6, 61 is a transistor for driving the organic EL layer 64, and 62 is a transistor for selecting a pixel.

  Further, the capacitor 63 is for holding the selected state, stores electric charge between the common electrode line 67 and the source portion of the transistor 2, and holds the signal of the gate of the transistor 1. Pixel selection is determined by the scanning electrode line 65 and the signal electrode line 66.

  More specifically, an image signal is applied as a pulse signal from a driver circuit (not shown) to the gate electrode through the scanning electrode 65.

  At the same time, a pixel is selected by applying a pulse signal from another driver circuit (not shown) through the signal electrode 66 to the transistor 62.

  At that time, the transistor 62 is turned on, and charges are accumulated in the capacitor 63 between the signal electrode line 66 and the source of the transistor 62.

  As a result, the gate voltage of the transistor 61 is maintained at a desired voltage, and the transistor 61 is turned on.

  This state is maintained until the next signal is received.

  While the transistor 61 is ON, voltage and current are continuously supplied to the organic EL layer 64 and light emission is maintained.

  In the example of FIG. 6, the configuration includes two transistors and one capacitor per pixel, but more transistors or the like may be incorporated in order to improve performance.

  Essentially, an effective electroluminescent element can be obtained by using an In—Ga—Zn—O-based TFT which is a transparent TFT and can be formed at a low temperature according to the present invention in the transistor portion.

  Next, embodiments of the present invention will be described with reference to the drawings.

Example 1
In this embodiment, a method of forming the inverted staggered (bottom gate) type MISFET element shown in FIG. 1 will be described.

  First, a gate terminal of Ti 10 nm / Au 100 nm was formed on a glass substrate (Corning Corporation 1737) using a photolithography method and a lift-off method.

  Furthermore, a high resistance oxide layer having a high resistivity is formed on the amorphous In— layer having a metal composition ratio of 400 nm in thickness of In: Ga: Zn = 1.00: 0.94: 0.65 by sputtering. A Ga—Zn—O film is formed at room temperature.

  As a target, a sintered body of In: Ga: Zn = 1: 1: 1 is used.

At that time, an oxygen-argon mixed gas is used as a sputtering gas, the total pressure of the oxygen-argon mixed gas is 5.0 × 10 ⁻¹ Pa, and the oxygen partial pressure is 7.0 × 10 ⁻² Pa.

Since the film thus obtained functions as an element isolation region, an oxide thin film having a high resistivity of 10 ¹⁰ Ω · cm or more sufficient can be obtained.

  Thereafter, Mo 100 nm / Ti 5 nm is formed by an electron beam evaporation method, and a source electrode and a drain electrode are formed by a photolithography method and a lift-off method.

  After that, the high-resistance amorphous In—Ga—Zn—O film transparent to visible light is lamp-heated in an inert gas atmosphere. Here, a channel region was formed by locally irradiating the region adjacent to the source electrode and the drain electrode by irradiating with a visible light lamp in an Ar gas atmosphere at atmospheric pressure for 10 minutes.

  Since the source / drain electrodes absorb and reflect the light of the lamp, the source / drain electrodes can be locally heated to 150 ° C. or higher and 250 ° C. or lower, thereby forming a semiconductor region (channel region).

  In this way, it is possible to complete the inverted staggered (bottom gate) type MISFET element shown in FIG. 1 in which the element isolation region and the oxide semiconductor region are integrally formed without using the etching process of the semiconductor region.

This MISFET element can have a field effect mobility of 1 cm ² / Vs or more and an off current of 1E-11 (A) or less.

(Example 2)
In this embodiment, a method of forming the inverted staggered (bottom gate) type MISFET element shown in FIG. 2 will be described.

  First, a gate terminal of Ti 10 nm / Ni 100 nm was formed on a glass substrate (Corning Corporation 1737) using a photolithography method and a lift-off method.

  Further, an insulating layer made of a-SiOx was formed to 100 nm thereon by sputtering.

At that time, a SiO ₂ target was used as the sputtering target, and an oxygen-argon mixed gas was used as the sputtering gas.

  Then, an amorphous material having a metal composition ratio of 35 nm used as an element isolation region and an oxide semiconductor region of In: Ga: Zn = 1.00: 0.94: 0.65 by sputtering at room temperature is used. An In—Ga—Zn—O film is formed.

At that time, an oxygen-argon mixed gas is used as the sputtering gas, the total pressure of the oxygen-argon mixed gas is 5.1 × 10 ⁻¹ Pa, and the oxygen partial pressure is 6.5 × 10 ⁻² Pa.

Since the film thus obtained functions as an element isolation region, an oxide thin film having a high resistivity of 10 ¹⁰ Ω · cm or more sufficient can be obtained.

  Thereafter, in an inert gas atmosphere (He gas), the a-SiOx and the high-resistance amorphous In-Ga-Zn-O film, which are insulating layers transparent to light in the visible light range, are heated by lamp. Here, the channel region was formed by locally irradiating the region adjacent to the source electrode and the drain electrode by irradiation for 15 minutes using a near-infrared lamp in a He gas atmosphere at atmospheric pressure.

  Since only the gate electrode absorbs and reflects the light of the lamp, only the upper portion of the gate electrode can be locally heated to 150 ° C. or higher and 200 ° C. or lower, thereby forming a semiconductor region (channel region).

  Finally, Au 100 nm / Ti 5 nm is formed by an electron beam evaporation method, and source and drain terminals are formed by a photolithography method and a lift-off method.

  In this way, it is possible to complete the inverted staggered (bottom gate) type MISFET element shown in FIG. 2 in which the element isolation region and the oxide semiconductor region are integrally formed without using the etching process of the semiconductor region.

This MISFET element can have a field effect mobility of 1 cm ² / Vs or more and an off current of 1E-11 (A) or less.

(Example 3)
In this embodiment, a display device using the liquid crystal cell of FIG. 5 will be described.

  The manufacturing process of the TFT is the same as that of the second embodiment.

  In the above TFT, extend the short side of the ITO film island forming the drain electrode to 100 μm, leave the extended 90 μm portion, and secure the wiring to the source and gate electrodes, and then cover the TFT with an insulating layer To do.

  A polyimide film is applied thereon and a rubbing process is performed.

  On the other hand, an ITO film and a polyimide film are similarly formed on a plastic substrate, and a rubbing process is prepared. The substrate on which the TFT is formed is opposed to the substrate with a 5 μm gap, and a nematic liquid crystal is injected therein. .

  Further, a pair of polarizing plates is provided on both sides of the structure.

  Here, when a voltage is applied to the source electrode of the TFT to change the voltage applied to the gate electrode, the light transmittance changes only in a 30 μm × 90 μm region that is a part of the island of the ITO film extended from the drain electrode.

  The transmittance can be continuously changed by the source-drain voltage under the gate voltage at which the TFT is turned on.

  In this manner, a display device having a liquid crystal cell as a display element corresponding to FIG. 5 is produced.

  In this embodiment, a white plastic substrate is used as a substrate for forming a TFT, each electrode of the TFT is replaced with gold, and the polyimide film and the polarizing plate are discarded.

  And it is set as the structure filled with the capsule which coat | covered the particle | grains and the fluid with the insulating film in the space | gap of a white and transparent plastic substrate.

  In the case of a display device having this configuration, the voltage between the drain electrode extended by the TFT and the upper ITO film is controlled, so that the particles in the capsule move up and down.

  Accordingly, display can be performed by controlling the reflectance of the extended drain electrode region viewed from the transparent substrate side.

  In this embodiment, a plurality of TFTs are formed adjacent to each other to form a current control circuit having a 4-transistor 1-capacitor configuration, and one of the final stage transistors is used as the TFT of FIG. 4 to drive the electroluminescence element. it can.

  For example, a TFT using the above ITO film as a drain electrode is used.

  Then, an organic electroluminescence element composed of a charge injection layer and a light emitting layer is formed in a 30 μm × 90 μm region that is a part of the island of the ITO film extended from the drain electrode.

  Thus, a display device using an electroluminescent element can be formed.

Example 4
In this embodiment, the display element and TFT of Embodiment 3 are arranged two-dimensionally.

  For example, the pixels occupying an area of about 30 μm × 115 μm including the display element such as the liquid crystal cell and electroluminescence element of Example 3 and the TFT are arranged as follows. The number is 7425 × 1790 at 40 μm pitch in the short side direction and 120 μm pitch in the long side direction.

  Then, there are 1790 gate wirings penetrating the gate electrodes of 7425 TFTs in the long side direction, and signals that the source electrodes of 1790 TFTs protrude 5 μm from the island of the amorphous oxide semiconductor film in the short side direction. 7425 wirings are provided.

  Then, each is connected to a gate driver circuit and a source driver circuit.

  Further, in the case of a liquid crystal display element, an A4 size active matrix type color image display device is constructed with about 211 ppi if a color filter having the same size as that of the liquid crystal display element and having RGB repeating in the long side direction is provided on the surface. Can do.

  Also, in the electroluminescence element, the gate electrode of the first TFT among the two TFTs included in one electroluminescence element is wired to the gate line, and the source electrode of the second TFT is wired to the signal line. Then, the emission wavelength of the electroluminescence element is repeated in RGB in the long side direction.

  By doing in this way, the light emission type color image display apparatus of the same resolution can be comprised.

  Here, the driver circuit for driving the active matrix may be configured using the same TFT of the present invention as the TFT of the pixel, or an existing IC chip may be used.

(Example 5)
In this embodiment, an electrophoretic display device having a configuration similar to that of the liquid crystal cell of FIG. 5 will be described.

  The manufacturing process of the TFT is the same as that of the second embodiment. However, the TFT used in this example has a channel length of 70 μm, a channel width of 140 μm, a gate overlap length of 5 μm, and a TFT suitable for the pixel size.

  In the above TFT, extend the short side of the ITO film island forming the drain electrode to 338 μm, leave the extended 230 μm portion, and secure the wiring to the source and gate electrodes, and then cover the TFT with an insulating layer To do.

  In addition, an electrode is formed on a transparent substrate (not shown), the electrode surface is disposed so as to face the ITO film side, and sealed with a partition or the like so that the colored solvent containing the electrophoretic particles does not leak. The distance between the electrodes was maintained at 80 μm. A solvent colored with a black pigment and white migrating particles (titanium oxide: average particle size 6 μm) were dispersed between the electrodes. Here, monochrome display can be performed by applying a voltage from the TFT side.

  Further, black and white display can also be achieved by using particles (average particle diameter of 1.5 μm) obtained by mixing carbon in colored charged electrophoretic particle polystyrene resin with colorless transparent liquid silicone oil. However, the electrode in this case may have higher contrast when the metal with high reflectivity is used.

  Further, the colored charged electrophoretic particles can be small color toner having a particle size of 10 μm or less, and can be easily displayed in color.

  Coloring can also be achieved by injecting cholesteric liquid crystal between the electrodes facing each other and reflecting light that matches the characteristics of the cholesteric liquid crystal.

  The electronic device comprising the thin film transistor (TFT) according to the present invention can be applied as a switching device for LCDs and organic EL displays.

  In addition, it is possible to form all TFT processes at low temperatures on flexible materials such as plastic films, and it can be widely applied to flexible displays, IC cards and ID tags.

1 is a cross-sectional view showing a configuration of a bottom gate thin film transistor as a thin film transistor of a first embodiment of the present invention. It is sectional drawing which shows the structure of the thin film transistor of a bottom gate structure as a thin film transistor of the 2nd Embodiment of this invention. It is a figure which shows the change of the resistivity at the time of annealing a high resistance amorphous In-Ga-Zn-O film | membrane in Ar gas. It is sectional drawing which shows the example using the electroluminescent element as a display element. It is sectional drawing which shows the example using the liquid crystal cell as a display element. It is a circuit diagram which shows the circuit of the display apparatus which has arrange | positioned the pixel containing an electroluminescent element and a thin-film transistor two-dimensionally. It is a graph which shows the relationship between the film resistivity and the leakage current. 6 is a flowchart illustrating a manufacturing process of a thin film transistor which is an embodiment of the present invention. 9 is a flowchart showing a manufacturing process of a thin film transistor having a step of providing a gate insulating film, which is a different form from FIG. 8.

Explanation of symbols

1 substrate 2 channel region (semiconductor region)
3 Gate insulation film 4 Gate electrode (gate terminal)
5 Drain electrode (drain terminal)
6 Source electrode (source terminal)
7 High resistance oxide layer (metal oxide layer)
411 base body 412 channel region 413 source electrode 414 drain electrode 415 gate insulation 416 gate electrode 417 interlayer insulating film 418 electrode 419 light emitting layer 420 electrode 421 high resistance oxide layer 511 base body 512 channel region 513 source electrode 514 drain electrode 515 gate insulation 516 gate Electrode 517 Protective layer 518 Electrode 520 Electrode 521 High resistance region 522 High resistance film 523 Liquid crystal cell or electrophoretic particle cell 524 High resistance film

Claims (10)

Forming a gate electrode on the substrate;
Forming a metal oxide layer so as to cover the gate electrode;
Forming a source electrode and a drain electrode on the metal oxide layer;
And a step of changing a part of the metal oxide layer into the channel region by heat-treating a region to be a channel region of the metal oxide layer in an inert gas. Forming method. Forming a gate electrode on the substrate;
Forming a gate insulating film so as to cover the gate electrode;
Forming a metal oxide layer on the gate insulating film;
Forming a source electrode and a drain electrode on the metal oxide layer;
And a step of changing a part of the metal oxide layer into the channel region by heat-treating a region to be a channel region of the metal oxide layer in an inert gas. Forming method. Forming a source electrode and a drain electrode on a substrate;
Forming a metal oxide layer so as to cover the source electrode and the drain electrode;
Forming a gate electrode on the metal oxide layer;
And a step of changing a part of the metal oxide layer into the channel region by heat-treating a region to be a channel region of the metal oxide layer in an inert gas. Forming method. Forming a source electrode and a drain electrode on a substrate;
Forming a gate insulating film on the source electrode and the drain electrode;
Forming a metal oxide layer on the gate insulating film;
Forming a gate electrode on the metal oxide layer;
And a step of changing a part of the metal oxide layer into the channel region by heat-treating a region to be a channel region of the metal oxide layer in an inert gas. Forming method. 5. The method for forming a thin film transistor according to claim 1, wherein the metal oxide layer contains Zn as a material. The metal oxide layer further includes at least one of In, Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge, has a resistance value of 10 ⁸ Ω · cm or more, and is amorphous. The method of forming a thin film transistor according to claim 5. 7. The method of forming a thin film transistor according to claim 6, wherein the inert gas is Ar gas. A display device, wherein a source electrode or a drain electrode of a thin film transistor formed by the method for forming a thin film transistor according to claim 1 is connected to an electrode of a display element. The display device according to claim 8, wherein the display element is an electroluminescence element. The display device according to claim 8, wherein the display element is a liquid crystal cell.