JP5406449B2 - Thin film transistor manufacturing method and display device using oxide semiconductor - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film transistor using an oxide semiconductor and a display device.

  As a thin film transistor used as a switching element of a display device such as an active matrix liquid crystal display element or an organic electroluminescence element, a thin film transistor having a semiconductor layer made of silicon has been used. For example, after a gate electrode is formed on an insulating substrate and a gate insulating film is formed on an insulating substrate including the gate electrode, a semiconductor layer made of amorphous silicon is formed. Next, a channel protective film is provided at the center of the upper surface of the semiconductor layer, and ohmic contact layers made of n-type amorphous silicon are formed on both sides of the protective film and on the semiconductor channel layer. Thereafter, a source electrode and a drain electrode are provided on the upper surface of the ohmic contact layer (Patent Document 1).

  However, since the silicon-based semiconductor material as described above is not transparent to visible light, the conventional thin film transistor using the silicon-based material for the channel layer absorbs visible light and causes malfunction. In order to prevent this, a light shielding layer is required for visible light incident from the outside, and thus a complicated element structure and manufacturing process are required.

  Therefore, in recent years, development of a thin film transistor using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component for a channel layer has been actively carried out. The thin film has higher mobility than amorphous silicon, can be formed at a low temperature, and can form a flexible transparent thin film transistor on a substrate such as a plastic plate or a film. Moreover, since it is transparent to visible light, a light shielding layer or the like is not required.

  An example of a method for manufacturing a thin film transistor mainly composed of ZnO as described above will be described below. First, a semiconductor layer made of intrinsic zinc oxide is formed on the gate insulating film, a protective film having the same shape as the end face of the semiconductor layer is formed, and after forming an upper insulating film on the upper surface, a contact hole is formed. The An ohmic contact layer made of n-type ZnO is formed on the upper surface of the semiconductor layer exposed through the contact hole, or a source electrode and an upper surface are subjected to a low resistance treatment in a region where the semiconductor layer and the electrode are in contact with each other. A drain electrode is formed (Patent Document 2). However, in order to obtain ohmic contact with the electrode, a process for reducing resistance or forming an ohmic contact layer is required.

In Non-Patent Document 1, a transparent amorphous oxide semiconductor film (a-IGZO) is used as a channel layer of a thin film transistor, and a semiconductor layer with good flatness and uniformity is formed by performing room temperature film formation by magnetron sputtering. It has gained. By doing so, it has been shown that a good thin film transistor having a field effect mobility of 12 cm ² V ⁻¹ s ⁻¹ can be obtained.
Japanese Patent Laid-Open No. 11-40814 JP 2006-100760 A Applied Physics Letters, 89, 112123, (2006)

  However, in the configuration of the thin film transistor element described above, no ohmic contact layer or the like is provided, and therefore, there is a concern about non-ohmic contact between the oxide semiconductor layer and the source and drain electrodes depending on the selection of the electrode material.

  The present invention has been made in view of the above problems. That is, an object of the present invention is to provide a thin film transistor using an oxide semiconductor and having good transistor characteristics in which an ohmic contact between the source and drain electrodes and the oxide semiconductor layer is achieved without increasing the number of manufacturing steps.

  As a result of intensive research and development on a thin film transistor using a transparent oxide semiconductor, the present inventors have obtained the following knowledge that can solve the above problems with the following configuration. That is, the second insulating film that covers the oxide semiconductor layer is formed using an oxide insulator in an atmosphere containing an oxidizing gas. The second insulating film covering the channel region of the oxide semiconductor layer is left as a protective layer, the second insulating film covering the oxide semiconductor layer other than the region is removed by patterning, and a contact region with the electrode (electrode and The region to be electrically joined is exposed. Through this step, the oxide semiconductor layer covered with the second insulating film is damaged and the resistance is reduced. That is, by patterning the second insulating film in this step, a channel region and a contact region between the electrodes are formed in the oxide semiconductor layer, and the latter has a low resistance. Next, a source electrode and a drain electrode are formed in the contact region. Thus, the source electrode or the drain electrode can be formed using the region where the resistance of the oxide semiconductor layer is reduced as the contact region of the electrode. Therefore, a thin film transistor with good ohmic contact can be stably manufactured without performing the step of forming an ohmic contact layer or the step of reducing the resistance of the contact region with the oxide electrode. Although a bottom-gate thin film transistor has been described here, the present invention can also be realized with a top-gate thin film transistor.

  The present invention will be specifically described below.

  The present invention is a method for manufacturing a thin film transistor having, on a substrate, at least a gate electrode, a first insulating film, an oxide semiconductor layer, a second insulating film, a source electrode, and a drain electrode. A step of forming a gate electrode on the substrate, a step of forming a first insulating film on the gate electrode, and a step of forming a semiconductor layer of amorphous oxide on the first insulating film; Patterning the first insulating film; patterning the oxide semiconductor layer; forming a second insulating film on the oxide semiconductor layer in an atmosphere containing an oxidizing gas; Patterning the second insulating film to expose a contact region with the electrode in the oxide semiconductor layer and reducing the resistance of the contact region; and a source electrode layer and Characterized in that it comprises a step of forming a drain electrode layer, and patterning the source electrode and the drain electrode.

  The present invention is also a method for manufacturing a thin film transistor having at least a gate electrode, an oxide semiconductor layer, a second insulating film, a source electrode, and a drain electrode on a substrate. A step of forming a semiconductor layer with an amorphous oxide, a step of patterning the oxide semiconductor layer, a step of forming a second insulating film on the oxide semiconductor layer in an atmosphere containing an oxidizing gas, Patterning the second insulating film to expose a contact region with the electrode in the oxide semiconductor layer and reducing the resistance of the contact region; and forming a source electrode layer and a drain electrode layer in the contact region A step of forming a gate electrode layer on the second insulating film, and a step of patterning the source electrode, the drain electrode and the gate electrode. And wherein the Mukoto.

Here, an O ₂ / Ar mixed gas is used as the atmosphere containing the oxidizing gas, and the mixing ratio is 10% by volume or more. The amorphous oxide includes an oxide containing at least one of In, Zn, and Sn, or contains In, Zn, and Ga. The second insulating film is an amorphous oxide insulator, and the components observed as O ₂ ⁺ and O ⁺ when observed by thermal desorption analysis are 3.8 × 10 ¹⁹ pieces / cm ^3. It contains above.

  Furthermore, the present invention is a thin film transistor manufactured by the manufacturing method described above.

  Furthermore, the present invention is a display device characterized in that a source or drain electrode of the thin film transistor is connected to an electrode of the display element. The display element is an electroluminescence element. The display element is a liquid crystal cell. In addition, a plurality of the display elements and the thin film transistors are two-dimensionally arranged on the substrate.

  According to the present invention, in a thin film transistor using an oxide semiconductor, the resistance of the contact region with the electrode of the oxide semiconductor layer can be reduced and connected to the source electrode and the drain electrode. Accordingly, it is possible to provide a thin film transistor having transistor characteristics with excellent ohmic contact.

  Hereinafter, an embodiment of a method for manufacturing a thin film transistor of the present invention will be described in detail with reference to the drawings.

In the thin film transistor of this embodiment, amorphous SiO _x (silicon oxide) is used as the gate insulating film material. It is also possible to form an Al ₂ O ₃ channel of amorphous oxide insulator or a-SiO _x N _y (silicon oxynitride) by sputtering. In the present invention, the SiO ₂ composition and the SiON composition are expressed as SiO _x and SiO _x N _{y in} order to show that they can be used even if they deviate from stoichiometry.

As a channel layer of the thin film transistor, an oxide semiconductor containing ZnO, In, Zn, and O is preferably used. The channel layer contains In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge, and the conductivity is 10 ^−3. It is preferable to use an amorphous oxide that is S / cm or more and 10 ⁻⁷ S / cm or less.

  As a first example of the thin film transistor according to this embodiment, a configuration of a bottom gate thin film transistor in which a contact region with an electrode of an oxide semiconductor layer is reduced in resistance and a source electrode and a drain electrode are connected to the contact region Is shown in FIG. It is provided with a gate electrode 2 on a substrate 1, a first insulating film 3, an oxide semiconductor layer 4, a second insulating film 5, a contact region 6 between the oxide semiconductor layer and the electrode, a source electrode 7 and the drain electrode 8 is provided.

  FIG. 13 is a cross-sectional view of an element in each manufacturing process of the thin film transistor in the first example. Hereafter, the manufacturing process of an element is demonstrated using FIG.

  FIG. 13A shows a process of forming the gate electrode 2 on the substrate 1. FIG. 13B shows a step of forming the first insulating film 3 on the gate electrode 2. FIG. 13C shows a step of forming the oxide semiconductor layer 4 over the first insulating film 3. In the case where an amorphous oxide containing In, Zn, and O is used as the oxide semiconductor layer 4, the oxide semiconductor layer 4 can be formed at room temperature. Can be formed. Further, a plastic substrate or a plastic film can be used as the substrate 1.

  FIG. 13D shows a process of patterning the first insulating film 3 and the oxide semiconductor layer 4. FIG. 13E shows a step of forming the second insulating film 5 of the present invention on the oxide semiconductor layer 4. The second insulating film 5 is an amorphous oxide insulating layer and is formed in an atmosphere containing an oxidizing gas. By forming the second insulating film 5 as a protective layer so that the oxide semiconductor does not have a low resistance, generation of oxygen defects in the oxide semiconductor containing ZnO as a main component is suppressed, and a large number of carrier electrons are generated. An increase in off-state current can be prevented.

FIG. 13F shows a process of patterning the second insulating film 5 covering the oxide semiconductor layer other than the channel region by dry etching the second insulating film 5 with CF ₄ gas containing Ar. . At this time, the oxide semiconductor layer in contact with the second insulating film to be etched is damaged by Ar ions or the like during etching because the etching gas contains Ar gas in addition to CF ₄ gas. Reduced resistance by generation. Therefore, the resistance of the etched oxide semiconductor layer is reduced, and the contact region 6 having good ohmic contact with the electrode is obtained. As the etching gas, gases listed below can be used in addition to CF ₄ . That is, SF ₆ , C ₄ F ₈ , CHF, Cl ₂ , BCl ₃ , CCl ₂ F ₂ , CCl _4, etc. are etching gases that are generally used as a dry etching gas for SiO ₂ . Furthermore, a mixed gas composed of a combination of these etching gas and inert gas (He, Ne, Ar, Kr, Xe, N ₂ ) can also be used in the present invention. Even in the case of a mixed gas composed of a combination of an etching gas containing these inert gases and a small amount of oxygen, the effects of the present invention can be obtained by adjusting etching conditions such as supply power for generating plasma.

  13G shows the step of forming the source electrode layer and the drain electrode layer a in the exposed contact region 6 between the oxide semiconductor layer and the electrode, and FIG. 13H shows the patterning of the source electrode 7 and the drain electrode 8. The process of forming is shown. A transparent conductive oxide film such as ITO or IZO is used for this electrode. Since the second insulating film 5 protects the channel region, the source electrode and the drain electrode can be formed not only by dry etching but also by patterning by wet etching. Further, metals such as Ni, Cr, Rh, Mo, Nd, Ti, W, Ta, Pb, and Al, alloys containing these, or silicide can be used as the source electrode and the drain electrode.

  As a second example of the thin film transistor according to this embodiment, a structure of a top gate thin film transistor in which a contact region with an electrode of an oxide semiconductor layer is reduced in resistance and a source electrode and a drain electrode are connected to the contact region. Is shown in FIG. It is formed by providing an oxide semiconductor layer 1402, a second insulating film 1403, a contact region 1404 between the oxide semiconductor layer and an electrode, a gate electrode 1405, a source electrode 1406, and a drain electrode 1407 over a substrate 1401. .

  FIG. 15 is a cross-sectional view of an element in each manufacturing process of the thin film transistor in the second example. Hereafter, the manufacturing process of an element is demonstrated using FIG.

  FIG. 15A illustrates a step of forming the oxide semiconductor layer 1402 over the substrate 1401. In the case where an amorphous oxide containing In, Zn, and O is used for the oxide semiconductor layer 1402, the oxide semiconductor layer 1402 can be formed at room temperature. Therefore, if the insulating film is also formed by a sputtering method, all film formation steps can be formed at room temperature. it can. Further, a plastic substrate, a plastic film, or the like can be used as the substrate 1401.

  FIG. 15B shows a step of patterning the oxide semiconductor layer 1402, and FIG. 15C shows a step of forming a second insulating film 1403 to be a gate insulating film over the oxide semiconductor layer 1402. The second insulating film 1403 is an amorphous oxide insulating layer like the second insulating film 5 of the first example, and is formed in an atmosphere containing an oxidizing gas. By forming the second insulating film 1403 so that the resistance of the oxide semiconductor is not reduced, generation of oxygen defects in the oxide semiconductor containing ZnO as a main component is suppressed, a large number of carrier electrons are generated, and the off-state current is increased. Can be prevented.

FIG. 15D shows a step of patterning the second insulating film 1403. The second insulating film 1403 is dry-etched with Ar-containing CF ₄ gas, and the second insulating film 1403 covering the oxide semiconductor layer other than the channel region is patterned. At this time, the oxide semiconductor layer in contact with the second insulating film 1403 to be etched is damaged by etching similarly to the above because the CF ₄ gas contains Ar, and the resistance is reduced by generation of oxygen vacancies or the like. . Accordingly, the resistance of the etched oxide semiconductor layer is reduced, and a contact region 1404 having a good ohmic contact with the electrode is obtained.

  FIG. 15E shows a step of forming an electrode layer b serving as a source electrode, a drain electrode, and a gate electrode over the contact region 1404 between the oxide semiconductor layer and the electrode and the second insulating film 1403. FIG. 15F shows a step of forming the gate electrode 1405, the source electrode 1406, and the drain electrode 1407 by patterning. A transparent conductive oxide film such as ITO or IZO is used for this electrode. Since the second insulating film 1403 protects the channel region, the source electrode and the drain electrode can be formed by patterning by wet etching as well as dry etching. Further, metals such as Ni, Cr, Rh, Mo, Nd, Ti, W, Ta, Pb, and Al, alloys containing these, or silicide can be used as the source electrode and the drain electrode.

  Next, as a comparison, a thin film transistor in which the second insulating film is formed in an atmosphere containing no oxidizing gas will be described.

FIG. 2 shows a configuration of a bottom gate inverted staggered thin film transistor using a low-resistance n-type crystalline silicon as a gate electrode / substrate 201 and a thermally oxidized silicon insulating film 202. The influence of the formation conditions of the second insulating film 204 on the characteristics of the thin film transistor using an oxide semiconductor was examined using the structure in FIG. First, amorphous InGaZnO was formed as the oxide semiconductor layer 203, and the source electrode 205 and the drain electrode 206 were deposited by a Ti / Au / Ti stacked structure and formed by lift-off. When there was no second insulating layer, the thin film transistor A was completed here. Thereafter, amorphous SiO _x was formed as a second insulating film to a thickness of 100 nm by sputtering using Ar 100 volume% gas. By forming contact holes on the source electrode 205 and the drain electrode 206 by wet etching, a thin film transistor B having a second insulating film was completed. FIG. 3 shows typical current-voltage characteristics of the thin film transistor A and the thin film transistor B manufactured by the above method. Thin film transistor: A shows thin film transistor characteristics with a good on / off ratio with minimized off-current. However, the thin film transistor to form an amorphous SiO _x considered normal oxide insulation layer as a second insulating film: The B, showed no off-state current in the gate voltage -20 V. As this cause, it is conceivable that the oxide semiconductor layer is reduced or oxygen defects are generated when the second insulating film is formed due to sputtering damage caused by Ar gas. An oxide semiconductor containing ZnO as a main component is likely to have oxygen defects and generate a large number of carrier electrons. FIG. 3 shows the result of using the sputtering method as the second insulating film forming method. However, when amorphous SiO _x or amorphous SiN _y is used as the second insulating film forming method by the P-CVD method, Furthermore, the on / off ratio cannot be obtained. In effect, it no longer operates as a thin film transistor. This is probably because the oxide semiconductor is very sensitive to hydrogen, and the portion of the oxide semiconductor in contact with the second insulating film has a very low resistance.

  Hereinafter, the effect of the second insulating film formed in an atmosphere containing an oxidizing gas, which is a feature of the present invention, will be described in detail.

(About the second insulating film)
Specifically, an amorphous oxide insulating layer is formed using sputtering, using SiO ₂ as a target, and using a mixed gas of O ₂ gas and Ar gas (hereinafter referred to as O ₂ / Ar mixed gas) as a sputtering gas. This can be achieved.

The O ₂ / Ar mixing ratio is represented by [O ₂ gas flow rate (SCCM)] / ([O ₂ gas flow rate (SCCM)] + [Ar gas flow rate (SCCM)]), unit: volume%. By forming an amorphous oxide insulating layer using an O ₂ / Ar mixed gas as a sputtering gas, an effect that the oxide semiconductor layer is not reduced or oxygen defects are not generated can be realized. The effect was recognized when the O ₂ / Ar mixed gas ratio was 10% by volume or more, and more preferably 50% by volume. Hereinafter, the O ₂ / Ar mixed gas ratio is a volume ratio. When the O ₂ / Ar mixed gas ratio was 50% by volume, good off-current characteristics were obtained under almost all oxide semiconductor conditions in which good off-current characteristics were obtained when the second insulating film was not formed.

An example of a method for measuring the oxygen content of amorphous SiO _x that is the second insulating film is a temperature programmed desorption analysis (TDS). Although depending on the sample, a desorption peak of oxygen present in the thin film is observed from about several tens of degrees Celsius to about 400 degrees Celsius at the temperature of the thermocouple brought into contact with the substrate surface.

In the present invention, oxygen desorbed from amorphous SiO _{x as} the second insulating film by temperature programmed desorption analysis has been desorbed at about 400 ° C. The measurement temperature range used for the determination was 50 ° C. to 800 ° C. as the temperature of the thermocouple brought into contact with the substrate surface.

That the desorbed gas species (also referred to as desorbed gas or desorbed component) is oxygen is based on the ionic strength of mass number (m / z) 32 corresponding to O ₂ ⁺ and mass number 16 corresponding to O ^+. Identified. However, there is the O ₂ desorbed from the sample is measured as ionized O ₂ ⁺ and O ⁺ by mass spectrometry, the presence form and chemical bond at the O ₂ ⁺ and O ⁺ in the sample is measured The state is not limited to O ₂ ⁺ and O ⁺ . Therefore, in the present invention, any existing form or chemical bonding state is included in the sample as long as it is a component (desorption component) observed as O ₂ ⁺ and O ⁺ when observed by temperature programmed desorption analysis. It may be. FIG. 4 shows an example of an oxygen desorption spectrum measured by the temperature programmed desorption method. The amount of oxygen desorbed from amorphous SiO _x as the second insulating film thus obtained was proportional to the oxygen concentration in the forming atmosphere. FIG. 5 shows the relationship between the amount of oxygen desorbed from amorphous SiO _x measured by the temperature programmed desorption method and the concentration of O ₂ gas contained in Ar as the forming atmosphere.

As a result of intensive research and development on the second insulating film of the thin film transistor using the transparent oxide semiconductor, the present inventors have found the following. That is, when an O ₂ / Ar mixed gas is used as the sputtering film forming gas of amorphous SiO _x and the mixing ratio is 10% by volume or more, generation of oxygen defects in the oxide semiconductor is suppressed, and a large number of carrier electrons are generated and turned off. An increase in current can be prevented.

Amorphous SiO _x with effective in suppressing generation of an oxygen vacancy, when observed by Atsushi Nobori spectroscopy, a component to be observed as O ₂ ⁺ and ^{O +} containing 3.8 × ^{10 19} atoms / cm ³ or more I found out.

In addition, the formation condition with a wider process margin and stable characteristics is a sputter deposition gas O ₂ / Ar mixture ratio of 50 vol%. By doing so, the components (desorption components) observed as O ₂ ⁺ and O ⁺ when observed by the temperature programmed desorption method were contained 1.2 × 10 ²⁰ pieces / cm ³ .

According to the knowledge of the present inventors, there is no upper limit to the sputter deposition gas O ₂ / Ar mixture ratio under the formation conditions of the amorphous SiO _{x having} the effect of suppressing the generation of oxygen defects, and the effect can be obtained even at 100% by volume of O _2. can get. However, since the film forming rate by increasing the O 2 _/ Ar mixing ratio decreases, productivity and the cost of the surface, sputter deposition gas O _{2 /} Ar mixing ratio of about 50% by volume or less is optimal to use is there. The relationship between the sputtering deposition gas O ₂ / Ar mixture ratio of amorphous SiO _x and the deposition rate depends on the deposition parameters such as the deposition gas pressure and the substrate-target distance, but it is very high with respect to the oxygen partial pressure. Sensitive. For this reason, the conditions for forming a high oxygen partial pressure are usually not used. In this formation condition, assuming that the gas O ₂ / Ar mixture ratio of 0 vol% is the reference of the film formation rate (100%), the gas O ₂ / Ar mixture ratio of 10 vol% and 50 vol% are 77% and 39 respectively. % Film formation rate.

A thin film transistor in which amorphous SiO _x was used as the second insulating film and amorphous InGaZnO was formed under the same conditions as the oxide semiconductor with the structure of FIG. 11 was manufactured. At the same time, a TEG element for measuring an oxide semiconductor conductivity was manufactured under the same process conditions, and the conductivity of the oxide semiconductor layer was measured. Von is a gate applied voltage when the drain current (Id) rises in the transfer characteristic of the thin film transistor. FIG. 9 shows the relationship between Von and the conductivity of the oxide semiconductor. There is a strong relationship between the conductivity of the oxide semiconductor and Von. As the conductivity of the oxide semiconductor increases, Von shifts to a negative value. When the conductivity further increases, Von is not observed even at −40 V or less. As is clear from this result, when the second insulating film is formed, the conductivity of the oxide semiconductor increases, and Von indicating the boundary between the off-current and the on-current shifts to the negative side and deteriorates. As a result, the off-current characteristics are deteriorated. Further, the increase in conductivity of the oxide semiconductor is suppressed by the formation conditions of the second insulating film. The suppression effect is recognized when the O ₂ / Ar mixed gas ratio is 10% by volume or more. At that time, the desorbed gas observed as O ₂ ⁺ and O ⁺ is 3.8 × 10 6 by the temperature programmed desorption method. ¹⁹ pieces / cm ³ or more were contained.

Next, as the second insulating film, a sputter deposition gas O ₂ / Ar mixing ratio of 50 vol%, and components observed as O ₂ ⁺ and O ⁺ (desorption) when observed by the temperature programmed desorption method A transistor using amorphous SiO _x containing 1.2 × 10 ²⁰ components / cm ^{3 of the} component was examined. Specifically, nine thin film transistors having the configuration shown in FIG. 2 were manufactured, and thin film transistor characteristics were measured. FIG. 10 shows the transfer characteristics of the nine thin film transistors. Von was controlled to almost 0 V, and a thin film transistor showing a good on / off ratio was obtained.

In the above description, the case where the second insulating film is amorphous SiO _x has been described. However, the amorphous oxide insulator as the second insulating film can use amorphous oxynitride or amorphous alumina. Further, although an example in which an O ₂ / Ar mixed gas is used as an oxidizing gas when forming the second insulating film has been described, the second insulating film is formed so as not to increase the conductivity of the oxide semiconductor. Is the essence of the present invention, and the oxidizing gas is not limited to oxygen.

For example, as a thin film transistor, an amorphous oxide semiconductor layer (a-IGZO thin film) having a composition ratio of indium, gallium, and zinc of 1: 1: 1 is formed by a sputtering method capable of forming a large area. Then, this amorphous oxide semiconductor layer is applied to a thin film transistor to have the configuration of FIG. In this way, the on / off ratio of the transistor can be increased to 10 ⁵ or more. The field effect mobility in that case shows 1 cm < ² > V ^{< -1} > s ^<-1 > or more.

Here, the patterning of the second insulating film will be described. When Ar is included in the gas used for dry etching, the oxide semiconductor layer in contact with the second insulating film to be etched is damaged by etching and has a low resistance due to generation of oxygen deficiency or the like. The mechanism for reducing the resistance is considered to be the same as that when the amorphous SiO _x as the second insulating film is formed in an atmosphere of Ar 100 volume%.

  With the above-described effects, a channel region capable of stably minimizing off-current is formed in a bottom-gate thin film transistor using an oxide semiconductor, and the contact region between the oxide semiconductor layer and the electrode is reduced in resistance. A thin film transistor can be obtained. As a result, a thin film transistor with favorable ohmic contact between the source and drain electrodes and the oxide semiconductor layer can be obtained. In addition, a thin film transistor having favorable transistor characteristics in which off-state current is minimized can be provided.

  In the above description, a transparent conductive oxide semiconductor polycrystalline thin film containing ZnO as a main component or a transparent conductive oxide semiconductor thin film containing ZnO containing a microcrystal as a main component is used as a semiconductor layer (channel layer). Explain the example. Further, an example in which an amorphous oxide including In—Ga—Zn—O is used is described; however, the oxide semiconductor layer is not limited thereto.

  As the amorphous oxide semiconductor layer including In—Ga—Zn—O, an amorphous oxide including at least one element of Sn, In, and Zn can be used.

Further, when Sn is selected as at least a part of the constituent elements of the amorphous oxide, Sn is replaced by Sn _1-x M4 _x (0 <x <1, M4 is Si of a group 4 element having an atomic number smaller than Sn, (Which can be selected from Ge or Zr).

In addition, when In is selected as at least a part of the constituent elements of the amorphous oxide, In is replaced with In _1-y M3 _y (0 <y <1, M3 is Lu or a Group 3 element having an atomic number smaller than In. Selected from B, Al, Ga, and Y).

Further, when Zn is selected as at least a part of the constituent elements of the amorphous oxide, Zn is replaced by Zn _1-z M2 _z (0 <z <1, M2 is a group 2 element Mg having an atomic number smaller than Zn or (Selected from Ca).

  Specifically, amorphous materials applicable to this embodiment are Sn—In—Zn oxide, In—Zn—Ga—Mg oxide, In oxide, In—Sn oxide, In—Ga oxide, In -Zn oxide, Zn-Ga oxide, Sn-In-Zn oxide, and the like. Of course, the composition ratio of the constituent materials is not necessarily 1: 1. In addition, although Zn or Sn may be difficult to form amorphous by itself, an amorphous phase is easily formed by including In. For example, in the case of an In—Zn-based material, it is preferable that the ratio of the number of atoms excluding oxygen be a composition containing In of about 20 atomic% or more. In the case of the Sn—In system, it is preferable that the ratio of the number of atoms excluding oxygen is a composition containing about 80 atomic% or more of In. In the case of the Sn—In—Zn system, it is preferable that the atomic ratio excluding oxygen is a composition containing In of about 15 atomic% or more.

  Amorphous can be confirmed by the fact that a clear diffraction peak is not detected (that is, a halo pattern is observed) when X-ray diffraction is performed on a thin film to be measured at a low incident angle of about 0.5 degrees. . Note that in this embodiment, when the above-described material is used for a channel layer of a field effect transistor, it does not exclude that the channel layer includes a constituent material in a microcrystalline state.

  A display device can be formed by connecting a drain which is an output terminal of the thin film transistor to an electrode of a display element such as an organic or inorganic electroluminescence (EL) element or a liquid crystal element. Hereinafter, an example of a specific display device configuration will be described using a cross-sectional view of the display device.

  For example, a thin film transistor having a structure as shown in FIG. 6 is formed. It includes a gate electrode 612, a gate insulating layer 613, an oxide semiconductor layer 614, a second insulating film 615, a contact region 616 between the oxide semiconductor layer and the electrode, and a drain (source) on the base 611. It comprises an electrode 617 and a drain (source) electrode 618. An electrode 619 is connected to the drain (source) electrode 618 through an interlayer insulating film 622, the electrode 619 is in contact with the light emitting layer 620, and the light emitting layer 620 is in contact with the electrode 621. With such a structure, the current injected into the light-emitting layer 620 can be controlled by the value of current flowing from the source electrode (drain) 617 to the drain (source) electrode 618 through a channel formed in the oxide semiconductor layer 614. It becomes possible. Therefore, this can be controlled by the voltage of the gate 612 of the thin film transistor. Here, the electrode 619, the light emitting layer 620, and the electrode 621 constitute an inorganic or organic electroluminescent element.

  Alternatively, as shown in FIG. 7, a drain (source) electrode 718 is extended to serve as an electrode 719, and this voltage is applied to a liquid crystal cell or an electrophoretic particle cell 722 sandwiched between high resistance films 721 and 723. A configuration in which the electrode 724 is applied can also be employed. The liquid crystal cell, the electrophoretic particle cell 722, the high resistance layers 721 and 723, the electrode 719, and the electrode 724 form a display element. Further, the first insulating film 713, the contact region 716 between the oxide semiconductor layer 714 and the electrode, and the second insulating film 715 are configured as shown in the drawing. The voltage applied to these display elements can be controlled by the value of current flowing from the source electrode 717 to the drain electrode 718 through a channel formed in the oxide semiconductor layer 714. Therefore, this can be controlled by the voltage of the gate 712 of the thin film transistor. If the display medium of the display element is a capsule in which a fluid and particles are sealed in an insulating film, the high resistance films 721 and 723 are unnecessary.

  In the above two examples, the thin film transistor is represented by a bottom-gate inverted staggered configuration, but the present invention is not necessarily limited to this configuration. For example, other configurations such as a coplanar type are possible if the connection between the drain electrode, which is the output terminal of the thin film transistor, and the display element are topologically identical.

  In the two examples described above, an example in which a pair of electrodes for driving the display element is provided in parallel with the base body is illustrated, but the present embodiment is not necessarily limited to this configuration. For example, as long as the connection between the drain electrode, which is the output terminal of the thin film transistor, and the display element are topologically the same, either electrode or both electrodes may be provided perpendicular to the substrate.

  Furthermore, in the above two examples, only one thin film transistor connected to the display element is illustrated, but the present invention is not necessarily limited to this configuration. For example, the thin film transistor shown in the drawing may be further connected to another thin film transistor according to the present invention, and the thin film transistor in the drawing may be the final stage of a circuit using these thin film transistors.

  Here, when a pair of electrodes for driving the display element is provided in parallel with the substrate, if the display element is a reflective display element such as an EL element or a reflective liquid crystal element, any one of the electrodes has an emission wavelength or a reflection wavelength. It is required to be transparent with respect to the wavelength of light. Alternatively, in the case of a transmissive display element such as a transmissive liquid crystal element, both electrodes are required to be transparent to transmitted light.

  Furthermore, in the thin film transistor of this embodiment, it is possible to make all the constituents transparent, whereby a transparent display element can be formed. Further, such a display element can be provided on a low heat-resistant substrate such as a lightweight, flexible and transparent resin plastic substrate.

  Next, a display device in which a plurality of pixels including an EL element (here, an organic EL element) and a thin film transistor are two-dimensionally arranged will be described with reference to FIGS.

  In FIG. 8, reference numeral 801 denotes a transistor for driving the organic EL layer 804, and reference numeral 802 denotes a transistor for selecting a pixel. The capacitor 803 is for holding a selected state, stores charge between the common electrode line 807 and the source portion of the transistor 802, and holds a signal of the gate of the transistor 801. Pixel selection is determined by the scanning electrode line 805 and the signal electrode line 806.

  More specifically, an image signal is applied as a pulse signal from a driver circuit (not shown) to the gate electrode through the scanning electrode 805. At the same time, a pixel is selected by applying a pulse signal from another driver circuit (not shown) to the transistor 802 through the signal electrode 806. At that time, the transistor 802 is turned on, and charge is accumulated in the capacitor 803 between the signal electrode line 806 and the source of the transistor 802. Accordingly, the gate voltage of the transistor 801 is held at a desired voltage, and the transistor 801 is turned on. This state is maintained until the next signal is received. While the transistor 801 is ON, voltage and current are continuously supplied to the organic EL layer 804 and light emission is maintained.

  In the example of FIG. 8, the configuration includes two transistors and one capacitor per pixel, but more transistors and the like may be incorporated in order to improve performance. Essentially, an effective EL element can be obtained by using an In—Ga—Zn—O-based thin film transistor that is a transparent thin film transistor that can be formed at a low temperature according to the present invention.

  Examples of the present invention will be described below, but the present invention is not limited to these examples.

Example 1
In this example, an inverted staggered (bottom gate) type MISFET element shown in FIG. 11 was produced. First, a gate terminal of Ti 5 nm / Au 40 nm / Ti 5 nm was formed on a glass substrate by using a photolithography method and a lift-off method. Further, an insulating layer made of a-SiO _x was formed to 200 nm thereon by sputtering. At that time, a SiO ₂ target was used as the sputtering target, and Ar gas was used as the sputtering gas. The RF high frequency power was 400 W and the film forming pressure was 0.1 Pa. The substrate temperature was room temperature and no intentional heating was performed. Then, 20 nm of an amorphous oxide semiconductor film used as a semiconductor layer was formed by sputtering at room temperature. At that time, a polycrystalline InGaZnO ₄ target was used, and an O ₂ / Ar gas mixture ratio of 5% by volume was used as the sputtering gas. The RF high frequency power was 200 W and the film forming pressure was 0.1 Pa. The substrate temperature was room temperature and no intentional heating was performed. The channel region was formed by photolithography and wet etching with hydrochloric acid. Thereafter, Ti 5 nm / Au 100 nm / Ti 5 nm was formed by electron beam evaporation, and source and drain terminals were formed by photolithography and lift-off. Furthermore, an insulating layer made of a-SiO _x was formed to 100 nm as the second insulating film by sputtering. At that time, SiO ₂ was used as a target, and an oxidizing atmosphere having an O ₂ / Ar mixture ratio of 50% by volume of O ₂ gas 5SCCM and Ar gas 5SCCM was used as a sputtering gas. The substrate temperature was room temperature and no intentional heating was performed. Thus, nine inverted staggered (bottom gate) type MISFET elements shown in FIG. 11 were completed. At that time, the metal composition ratio of the amorphous oxide semiconductor film was In: Ga: Zn = 1.00: 0.94: 0.65. As a result of evaluation of IV characteristics of this MISFET element, nine thin film transistors had an average field effect mobility of 5.0 cm ² / Vs and an average on / off ratio of 10 ⁶ or more. FIG. 12 shows the transfer characteristics.

  When the second insulating film of the present invention is used, a thin film transistor having favorable transistor characteristics in which off-state current is minimized can be stably manufactured.

(Example 2)
In this example, an inverted staggered (bottom gate) type MISFET element shown in FIG. 11 was produced in the same manner as in Example 1 except for the conditions for forming the second insulating film.

As the second insulating film, an insulating layer made of a-SiO _x was formed to a thickness of 100 nm by a sputtering method. At that time, an oxidizing atmosphere having an O ₂ / Ar mixed gas ratio of 10 vol% was used as a sputtering gas. Thus, nine inverted staggered (bottom gate) type MISFET elements shown in FIG. 11 were completed.

At the same time, a TEG element for measuring an oxide semiconductor conductivity was manufactured under the same process conditions, and the conductivity of the oxide semiconductor layer was measured. Von is a gate applied voltage when the drain current (Id) rises in the transfer characteristic of the thin film transistor. FIG. 9 shows the relationship between Von and the conductivity of the oxide semiconductor. In addition, the second insulating film made of a-SiO _x using an O ₂ / Ar mixed gas ratio of 10% by volume as the sputtering gas is observed as O ₂ ⁺ and O ⁺ when observed by the temperature programmed desorption method. The component (desorbed component) contained 3.8 × 10 ¹⁹ pieces / cm ³ .

As a result, the second insulating film made of a-SiO _x using an O ₂ / Ar mixed gas ratio of 10% by volume has an effect of suppressing the generation of oxygen defects in the oxide semiconductor, and Von: −40 V is set as an average value. A good on / off ratio of 10 ⁶ or more was exhibited.

(Comparative Example 1)
In this comparative example, an inverted staggered (bottom gate) type MISFET element shown in FIG. 11 was fabricated in the same manner as in Example 1 except for the conditions for forming the second insulating film.

As the second insulating film, an insulating layer made of a-SiO _x was formed to a thickness of 100 nm by a sputtering method. At that time, an oxidizing atmosphere having an O ₂ / Ar mixed gas ratio of 1 vol% and 0 vol% was used as a sputtering gas. Thus, nine inverted staggered (bottom gate) type MISFET elements shown in FIG. 11 were completed.

As a result, when the O ₂ / Ar mixed gas ratio is 1% by volume and 0% by volume, variation in characteristics increases, and even when −50 V is applied as the gate voltage, a clear Von may not be observed. On the other hand, no clear deterrent effect was observed for the generation of oxygen defects.

(Example 3)
In this example, the inverted staggered (bottom gate) type MISFET element shown in FIG. 1 was produced.

First, the gate electrode layer 150 nm of the transparent conductive film IZO was formed on the glass substrate by sputtering. A gate electrode was formed by wet etching using photolithography and hydrochloric acid. Further, an insulating layer made of a-SiO _x was formed to 200 nm thereon by sputtering. At that time, a SiO ₂ target was used as the sputtering target, and Ar gas was used as the sputtering gas. The RF high frequency power was 400 W and the film forming pressure was 0.1 Pa. The substrate temperature was room temperature and no intentional heating was performed. Then, 20 nm of an amorphous oxide semiconductor film used as a semiconductor layer was formed by sputtering at room temperature. At that time, a polycrystalline InGaZnO ₄ target was used, and an O ₂ / Ar gas mixture ratio of 5% by volume was used as the sputtering gas. The RF high frequency power was 200 W and the film forming pressure was 0.1 Pa. The substrate temperature was room temperature and no intentional heating was performed. The channel region was formed by photolithography and wet etching with hydrochloric acid. Thereafter, an insulating layer made of a-SiO _x was formed to a thickness of 100 nm as a second insulating film by sputtering. At that time, an oxidizing atmosphere having an O ₂ / Ar mixed gas ratio of 50 vol% was used as a sputtering gas. The RF high frequency power was 400 W and the film forming pressure was 0.1 Pa. The substrate temperature was room temperature and no intentional heating was performed. Using the photolithography method and dry etching with Ar-containing CF 4 gas, the contact region between the oxide semiconductor layer and the electrode, which has been reduced in resistance by etching, was completed. At that time, a mixed gas of CF ₄ gas 20 SCCM and Ar gas 5 SCCM was used as an etching gas. The RF high frequency power was 150 W and the etching pressure was 5 Pa. Thereafter, a transparent conductive film ITO was formed by a 150 nm sputtering method. At that time, an Sn target of Sn 5% by mass was used as a target. The RF high frequency power was 200 W and the film forming pressure was 0.2 Pa. The substrate temperature was room temperature and no intentional heating was performed. Thereafter, source and drain terminals were formed by photolithography and etching. Thus, the inverted staggered (bottom gate) type transparent MISFET element shown in FIG. 1 was formed.

  As a source electrode and a drain electrode, not only a transparent conductive oxide film such as IZO but also a metal such as Ni, Cr, Rh, Mo, Nd, Ti, W, Ta, Pb, Al, an alloy containing these, or a silicide is used. be able to. In addition, the source electrode and the drain electrode can be formed of different materials.

  In this inverted staggered (bottom gate) type MISFET element, a channel region capable of stably minimizing off-current is formed in the oxide semiconductor layer, and a contact region between the oxide semiconductor layer and the electrode is formed with a low resistance. Yes. Accordingly, a thin film transistor in which off current is minimized and an ohmic contact between the source and drain electrodes and the oxide semiconductor layer is favorable.

Example 4
In this embodiment, a display device using the thin film transistor of FIG. 7 will be described. The manufacturing process of the thin film transistor used is the same as in Example 3.

  In the above thin film transistor, the short side of the ITO film island forming the drain electrode is extended to 100 μm, leaving the extended 90 μm portion, ensuring wiring to the source electrode and the gate electrode, and then covering the thin film transistor with an insulating layer did. A polyimide film was applied thereon and subjected to a rubbing process. On the other hand, an ITO film and a polyimide film are similarly formed on a plastic substrate, and a rubbing process is prepared. The substrate on which the thin film transistor is formed is opposed to the substrate with a gap of 5 μm, and nematic liquid crystal is injected therein. . Furthermore, a pair of polarizing plates was provided on both sides of the structure. Here, when a voltage is applied to the source electrode of the thin film transistor and the applied voltage of the gate electrode is changed, the light transmittance changes only in the 30 μm × 90 μm region that is a part of the island of the ITO film extended from the drain electrode. did. Further, the transmittance can be continuously changed by the source-drain voltage under the gate voltage at which the thin film transistor is turned on. In this way, a display device having a liquid crystal cell as a display element corresponding to FIG. 7 was produced.

  In this embodiment, a white plastic substrate is used as a substrate for forming a thin film transistor, each electrode of the thin film transistor is replaced with gold, and the polyimide film and the polarizing plate are eliminated. And it is set as the structure filled with the capsule which coat | covered the particle | grains and the fluid with the insulating film in the space | gap of a white and transparent plastic substrate. In the case of a display device having this configuration, the voltage between the drain electrode extended by the thin film transistor and the ITO film on the upper part is controlled, so that the particles in the capsule move up and down. Accordingly, display can be performed by controlling the reflectance of the extended drain electrode region viewed from the transparent substrate side.

  In this embodiment, a plurality of thin film transistors are formed adjacent to each other to form a current control circuit having, for example, a normal 4-transistor 1-capacitor configuration, and one of the final stage transistors is used as the thin film transistor in FIG. It can also be driven. For example, a thin film transistor using the above ITO film as a drain electrode is used. Then, an organic electroluminescence element composed of a charge injection layer and a light emitting layer is formed in a 30 μm × 90 μm region that is a part of the island of the ITO film extended from the drain electrode. Thus, a display device using an EL element can be formed.

(Example 5)
The display element of Example 3 and the thin film transistor were two-dimensionally arranged. For example, a pixel occupying an area of about 30 μm × 115 μm including a display element such as a liquid crystal cell or an EL element of Example 4 and a thin film transistor is 7425 × each at a pitch of 40 μm in the short side direction and a pitch of 120 μm in the long side direction. 1790 square array. Then, there are 1790 gate wirings penetrating through the gate electrodes of 7425 thin film transistors in the long side direction, and a signal through which the source electrode of the 1790 thin film transistors protrudes 5 μm from the island of the amorphous oxide semiconductor film in the short side direction. 7425 wirings were provided. And each was connected to the gate driver circuit and the source driver circuit. Further, in the case of a liquid crystal display element, an A4 size active matrix type color image display apparatus of about 211 ppi can be configured by providing a color filter on the surface with the same size as that of the liquid crystal display element and with RGB repeating in the long side direction. be able to.

  Also, in the EL element, among the two thin film transistors included in one EL element, the gate electrode of the first thin film transistor is wired to the gate line, the source electrode of the second thin film transistor is wired to the signal line, and the light emission of the EL element is further performed. The wavelength is repeated in RGB in the long side direction. In this way, a light emitting color image display device having the same resolution can be configured.

  Here, the driver circuit for driving the active matrix may be configured using the thin film transistor of the present invention which is the same as the thin film transistor of the pixel, or an existing IC chip may be used.

(Example 6)
In this example, the top gate type MISFET element shown in FIG. 14 was produced. First, an amorphous oxide semiconductor layer used as a semiconductor layer was formed to a thickness of 100 nm on a glass substrate by sputtering at room temperature. At that time, a polycrystalline InGaZnO ₄ target was used, and an O ₂ / Ar gas mixture ratio of 1.5 vol% was used as the sputtering gas. The RF high frequency power was 300 W and the film forming pressure was 0.2 Pa. The substrate temperature was room temperature and no intentional heating was performed. Photolithography and wet etching with hydrochloric acid were used for patterning the channel region. Thereafter, an insulating layer made of a-SiO _x was formed to a thickness of 200 nm as the second insulating film by sputtering. At that time, SiO ₂ was used as a target, and an oxidizing atmosphere with an O ₂ / Ar mixture ratio of 50 volume% was used as a sputtering gas. The RF high frequency power was 500 W and the film forming pressure was 0.2 Pa. The substrate temperature was room temperature and no intentional heating was performed. Thereafter, as a method for forming a contact region between the electrode layer and the amorphous oxide semiconductor, the second insulating film is dry-etched with Ar-containing CF ₄ gas to cover the oxide semiconductor layer other than the channel region. The film was patterned. A mixed gas of CF ₄ gas 20 SCCM and Ar gas 5 SCCM was used as an etching gas. The RF high frequency power was 150 W and the etching pressure was 5 Pa. Next, an IZO electrode layer serving as a source electrode, a drain electrode, and a gate electrode was formed to a thickness of 150 nm on the contact region between the patterned second insulating film and the amorphous oxide semiconductor layer by a sputtering method. At that time, an IZO target of ZnO 10 mass% was used as a target. The RF high frequency power was 200 W and the film forming pressure was 0.2 Pa. The substrate temperature was room temperature and no intentional heating was performed. The electrode layer was patterned by etching to form a source electrode, a drain electrode, and a gate electrode.

  Thus, the top gate type MISFET element shown in FIG. 14 was formed.

As described above, when the second insulating film of the present invention is used and patterning is performed by dry etching using Ar-containing CF ₄ gas, the following results can be obtained. That is, the off-state current is minimized, and a thin film transistor having favorable transistor characteristics with an ohmic contact between the source electrode and the drain electrode and the amorphous oxide semiconductor can be stably manufactured.

  The thin film transistor produced by the method for producing a thin film transistor according to the present invention can be applied as a switching element for an LCD or an organic EL display. In addition, all processes of thin film transistors can be formed at low temperatures on flexible materials such as plastic films, and can be widely applied to flexible displays, IC cards, ID tags, and the like.

FIG. 10 is a structural diagram of an inverted staggered thin film transistor in which a contact region between an oxide semiconductor layer and an electrode has a reduced resistance. It is a structural diagram of an inverted staggered thin film transistor using a thermal oxide film silicon gate insulating film on a low resistance n-type silicon substrate. It is a figure which shows the typical current-voltage characteristic at the time of producing the reverse stagger type thin-film transistor of FIG. It is an example of the oxygen desorption spectrum of the 2nd insulating layer measured by the temperature programmed desorption method. Is a diagram showing an O ₂ gas concentration relationships contained in Ar is forming atmosphere and amount of oxygen released from amorphous SiOx measured by Atsushi Nobori spectroscopy. It is sectional drawing of an example of the display apparatus concerning this invention. It is sectional drawing of the other example of the display apparatus concerning this invention. It is a figure which shows the structure of the display apparatus which has arrange | positioned the pixel containing an organic EL element and a thin-film transistor two-dimensionally. It is a figure which shows the relationship between the conductivity of Von and an oxide semiconductor in a reverse stagger (bottom gate) type MISFET element. 9 is a graph showing the transfer characteristics of nine thin film transistors when nine thin film transistors having the configuration of FIG. 2 are manufactured and the thin film transistor characteristics are measured. It is a structural diagram of an inverted staggered thin film transistor having a protective film. 12 is a graph showing the transfer characteristics of the nine thin film transistors when nine thin film transistors having the configuration shown in FIG. 11 are manufactured and the thin film transistor characteristics are measured. FIG. 11 is a cross-sectional view of an element for each manufacturing process of an inverted staggered thin film transistor element in which a contact region between an oxide semiconductor layer and an electrode has a reduced resistance. FIG. 10 is a structural diagram of a top-gate thin film transistor in which a contact region between an oxide semiconductor layer and an electrode has a reduced resistance. It is a figure of the element for every manufacturing process of the top gate type thin-film transistor element in which the contact region of an oxide semiconductor layer and an electrode was made low resistance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 First insulating film 4 Oxide semiconductor layer 5 Second insulating film 6 Contact region 7 with reduced resistance Source electrode (source terminal)
8 Drain electrode (drain terminal)
201 gate electrode / substrate 202 thermally oxidized silicon insulating film 203 oxide semiconductor layer 204 second insulating film 205 source electrode 206 drain electrode 611 base 612 gate electrode 613 gate insulating layer 614 oxide semiconductor layer 615 second insulating layer 616 contact Region 617 Drain (source) electrode 618 Drain (source) electrode 619 Electrode 620 Light emitting layer 621 Electrode 622 Interlayer insulating film 711 Substrate 712 Gate electrode 713 First insulating film 714 Oxide semiconductor layer 715 Second insulating film 716 Contact region 717 Source electrode 718 Drain electrode 719 Electrode 720 Light emitting layer 721 High resistance film 722 Liquid crystal cell or electrophoretic particle cell 723 High resistance film 801 Transistor 802 Transistor 803 Capacitor 804 Organic EL layer 805 Scanning electrode line 806 Signal electrode line 807 Common electrode line 1401 Base 1402 Oxide semiconductor layer 1403 Second insulating film 1404 Contact region 1405 Gate electrode 1406 Source electrode 1407 Drain electrode

Claims (12)

A method of manufacturing a thin film transistor having a gate electrode, a first insulating film, an oxide semiconductor layer, a second insulating film, a source electrode, and a drain electrode on a substrate,
Forming a gate electrode on the substrate;
Forming a first insulating film on the gate electrode;
Forming an oxide semiconductor layer on the first insulating film;
Patterning the oxide semiconductor layer;
Forming the second insulating film on the oxide semiconductor layer in an atmosphere containing an oxidizing gas;
Patterning the second insulating film using an etching gas containing an inert gas, exposing a contact region with the electrode in the oxide semiconductor layer, and reducing the resistance of the contact region;
Forming an electrode layer to be a source electrode and a drain electrode in the contact region;
Patterning the electrode layer to form a source electrode and a drain electrode;
Only including,
The method of manufacturing a thin film transistor, wherein an on / off ratio of the thin film transistor is 10 ⁶ or more . A method of manufacturing a thin film transistor having, on a substrate, at least a gate electrode, an oxide semiconductor layer, a second insulating film, a source electrode, and a drain electrode,
Forming an oxide semiconductor layer over the substrate;
Patterning the oxide semiconductor layer;
Forming a second insulating film on the oxide semiconductor layer in an atmosphere containing an oxidizing gas;
Patterning the second insulating film using an etching gas containing an inert gas, exposing a contact region with the electrode in the oxide semiconductor layer, and reducing the resistance of the contact region;
Forming an electrode layer to be a source electrode and a drain electrode in the contact region;
Forming a gate electrode on the second insulating film;
Patterning the electrode layer to form a source electrode and a drain electrode;
Only including,
The method of manufacturing a thin film transistor, wherein an on / off ratio of the thin film transistor is 10 ⁶ or more . 3. The method of manufacturing a thin film transistor according to claim 1, wherein an O ₂ / Ar mixed gas is used as the oxidizing gas, and a mixing ratio thereof is 10% by volume or more.   4. The thin film transistor according to claim 1, wherein the oxide semiconductor layer includes an oxide containing at least one of In, Zn, and Sn, or In, Zn, and Ga. 5. Method. The second insulating film is an amorphous oxide insulator and contains 3.8 × 10 ¹⁹ / cm ³ or more of components observed as O ₂ ⁺ and O ⁺ when observed by thermal desorption analysis. 4. The method of manufacturing a thin film transistor according to claim 1, wherein:   5. The method of manufacturing a thin film transistor according to claim 1, wherein the second insulating film is any one of silicon oxide, silicon oxynitride, and aluminum oxide. 7. The method for manufacturing a thin film transistor according to claim 1, wherein the oxide semiconductor layer has a conductivity of 10 ⁻³ S / cm or more and 10 ⁻⁷ S / cm or less.   A thin film transistor manufactured by the manufacturing method according to claim 1.   A display device, wherein the source or drain electrode of the thin film transistor according to claim 8 is connected to an electrode of the display element.   The display device according to claim 9, wherein the display element is an electroluminescence element.   The display device according to claim 9, wherein the display element is a liquid crystal cell.   The display device according to claim 9, wherein a plurality of the display elements and the thin film transistors are two-dimensionally arranged on a substrate.