JP5084160B2 - Thin film transistor and display device - Google Patents

Description

  The present invention relates to a thin film transistor and a display device, and more particularly to a shape structure of a gate insulating layer included in the thin film transistor. The thin film transistor of the present invention is suitably used for an active matrix liquid crystal display device or the like.

  A thin film transistor (TFT) is a three-terminal element including a gate electrode, a source electrode, and a drain electrode. The thin film transistor is an electronic active element having a function of applying a voltage to the gate electrode to control a current flowing in the channel layer and switching a current between the source electrode and the drain electrode.

  The TFT is suitable for a driving substrate such as an active matrix liquid crystal display. However, when these are applied to a liquid crystal display panel having a large area, cost reduction of the substrate is required. For this reason, glass substrates are now being used instead of conventional high-quality quartz substrates. When a glass substrate is used, since the heat resistance is low, it is required to form a thin film transistor by a low temperature process of 600 ° C. or lower. Currently, the most widely used is a metal-insulator-semiconductor field effect transistor (MIS-FET) element using a polycrystalline silicon or amorphous silicon film as a channel layer material. However, amorphous silicon is superior in consistency with a low temperature process.

  In normal driving of an active matrix circuit, a forward bias voltage (a positive voltage for the N channel type and a negative voltage for the P channel type) is applied at the time of selection, and the reverse voltage is applied at other times of non-selection. If the insulating property between the source and drain of the TFT is insufficient at the time of non-selection, the charge accumulated in the pixel is immediately released, and an image with high contrast cannot be obtained. Therefore, in order to use a TFT as a switching element of an active matrix circuit, a small leak current is required even with reverse bias. A TFT formed from amorphous silicon has a feature of low off-state current when not selected, although the field effect mobility is inferior to that of polycrystalline silicon, and an amorphous silicon TFT is suitable for the above purpose.

  Recently, an oxide material has attracted attention as a material applicable to a TFT channel layer.

  For example, TFTs using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component for a channel layer are being actively developed. The thin film can be formed at a low temperature and can be formed on a substrate such as a plastic plate or a film. Further, in a TFT having a ZnO film as a semiconductor active layer, the semiconductor active layer is hardly affected by light because the ZnO film is transparent to visible light even if light enters the semiconductor active layer. Therefore, a TFT having a ZnO film as a semiconductor active layer hardly causes a problem that it cannot operate normally even when light is incident.

As another semiconductor element using a metal oxide semiconductor for a channel layer, a TFT using an In—Ga—Zn—O-based amorphous oxide has been reported (Non-patent Document 1). The thin film can also be formed on a plastic or glass substrate at room temperature, and is characterized by being transparent to visible light. In addition, TFTs using an amorphous In-Ga-Zn-O film for the channel layer have a field-effect mobility of about 10 cm ² / Vs and normally-off transistor characteristics. have.

Conventionally, SiO ₂ is generally used as a gate insulating layer of a thin film transistor. Even in a transistor in which an oxide is applied to a channel layer, studies using these gate insulating layers have been made. Attempts have also been made to realize a thin film transistor having a large on-current by using a gate insulating layer having a high dielectric constant such as Al ₂ O ₃ or Y ₂ O ₃ .

As a method for forming the SiO ₂ film, a CVD method, a sputtering method, a thermal oxidation method, etc. are generally used, but the sputtering method is superior in that a low temperature process is possible and an oxide film having excellent characteristics can be obtained. You can say that. Further, as a method for forming a gate insulating layer made of a metal oxide such as Al ₂ O ₃ or Y ₂ O ₃ , a sputtering method that is excellent in mass productivity is currently mainstream.
K. Noumra et.al, Nature 432, 488 (2004)

However, in a bottom gate type TFT using an amorphous In—Ga—Zn—O film as an active layer for the channel layer, sputtered SiO ₂ , Al ₂ O ₃ and Y ₂ O ₃ were used for the insulating layer. TFT has a large hysteresis and it is difficult to obtain good transistor characteristics. At this time, the field effect mobility was about 60% of the mobility originally predicted from the physical properties of the amorphous In—Ga—Zn—O film, and the gate leakage current also showed a relatively large value.

  The present invention has been made to solve the above-described problems, and provides a thin film transistor capable of preventing a reduction in field-effect mobility and hysteresis and reducing a gate leakage current by devising a gate insulating layer structure. For the purpose.

The present inventor observed a bottom gate type TFT element using an amorphous In—Ga—Zn—O film as an active layer in the channel layer as described above with a cross-sectional transmission electron microscope (TEM). It was found that a columnar structure of about 50 nm was formed. In the Y ₂ O ₃ insulating film, a polycrystalline phase was formed in the film, and it was confirmed that the crystal grains had a columnar structure. A columnar structure was also confirmed in a film having an amorphous structure, and it was found that a columnar structure was formed due to the density of atoms existing per unit volume. In these cases, it is considered that a columnar structure is easily formed in the insulating film because sputtering gas ions having a large energy accelerated by the electric field and the ionized target material are perpendicularly incident on the substrate.

  From the results of the cross-sectional TEM, the TFT using the sputtered insulating layer has a large hysteresis and a low field-effect mobility, and the columnar structure that becomes a trap of carriers at the interface between the active layer and the insulating film. It is possible that there was a boundary. The reason why the gate leakage current is large is that a leak path is formed along the boundary of the columnar structure. This gate leakage increases the power consumption of the device and prevents stable operation of the device, so it must be suppressed as much as possible. It was also found that the fracture strength in the direction perpendicular to the substrate was low due to the grain boundaries being oriented perpendicular to the substrate.

Based on these results, the present inventor continued further research and came to invent the following thin film transistor of the present invention. That is, the thin film transistor of the present invention has a structure in which a semiconductor layer and a gate insulating layer are stacked, and the semiconductor layer is an oxide semiconductor containing at least one of In, Sn, and Zn, and the gate insulating layer includes It has a columnar structure, and the columnar structure is inclined with respect to the thickness direction of the gate insulating layer.

  The display device of the present invention uses the thin film transistor of the present invention.

  According to the present invention, in the gate insulating layer, since the diameter of the columnar structure on the surface in contact with the semiconductor layer is increased, interface defects are reduced, and a TFT having higher field effect mobility and low hysteresis can be obtained. . Further, since the leak path has an inclination with respect to the electric field direction and the leak path itself becomes long, the leak current is reduced and the withstand voltage is improved. Furthermore, since the layer thickness direction and the columnar structure do not coincide with each other, the mechanical strength can be increased and the durability can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  1A and 1B are cross-sectional views showing an embodiment of a field effect thin film transistor of the present invention. As shown in FIG. 1, a gate electrode 11 is provided on a substrate 10, and a gate insulating layer 12, a channel layer (semiconductor layer) 13, a source electrode 14, and a drain electrode 15 are provided on the gate electrode 11. The gate insulating layer 12 has a structure having an inclined columnar structure.

(Gate insulation layer)
In the thin film transistor of this embodiment, as the gate insulating layer 12, in addition to generally used SiO ₂ , any one of Al ₂ O ₃ and Y ₂ O ₃ having a high dielectric constant or a film in which these are laminated is used. It may be used. In particular, when Y ₂ O ₃ is used as a gate insulating layer in a TFT in which a channel layer is formed of an In—Ga—Zn—O-based oxide thin film, a TFT having a high field effect mobility and a low threshold can be obtained, and hysteresis is also reduced. be able to. The layer thickness of the gate insulating layer is required to ensure the insulation between the gate electrode and the channel layer or another electrode, but may be 100 nm or more.

  As a method for forming the gate insulating layer, it is preferable to use a vapor deposition method such as a sputter deposition method, an electron beam deposition method, or an atomic layer deposition method. When a gate insulating layer is generally manufactured by a PVD (physical vapor deposition) method, the gate insulating layer has a columnar structure, and is particularly noticeable in a sputter deposition method. The direction of the columnar structure can be adjusted by changing the angle of the substrate with respect to the deposition source. The adjustment of the angle of the columnar structure with respect to the layer thickness direction can be realized by tilting the substrate with respect to the vapor deposition source from a parallel position. Note that the columnar structure may be inclined clockwise with respect to the thickness direction of the gate insulating layer 12, or the columnar structure may be inclined counterclockwise with respect to the layer thickness direction of the gate insulating layer 12.

  FIG. 2A is a layout diagram of a vapor deposition source and a substrate in the film forming apparatus used in this embodiment, and FIG. 2B is a schematic diagram of a columnar structure in an insulating film.

  It is also possible to form a columnar structure having two or more different inclination directions in the gate insulating layer 12 by changing the angle of the substrate during film formation. For example, as shown in FIG. 1B, the gate insulating layer is composed of two regions 12a and 12b so that a columnar structure having two or more different inclination directions is formed in the gate insulating layer 12. The region 12 a is a region that forms an interface with the channel layer 13, and the columnar structure is inclined clockwise with respect to the layer thickness direction of the gate insulating layer 12. On the other hand, the region 12 b is a region that forms an interface with the substrate 10 and the gate electrode 11, and the columnar structure is inclined counterclockwise with respect to the thickness direction of the gate insulating layer 12. In this manner, by forming a columnar structure having two or more different inclination directions in the gate insulating layer, resistance to stress can be improved. For example, when a flexible substrate is used as the substrate, the substrate is curved and stress is applied to the gate insulating layer 12 as well. Therefore, such a gate having a columnar structure having two or more different inclination directions is used. An insulating layer can be suitably used.

  FIG. 3 shows a schematic diagram of a gate insulating layer and a semiconductor layer of the thin film transistor of the present invention. FIG. 3A is a perspective view of a cross section in a direction parallel to the substrate of the gate insulating layer. FIG. 3B is a perspective view showing an interface between the gate insulating layer and the semiconductor layer. For comparison, FIG. 4 shows a schematic diagram of a gate insulating layer and a semiconductor layer of a thin film transistor in which a substrate is formed in a parallel position with respect to an evaporation source. FIG. 4A is a perspective view of a cross section in a direction parallel to the substrate of the gate insulating layer. FIG. 4B is a perspective view showing an interface between the gate insulating layer and the semiconductor layer.

In the gate insulating layer of this embodiment, as shown in FIG. 3, since the diameter of the columnar structure on the surface in contact with the active layer is larger than that in the configuration of FIG. 4, the interface defect density is reduced. That is, a TFT having higher field effect mobility and low hysteresis can be realized. Further, since the leak path has an inclination with respect to the electric field direction, and the leak path itself becomes longer, the leak current is reduced and the withstand voltage is improved.
Further, it has been found that in a very thin structure configured by stacking thin films, the direction perpendicular to the film surface is the weakest in strength. In the insulating layer in the present embodiment, the layer thickness direction and the columnar structure direction do not coincide with each other, so that the mechanical strength can be increased and the durability can be improved.

  According to the diligent study by the present inventors, it is particularly preferable that the inclination angle of the columnar structure with respect to the layer thickness direction is 5 degrees or more. With respect to a TFT having such an insulating layer, a TFT having particularly small hysteresis and excellent characteristics can be realized. The inclination angle may be 5 degrees or more, but as the inclination angle approaches 90 degrees, that is, as it approaches parallel to the channel layer, as shown in FIG. The surface in the B direction is harder to deposit than the surface in the A direction, so that uniform film growth becomes difficult. Therefore, the upper limit of the tilt angle is defined within a range where uniform film growth is possible.

(Channel layer)
As a material for the channel layer, an oxide including at least one element of Sn, In, and Zn, or a channel layer made of amorphous silicon can be used. When the gate insulating layer of the present embodiment is applied, the diameter of the columnar structure at the interface of the gate insulating layer, which has been a cause of lowering the field effect mobility, is increased. Therefore, by using an In—Ga—Zn—O-based oxide thin film and a ZnO thin film, which originally have a large electron carrier mobility, for a channel layer, a TFT having a high field effect mobility can be realized. In addition, since an In—Ga—Zn—O-based oxide thin film in which the atomic ratio of Zn to In is 65% or less forms a stable amorphous phase at room temperature, a better interface with the gate insulating layer of this embodiment is obtained. A TFT which is formed and has particularly excellent characteristics can be obtained. In some cases, an intermediate layer such as amorphous SiO, amorphous SiN, or amorphous SiON may be formed between the channel layer and the insulating film. As a result, the capability of the gate insulating layer can be prevented from being lowered, for example, leakage current can be suppressed, and the on / off ratio of the transistor can be improved. As a method for forming the intermediate layer, it is preferable to use a sputtering method, a pulse laser deposition method, an electron beam evaporation method, and a plasma CVD (chemical vapor deposition) method, but the film formation method is limited to these methods. is not.

  As a film forming method of the metal oxide used for the channel layer, it is preferable to use a vapor phase method such as a sputtering method, a pulse laser vapor deposition method and an electron beam vapor deposition method. Of the vapor phase methods, the sputtering method is suitable from the viewpoint of mass productivity. Further, as a method for forming an amorphous silicon film, a plasma CVD method, a thermal CVD method, or the like may be used in addition to the vapor deposition method and the sputtering method. However, the film forming method is not limited to these methods.

In particular, in a thin film transistor in which a metal oxide is applied to a channel layer, a semi-insulating oxide film having an electric conductivity of 10 S / cm or less and 0.0001 S / cm or more is used for the channel layer in order to obtain good TFT characteristics. It is preferable to apply to the channel layer. In order to obtain such electrical conductivity, it is preferable to form an oxide film having an electron carrier concentration of about 10 ¹⁴ to 10 ¹⁸ / cm ³ depending on the material composition of the channel layer.

  When the electrical conductivity is 10 S / cm or more, a normally-off transistor cannot be formed, and the on / off ratio cannot be increased. In an extreme case, even when a gate voltage is applied, the current between the source and drain electrodes is not turned on / off, and transistor operation is not exhibited. On the other hand, when the insulator, that is, the electric conductivity is 0.0001 S / cm or less, the on-current cannot be increased. In an extreme case, even when a gate voltage is applied, the current between the source and drain electrodes is not turned on / off, and transistor operation is not exhibited.

Usually, in order to control the electrical conductivity and the electron carrier concentration of an oxide, it is performed by controlling the oxygen partial pressure during film formation. That is, by controlling the oxygen partial pressure, mainly the amount of oxygen vacancies in the thin film is controlled, thereby controlling the electron carrier concentration. FIG. 5 is a diagram illustrating an example of the oxygen partial pressure dependence of the carrier concentration when an In—Ga—Zn—O-based oxide thin film is formed by a sputtering method. Actually, by controlling the oxygen partial pressure to a high degree, an oxide semi-insulating film having an electron carrier concentration of 10 ¹⁴ to 10 ¹⁸ / cm ³ and having semi-insulating properties can be obtained. A good TFT can be produced by applying to the channel layer. As shown in FIG. 5, typically, a semi-insulating thin film can be obtained by forming a film at an oxygen partial pressure of about 0.005 Pa. At 0.001 Pa or less, insulation is obtained. On the other hand, at 0.01 Pa or more, the electric conductivity is too high, which is not suitable as a channel layer of a transistor.

The material of the source electrode 14, the drain electrode 15, and the gate electrode 11 is not particularly limited as long as it can provide good electrical conductivity and electrical connection to the channel layer. For example, a transparent conductive film such as In ₂ O ₃ : Sn or ZnO or a metal film such as Au, Pt, Al, or Ni can be used.

  As the substrate 10, a glass substrate, a metal substrate, a plastic substrate, a plastic film, or the like can be used although depending on a material such as a channel layer.

(TFT characteristics)
FIG. 6 shows typical characteristics of the field effect transistor of the present invention. When a voltage Vd of about 5 V is applied between the source and drain electrodes, the current Id (μA) between the source and drain electrodes can be controlled (turned on and off) by sweeping the gate voltage Vg between −1 V and 5 V. it can. FIG. 6A is an example of Id-Vd characteristics at various Vg, and FIG. 6B is an example of Id-Vg characteristics (transfer characteristics) at Vd = 6V.

(Hysteresis)
The hysteresis will be described with reference to FIG. In the evaluation of TFT transfer characteristics, hysteresis means that when Vd is fixed and Vg is swept (up and down) as shown in FIG. 7, Id shows different values when the voltage rises and when it falls. . If the hysteresis is large, the value of Id obtained with respect to the set Vg varies. Therefore, an element having a small hysteresis is preferable.

  7A and 7B, respectively, in the gate insulating layer, the columnar structure grows in parallel to the layer thickness direction, and the columnar structure inclines with respect to the layer thickness direction ( Hereinafter, an example of the TFT transfer characteristic of the columnar inclined film) is shown. When a gate insulating layer in which a columnar structure grows in parallel with the layer thickness direction is applied, the hysteresis characteristic as shown in FIG. 7A is shown. In such a case, an element having a small hysteresis can be obtained as shown in FIG. Further, when the columnar inclined layer is applied as an insulating layer, a TFT element having a large On current and a large field effect mobility can be realized. This is presumably because a channel layer / insulating layer interface in which carriers are not easily trapped is realized by applying an insulating layer having the structure of this embodiment to the gate insulating layer.

  A display device can be formed by connecting a drain which is an output terminal of the thin film transistor to an electrode of a display element such as an organic or inorganic electroluminescence (EL) element or a liquid crystal element. Hereinafter, an example of a specific display device configuration will be described using a cross-sectional view of the display device.

  For example, as illustrated in FIG. 9, a TFT including the amorphous oxide semiconductor film 112, the source electrode 113, the drain electrode 114, the gate insulating layer 115, and the gate electrode 116 is formed on the base 111. . An electrode 118 is connected to the drain electrode 114 through an interlayer insulating film 117, the electrode 118 is in contact with the light emitting layer 119, and the light emitting layer 119 is in contact with the electrode 120. With this configuration, the current injected into the light-emitting layer 119 can be controlled by the value of current flowing from the source electrode 113 to the drain electrode 114 through the channel formed in the amorphous oxide semiconductor film 112. Therefore, this can be controlled by the voltage of the gate 116 of the TFT. Here, the electrode 118, the light emitting layer 119, and the electrode 120 constitute an inorganic or organic electroluminescence element.

  Alternatively, as shown in FIG. 10, the drain electrode 114 is extended to serve as the electrode 118, and an electrode for applying a voltage to the liquid crystal cell or the electrophoretic particle cell 123 sandwiched between the high resistance films 121 and 122. 118 can be adopted. The liquid crystal cell, the electrophoretic particle cell 123, the high resistance layers 121 and 122, the electrode 118, and the electrode 120 constitute a display element. The voltage applied to these display elements can be controlled by the value of current flowing from the source electrode 113 to the drain electrode 114 through the channel formed in the amorphous oxide semiconductor film 112. Therefore, this can be controlled by the voltage of the gate electrode 116 of the TFT. Here, if the display medium of the display element is a capsule in which a fluid and particles are sealed in an insulating film, the high resistance films 121 and 122 are unnecessary.

  In the above-described two examples, the TFT is represented by a top gate coplanar configuration, but the present invention is not necessarily limited to this configuration. For example, if the connection between the drain electrode, which is the output terminal of the TFT, and the display element are topologically identical, other configurations such as a staggered type are possible.

  In the two examples described above, an example in which a pair of electrodes for driving the display element is provided in parallel with the base body is illustrated, but the present embodiment is not necessarily limited to this configuration. For example, as long as the connection between the drain electrode, which is the output terminal of the TFT, and the display element are topologically the same, either electrode or both electrodes may be provided perpendicular to the substrate.

  Furthermore, in the above two examples, only one TFT connected to the display element is illustrated, but the present invention is not necessarily limited to this configuration. For example, the TFT shown in the figure may be further connected to another TFT according to the present invention, and the TFT in the figure may be the final stage of the circuit using these TFTs.

  Here, when a pair of electrodes for driving the display element is provided in parallel with the substrate, if the display element is a reflective display element such as an EL element or a reflective liquid crystal element, any one of the electrodes has an emission wavelength or a reflection wavelength. It must be transparent to the wavelength of light. Alternatively, in the case of a transmissive display element such as a transmissive liquid crystal element, both electrodes need to be transparent to transmitted light.

  Furthermore, in the TFT of this embodiment, it is possible to make all the constituents transparent, thereby forming a transparent display element. Further, such a display element can be provided on a low heat-resistant substrate such as a lightweight, flexible and transparent resin plastic substrate.

  Next, a display device in which pixels including an EL element (here, an organic EL element) and a thin film transistor are two-dimensionally arranged will be described with reference to FIGS.

  In FIG. 11, reference numeral 181 denotes a transistor that drives the organic EL layer 184, and reference numeral 182 denotes a transistor that selects a pixel. The capacitor 183 is for holding a selected state, stores electric charge between the common electrode line 187 and the source portion of the transistor 182, and holds a signal of the gate of the transistor 181. Pixel selection is determined by the scanning electrode line 185 and the signal electrode line 186.

  More specifically, an image signal is applied as a pulse signal from a driver circuit (not shown) to the gate electrode through the scanning electrode 185. At the same time, a pixel is selected by applying another pulse signal from another driver circuit (not shown) to the transistor 182 through the signal electrode 186. At that time, the transistor 182 is turned on, and charge is accumulated in the capacitor 183 between the signal electrode line 186 and the source of the transistor 182. As a result, the gate voltage of the transistor 181 is maintained at a desired voltage, and the transistor 181 is turned on. This state is maintained until the next signal is received. While the transistor 181 is ON, voltage and current are continuously supplied to the organic EL layer 184 and light emission is maintained.

  In the example of FIG. 11, the configuration includes two transistors and one capacitor per pixel, but more transistors and the like may be incorporated in order to improve performance. Essentially, an effective EL element can be obtained by using an In—Ga—Zn—O TFT which is a transparent TFT and can be formed at a low temperature according to the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  This example is an example in which the bottom gate TFT element shown in FIG.

Further, a channel layer made of an In—Ga—Zn—O-based amorphous oxide and a gate insulating layer made of a polycrystalline Y ₂ O ₃ film are provided.

  First, the gate electrode 11 was formed by patterning on the glass substrate 10 (1737 manufactured by Corning) by the photolithography method and the lift-off method. The channel length is 50 μm and the channel width is 200 μm. The electrode material was Au and the thickness was 40 nm.

Next, a Y ₂ O ₃ film having a thickness of 150 nm was formed by patterning as the gate insulating layer 12 by photolithography and lift-off.

In this example, a Y ₂ O ₃ polycrystalline film was formed by high-frequency sputtering in a mixed atmosphere of argon gas and oxygen gas.

As a target (material source), a 2-inch sized sintered body having a Y ₂ O ₃ composition was used, and the input RF power was 150 W. The atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow rate ratio was Ar: O ₂ = 100: 5. The substrate temperature during film formation is 25 ° C. In this embodiment, the Y ₂ O ₃ film is formed by tilting the substrate 60 degrees from the parallel position with respect to the target as the vapor deposition source. Thereby, in the gate insulating layer, a structure in which the columnar structure made of crystal grains is inclined with respect to the layer thickness direction is formed. When the TEM observation of the insulating layer was actually performed, it was confirmed that the columnar structure made of crystal grains was inclined by about 30 degrees with respect to the layer thickness direction.

  Next, an amorphous oxide film was formed as a channel layer 13 on the gate insulating layer. In this example, an In—Zn—Ga—O-based amorphous oxide film was formed by high-frequency sputtering in a mixed atmosphere of argon gas and oxygen gas.

In this example, a sintered body having a 2 inch size In ₂ O ₃ , ZnO, and Ga ₂ O ₃ composition is used as the target. The atmosphere during the film formation was a total pressure of 0.4 Pa, and the gas flow rate ratio was Ar: O ₂ = 100: 1. The substrate temperature is 25 ° C.

  With respect to the obtained film, grazing incidence X-ray diffraction (thin film method, incident angle 0.5 degree) was performed on the film surface, but no clear diffraction peak was detected, and the produced In—Zn—Ga—O-based film was amorphous. It was confirmed to be a membrane.

  Furthermore, as a result of spectroscopic ellipsometry measurement and pattern analysis, it was found that the mean square roughness (Rrms) of the thin film was about 0.5 nm and the layer thickness was about 50 nm. As a result of X-ray fluorescence (XRF) analysis, the metal composition ratio of the thin film was In: Ga: Zn = 54: 10: 36.

  Next, the drain electrode 15 and the source electrode 14 were formed by patterning using a photolithography method and a lift-off method. The electrode material is Au and the thickness is 40 nm.

(Comparative Example 1)
Except for the gate insulating layer, the structure is the same as in the above embodiment. The gate insulating layer is formed by sputtering a Y ₂ O ₃ film and has a thickness of 150 nm. At this time, a Y ₂ O ₃ film is formed on the target as a deposition source in a parallel position with the substrate. As a result of TEM observation of the insulating film, it was confirmed that a columnar structure made of crystal grains was grown in parallel to the layer thickness direction.
(Characteristic evaluation of TFT elements)
FIG. 6 shows an example of current-voltage characteristics of the TFT element measured at room temperature. 6A shows the Id-Vd characteristic, and FIG. 6B shows the Id-Vg characteristic. As shown in FIG. 6A, when a constant gate voltage Vg is applied and the dependence of the source-drain current accompanying the change in Vd on the drain voltage Vd dependency of Id is measured, saturation (pinch-off) occurs at about Vd = 6 V. ) Showed the behavior of a typical semiconductor transistor. When the gain characteristics were examined, the threshold value of the gate voltage VG when Vd = 4 V was applied was about −0.5 V. Further, the ON current was larger than that in Comparative Example 1, and when Vg = 10 V, a current of about Id = 5.0 × 10 −4 A flowed. Further, when the field effect mobility was calculated from the output characteristics, a field effect mobility of about 14 cm ² (Vs) ⁻¹ was obtained in the saturation region, and a value about 15% higher than that of Comparative Example 1 was obtained. Furthermore, the gate leakage current was about an order of magnitude lower than that of Comparative Example 1, and the on / off ratio of the transistor was a high value exceeding 10 ⁸ .

Further, the characteristics of the TFT of this example are characterized in that the hysteresis is smaller than that of the TFT of Comparative Example 1. In FIG. 7, Id-Vg of the present example and the comparative example are illustrated and compared. 7A shows an example of the TFT characteristics of Comparative Example 1, and FIG. 7B shows an example of the TFT characteristics of this example. Thus, by applying the Y ₂ O ₃ columnar inclined film to the gate insulating layer, the hysteresis of the TFT can be reduced.

  This example is an example in which the bottom gate type TFT element shown in FIG. 8 was produced.

In addition, a channel layer made of an In—Ga—Zn—O-based amorphous oxide, a gate insulating layer made of Y ₂ O _3, and an intermediate layer made of amorphous SiO formed at the interface between them.

  First, the gate electrode 11 was formed by patterning on the glass substrate 10 (1737 manufactured by Corning) by the photolithography method and the lift-off method. The channel length is 50 μm and the channel width is 200 μm. The electrode material was Au and the thickness was 40 nm.

Next, a Y ₂ O ₃ polycrystalline film used as the insulating layer 12 was deposited by a high-frequency sputtering method using a mixed gas of argon and oxygen as a target with a sintered body having a Y ₂ O ₃ composition as a target. The substrate temperature was 25 ° C. In this embodiment, the Y ₂ O ₃ film is formed by tilting the substrate 60 degrees from the parallel position with respect to the target as the vapor deposition source. Thereby, in the gate insulating layer, a structure in which the columnar structure made of crystal grains is inclined with respect to the layer thickness direction is formed. When the TEM observation of the insulating layer was actually performed, it was confirmed that the columnar structure made of crystal grains was inclined by 30 degrees with respect to the layer thickness direction.

  Thereafter, an amorphous SiN film having a thickness of 3 nm was deposited as the intermediate layer 16. In this example, the amorphous SiN film was deposited by the plasma CVD method.

  With respect to the obtained film, grazing incidence X-ray diffraction (thin film method, incident angle 0.5 degree) was performed on the film surface. As a result, a clear diffraction peak was not detected, and it was confirmed that the produced SiN film was an amorphous film. It was.

  Next, an In—Zn—Ga—O-based amorphous oxide film used as the channel layer 13 was deposited by a high-frequency sputtering method using a mixed gas of argon and oxygen as an atmosphere. The substrate temperature was 25 ° C. As a result of X-ray fluorescence (XRF) analysis, it was confirmed that the metal composition ratio of the thin film was In: Ga: Zn = 54: 10: 36.

  With respect to the obtained film, grazing incidence X-ray diffraction (thin film method, incident angle 0.5 degree) was performed on the film surface, but no clear diffraction peak was detected, and the produced In—Zn—Ga—O-based film was amorphous. It was confirmed to be a membrane.

  Next, the drain electrode 15 and the source electrode 14 were formed by patterning using a photolithography method and a lift-off method. The electrode material is Au and the thickness is 40 nm.

(Characteristic evaluation of TFT elements)
The thin film transistor of this example showed the behavior of a typical semiconductor transistor that saturates (pinch off) at about Vd = 6 V. The on / off ratio of the transistor is over 10 ⁸ and the field effect mobility is about 12 cm ² (Vs) ⁻¹ .

  Further, the TFT of this embodiment has a feature that both hysteresis and gate leakage are small. In particular, the hysteresis is smaller than that of the first embodiment, and the hysteresis width is about 15% lower.

  Thus, by providing the intermediate layer made of amorphous SiN between the gate insulating layer and the channel layer, it is possible to reduce TFT hysteresis and gate leakage while maintaining high field-effect mobility.

  In this example, a top gate type TFT device shown in FIG. 1A is formed on a plastic substrate.

In addition, a channel layer made of an In—Ga—Zn—O-based amorphous oxide and a gate insulating layer made of Y ₂ O ₃ are provided.
The production method and configuration are the same as in Example 1. However, a polyethylene terephthalate (PET) film is used as the substrate.

(Characteristic evaluation of TFT elements)
The TFT formed on the PET film was measured at room temperature. The on / off ratio of the transistor is more than 10 ⁵ . Further, when the field effect mobility was calculated, the field effect mobility was about 6 cm ² (Vs) ⁻¹ . Moreover, it has a good hysteresis characteristic equivalent to that of the first embodiment.

Next, the device prepared on the PET film was bent with a curvature radius of 30 mm, and the same transistor characteristics were measured, but no significant change was observed in the transistor characteristics, and the breakdown strength of the Y ₂ O ₃ columnar gradient film was It was confirmed that it was high enough.

This example is an example in which the bottom gate TFT element shown in FIG.
The production method and configuration are the same as in Example 1. However, a SiO ₂ film is used as the gate insulating layer 12 and a polycrystalline ZnO film is used as the channel layer 13.

The thickness of the SiO ₂ film used for the gate insulating layer was 100 nm, and was deposited on the gate electrode by a high frequency sputtering method using a sintered body having a SiO ₂ composition as a target and a mixed gas of argon and oxygen. . The substrate temperature was 25 ° C. In this embodiment, the SiO ₂ film is formed by tilting the substrate by 60 degrees from the parallel position with respect to the target as the vapor deposition source. As a result, in the gate insulating layer, a structure in which the columnar structure is inclined with respect to the layer thickness direction is formed. When the TEM observation of the insulating film was actually performed, it was confirmed that the columnar structure was inclined by about 25 degrees with respect to the layer thickness direction.

  The ZnO film used for the channel layer had a thickness of 50 nm, and was deposited on the gate insulating layer by a high frequency sputtering method using a sintered body having a ZnO composition as a target and a mixed gas of argon and oxygen. The substrate temperature was 25 ° C.

(Comparative Example 2)
Except for the gate insulating layer, the structure is the same as in the above embodiment. As the gate insulating layer, a SiO ₂ film is formed by sputtering, and the thickness is 100 nm. At this time, a SiO ₂ film is formed on the target as a vapor deposition source in a parallel position with the substrate. As a result of TEM observation of the insulating film, it was confirmed that the columnar structure was grown in parallel to the layer thickness direction.

(Characteristic evaluation of TFT elements)
The thin film transistor of this example showed the behavior of a typical semiconductor transistor that saturates (pinch off) at about Vd = 6 V. When the field effect mobility was calculated from the output characteristics, a field effect mobility of about 60 cm ² (Vs) ⁻¹ was obtained in the saturation region, and a value about 7% higher than that of Comparative Example 2 was obtained. Furthermore, the gate leakage current was about one order of magnitude lower than that of Comparative Example 2, and the on / off ratio of the transistor was a high value exceeding 10 ⁶ .
Further, the characteristics of the TFT of this example are characterized in that the hysteresis is smaller than that of the TFT of Comparative Example 2. Thus, by applying the SiO ₂ columnar inclined film to the gate insulating layer, the hysteresis of the TFT can be reduced.

This example is an example in which the bottom gate TFT element shown in FIG.
The production method and configuration are the same as in Example 1. However, a SiO ₂ film is used as the gate insulating layer 12 and amorphous Si is used as the channel layer 13.

The thickness of the SiO ₂ film used for the gate insulating layer was 100 nm, and was deposited on the gate electrode by a high frequency sputtering method using a sintered body having a SiO ₂ composition as a target and a mixed gas of argon and oxygen. . The substrate temperature was 25 ° C. In this embodiment, the SiO ₂ film is formed by tilting the substrate by 60 degrees from the parallel position with respect to the target as the vapor deposition source. As a result, in the gate insulating layer, a structure in which the columnar structure is inclined with respect to the layer thickness direction is formed. When the TEM observation of the insulating film was actually performed, it was confirmed that the columnar structure was inclined by about 30 degrees with respect to the layer thickness direction.

  The amorphous Si film used for the channel layer had a thickness of 50 nm, and was deposited by a high frequency sputtering method using a Si target and an atmosphere of a mixed gas of argon and oxygen. The substrate temperature was 25 ° C.

(Comparative Example 3)
Except for the gate insulating layer, the structure is the same as in the above embodiment. As the gate insulating layer, a SiO ₂ film is formed by sputtering, and the thickness is 100 nm. At this time, a SiO ₂ film is formed on the target as a vapor deposition source in a parallel position with the substrate. When the TEM observation of the insulating layer was performed, it was confirmed that the columnar structure had grown in parallel to the layer thickness direction.

(Characteristic evaluation of TFT elements)
The thin film transistor of this example showed the behavior of a typical semiconductor transistor that saturates (pinch off) at about Vd = 6 V. When the field effect mobility was calculated from the output characteristics, a field effect mobility of about 0.5 cm ² (Vs) ⁻¹ was obtained in the saturation region. Further, the gate leakage current was about one order of magnitude lower than that of Comparative Example 3, and the on / off ratio of the transistor was a high value exceeding 10 ⁶ .
Further, the characteristics of the TFT of this example are characterized in that the hysteresis is smaller than that of the TFT of Comparative Example 3. Thus, by applying the SiO ₂ columnar inclined film to the gate insulating layer, the hysteresis of the TFT can be reduced.

  In this embodiment, a display device using the TFT of FIG. 10 will be described. The manufacturing process of the TFT is in accordance with Example 1. In the above TFT, extend the short side of the ITO film island forming the drain electrode to 100 μm, leave the extended 90 μm portion, and secure the wiring to the source and gate electrodes, and then cover the TFT with an insulating layer To do. A polyimide film is applied thereon and a rubbing process is performed. On the other hand, an ITO film and a polyimide film are similarly formed on a plastic substrate, and a rubbing process is prepared. The substrate on which the TFT is formed is opposed to the substrate with a 5 μm gap, and a nematic liquid crystal is injected therein. . Further, a pair of polarizing plates is provided on both sides of the structure. Here, when a voltage is applied to the source electrode of the TFT and the applied voltage of the gate electrode is changed, the light transmittance changes only in the 30 μm × 90 μm region that is a part of the island of the ITO film extended from the drain electrode. To do. The transmittance can be continuously changed by the source-drain voltage under the gate voltage at which the TFT is turned on. In this way, a display device having a liquid crystal cell as a display element corresponding to FIG. 7 is produced.

  In this embodiment, a white plastic substrate is used as a substrate for forming a TFT, each electrode of the TFT is replaced with gold, and the polyimide film and the polarizing plate are discarded. And it is set as the structure filled with the capsule which coat | covered the particle | grains and fluid with the insulating film in the space | gap of a white and transparent plastic substrate. In the case of a display device having this configuration, the voltage between the drain electrode extended by the TFT and the ITO film on the upper part is controlled, and thus the particles in the capsule move up and down. Accordingly, display can be performed by controlling the reflectance of the extended drain electrode region viewed from the transparent substrate side.

  In this embodiment, a plurality of TFTs are formed adjacent to each other to form a current control circuit having a normal 4-transistor 1-capacitor configuration, for example, and one of the final stage transistors is set as the TFT in FIG. It can also be driven. For example, a TFT using the above ITO film as a drain electrode is used. Then, an organic electroluminescence element composed of a charge injection layer and a light emitting layer is formed in a 30 μm × 90 μm region which is a part of the island of the ITO film extended from the drain electrode. Thus, a display device using an EL element can be formed.

  The display element and TFT of Example 6 are arranged two-dimensionally. For example, the pixel occupying an area of about 30 μm × 115 μm including the display element such as the liquid crystal cell and EL element of Example 6 and the TFT is 7425 × at a pitch of 40 μm in the short side direction and 120 μm in the long side direction. 1790 square array. Then, there are 1790 gate wirings penetrating the gate electrodes of 7425 TFTs in the long side direction, and signals that the source electrodes of the 1790 TFTs protrude 5 μm from the island of the amorphous oxide semiconductor film in the short side direction. Provide 7425 wires. Then, each is connected to a gate driver circuit and a source driver circuit. Furthermore, in the case of a liquid crystal display element, an A4 size active matrix color image display device can be constructed at approximately 211 ppi if a color filter with the same size as the liquid crystal display element is aligned and RGB is repeated on the long side. can do.

  Also in the EL element, the gate electrode of the first TFT of the two TFTs included in one EL element is wired to the gate line, the source electrode of the second TFT is wired to the signal line, and the emission wavelength of the EL element is further increased. Is repeated in RGB in the long side direction. In this way, a light emitting color image display device having the same resolution can be configured.

  Here, the driver circuit for driving the active matrix may be configured by using the same TFT of the present invention as the pixel TFT, or an existing IC chip may be used.

  The thin film transistor of the present invention can be formed on a flexible material such as a PET film or a light transmissive substrate. When formed on a flexible material, switching in a curved state is possible, and when formed on a light-transmitting substrate, it is transparent to visible and infrared light having a wavelength of 400 nm or more. it can. Utilizing these properties, the thin film transistor of the present invention can be applied as a switching element of an LCD or an organic EL display, and can be widely applied to a flexible display, a see-through display, an IC card, an ID tag, and the like.

It is sectional drawing which shows the structural example of the thin-film transistor of this invention. It is a figure which shows the schematic diagram of the columnar structure | tissue in a vapor deposition source, a board | substrate, and an insulating film in the film forming apparatus used by this invention. 1A and 1B are schematic views of a gate insulating layer and a semiconductor layer of a thin film transistor of the present invention, in which FIG. 1A is a perspective view of a cross section in a direction parallel to the substrate of the gate insulating layer, and FIG. It is a perspective view which shows the interface of a semiconductor layer. FIG. 2 is a schematic diagram of a gate insulating layer and a semiconductor layer produced in a parallel position with respect to a vapor deposition source, (a) is a perspective view of a cross section in a direction parallel to the substrate of the gate insulating layer; (B) is a perspective view showing an interface between a gate insulating layer and a semiconductor layer. It is a graph which shows the relationship between the electron carrier density | concentration of an In-Ga-Zn-O type amorphous oxide film, and the oxygen partial pressure during film-forming. It is a graph which shows the TFT characteristic of the thin-film transistor of this invention. It is a graph which shows the hysteresis characteristic of the thin-film transistor of this invention. It is sectional drawing which shows the structural example of the thin-film transistor of this invention. It is sectional drawing of an example of the display apparatus concerning this invention. It is sectional drawing of the other example of the display apparatus concerning this invention. It is a figure which shows the structure of the display apparatus which has arrange | positioned the pixel containing an organic EL element and a thin-film transistor two-dimensionally.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11 Gate electrode 12 Gate insulating layer 13 Channel layer 14 Source electrode 15 Drain electrode 16 Intermediate layer

Claims (11)

It has a structure in which a semiconductor layer and a gate insulating layer are stacked,
The semiconductor layer is an oxide semiconductor containing at least one of In, Sn, and Zn,
The gate insulating layer has a columnar structure, and the columnar structure is inclined with respect to a layer thickness direction of the gate insulating layer.   The thin film transistor according to claim 1, wherein the gate insulating layer includes at least one of Y2O3, Al2O3, and SiO2.   3. The thin film transistor according to claim 1, wherein an inclination angle of the columnar structure with respect to a layer thickness direction of the gate insulating layer is at least 5 degrees.   The thin film transistor according to claim 1, wherein the semiconductor layer is an oxide semiconductor containing In, Ga, and Zn.   The thin film transistor according to claim 1, wherein the semiconductor layer is ZnO. The thin film transistor according to any one of claims 1 to 5, characterized in that an intermediate layer between the semiconductor layer and the gate insulating layer. The thin film transistor according to claim 6 , wherein the intermediate layer includes at least one of an amorphous Si oxide film, an amorphous Si nitride film, and an amorphous Si oxynitride film. The electrodes of the display elements, the display source or drain electrode of the thin film transistor according to any one of claims 1 to 7 is connected to the device. The display device according to claim 8 , wherein the display element is an electroluminescence element. The display device according to claim 9 , wherein the display element is a liquid crystal cell. Display device according to any one of claims 8 to the display element and the thin film transistor on the substrate are two-dimensionally a plurality placed 10.