CN102789808B - The memory device and a method for driving the memory device - Google Patents

The memory device and a method for driving the memory device Download PDF

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CN102789808B
CN102789808B CN201210149184.9A CN201210149184A CN102789808B CN 102789808 B CN102789808 B CN 102789808B CN 201210149184 A CN201210149184 A CN 201210149184A CN 102789808 B CN102789808 B CN 102789808B
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transistor
potential
signal
gate
electrically connected
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CN102789808A (en
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远藤正己
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株式会社半导体能源研究所
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26Accessing multiple arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selections, chip selection, array selection
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206Location of test circuitry on chip or wafer

Abstract

根据本发明的存储器装置能够利用单个电位来工作,据此能够免去电压变换器的使用,从而促成功耗的降低。 The memory device according to the invention can be to work with a single potential, whereby the voltage converter can be removed from use, thus contributing to reduction in power consumption. 此类操作能够利用连接到晶体管的栅极电容器的电容耦合进行数据写入来实现。 Such operations can be implemented using the capacitive coupling of the capacitor is connected to the gate of transistor data writing. 即,通过将由延迟电路提供的信号输入到电容器来引起电容耦合,该延迟电路配置成将具有等于电源电位的写信号延迟。 That is, the signal provided by the delay circuit input via a capacitor to the capacitive coupling caused by the delay circuit is configured to supply a signal having a potential equal to the write delay. 通过电容耦合增大栅极的电位使得晶体管能够与从电源施加到栅极的电源电位关联地被导通。 Increasing the gate potential by capacitive coupling of the transistor to be turned on so that the power supply potential applied from the power associated to the gate. 经由晶体管将等于电源电位或接地电位的信号输入到结点来写入数据。 Will be equal to the power supply potential via a transistor or a ground potential signal is input to the node to write the data.

Description

存储器装置和用于驱动存储器装置的方法 The memory device and a method for driving the memory device

技术领域 FIELD

[0001] 本发明涉及存储器装置和用于驱动存储器装置的方法。 [0001] The present invention relates to a method for driving a memory device and a memory device.

背景技术 Background technique

[0002] 有许多种类的包含半导体的存储器装置。 [0002] There are many types of memory devices comprises a semiconductor. 例如,可以给出动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、电可擦除和可编程只读存储器(EEPROM)、闪速存储器(闪存)等。 For example, given a dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM), flash memory (flash memory).

[0003] 易失性存储器装置的典型示例是DRAMt3DRAM的存储器单元包括写和读晶体管和电容器,并且通过将电荷保持在存储器单元中设置的电容器中来存储数据(参见非专利文献1)。 [0003] A typical example of a volatile memory device includes a memory cell is DRAMt3DRAM write and read transistors and capacitors, and by storing data in the memory unit charge holding capacitor is provided (see Non-Patent Document 1). 但是,因为即使在开关晶体管处于截止状态时泄漏电流仍在开关晶体管中流动,所以需要按数十毫秒的间隔时间执行重写(刷新)操作来进行数据保持,这导致功耗的增加。 However, since the leakage current even when the switching transistor is in the off state of the switching transistor is still flowing, it is necessary to perform rewriting (refreshing) the data holding operation is performed at the intervals of tens of milliseconds, which results in an increase in power consumption.

[0004] 非专利文献1中描述的DRAM采用一种减少一个存储器单元占用的区域并且还保持晶体管的有效沟道长度以不至于因在存储器单元中形成三维晶体管而导致短沟道效应。 The DRAM 1 is described in [0004] Non-Patent Document employ a method of reducing the area occupied by one memory cell and also to maintain an effective channel length of the transistor to be formed not because of the three-dimensional transistor in the memory cell caused by the short channel effect. 例如,公开一种结构,其中在形成晶体管的沟道部分的区域中形成U形垂直长槽,沿着槽中的壁部表面形成栅绝缘层,以及形成栅电极以填充该槽。 For example, there is disclosed a structure in which a channel region is formed in the portion of the U-shaped transistor is formed vertically elongated slot, forming a gate insulating layer along the wall surface of the groove portion, and a gate electrode formed to fill the groove.

[0005] 但是,常规DRAM仍需要按几十毫秒的间隔来刷新以便保持数据,这导致功耗的增加。 [0005] However, the conventional DRAM still Yaoan intervals of tens of milliseconds to refresh to maintain data, which results in increase of power consumption. 此外,其中的晶体管频繁地导通和截止;因此,晶体管的劣化也是问题。 Further, where the transistor is turned on and off frequently; therefore, deterioration of the transistor is also a problem.

[0006] 非易失性存储器装置的典型示例是闪存。 [0006] A typical example of a nonvolatile memory device is a flash memory. 闪存包括栅电极与晶体管中的沟道形成区域之间的浮动栅极,并通过将电荷保持在浮动栅极中来存储数据。 Flash memory transistor includes a gate electrode and a channel region formed between the floating gate and the charge held by the floating gate to store data. 因此,闪存是有优势的,因为数据保持期间长且无需易失性存储器装置中所需的刷新操作(参见专利文献1)。 Thus, flash memory is advantageous, since the required data holding for a long period and without a volatile memory device refresh operation (see Patent Document 1).

[0007] 但是,存储器装置中包括的栅绝缘层因写入时的隧道电流(tunneling current) 而劣化,以致存储器装置在许多次写操作之后失效。 [0007] However, the memory device comprising a gate insulating layer due to the tunnel current at the time of writing (tunneling current) is deteriorated, so that the failure of the memory device after a number of write operations. 再者,向浮动栅极注入电荷以及从其中移出电荷需要相对较高的电压和相对较长的时间;因此,提高写和擦除操作的速度是不容易的。 Further, charge injection to the floating gate and the charge is removed from it requires a relatively high voltage and a relatively long time; therefore, increase the speed of write and erase operations are not easy.

[0008] [参考文献] _9][专利文献] [0008] [References] [9] [Patent Document]

[0010] [专利文献1]日本专利申请公开NO.S57-105889。 [0010] [Patent Document 1] Japanese Patent Application Publication NO.S57-105889.

[0011] [非专利文献] [0011] [Patent Document]

[0012] [非专利文献1]Kinam Kim, "Technology for sub_50nm DRAM and NAND Flash Manufacturing", International Electron Devices Meeting, 2005. IEDM Technical Digest, Dec. 2005, pp. 333-336〇 [0012] [Patent Document 1] Kinam Kim, "Technology for sub_50nm DRAM and NAND Flash Manufacturing", International Electron Devices Meeting, 2005. IEDM Technical Digest, Dec. 2005, pp. 333-336〇

发明内容 SUMMARY

[0013] 使用半导体的许多存储器装置通过采用其中将多个电源电位用于驱动的配置来提高它们的数据写入速度。 [0013] Many semiconductor memory device wherein by using the power supply potential for driving a plurality of configuration data to improve their writing speed.

[0014] 例如,在通过用作写入数据的开关的晶体管将电荷存储在电容器中的许多装置中,晶体管中的源极和栅极的电位之差需要足够大以便高速地将数据写入存储器装置。 [0014] For example, in writing data through transistor serving as a switch means in a number of capacitors, the potential difference between the transistor source and gate of the need to store large enough to charge the data into the memory at high speed device. 相应地,用于驱动晶体管的栅极的电源电位和将数据写入电容器的信号的电源电位是必不可少的,以及此外,用于驱动栅极的电源电位需要高于将数据写入电容器的信号的电源电位。 Accordingly, the power supply potential for driving the gate of the transistor and the data write power supply potential of the capacitor is essential, and in addition, the power supply potential for driving the gate of the data written needs to be above the capacitor power supply potential signal.

[0015] 多个电源电位是使用电压变换器(也称为变换器)生成的。 [0015] The use of a plurality of power supply potential is a voltage converter (also referred to as a converter) is generated. 电压变换器的变换效率低于1;相应地,随着存储器装置中使用的变换器的数量增加,存储器中的电功率的使用效率下降。 Conversion efficiency is lower than the voltage converter 1; accordingly, increasing the number of memory devices for use with the inverter, the memory efficiency of electric power decreases.

[0016] 鉴于前文的技术背景,完成本发明。 [0016] In view of the foregoing technical background, the present invention is completed. 本发明的实施例的目的在于提供一种不牺牲写入速度的情况下降低功耗的存储器装置。 Object of embodiments of the present invention to provide a memory device to reduce power consumption without sacrificing the case where one kind writing speed. 本发明的实施例的另一个目的在于提供一种用于驱动存储器装置的方法。 Another object of embodiments of the present invention is to provide a method for driving a memory device.

[0017] 为了实现目的,使用自举电路(bootstrap circuit)而不使用电压变换器,从而能够形成仅通过等于用于数据写入的信号的电位的单个电位就能够操作的存储器装置。 [0017] For the purpose of the memory device, the potential use of a bootstrap circuit (bootstrap circuit) without using a voltage converter can be formed only by a signal equal to a data writing potential can be a single operation. 具体地来说,将电源电位从电源输入到晶体管的栅极和第一电容器的一个电极所连接的第一结点,以便将电荷累积在第一结点中。 Specifically, the gate electrode of a first node from the power supply potential is inputted to the first transistor and the capacitor connected to the charge accumulated in the first node. 然后,将等于电源电位的电位施加于第一电容器的另一个电极,以使晶体管的栅极的电位由于电容耦合而变为高于电源电位。 Then, the potential equal to the power supply potential is applied to the other electrode of the first capacitor, so that the potential of the gate of the transistor due to the capacitive coupling becomes higher than the power source potential. 晶体管的栅极的电位增大使得晶体管能够被导通,并且将具有等于电源电位或接地电位的输入数据信号经晶体管输入到结点,由此完成数据写入。 The potential of the gate of the transistor can be increased so that the transistor is turned on, and the power supply potential equal to the ground potential or the input data signal is input to the node via the transistor, thereby completing the data writing. 这种数据写入机制能够使用单个电位操作存储器装置,晶体管的栅极的电位高于电源电位能够减少电压变换器的数量且提高写入速度,这对减少存储器装置的功耗给予贡献。 This mechanism can be a single data write operation of the memory device of the potential, the potential of the gate of the transistor is higher than the power source potential capable of reducing the number of voltage converters and increase writing speed, which gives the contribution to the reduction of power consumption of the memory device.

[0018] 本发明的实施例是一种存储器装置,其包括控制器,该控制器配置成根据写信号从电源电位对第一结点的输入操作、电位在第一结点处的保持操作和根据写信号的电位在第一结点处的接地操作中选择操作;第一电容器,其包括连接到第一结点的一个电极;延迟电路,其配置成将写信号延迟并将延迟的写信号输出到第一电容器的另一个电极;第一晶体管(η沟道常截止晶体管),其包括连接到第一结点的栅电极、将输入数据信号输入到的第一电极以及连接到存储输入数据信号的第二结点的第二电极;以及读取电路,其连接到第二结点。 [0018] Example embodiments of the present invention is a memory device, comprising a controller configured according to the write signal input from the first power supply potential node operation, holding operation, and the potential at the first node the potential of the write signal selecting operation at the ground operation at the first node; a first capacitor includes one electrode connected to the first node; a delay circuit configured to delay the write signal and the delayed write signal output to the other electrode of the first capacitor; a first transistor ([eta] channel normally-off transistor), which includes a gate electrode connected to a first node, the input data signal is input to a first electrode and a data input connected to the memory a second electrode of the second signal node; and a read circuit connected to the second node. 在该存储器装置中,第二结点连接到第二电容器的电极之一和读取电路中包含的第二晶体管的栅电极。 In this memory device, a second node connected to one electrode of the second capacitor and the gate electrode of the second reading transistor included in a circuit. 第二电容器的另一个电极接地。 The other electrode of the second capacitor is grounded. 该读取电路根据读信号输出与第二结点处保持的电位对应的信号。 The read circuit according to the potential corresponding to the read signal and the output remains at the second node signal.

[0019] 本发明的实施例的存储器装置使用等于作为数据写入的信号的电位的电位,从而实现高速写入操作。 [0019] The memory device according to embodiments of the present invention is used as a potential equal to the potential of the signal data is written, in order to achieve high-speed writing operation. 相应地,能够减少电压变换器的数量,并且能够降低存储器装置的功耗。 Accordingly, it is possible to reduce the number of voltage converters, and power consumption of the memory device can be reduced.

[0020] 根据本发明的存储器装置中使用的控制器优选地包括电源与第一结点之间的开关,该开关根据写信号向第一结点输入电源电位或接地电位;以及二极管,该二极管连接在电源与开关之间以使从电源到第一结点的方向是二极管的正向。 [0020] The controller is preferably a memory device of the present invention include a switch between the supply and the first node, according to the write signal input of the switching node to the first power supply potential or a ground potential; and a diode connected between the power switch and the power source so that a direction from the first node to the diode is forward.

[0021] 在采用控制器的上述电路配置的情况中,能够形成具有相对较简单的电路的控制器。 [0021] In the case of the circuit configuration of the controller, the controller can be formed with a relatively simple circuit. 因此,能够提供功耗降低而不使用复杂化的电路的存储器装置。 Thus, reducing the power consumption of the memory device can be provided without using complicated circuits.

[0022] 存储器装置中使用的第一晶体管的源电极和漏电极的其中之一电连接到保持数据的第二结点。 [0022] wherein one holder is electrically connected to the second data node of the source electrode and the drain electrode of the first transistor used in a memory device. 因此,第一晶体管优选地是具有小截止态电流(of f-state current)的晶体管。 Accordingly, the first transistor is preferably a transistor with small off-state current (of f-state current) is. 例如,沟道宽度的每个微米上第一晶体管的截止态电流优选地等于或低于I XKT17 A/ um〇 For example, each micron channel width of the first transistor off-state current is preferably equal to or lower than I XKT17 A / um〇

[0023] 优选地,使用在半导体层中包括氧化物半导体的晶体管作为第一晶体管。 [0023] Preferably, in the semiconductor layer comprises an oxide semiconductor transistor as the first transistor. 包括其中形成沟道的氧化物半导体层的晶体管具有少量的载流子,并且由此能够具有极其小的截止态电流。 Wherein the transistor includes an oxide semiconductor layer forming a channel having a small number of carriers, and thus can have an extremely small off-state current.

[0024] 本发明的另一个实施例是用于驱动存储器装置的方法,其包括如下的第一至第五步骤。 Another [0024] embodiment of the present invention is a method for driving a memory device, comprising the following first to fifth steps. 第一步骤是将具有等于电源电位的电位的第一写信号输入到控制器和延迟电路,从而控制器响应第一写信号将电源电位输入到第一结点,从而在第一电容器的一个电极连接的第一结点处保持与电源电位对应的电荷。 The first step is equal to the potential of the power supply potential of the first write signal is input to the controller and a delay circuit, so that the write controller responds to a first signal input to the first power supply potential node to a first electrode of the capacitor at a first node connected to the power supply potential holding charges corresponding. 第二步骤是将由延迟电路进行延迟的第一写信号输入到第一电容器的另一个电极,从而使连接到第一晶体管的栅电极的第一结点处的电位高于电源电位。 The second step is delayed by the delay circuit and the other electrode of the first write signal is input to the first capacitor, so that the potential at the first node is connected to the gate electrode of the first transistor is higher than the power source potential. 第三步骤是将输入数据信号输入到第一晶体管的第一电极,从而将与输入数据信号的电位对应的电荷写入第一晶体管的第二电极和一个第二电容器的电极连接的第二结点,其中该第二电容器的另一个电极接地。 The third step is the first electrode of the input data signal is input to the first transistor, so that the potential of an input data signal corresponding to the charge written in the second junction electrode of the first electrode of the second transistor and a second capacitor connected point, wherein the other electrode of the second capacitor is grounded. 第四步骤是将具有接地电位的第二写信号输入到控制器和延迟电路,从而将栅电极接地,并利用第一晶体管具有接地的栅电极将输入数据信号保持在第二结点处。 The fourth step is a ground potential of the second write signal is input to the controller and a delay circuit such that the gate electrode is grounded, and the gate electrode with the first transistor having a grounded input data signal is held at the second node. 第五步骤是将读信号输入到读取电路,该读取电路包括具有连接到第二结点的栅电极的第二晶体管,从而确定第二晶体管的导通态和截止态, 并由此读取第二结点处的电位。 The fifth step is to read the input signal to the reading circuit, the reading circuit comprises a second transistor having a gate electrode connected to the second node, thereby determining the on-state and off-state of the second transistor, and thus read takes on the potential at the second node.

[0025] 利用本发明,能够提供一种在不牺牲写入速度的情况下降低功耗的存储器装置。 [0025] With the present invention, it is possible to provide a memory device for reducing power consumption without sacrificing write speed. 再者,能够提供用于驱动该存储器装置的方法。 Further, it is possible to provide a method for driving the memory device.

附图说明 BRIEF DESCRIPTION

[0026] 在附图中: [0026] In the drawings:

[0027] 图1图示根据本发明的实施例的存储器装置; [0027] FIG 1 illustrates a memory device according to an embodiment of the present invention;

[0028] 图2图示根据本发明的实施例的存储器装置的一部分; A portion of the memory device [0028] FIG 2 illustrates an embodiment according to the present invention;

[0029] 图3图示根据本发明的实施例的存储器装置的一部分; A portion of the memory device [0029] FIG. 3 illustrates an embodiment of the present invention;

[0030] 图4A和图4B是根据本发明的存储器装置的时序图; [0030] FIGS 4A and 4B are a timing chart of the memory device according to the present invention;

[0031] 图5图示根据本发明的实施例的存储器装置的一部分; Portion of a memory device of an embodiment of the present invention [0031] FIG. 5 illustrates;

[0032] 图6图示根据本发明的实施例的存储器装置的一部分; Portion of a memory device of an embodiment of the present invention [0032] FIG. 6 illustrates a;

[0033] 图7A至图7E示出氧化物材料的晶体结构; [0033] FIGS. 7A to 7E shows the crystal structure of the oxide material;

[0034] 图8A至图8C示出氧化物材料的晶体结构; [0034] FIGS. 8A to 8C show a crystal structure of the oxide material;

[0035] 图9A至图9C示出氧化物材料的晶体结构; [0035] FIGS. 9A to 9C shows the crystal structure of the oxide material;

[0036] 图IOA和图IOB各图示氧化物的结构; [0036] FIGS. IOA and IOB each illustrating the structure of an oxide;

[0037] 图11示出通过计算获得的迀移率的栅极电压相关性; [0037] FIG. 11 illustrates the gate voltage obtained Gan shift rate calculated correlation;

[0038] 图12A至图12C示出通过计算获得的漏极电流和迀移率的栅极电压相关性; [0038] FIGS. 12A to 12C show the drain current and the gate voltage obtained by calculation Gan correlation shift rate;

[0039] 图13A至图13C示出通过计算获得的漏极电流和迀移率的栅极电压相关性; [0039] FIGS. 13A to 13C illustrate the drain current and the gate voltage obtained by calculation Gan correlation shift rate;

[0040] 图14A至图14C示出通过计算获得的漏极电流和迀移率的栅极电压相关性; [0040] FIGS. 14A to 14C show the drain current and the gate voltage obtained by calculation Gan correlation shift rate;

[0041] 图15A和图15B图示计算中使用的晶体管的横截面结构;以及 [0041] The cross-sectional structure of a transistor using the calculated FIGS. 15A and 15B illustrate; and

[0042] 图16A至图16D图示本发明的实施例中使用的晶体管的横截面结构。 [0042] The cross-sectional structure of the embodiment illustrated in FIGS. 16A to 16D used in the present invention is a transistor.

具体实施方式 Detailed ways

[0043] 下文中,将参考附图详细地描述本发明的实施例。 In [0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 注意本发明并不局限于下文描述,并且本领域技术人员容易地理解,在不背离本发明精神和范围的前提下可以采用多种方式修改其模式和细节。 Note that the present invention is not limited to the following description, and those skilled in the art will readily appreciate, without departing from the spirit and scope of the present invention may be modified in various ways that modes and details thereof. 因此,本发明应该不局限于下文对实施例的描述。 Accordingly, the present invention should not be limited to the description of the embodiments below. 注意,在下文描述的本发明的结构中,相同的部分或具有相似功能的部分在不同附图中以相同的参考标记表示,并且不重复其描述。 Note that the structure of the invention described below, the same portions or portions having similar functions with the same reference numerals in different drawings, and description thereof will not be repeated.

[0044] 注意,在本说明书中描述的每个附图中,在一些情况下为了清晰的目的,将每个组件的尺寸、层厚度或区域放大。 [0044] Note that, in each of the figures described in this specification, in some cases, for clarity purposes, the size of each component, the layer thickness or area enlargement. 因此,本发明的实施例不局限于这种比例。 Accordingly, embodiments of the present invention is not limited to this ratio.

[0045] 当例如使用相反极性的晶体管时或在电路操作中改变电流的方向时,“源极”和“漏极”的功能可以互换。 [0045] When, for example when using transistors of opposite polarity current in the circuit or changing the direction of operation, a "source" and "drain" are interchangeable. 因此,在本说明书中能分别使用术语“源极”和“漏极”来表示漏极和源极。 Accordingly, in the present specification can be used, respectively, the terms "source" and "drain" to indicate the source and the drain. 再者在本说明书中,在一些情况中,将晶体管的源极和漏极的其中之一称为“第一电极”,以及将源极和漏极的其中另一个称为“第二电极”。 Note that in the present specification, in some cases, one of the source and the drain of the transistor is referred to as "first electrode", and the source and the drain of another of the "second electrode" .

[0046] 注意,在本说明书等中,术语“电连接”包括经由“具有任何电功能的物体”连接组件的情况。 [0046] Note that in this specification and the like, the term "electrically connected" includes the case where via the "object having any electric function" connector assembly. 对于“具有任何电功能的物体”没有具体限定,只要能够在经由该物体连接的组件之间传送和接收电信号即可。 For the "object having any electric function" is not particularly limited, and can transmit and receive electrical signals between the components as long as the object via the connection. 除了电极和布线外,“具有任何电功能的物体”的示例包括如晶体管的开关元件、电阻器、线圈、电容器以及具有多种功能的元件。 In addition to the electrodes and the wiring example of the "object having any electric function" switching element comprises a transistor, a resistor, a coil, a capacitor and an element having multiple functions.

[0047] 注意,在本说明书等中的结点表示能够使电路中包含的元件之间进行电连接的元件(例如,布线)。 [0047] Note that in this specification and the like of the nodes represent elements capable of electrical (e.g., wiring) connected between elements included in a circuit. 因此,uA连接的结点”是指电连接到4且可以视为具有与尉目同的电位的布线。注意,即使在布线的一部分中插入能够进行电连接的一个或多个元件(例如,开关、晶体管、电容器、电感器、电阻器或二极管)时,只要它具有与4相同的电位,则该布线仍可被视为3连接的结点”。 Thus, the node uA linked "means electrically connected to the wiring 4 and may be considered to have the same potential Wei mesh. Note that, even if the inserted portion of the wiring can be electrically connected to one or more elements (e.g., when switch, a transistor, a capacitor, an inductor, a resistor or a diode), as long as it has the same potential 4, the wiring may still be considered node 3 "connected.

[0048] 注意,术语“电压”一般表示两个点处的电位之差(也称为电位差)。 [0048] Note that the term "voltage" generally indicates the potential difference between two points (also referred to as a potential difference). 但是,在一些情况中,电压和电位的值均在电路图等中使用伏特(V)表示,以致难以在它们之间进行区别。 However, in some cases, values ​​of voltage and potentials have indicated that it is difficult to distinguish between them using volts (V) in the circuit diagram and the like. 因此,在此说明书中,除非另行指定,否则一个点处的电位与参考电位之间的电位差有时称为该点处的电压。 Thus, in this specification, unless otherwise specified potential difference between the potential of the reference potential at a point, sometimes it referred to the voltage at that point.

[0049] (实施例1) [0049] (Example 1)

[0050] 在本实施例中,将描述本发明的实施例的存储器装置。 [0050] In the present embodiment, the memory device according to embodiments of the present invention will be described. 图1中图示了本实施例的存储器装置。 Figure 1 illustrates an embodiment of a memory device of the present embodiment.

[0051] 图1中的存储器装置包括控制器151、延迟电路153、读取电路155、第一电容器157、 第一晶体管159和第二电容器161。 In [0051] FIG 1 memory device includes a controller 151, a delay circuit 153, reading circuit 155, a first capacitor 157, first capacitor 161 and second transistor 159.

[0052] 控制器151的输出端、第一电容器157的第一电极和第一晶体管159的栅电极彼此电连接以形成保持电荷的第一结点(Ml)。 An output terminal [0052] controller 151, a first electrode of the first capacitor 157 and the gate electrode of the first transistor 159 is electrically connected to each other to form a first node holding charges (Ml). 此外,第一晶体管159的第二电极、第二电容器161 的电极之一和读取电路155的输入端彼此电连接以形成保持电荷的第二结点(M2)。 Further, the second electrode of the first transistor 159, one electrode of the second capacitor 161 and the input of the reading circuit 155 is electrically connected to each other to form a second node (M2) holding charges. 第二电容器161的另一个电极接地。 The other electrode of the second capacitor 161 is grounded.

[0053] 将写信号(0S_WE)输入到控制器151,并且根据写信号的电位,将电源电位(Vdd)或接地电位输入到第一结点。 [0053] The write signal (0S_WE) is input to the controller 151, and based on the potential of the write signal, the power supply potential (Vdd) or a ground potential is input to the first node. 当将电源电位输入到第一结点时,在连接到第一结点的第一电容器中累积与电源电位对应的电荷。 When the power supply voltage input to the first node, accumulated charge corresponding to the power supply potential of the first capacitor is connected to the first node. 注意,在本说明书中,从控制器151向第一结点输入电源电位到在第一结点和第一电容器中累积与电源电位对应的电荷的期间称为“预充电期间”。 Note that, in this specification, the power supply potential to the input "precharge period" is referred to during the accumulation of charge corresponding to a power supply potential at the first node and the first capacitor from the controller 151 to the first node.

[0054] 在本实施例中,当将H-电平信号作为写信号(0S_WE)输入到控制器151时,第一结点连接到电源。 [0054] In the present embodiment, when the H- level signal is input to the controller 151 as a write signal (0S_WE), a first node connected to a power source. 当将L-电平信号作为写信号(0S_WE)输入到控制器151时,第一结点接地。 When the L- level signal is input to the controller 151 as a write signal (0S_WE), a first ground node. 控制器151还具有保持累积在电连接到第一结点的第一电容器中的电荷的功能。 The controller 151 also has a function of charge on a first capacitor electrically connected to the first node remains accumulated. 存储器装置中能够使用的控制器不限于具有上述结构的控制器,并且可以具有其中在H-电平信号作为写信号输入时,第一结点接地而在输入L-电平信号时,第一结点连接到电源的结构。 The memory controller means can be used with a controller is not limited to the above structure, and may have H- wherein the level of the signal input as a write signal, a first node and ground level when the input signal L-, first node structure connected to the power supply.

[0055] 注意,此处的H-电平和L-电平信号分别是具有等于电源电位的电位的信号以及具有等于接地电位的电位的信号。 [0055] Note that, H- level L- level signal here is a signal are equal to the ground potential and a signal potential having a potential equal to the power supply potential. 通过作为H-电平信号输入具有等于电源电位的电位的信号和作为L-电平信号输入具有等于接地电位的电位的信号,能够减少存储器装置中的电压变换器的数量,从而能够降低功耗。 Signal having a potential equal to the power supply potential by the level signal is input as a signal H- and L- level signal is input as having a potential equal to the ground potential, the voltage converter can reduce the number of memory devices, power consumption can be reduced . 此处,使用表述“等于电源电位或接地电位的电位”来表示该电位不是利用改变电压的电路(如电压变换器)来改变电源电位或接地电位的电位而获得的电位。 Here, the expression "power supply potential or a ground potential equal to the potential" to indicate that the potential is not a potential change in the voltage using a circuit (e.g., voltage converter) by changing the potential of the power supply potential or a ground potential is obtained. 相应地,即便作为电源电位的电位输入因布线等降低而变成不是刚好等于电源电位的电位,该电位仍作为具有等于电源电位的电位的电位来处理。 Accordingly, even as the potential of the input power source potential wiring and the like due to a decrease rather than just becomes equal to the supply potential potential which is still treated as a potential equal to the potential of the power supply potential. 这同样适用于本实施例中描述的其他信号。 The same applies to the other signals described in the present embodiment.

[0056] 当将H-电平信号作为输入数据信号输入到存储器装置时,存储器装置保持与电源电位对应的电荷来存储数据。 [0056] When the H- level signal as an input data signal is input to the memory means, the memory means stores data holding charge corresponding to the power supply potential.

[0057] 将写信号(0S_WE)输入到延迟电路153。 [0057] The write signal (0S_WE) input to the delay circuit 153. 延迟电路153将输入的写信号延迟并将延迟的写信号输出到第一电容器157的另一个电极。 Output of the delay circuit 153 delays the inputted write signal and the delayed write signal 157 to the other electrode of the first capacitor. 延迟电路153将写信号延迟的时间至少等于或长于根据输入到控制器151的写信号将电源电位输入到第一结点以及在第一结点中累积与电源电位对应的电荷所需的时间。 The delay circuit 153 a write signal delay time at least equal to or longer than a write signal according to an input to the controller 151 of the power supply potential is input to the first node and the charge accumulation time required for the corresponding power supply potential of the first node.

[0058] 图2图示控制器151和延迟电路153的具体电路配置的示例。 [0058] FIG 2 illustrates an example of controller 151 and a specific circuit configuration of the delay circuit 153.

[0059] 图2所示的控制器151包括二极管201、倒相器(inverter) 202和第一开关晶体管203。 Controller 151 shown in [0059] FIG 2 comprises a diode 201, an inverter (inverter) 202, and a first switching transistor 203. 二极管201设在电源与第一结点之间,并连接以使从电源到第一结点的方向是二极管201的正向。 Diode 201 is provided between the power supply and the first node, and connected so that a direction from the first node to the power source is a diode 201 forward. 二极管201还具有保持累积在电连接到第一结点的第一电容器中的电荷的功能。 A charge diode 201 also has the function of a first capacitor electrically connected to the first node remains accumulated. 将写信号(〇S_WE)输入到倒相器202,然后将写信号的倒相的值输出到第一开关晶体管203的栅电极。 The write signal (〇S_WE) is input to the inverter 202, and then write the output value of the inverted signal to the gate electrode of the first switching transistor 203. 第一开关晶体管203的第一电极接地,以及其第二电极电连接到二极管201的负极。 A first electrode of the first switching transistor 203 is grounded, and a second electrode electrically connected to the cathode of the diode 201.

[0060] 当将H-电平信号作为写信号(0S_WE)输入时,倒相器202产生的L-电平信号被输入到第一开关晶体管203的栅电极,从而将第一开关晶体管截止。 [0060] When the H- level signal as a write signal (0S_WE) input, L- level signal is generated by inverter 202 is input to the gate electrode of the first switching transistor 203, thereby the first switching transistor is turned off. 由此,将电源电位输入到第一结点(Ml)以使第一结点处的电位等于电源电位。 Accordingly, the power supply potential is input to the first node (of Ml) such that the potential at the node is equal to a first power source potential. 当将L-电平信号作为写信号输入时,倒相器产生的H-电平信号被输入到第一开关晶体管203,从而将第一开关晶体管导通。 When the L- level signal input as a write signal, an H-level signal is inverted phase are inputted to the first switching transistor 203, so that the first switching transistor is turned on. 由此, 将接地电位输入到第一结点,并释放累积的电荷。 Thus, the ground potential is input to the first node, and releases the accumulated charge.

[0061] 图2所示的延迟电路153包括电阻器205、电容器207和缓冲电路209。 The delay circuit 153 shown in [0061] FIG 2 comprises a resistor 205, a capacitor 207 and a buffer circuit 209. 将写信号(0S_ WE)输入到电阻器205。 The write signal (0S_ WE) input to the resistor 205. 电阻器205电连接到具有一个接地的电极的电容器207和缓冲电路209的输入端。 Electrical resistor 205 is connected to an electrode having a grounded capacitor 207 and the input terminal of the buffer circuit 209. 缓冲电路209的输出端电连接到第一电容器157。 Output terminal of the buffer circuit 209 is connected to a first capacitor 157.

[0062] 如图1所示,第一电容器157的一个电极电连接到控制器151的输出端和第一晶体管159的栅电极。 [0062] As shown in FIG. 1, a first capacitor electrode 157 is electrically connected to the gate electrode of the output of the controller 151 and the first transistor 159. 经控制器151,将电源电位输入到第一电容器157的一个电极。 By the controller 151, the power supply potential is inputted to a first electrode of the capacitor 157. 第一电容器157的另一个电极电连接到延迟电路153的输出端,并且将延迟的写信号从延迟电路153输入到第一电容器157的该另一个电极。 A first capacitor the other electrode 157 is connected to the output terminal of the delay circuit 153, and the delayed write signal input from the delay circuit 153 to the other electrode of the first capacitor 157.

[0063] 将输入数据信号(Data)输入到第一晶体管159的第一电极。 [0063] The input data signal (Data) inputted to a first electrode of the first transistor 159.

[0064] 第一晶体管159的第二电极形成第二结点(M2),其中保持输入数据信号。 [0064] The second electrode of the first transistor 159 is formed a second node (M2), wherein the hold input data signal. 因此,优选地,第一晶体管159的第一电极与第二电极之间的截止态电流是小的。 Thus, preferably the off-state current between the first electrode of the first transistor and the second electrode 159 is small. 沟道宽度每微米的截止态晶体管的泄漏电流优选地等于或低于10 aA (I XKT17 A),进一步优选地等于或低于I aA (IX 10—18 A),以及进一步优选地等于或低于100 yA (1X10—22 A)。 A leakage current per micrometer of channel width of a transistor off-state preferably equal to or less than 10 aA (I XKT17 A), more preferably equal to or lower than I aA (IX 10-18 A), and more preferably equal to or lower to 100 yA (1X10-22 A).

[0065] 此处,例如,将使用氧化物半导体的晶体管应用于第一晶体管159。 [0065] Here, for example, a transistor using an oxide semiconductor is applied to the first transistor 159. 使用氧化物半导体的晶体管具有显著小的截止态电流的特征。 A transistor using an oxide semiconductor having a significantly small off-state current characteristics. 由于此原因,能够在第一晶体管159截止时将第二结点处的电位保持极其长的期间。 For this reason, the potential can be held at the second node extremely long period when the first transistor 159 is turned off. 在存储器装置包括第二电容器161时,能够更容易地保持供给到第二结点的电荷。 When the memory device includes a second capacitor 161, it can be more easily supplied to the charge holding the second node. 在附图中,将字母符号“0S”置于第一晶体管159的电路符号下方以便指示第一晶体管159是使用氧化物半导体的晶体管。 In the drawings, the letter symbol "0S" symbol disposed below the first transistor circuit 159 so as to indicate the first transistor 159 is a transistor using an oxide semiconductor.

[0066] 经由第一晶体管159,将输入数据信号(Data)输入到第二结点,并且在第二电容器161中累积与输入数据信号对应的电荷。 [0066] 159 via a first transistor, the input data signal (Data) inputted to the second node, and the input data signal corresponding to the accumulated charge in the second capacitor 161.

[0067] 读取电路155是电连接到第二结点的电路,其根据读信号(0S_RD)读取与第二结点处保持的电荷对应的信号,并将读取的信号作为输出信号Q输出。 [0067] The reading circuit 155 is electrically connected to the second circuit node, which holds signal charges corresponding to a read signal (0S_RD) read according to the second node, and the read signal as the output signal Q output. 读取电路155连接到未示出且由电源电位驱动的电源。 The read circuit 155 is connected to and driven by the power supply potential of the power supply, not shown. 因此,此实施例的存储器装置无需设有用于生成电位的电压变换器等,从而促成功耗的降低。 Thus, the memory device of this embodiment need not be provided with a voltage converter or the like for generating potential, thus contributing to reduction in power consumption.

[0068] 本实施例中的读取电路155包括晶体管,其栅极电连接到第一晶体管159的第二电极和第二电容器161的电极。 [0068] The present embodiment the read circuit 155 in this embodiment includes a transistor having a gate electrode electrically connected to a second electrode of the first transistor 159 and the second capacitor 161. 利用此结构,读取电路中的晶体管的栅电极连接到第二结点, 这使得从第二结点流到读取电路的截止态电流极小。 With this structure, the gate electrode of the read transistor is connected to a second circuit node, which makes the reading circuit flows from the second node off-state current is very small. 相应地,第二结点能够长时间地保持电荷。 Accordingly, the second node capable of holding a charge for a long time.

[0069] 例如,读取电路155可以具有图3所示的电路配置。 [0069] For example, the read circuit 155 may have a circuit configuration shown in FIG.

[0070] 图3中的读取电路155包括具有电连接到第二结点(M2)的栅电极的第二晶体管301、具有与第二晶体管301相同导电类型的第三晶体管303和具有与第二晶体管301和第三晶体管303不同导电类型的第四晶体管305。 The read circuit 155 in [0070] FIG. 3 includes a second transistor 301 having a gate electrode electrically connected to the second node (M2) are of a second transistor 301 having the same conductivity type and having a third transistor 303 and the second second transistor 301 and third transistor 303 of different conductivity type fourth transistor 305. 在本实施例中,第二晶体管301和第三晶体管303是η沟道晶体管,以及第四晶体管305是p沟道晶体管。 In the present embodiment, the second transistor 301 and third transistor 303 is η-channel transistor, and the fourth transistor 305 is a p-channel transistor.

[0071] 第二晶体管301的栅电极电连接到第一晶体管159的第二电极和第二电容器161的电极,并形成其中保持电荷的第二结点(M2)。 [0071] The gate electrode of the second transistor 301 is connected to the second electrode of the first transistor 159 and the second capacitor electrode 161, and forms a second node which (M2) holding charges. 第二晶体管301的第一电极接地,以及其第二电极电连接到第三晶体管303的第一电极。 The first electrode of the second transistor 301 is grounded, and a second electrode is electrically connected to a first electrode of the third transistor 303.

[0072] 第三晶体管303的第二电极电连接到第四晶体管305的第一电极,以及第四晶体管305的第二电极电连接到电源。 The first electrode of the second electrode [0072] The third transistor 303 is connected to the fourth transistor 305, and a second electrode of the fourth transistor 305 is connected to a power supply.

[0073] 将读信号(0S_RD)输入到第三晶体管303的栅电极和第四晶体管305的栅电极。 [0073] A read signal (0S_RD) is input to the gate electrode of the third transistor 303 and the gate electrode of the fourth transistor 305. 因为第三晶体管303和第四晶体管305具有不同的导电类型,所以当第三晶体管303和第四晶体管305的其中之一导通时,其中另一个截止。 Since the third transistor 303 and fourth transistor 305 having a different conductivity type, so that when the third transistor 303 and fourth transistor 305 are turned on one of which the other is turned off.

[0074] 第三电容器307的一个电极接地。 A ground electrode [0074] 307 of the third capacitor. 第三电容器307的另一个电极电连接到第三晶体管303的第二电极、第四晶体管305的第一电极和倒相器309,以形成第三结点(M3)。 Another third capacitor electrode 307 is electrically connected to the second electrode of the third transistor 303, a first electrode of the fourth transistor 305 and the inverter 309, to form a third node (M3).

[0075] 倒相器309的输入端电连接到第三结点(M3)。 [0075] The inverting input of phase detector 309 is electrically connected to the third node (M3). 因此,将第三结点处的电位输入到倒相器309。 Thus, the potential at the third node 309 is input to the inverter. 倒相器309的输出端用作读取电路155的输出端。 The output terminal of the inverter 309 is used as the reading of the output of the circuit 155. 因此,从倒相器309输出的值作为存储器装置中保持的值被读出。 Thus, the inverted value of the value held in the output from the phase detector 309 as a memory means is read out.

[0076] 读取电路155的配置不限于上文描述的配置,读取电路155可以是使用比较器等的电路,只要它是能够确定第二结点(M2)处保持的电荷的量的电路即可。 [0076] The configuration of the read circuit 155 is not limited to the above described configuration, the read circuit 155 may be a comparator circuit or the like is used, the amount held as long as it is capable of determining a second node (M2) at a charge circuit It can be.

[0077] 接下来,将描述用于驱动本实施例的存储器装置的方法。 [0077] Next, will be described a method of driving the memory device of the present embodiment is used. 图4A和图4B是根据本发明的驱动存储器装置的时序图。 4A and FIG. 4B is a timing chart of driving a memory device according to the invention.

[0078] 图4A是本实施例的存储器装置的写入操作的时序图。 [0078] FIG 4A is a timing chart showing a write operation of the memory device according to the present embodiment. 在时序图中,Vs表示从电源输入到控制器的电位,以及〇S_WE表不写信号的电位。 In the timing chart, Vs represents the input to the controller from the power potential, and the table does not write 〇S_WE potential signal. 再者,Al表不第一电容器157的另一个电极的电位,Data表不输入数据信号的电位,Ml表不第一结点的电位,以及M2表不第二结点的电位。 Further, the potential of the other electrode potential of Al sheet is not the first capacitor 157, Data Table potential does not input data signal, the potential of the first node table does not Ml and M2 does not list the second node.

[0079] 在初始状态中,第一结点接地,以使连接到第一结点的第一电容器157中不累积电荷。 [0079] In the initial state, a first node to ground, so that the first capacitor is connected to the first node 157 does not accumulate charges. 因此,第一结点处的电位是接地电位。 Thus, the potential at the first node is a ground potential. 相似地,将第二结点(M2)处的电位设为接地电位。 Similarly, the potential of the second node (M2) at the ground potential. 电源在初始状态中是导通的(H-电平电位)。 Power supply is turned on (H- level potential) in the initial state. 注意,H-电平信号的电位是电源电位Vdd。 Note that, the potential level of a signal is H- power supply potential Vdd.

[0080] 将描述用于将数据写入存储器装置的方法。 [0080] The method will be described for writing data to the memory means.

[0081] 在写入存储器装置的第一步骤中,将作为写信号(0S_WE)的H-电平信号输入到控制器151和延迟电路153。 [0081] In a first step of writing in memory means, the input level signal as the write signal H- (0S_WE) to the controller 151 and the delay circuit 153. 当H-电平信号输入到控制器时,电源电位被输入到第一结点,然后第一结点处的电位(Ml)上升到电源电位VdcK参见图4A中的期间Tl)。 When the H- level signal is input to the controller, the power supply potential is inputted to the first node, and the potential at the first node (of Ml) rises to the power source potential in the period Tl VdcK see FIG. 4A).

[0082] 当将电源电位Vdd输入到第一结点时,在连接到第一结点的第一电容器157中累积与电源电位Vdd对应的电荷,并且预充电期间(图4A中的期间Tl)结束。 [0082] When the power supply potential Vdd is input to the first node, and the power supply potential Vdd corresponding to the accumulated charge in the first capacitor is connected to the first node 157, and the precharge period (period in FIG. 4A Tl) End.

[0083] 在下面的第二步骤中,由延迟电路153将输入到该延迟电路的写信号(H-电平信号)延迟,并输入到第一电容器157的另一个电极(Al)(参见图4A中的期间T2)。 [0083] In the second step below, by the delay circuit 153 is inputted to the delay circuit write signal (H- level signal) is delayed, and the other input to the first capacitor electrode (of Al) (see 157 of FIG. 4A in the period T2).

[0084] 响应H-电平信号输入到第一电容器157的另一个电极,第一电容器157的该另一个电极的电位上升输入信号的电位,即,上升等于H-电平信号的电位(=电源电位Vdd)的电位。 [0084] H- response level signal is input to the other electrode of the first capacitor 157, the potential of the first capacitor 157 rises other electrode potential of the input signal, i.e., equal to the potential rise of the signal level of H- (= power supply potential Vdd) potential. 对此响应,由于与第一电容器157的该另一个电极电容親合,所以第一电容器157的一个电极也上升了电源电位Vdd。 In response to this, since the first capacitor and the other electrode of the capacitor 157 of the affinity, the first electrode of a capacitor 157 also increases the power supply potential Vdd.

[0085] 此时,预充电期间中累积的与电源电位对应的电荷被累积在第一电容器157中。 [0085] At this time, charge corresponding to the power supply potential during the precharge period accumulated is accumulated in the first capacitor 157. 控制器151中包含的二极管保持第一结点中累积的电荷。 Diode controller 151 included in the holding charges accumulated in the first node. 因此,当输入来自延迟电路153的延迟的信号时,第一电容器157的一个电极的电位达到通过将延迟的输入信号导致的电荷加上预充电期间中累积对应于电源电位Vdd的电荷而获得的电位,理想地为2Vdd。 Thus, when the input of the delay signal from the delay circuit 153, the potential of one electrode of the first capacitor 157 reaches a charge by the delayed input signal leads plus precharge period corresponding to the charge accumulated in the power supply potential Vdd obtained potential, ideally 2Vdd. 换言之,在第二步骤中执行借助于电容耦合提升第一结点处的电位所采用的自举操作。 In other words, performing bootstrap operation by means of the potential at the first node to enhance capacitive coupling employed in the second step.

[0086] 在下面的第三步骤中,响应第一结点的电位上升,第一晶体管159被导通,然后经由第一晶体管159将输入数据信号输入到第二结点(M2)(参见图4A中的期间T2和期间T3)。 [0086] In a third step below, in response to the increased potential of the first node, the first transistor 159 is turned on, and the input data signal is input to a second node (M2) via a first transistor 159 (see FIG. 4A period T3 and the period T2).

[0087] 作为输入数据信号将电源电位或接地电位输入到第一晶体管159的第一电极(源电极)。 [0087] The data signal as input power supply potential or the ground potential input to the first electrode of the first transistor 159 (a source electrode). 为了导通第一晶体管159,对第一晶体管的栅电极需要高于电源电位的电位。 In order to turning on the first transistor 159, a gate electrode of the first transistor pair needs to be above the power-supply potential.

[0088] 但是,如果使用电压变换器来实现高电位的输入,则会增加功耗。 [0088] However, if the input voltage converter to achieve a high electric potential, power consumption will increase. 再者,因为电压变换器的变换效率不是100%,所以使用电压变换器导致电功率损耗。 Further, since the conversion efficiency of the voltage converter is not 100%, so the use of electric power loss results in the voltage converter.

[0089] 但是,本实施例的存储器装置能够在没有电压变换器的情况下利用上述自举操作来向第一晶体管159的栅电极输入高电位,从而实现高速操作。 [0089] However, the memory device of the present embodiment is capable of using the bootstrap operation in the case where no voltage converter to the input of the high potential to the gate electrode of the first transistor 159, thereby realizing a high speed operation. 因为能够减少电压变换器的数量,所以能够形成降低功耗的电路。 Since it is possible to reduce the number of the voltage converter circuit to reduce the power consumption can be formed.

[0090] 当第一晶体管159导通时,输入数据信号经由第一晶体管159输入到第二结点,并且在第二电容器中累积与输入数据信号对应的电荷。 [0090] When the first transistor 159 is turned on, the data signal input via the first input transistor 159 to the second node, and the input data signal corresponding to the accumulated charge in the second capacitor.

[0091] 作为输入数据信号,输入电源电位或接地电位。 [0091] as the input data signal, the input power supply potential or a ground potential. 此处,将输入电源电位(H-电平信号)视为写入数据“Γ,以及将输入接地电位(L-电平信号)视为写入数据“0”。通过选择性地输入数据的其中之一,能够将1位数据写入到存储器装置。 Here, the input power supply potential (H- level signal) is regarded as data "Gamma], and the input to ground potential (L- level signal) is regarded as the data" 0. "The input data by selectively one of them, capable of writing data to a memory means.

[0092] 此时,由于自举操作的原因,无论输入数据信号的电位(电源电位或接地电位)如何,第一晶体管159的栅电极的电位是2Vdd,所以第一晶体管159的第一电极(源电极)与栅电极的电位之差足够以高速将第一晶体管159导通。 [0092] At this time, due to the bootstrap operation, regardless of the input data signal potential (power supply potential or ground potential) how the potential of the gate electrode of the first transistor 159 is 2Vdd, so that a first electrode of the first transistor 159 ( source electrode) and the potential difference between the gate electrode of the first transistor at a high enough 159 is turned on. 因此,对存储器装置的写入操作能够以高速执行。 Therefore, the write operation of the memory device can be performed at high speed.

[0093] 将输入数据信号输入到第一晶体管159的第一电极所处的时间可以是通过自举操作提升第一结点处的电位之前的任何时间。 [0093] The input data signal is input to the time at which the first electrode of the first transistor 159 may be any time before the potential at the bootstrap operation by lifting the first node. 在本实施例中,输入数据信号在第一步骤中将写信号(〇S_WE)的电位设为H电平的同时被输入。 In the present embodiment, the potential of the input signal data write signal (〇S_WE) in a first step the H level is input at the same time.

[0094] 此处,将数据写入存储器装置被完成。 [0094] Here, the data is written to the memory device is completed. 在接下来的步骤中,将数据保持在存储器装置中,并将电源切断,下文将对此予以描述。 In the next step, the data held in the memory means, and cut off the power, as will be described hereinafter.

[0095] 在第四步骤中,将L-电平信号作为写信号输入到控制器151和延迟电路153。 [0095] In a fourth step, the L- level signal is input to the controller 151 and the delay circuit 153 as a write signal. 响应L-电平信号作为写信号输入到控制器,控制器151将接地电位输入到第一结点。 L- level signal as response to a write signal is input to the controller, the controller 151 is input to the first ground potential node. 由此,第一结点中累积的电荷被释放,以使第一结点处的电位变为接地电位(参见图4A中的期间T4)。 Accordingly, the first node charge accumulated is released, so that the potential at the first node and the ground potential (period T4 see FIG. 4A).

[0096] 对此响应,电连接到第一结点的第一晶体管159的栅电极的电位变为接地电位,并且第一晶体管159被截止,这停止输入数据信号向第二结点输入。 [0096] In response to this, electrically connected to the gate electrode of the first transistor 159 to the first node of the potential at the ground potential, and the first transistor 159 is turned off, it stops the data input signal to the second input node.

[0097] 第一晶体管159是其中在氧化物半导体上形成沟道的晶体管。 [0097] The first transistor 159 is a transistor in which a channel is formed on the oxide semiconductor. 相应地,该晶体管具有极小的截止态电流。 Accordingly, the transistor has an extremely small off-state current. 即使第一晶体管159被截止且对第二结点的输入数据信号的输入停止,第二结点中累积的电荷仍能够长时间保持。 Even when the first transistor 159 is turned off and the input node of the second input data signal is stopped, the second node is still able to charge accumulated long period of time.

[0098] 因此,即使电源被切断且对存储器装置的电功率的输入停止,写入第二结点的数据仍能够长时间保持。 [0098] Accordingly, even when the power is turned off and the input electric power to the memory device is stopped, data written in the second node still can be maintained for a long time. 电功率的提供对于数据保持不是必不可少的;相应地,能够减少功耗。 Providing electric power for holding data is not essential; accordingly, power consumption can be reduced.

[0099] 通过上述操作,数据能够被保持在存储器装置中。 [0099] By the above operation, data can be held in the memory device.

[0100] 接下来,将描述用于读取保持在存储器装置中的数据的操作。 [0100] Next, description will be held in the memory means for reading the data operation. 图4B是读取存储器装置中保持的数据的时序图。 4B is a timing chart of data read from the memory means retained. 在本实施例中,将使用图3所示的电路作为读取电路155来提供读取操作的描述。 In the present embodiment, the use of the circuit shown in FIG. 3 as described with the read circuit 155 to provide the read operation.

[0101] 在图4B的时序图中,Vs表示电源的电位,0S_RD表示读信号的电位,M3表示第三电容器307的另一个电极,以及Q表示存储器装置的输出的电位。 [0101] In the timing chart of FIG. 4B, Vs denotes the potential of the power source, 0S_RD indicates the potential of the read signal, M3 represents the other electrode of the third capacitor 307, and Q represents a potential of the output of the memory device. 该存储器装置输出与第二结点处保持的电荷对应的信号。 The signal corresponding to the charges held in the memory device at the second output node. 注意,图4B的时序图示出将H-电平信号存储在存储器装置中的情况中的操作。 Note that FIG. 4B illustrates a timing operation of the H- level signal is stored in the memory means in.

[0102] 在读取操作之前,作为读信号(〇S_RD)输入L-电平信号。 [0102] Prior to a read operation, a read signal (〇S_RD) L- level signal is input. 相应地,作为η沟道晶体管的第三晶体管303处于截止态。 Accordingly, the third transistor η channel transistor 303 in an off state. 另一方面,作为ρ沟道晶体管的第四晶体管305处于导通态。 On the other hand, as the fourth transistor ρ-channel transistor 305 in the ON state. 当第四晶体管305导通时,电源电连接到第三电容器307,使得与电源电位对应的电荷累积在第三电容器307中(参见图4Β中的期间Τ5)。 When the fourth transistor 305 is turned on, the power supply 307 is electrically connected to the third capacitor, so that charge accumulation corresponding to a power supply potential (Τ5 period see FIG. 4 beta) in the third capacitor 307.

[0103] 注意,因为在电源导通之前,第三电容器307中累积的电荷的量是无限的,所以时序图中以虚线将此类状态表示为无限大状态(X) [0103] Note that, because before the power is turned on, the accumulated amount of charge the third capacitor 307 is infinite, so the timing chart in phantom such state is represented as the infinite state (X)

[0104] 在读取存储器装置中存储的数据时,首先将读信号(0S_RD)设为H-电平信号(期间T6)。 [0104] When reading data stored in the memory means, first a read signal (0S_RD) level signal to H- (period T6). 响应H-电平信号的输入,作为ρ沟道晶体管的第四晶体管305被截止,而作为η沟道晶体管的第三晶体管303被导通。 H- response to the input level of the signal, the fourth transistor 305 is turned off as ρ-channel transistor and a third transistor η-channel transistor 303 is turned on. 因此,第三电容器307与电源断开电连接,并由此第三电容器中累积的电荷流到第三晶体管303。 Accordingly, third capacitor 307 is electrically connected to the power supply is disconnected, and thus the charge accumulated in the third capacitor 303 flows to the third transistor.

[0105] 此时,因为第三电容器303是导通的,所以第三电容器307中累积的电荷经由第三晶体管303流进第二晶体管301。 [0105] At this time, since the third capacitor 303 is turned on, the third capacitor 307 charges accumulated in the third transistor 303 via the transistor 301 flows into the second. 此时,如果在第二结点M2处保持H-电平信号,并将H-电平信号输入到第二晶体管301的栅电极,则第二晶体管301导通,并且第三电容器307中累积的电荷流动并经第二晶体管301释放到接地电位中。 At this time, if the level of the signal holding H-, H- level signal is input and a second node M2 ​​to the gate electrode of the second transistor 301, second transistor 301 is turned on, and the third capacitor 307 is accumulated the charge flow and released into the ground potential through the second transistor 301. 因此,第三电容器307的另一个电极的电位变为L电平(参见图4B中的期间T6)。 Thus, the potential of the other electrode of the capacitor 307 becomes a third (T6 period see FIG. 4B) L level.

[0106] 然后,将L-电平信号输入到倒相器309,并从倒相器309输出H-电平信号。 [0106] Then, the L- level signal is input to the inverter 309, and outputs the H- level signal from inverter 309. 因为倒相器309的输出作为存储器装置的输出被提取,所以从存储器装置输出H-电平信号。 Because the output of the inverter 309 is extracted as the output of the memory means, the memory means output signal level from H-.

[0107] 此处,将描述另一方面在第二结点处保持L-电平信号的情况。 [0107] Here, the other hand holding L- level signal at the second node will be described.

[0108] 在第二结点处保持L-电平信号的情况中,第二晶体管301截止。 [0108] In the case of holding at the second node L- level signal, the second transistor 301 is turned off. 即使作为读信号输入H-电平信号以导通第三晶体管303时,第三电容器307仍未连接到接地电位,且保持累积的电荷。 As a read signal even when the input signal level H- to turn on the third transistor 303, a third capacitor 307 is connected not to a ground potential, and maintaining charge accumulation.

[0109] 因此,第三电容器中累积的电荷(电源电位=H-电平信号)被输入到倒相器309, 然后从倒相器309的输出变为L-电平。 [0109] Accordingly, charges accumulated in the third capacitor (power supply potential = H- level signal) is input to the inverter 309, and the output of the inverter 309 becomes L- level. 相应地,存储器装置输出L-电平信号。 Accordingly, the memory device outputs L- level signal.

[0110] 通过上述的操作,读取电路155根据第二晶体管301的导通/截止态读取第二晶体管301的栅电极中保持的电荷,并读取与第二结点处保持的数据对应的信号。 [0110] Through the above operation, the read circuit 155 according to the second transistor 301 is turned on / off-state of the gate electrode 301 of the read charge held in the second transistor, and the read data held at the second node and the corresponding signal of.

[0111] 通过上述操作,存储器装置读取了数据。 [0111] By the above operation, the memory device reads data.

[0112] 在读取操作完成之后,将读信号返回到L-电平(参见图4B中的期间T7)。 [0112] After the read operation is completed, the read signal is returned to the L- level (period T7 see FIG. 4B). 在作为读信号输入L-电平信号的情况中,作为p沟道晶体管的第四晶体管305是导通的,并在第三电容器307中累积与电源电位对应的电荷。 In the case of a read signal input L- level signal, the p-channel transistor, the fourth transistor 305 is conductive, and the charge accumulated in the power supply potential corresponding to the third capacitor 307.

[0113] 在作为读信号输入L-电平信号期间,无论第二结点处保持的电位如何,从存储器装置的输出是L电平。 [0113] During the read signal input level signal as the L-, regardless of holding the potential at the second node, the L level is output from the memory device. 因此,从存储器装置读取数据仅在读信号是H电平的期间执行。 Thus, data is read from the memory means only during the execution of the read signal is the H level. 由于此原因,在H-电平信号不作为读信号输入的期间从存储器的输出在时序图中表示为无限大(X) 〇 For this reason, not as a read signal input period in the timing diagram represents the H- level signal outputted from the memory is infinite (X) square

[0114] 为了进一步减少功耗,读取电路155可以具有这样的结构:在电源与第四晶体管305之间设置开关以在读信号处于L电平时,即在未执行读取操作时,切断电源与其他元件之间的连接。 [0114] In order to further reduce power consumption, the reading circuit 155 may have a structure: a switch disposed between the power supply and the fourth transistor 305 to a read signal at the L level, i.e., when the reading operation is not performed, and cut off the power the connection between the other elements.

[0115] 本实施例的存储器装置是利用自举电路并由此在操作中仅使用等于作为数据写入的信号的电位的电位的存储器装置。 The memory device [0115] This embodiment is the use of a bootstrap circuit and thus the potential of the memory device using only the potential of the signal is equal to a data write in operation. 具体来说,将供电电位从电源输入到晶体管的栅极和第一电容器的一个电极连接的第一结点,以便将电荷累积在第一结点中。 Specifically, a first gate electrode of a node from the power supply potential is input to the transistor and a first capacitor connected to the charge accumulated in the first node. 然后,将等于电源电位的电位施加于第一电容器的另一个电极,以使晶体管的栅极的电位变为高于电源电位。 Then, the potential equal to the power supply potential is applied to the other electrode of the first capacitor, so that the potential of the gate of the transistor becomes higher than the power source potential. 晶体管的栅极的电位高于电源电位能够实现高速数据写入,并且能够减少电压变换器的数量,从而降低存储器装置的功耗。 Gate of the transistor is higher than the potential of the power supply potential capable of high-speed data writing, and to reduce the number of voltage inverter, thereby reducing power consumption of the memory device.

[0116] 本实施例的存储器装置使用其中在氧化物半导体层中形成沟道层的晶体管作为形成保持数据的结点的晶体管。 The memory device [0116] This embodiment uses a transistor in which a channel layer is formed in the oxide semiconductor layer is formed as the transistor to keep the junction data. 因此,减少截止态电流,从而该存储器装置能够长时间保持所存储的数据。 Thus, to reduce off-state current, so that the memory device capable of holding stored data for a long time.

[0117] 本实施例的存储器装置使用延迟电路来以一个信号控制自举电路和数据输入电路,从而能够以相对简单的电路配置形成功耗降低的电路。 The memory device using the [0117] embodiment of the present embodiment to a signal delay circuit to control the bootstrap circuit and the data input circuit, it is possible to reduce the power consumption of the circuit forming a relatively simple circuit configuration.

[0118] 本实施例的存储器装置能够适当地与任意其他实施例组合。 The memory device of [0118] embodiment of the present embodiment can be combined with any other embodiment as appropriate.

[0119] (实施例2) [0119] (Example 2)

[0120] 在本实施例中,将描述实施例1中的存储器装置中包含的控制器的结构,此结构不同于实施例1中的结构。 [0120] In the present embodiment, the configuration of the controller described in Example 1 of the embodiment comprises a memory device, this configuration is different from the structure of Example 1 embodiment.

[0121] 图5是本实施例的存储器装置中包含的控制器的电路图。 [0121] FIG. 5 is a circuit diagram of a memory device of the controller according to the present embodiment contains. 在本实施例中,实施例I 中描述的点不予重复,而将主要描述与实施例1中那些不同的点。 Point in the present embodiment, as described in Example I are not repeated, but will be mainly described in Example 1 are different from those points embodiment.

[0122] 除了图2所示的元件外,图5中的控制器151在二极管201与电源之间具有第二开关晶体管503,第二开关晶体管503具有与第一开关晶体管203不同的导电类型。 [0122] In addition to the elements shown in FIG. 2, the controller 151 of FIG. 5 has a second switching transistor 503 between the diode 201 and the power supply, a second switching transistor 503 having a conductivity type different from the first switching transistor 203.

[0123] 经倒相器202将写信号(0S_WE)输入到第二晶体管503的栅电极。 [0123] via the inverter 202, a write signal (0S_WE) inputted to the gate electrode of the second transistor 503. 第二开关晶体管503的第一电极电连接到电源,以及第二开关晶体管503的第二电极经二极管201电连接到第一结点Ml。 A first electrode of the second switching transistor 503 is connected to a power supply, and a second electrode of the second switching transistor is electrically connected via a diode 201 to the first node 503 of Ml.

[0124] 第一开关晶体管203是确定第一结点是否接地的开关。 [0124] The first switching transistor 203 is to determine whether a first grounding switch node. 第二开关晶体管503是确定第一结点与电源之间的连接状态的开关。 A second switching transistor 503 is to determine the state of switch connection between the first node and the power supply.

[0125] 还经倒相器202将写信号输入到第一开关晶体管203的栅电极。 [0125] via the inverter 202 is also a write signal is input to the first gate electrode 203 of the switching transistor. 因为第一开关晶体管203和第二开关晶体管503是具有不同导电类型的晶体管,所以当第一开关晶体管203和第二开关晶体管503的其中之一导通时,另一个截止。 Because the first switching transistor 203 and the second switching transistor 503 is a transistor having a different conductivity type, when the first switching transistor 203 and the second switching transistor 503 is turned on one of, the other off.

[0126] 因此,当第一结点接地且释放电荷时,第一结点与电源之间的电连接被切断。 [0126] Thus, when the first node to ground and discharge the charge, the electrical connection between a first node connected to the supply is cut off. 当第一结点连接到电源时,不输入接地电位。 When the power supply is connected to the first node, the ground potential is not input.

[0127] 利用此结构,能够防止在第一结点接地的时间期间将电荷从电源输入到第一结点,这样能够实现功耗的降低。 [0127] With this structure, it is possible to prevent the ground node during a first time the charge from the power input to the first node, so that the power consumption can be reduced.

[0128] 图6图示具有不同结构的控制器电路。 [0128] FIG. 6 illustrates a controller circuit having a different structure.

[0129] 与图5中的控制器比较,图6中的控制器包括NOR电路701以代替倒相器202,其中经由NOR电路701将写信号输入到第一开关晶体管203和第二开关晶体管503。 In [0129] FIG. 5 compared with the controller, the controller 6 includes a NOR circuit 701 in place of the inverter 202, via a NOR circuit 701 in which a write signal is input to the first switching transistor 203 and the second switching transistor 503 . 不仅写信号,而且包括电阻器和电容器的延迟电路703延迟的写信号和延迟电路153延迟的写信号均被输入到NOR电路701。 Not only write signal, and a delay circuit comprising a resistor and a capacitor 703 delayed write signal delay circuit 153 delays the write signal to the NOR circuit 701 are inputted.

[0130] 延迟电路703具有比延迟电路153更长的延迟时间。 [0130] The delay circuit 703 having a delay time longer than the delay circuit 153. 延迟电路将输入信号延迟的时间能够通过公知的调整方法来调整;但是,本实施例中的延迟电路的延迟时间优选地通过更改延迟电路的电容器的电容来进行调整。 The delay circuit delays the input signal a time can be adjusted by adjusting the known method; however, the delay time of the delay circuit is preferably in the present embodiment to be adjusted by changing the capacitance of the capacitor delay circuit. 该延迟电路的延迟时间还可以通过改变电阻器的电阻来改变;但是,用于通过改变电容调整延迟时间的方法能够更稳定地调整电路的延迟时间。 The delay time of the delay circuit may also be varied by changing the resistance of the resistor; however, a method for changing the delay time by adjusting a capacitance can be more stably adjust the delay time of the circuit.

[0131] 当输入到NOR电路701的三个信号中至少一个是H-电平信号时,NOR电路701输出L-电平信号。 [0131] When the three signals are input to the NOR circuit 701 is at least a H- level signal, NOR circuit 701 outputs L- level signal. 即,当这些信号中至少一个是H-电平信号时,第二开关晶体管503导通以将第一结点电连接到电源。 That is, when at least one of these signals is an H- level signal, the second switching transistor 503 is turned on to a first node electrically connected to the power source.

[0132] 正如实施例1中描述的,当从延迟电路153将延迟的写信号输入到第一电容器157 时,由于电容耦合,第一结点(Ml)处的电位上升。 [0132] As described in Example 1, from the delay circuit 153 when the delayed write signal is input to a first capacitor 157, due to capacitive coupling, the potential of the first node (of Ml) at the rise. 此时,为了导通具有连接到第一结点的栅电极的第一晶体管159,第一结点需要保持与电源电位对应的电荷,换言之,并非需要将接地电位而是需要将电源电位输入到第一结点。 In this case, to a first transistor having a conductive gate electrode connected to a first node 159, the first node needs to maintain power source potential corresponding to the charge, in other words, need not be ground potential but rather is input to the power supply potential the first node.

[0133] 如图6中所示的电路中所示,不仅可以通过直接输入写信号0S_WE,而且可以通过将延迟电路153延迟的写信号和延迟电路703延迟的写信号输入到NOR电路701来延长NOR电路输出L-电平信号的期间。 [0133] As shown in the circuit shown in FIG. 6, not only through the direct input 0S_WE write signal, and may be extended by the delay circuit 153 a write signal is inputted to the NOR circuit 701 and the delayed write signal delay circuit 703 delays during the output of the NOR circuit L- level signal. 因为当延迟电路153延迟的信号输入到第一电容器157时,这些信号中至少任何一个被输入到NOR电路701,所以能够在将由延迟电路153延迟的信号输入到第一电容器157时,确定地将电源电位输入到第一结点。 Because when the delay circuit 153 delays a signal input to the first capacitor 157, at least any one of these signals is input to the NOR circuit 701, it is possible to delay circuit 153 delays a signal input to the first capacitor 157 will be determined to be input to the first power supply potential node.

[0134] 再者,利用其中设置具有比延迟电路153更长的延迟时间的延迟电路703的结构, 还能够在将来自延迟电路153的信号输入到第一电容器157之后向NOR电路701输入信号。 [0134] Further, the use of which the structure is provided having a delay time of the delay circuit 703 than the longer the delay circuit 153, it is also possible to input the signal from the delay circuit 153 to the first capacitor 157 after a signal is input to the NOR circuit 701. 相应地,由于电容耦合所致的电位提升能够明确地导通第一晶体管159,并且能够将数据写入存储器装置。 Accordingly, the potential due to capacitive coupling caused by lifting can clearly turn on the first transistor 159, and the memory means data can be written.

[0135] 本实施例中描述的控制器比实施例1中描述的控制器包含更多的开关晶体管,并且能够在未从电源输入电位的期间断开第一结点Ml与电源之间的连接。 [0135] The present embodiment described the controller than the controller described in Example 1 contains more switching transistors, and is not able to disconnect the power supply and the first node Ml period from the input power source potential . 相应地,包含本实施例中描述的任何一个控制器的存储器装置比实施例1中描述的存储器装置具有更低的功耗。 Accordingly, any memory device comprising a controller according to the present embodiment described in the embodiment having lower power consumption than the memory device described in Example 1.

[0136] 在本实施例中,使用多个延迟电路,延长将包括由延迟电路153和703延迟的信号的信号输入到NOR电路701的期间是可能的。 [0136] In the present embodiment, a plurality of delay circuits, an input extension including a signal delay circuit 153 delays the signal 703 to the NOR circuit 701 is the period possible. 因此,能够延展将电源电位输入到第一晶体管159的期间,这样允许明确地将电源电位输入到第一晶体管159,直到自举操作完成为止。 Accordingly, it is possible to extend the power supply potential during the first input transistor 159, which allows the power supply potential explicitly input to the first transistor 159 until the bootstrap operation is completed.

[0137] 本实施例能够适当地与任意其他实施例组合。 [0137] This embodiment can be appropriately implemented in combination with any other embodiment.

[0138] (实施例3) [0138] (Example 3)

[0139] 在本实施例中,将描述上文实施例中描述的存储器装置(非易失性随机存取存储器)中使用的在氧化物半导体层中形成沟道的晶体管。 [0139] In the present embodiment, the transistor channel formed in the oxide semiconductor layer used in the memory device (nonvolatile random access memory) in the above described embodiment is described. 首先,下文将详细地描述氧化物半导体。 First, an oxide semiconductor will be described below in detail.

[0140] 氧化物半导体包括选自In、Ga、Sn和Zn的至少一种元素。 [0140] The semiconductor oxide includes at least one element selected from In, Ga, Sn and Zn. 作为氧化物半导体,例如可以使用如下的任何一种:氧化铟;氧化锡;氧化锌;二元金属氧化物,如In-Zn基氧化物、 Sn-Zn基氧化物、Al-Zn基氧化物、Zn-Mg基氧化物、Sn-Mg基氧化物、In-Mg基氧化物或In-Ga 基氧化物;三元金属氧化物,如Sn-Ga-Zn基氧化物、Al-Ga-Zn基氧化物、Sn-Al-Zn基氧化物、 In-Ga-Zn基氧化物(也称为IGZ0)、In-Al-Zn基氧化物、In-Sn-Zn基氧化物、In-Hf-Zn基氧化物、In-La-Zn基氧化物、In-Ce-Zn基氧化物、In-Pr-Zn基氧化物、In-Nd-Zn基氧化物、In-Sm-Zn基氧化物、In-Eu-Zn基氧化物、In-Gd-Zn基氧化物、In-Tb-Zn基氧化物、In-Dy-Zn基氧化物、In-Ho-Zn基氧化物、In-Er-Zn基氧化物、In-Tm-Zn基氧化物、In-Yb-Zn基氧化物或In-Lu-Zn基氧化物;以及四元金属氧化物,如In-Sn-Ga-Zn基氧化物、In-Hf-Ga-Zn基氧化物、 In-Al-Ga-Zn 基氧化物、In-Sn-Al-Zn 基氧化物、In-Sn-Hf-Zn 基氧化物或In-Hf-Al-Zn 基氧化物。 As the oxide semiconductor, for example, any of the following may be used: indium oxide; tin oxide; zinc oxide; binary metal oxides, such as In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide , Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide or In-Ga-based oxide; ternary metal oxides, such as Sn-Ga-Zn-based oxide, Al-Ga-Zn based oxide, Sn-Al-Zn-based oxide, In-Ga-Zn-based oxide (also referred IGZ0), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf- Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide or In-Lu-Zn-based oxide; and quaternary metal oxides, such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide or In-Hf-Al- Zn-based oxide.

[0141] 此处注意,例如,In-Ga-Zn基氧化物表示包含In、Ga和Zn作为其主要组分的氧化物,并且对In:Ga: Zn的比例没有限定。 [0141] Note here that, for example, In-Ga-Zn-based oxide represented containing In, Ga, and Zn as a main component an oxide thereof, and of In: Ga: Zn ratio is not limited. 再者,In-Ga-Zn基氧化物可以包含In、Ga和Zn以外的属兀素。 Further, In-Ga-Zn-based oxide may contain other than In, Ga and Zn metal element Wu.

[0142] 例如,可以使用具有如下原子比的In-Ga-Zn基氧化物:In: Ga: Zn = 1:1:1 (=1/ 3:1/3:1/3)或In:Ga:Zn = 2:2:1(= 2/5: 2/5:1/5)或其成分接近上面的成分的任何氧化物。 [0142] For example, having the following atomic In-Ga-Zn-based oxide ratios: In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga : Zn = 2: 2: 1 (= 2/5: 2/5: 1/5), or a composition close to the composition of any oxide thereon. 作为备选,可以使用具有如下原子比的In-Sn-Zn基氧化物:In:Sn:Zn = 1:1:1 (=1/3: l/3:l/3)、In:Sn:Zn = 2:1:3(= 1/3:1/6:1/2)或In:Sn:Zn = 2:1:5(= 1/4:1/8:5/8),或其成分接近上面的成分的任何氧化物。 Alternatively, the following may be used having an atomic ratio of In-Sn-Zn-based oxide: In: Sn: Zn = 1: 1: 1 (= 1/3: l / 3: l / 3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8), or any oxide composition close to the above ingredients.

[0143] 但是,成分不限于上文描述的那些,可以具体根据所需的半导体特征(例如,迀移率、阈值电压和变化(variation))来使用具有适合成分的材料。 [0143] However, the component is not limited to those described above, can be specifically depending on the desired semiconductor characteristics (e.g., Gan drift rate, and a threshold voltage variation (Variation)) is used for a material composition. 为了获得所需的半导体特征,优选地,应将载流子含量、杂质含量、缺陷密度、金属元素对氧的原子比、原子间距离、密度等设为适合的值。 In order to obtain desired semiconductor characteristics, preferably, the carrier should be streaming content, impurity content, defect density, metallic element of atomic ratio of oxygen, the interatomic distance, density and the like is set to an appropriate value.

[0144] 例如,可以在使用In-Sn-Zn基氧化物的情况中相对容易地获得高迀移率。 [0144] For example, relatively easy to obtain a high rate in the case of using the shift Gan In-Sn-Zn-based oxide. 但是,在使用In-Ga-Zn基氧化物的情况中还可以通过降低体积块中的缺陷密度来提高迀移率。 However, in the case of using a group In-Ga-Zn oxide can also be improved by reducing the rate of shift Gan defect density in the volume block.

[0145] 注意,例如,表述“包含原子比为In:Ga:Zn = a: b: c(a+b+c = 1)的In、Ga和Zn的氧化物成分接近于包含原子比为In:Ga:Zn = A: B: C(A+B+C = 1)的In、Ga和Zn的氧化物成分”表示a、b和c满足如下的关系:(aA)2+ (bB)2+ (cC)2彡r2并且r可以是例如0.05。 [0145] Note that, for example, the expression "containing an atomic ratio of In: Ga: Zn = a: b: c (a + b + c = 1) of In, Ga, and Zn oxide component comprises close to the atomic ratio of In : Ga: Zn = a: B: C (a + B + C = 1) of in, Ga, and Zn oxide component "indicates a, b and c satisfy the following relationship: (aA) 2+ (bB) 2 + (cC) 2 San r2 and r may be, for example, 0.05. 这同样适用于其他氧化物。 The same applies to other oxides.

[0146] 氧化物半导体可以是单晶体或非单晶体的。 [0146] the oxide semiconductor may be monocrystalline or non-monocrystalline. 在后一种情况中,氧化物半导体可以是非晶体或多晶体。 In the latter case, the oxide semiconductor may be amorphous or polycrystalline. 再者,该氧化物半导体还可以具有包含有结晶性的部分的非晶体结构或非非晶体结构。 Further, the oxide semiconductor may also have an amorphous structure or a crystal structure of the crystalline feifei portion comprises.

[0147] 在非晶态的氧化物半导体中,可以相对容易地获得平坦表面,以便在使用氧化物半导体制造晶体管时,能够减少界面散射,以及能够相对容易地获得相对较高的迀移率。 [0147] In the amorphous oxide semiconductor can be relatively easily obtained a flat surface, so that when a transistor is manufactured using an oxide semiconductor, interface scattering can be reduced, and can be relatively easily obtained a relatively high rate Gan shift.

[0148] 在具有结晶性的氧化物半导体中,体积块中的缺陷能进一步减少,并且在表面平坦度得到提高时,能够获得比非晶态中的氧化物半导体更高的迀移率。 [0148] In an oxide semiconductor having crystallinity, the volume of the defect blocks can be further reduced, and when the surface flatness is improved, can be higher than in the amorphous oxide semiconductor Gan shift rate. 为了提高表面平坦度,优选地在平坦表面上形成氧化物半导体。 In order to improve the flatness of the surface, preferably an oxide semiconductor is formed on a flat surface. 具体来说,优选地在平均表面粗造度(&)小于或等于I nm,优选地小于或等于0.3 nm的表面上形成该氧化物半导体。 Specifically, it is preferably made in surface average roughness (& amp;) is less than or equal to I nm, preferably less than or equal to that of the oxide semiconductor is formed on the surface of 0.3 nm.

[0149] 注意,平均表面粗造度0?a)是通过将JIS B 0601定义的中心线平均粗造度延展到三维中以便能够将其应用于表面而获得的。 [0149] Note that the average surface roughness 0? A) is defined in JIS B 0601 by the extension of the center line average roughness in a three-dimensional surface to be able to apply obtained. 可以表示为“从参考表面到指定的表面的偏移量的绝对值的平均值”,是由如下的公式(1)定义的。 May be expressed as "an average value of the absolute value of the offset from the reference surface to a specified surface" and is (1) defined by the following formulas.

[0150] [公式1] [0150] [Equation 1]

[0151] i II Ί; f(¾,: 1?:> _ [0151] i II Ί; f (¾ ,: 1:> _?

[0152] 在上面的公式中,So表示要测量的平面的面积(由坐标(XI,yi)、(XI,_F2)、(X2, 3α)和(《,72)表示的四个点定义的四角形区域),Zo表示要测量的平面的平均高度丄可以使用原子力显微镜(AFM)来测量。 [0152] In the above formula, So represents an area of ​​the plane to be measured (by the coordinates (XI, yi), (XI, _F2), (X2, 3α) and ( ", 72) is defined by four points quadrangular region), Zo represents the average height to be measured can be Shang plane using an atomic force microscope (AFM) was measured.

[0153] 此处,将描述CAAC-〇S(c-轴对齐的晶体氧化物半导体)薄膜,这是氧化物半导体的晶体结构的实施例。 [0153] Here, description will be CAAC-〇S (the C-axis-aligned crystalline oxide semiconductor) film, which is an embodiment of the crystal structure of the oxide semiconductor.

[0154] CAAC-OS薄膜不是完全单晶体的,也不是完全非晶体的。 [0154] CAAC-OS film is not completely single crystal nor completely amorphous. CAAC-OS薄膜是具有晶体- 非晶体混合相结构的氧化物半导体薄膜,其中在非晶体相中包含晶体部分和非晶体部分。 CAAC-OS film is a crystalline - amorphous oxide semiconductor thin film of a mixed phase structure, which comprises a crystal phase and an amorphous portion in the amorphous portion. 注意在大多数情况中,晶体部分镶在其一边小于100 nm的立方体内。 Note that in most cases, a cubic crystal portions in which the insert side of less than 100 nm. 根据利用透射电子显微镜(TEM)获得的观察图像,CAAC-OS薄膜中非晶体部分与晶体部分之间的边界并不明显。 The observation image by a transmission electron microscope (TEM) is obtained, the boundary between the crystalline portion and the crystalline portion of the film is not obvious CAAC-OS Africa. 再者,利用TEM,未发现CAAC-OS中的颗粒边界。 Further, by using the TEM, grain boundary is not found in the CAAC-OS. 因此,在CAAC-OS薄膜中,抑制了由于颗粒边界所致的电子迀移率的降低。 Thus, the CAAC-OS film, the grain boundary is suppressed due to the reduction caused by the electron shift Gan rate.

[0155] 在CAAC-OS薄膜中包含的每个晶体部分中,c轴沿着与其上形成CAAC-OS薄膜的表面的法线矢量或CAAC-OS薄膜的上表面的法向矢量平行的方向对齐,形成从垂直于ab平面的方向观看到的三角形或六角形原子排列,并且当从与c轴垂直的方向观看时,金属原子以分层方式排列或金属原子和氧原子以分层方式排列。 [0155] Each crystal portion included in the CAAC-OS film, c is the axis along the upper surface thereof on which the normal vectors of the film or CAAC-OS CAAC-OS film surface normal is aligned parallel to the direction vector formed viewed from a direction perpendicular to the ab plane of a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, are arranged in a layered metal atoms or metal atoms and oxygen atoms arranged in a hierarchical manner. 注意,在晶体部分之间,一个晶体部分的a轴和b轴的方向可能与另一个晶体部分的a轴和b轴的方向不同。 Note that, among crystal portions, a direction of the a-axis and b-axis of the crystal portion may be different from the a-axis direction and the other portion of the crystal b-axis. 在本说明书中,简单术语“垂直”包括从85°至95°的范围。 In the present specification, the simple term "perpendicular" includes a range from 85 ° to 95 °. 此外,简单术语“平行”包括从-5°至5°的范围。 Further, the simple term "parallel" includes a range from -5 ° to 5 °.

[0156] 在CAAC-OS薄膜中,晶体部分的分布不一定是均匀的。 [0156] In the CAAC-OS film, distribution of crystal portions is not necessarily uniform. 例如,在晶体生长从氧化物半导体薄膜的表面侧进行的情况中,氧化物半导体层的上表面附近中晶体部分的比例高于一些情况中其上形成氧化物半导体层的表面附近中晶体部分的比例。 For example, in the case of the crystal growth proceeds from the surface side of the oxide semiconductor thin film, the proportion of crystals in the vicinity of the upper surface portion of the oxide semiconductor layer is higher than that near the surface of the oxide semiconductor layer is formed in some cases in the crystalline portion thereof proportion. 再者,当向CAAC-OS薄膜添加杂质等时,一些情况中,晶体部分变为非晶体。 Further, when an impurity is added to the CAAC-OS like film, in some cases, part of the crystal becomes amorphous.

[0157] 因为CAAC-OS薄膜中包含的晶体部分的c轴沿着与其上形成CAAC-OS薄膜的表面的法线矢量或CAAC-OS薄膜的上表面的法向矢量平行的方向对齐,所以具体根据CAAC-OS薄膜的形状(形成CAAC-OS薄膜所在的表面的横截面形状或CAAC-OS薄膜的表面的横截面形状), 这些c轴的方向可能彼此不同。 [0157] aligned parallel to the direction vector c axis of the crystal portion as CAAC-OS film contained along the upper surface thereof on which the normal vector or CAAC-OS film surface CAAC-OS film method, particularly so (cross-sectional shape or cross-sectional surface of the CAAC-OS film forming surface CAAC-OS film resides) CAAC-OS depending on the shape of the film, the c-axis direction which may be different from each other. 晶体部分是通过薄膜形成或执行晶体化的处理,如薄膜形成之后热处理而形成。 Crystal part is formed by a thin film process or perform crystallization, and heat treatment after forming the thin film is formed.

[0158] 利用CAAC-OS薄膜,可以减少因可见光或紫外线光照射而导致晶体管的电特征的变化。 [0158] With the CAAC-OS film, can reduce variation due to irradiation with visible light or ultraviolet light caused by the electrical characteristics of the transistor. 由此,能够形成具有高可靠性的晶体管。 Accordingly, a transistor can be formed with high reliability.

[0159] 接下来,将参考图7A至7E、图8A至8C和图9A至9C详细地描述CAAC-OS薄膜的晶体结构。 [0159] Next, with reference to FIGS. 7A to 7E, 8A to 8C and 9A to 9C CAAC-OS film described detail crystal structure. 在图7A至7E、图8A至8C和图9A至9C中,垂直方向对应于c轴方向,以及与c轴方向垂直的平面对应于ab平面。 In FIGS. 7A to 7E, 8A to 8C and 9A to 9C, the vertical direction corresponds to the c-axis direction, and a plane perpendicular to the c-axis direction corresponds to the ab plane.

[0160] 在本实施例中,表述“上半部”和“下半部”分别是指ab平面上方的上半部和ab平面下方的下半部。 [0160] In the present embodiment, the expressions "upper half" and "bottom half" refer to the lower half of the upper half of the ab plane above and below the ab plane. 而且,在图7A至7E中,圆围绕的0表示四配位0和双圆表示三配位0。 Further, in FIG. 7A to 7E, 0 represents a circle around the four-coordinate 0 and the double circle represents a tridentate 0.

[0161] 图7A图示包含一个六配位In原子和邻接In原子的六个四配位氧(下文称为四配位0)原子的结构A。 [0161] FIG 7A illustrates comprises a hexacoordinate In atom adjacent to an In atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate 0) of the atomic structure of A. 此处,包含一个金属原子和与之邻接的多个氧原子的结构称为小基团。 Here, containing a metal atom and an oxygen atom adjacent thereto a plurality of structures called small group. 结构A实际是八面体结构,出于简明的目的,图示为平面结构。 A structure is actually an octahedral structure, for simplicity purposes, illustrated as a planar structure. 注意,结构A的上半部和下半部的每个一半部分中各存在三个四配位0原子。 Note that each half of the upper and lower halves of the structure A is present in each of the three tetracoordinate 0 atoms. 在结构A的小基团中,电荷是0。 A small group of the structure, the charge is zero.

[0162] 图7B图示包含一个五配位Ga原子、邻接Ga原子的三个三配位氧(下文称为三配位0)原子和邻接Ga原子的两个四配位0原子的结构B。 [0162] FIG 7B illustrates a pentacoordinate comprising Ga atom, three adjacent three coordinate oxygen Ga atoms (hereinafter referred to as tridentate 0) and two adjacent atoms of Ga atoms four coordinating atoms of the structure B 0 . 所有三配位0原子于ab平面上。 All three coordinating atoms 0 on the ab plane. 结构B的上半部和下半部的每个一半部分中各存在一个四配位〇原子。 Each half of the upper and lower halves of the structure B in the presence of a tetracoordinate each billion atoms. In原子也可以具有结构B,因为In原子可以具有五个配位体。 In atom may have a structure B, and since the In atom can have five ligands. 在结构B的小基团中,电荷是0。 In a small group of structure B, the charge is zero.

[0163] 图7C图示包含一个四配位Zn原子和邻接Zn原子的四个四配位0原子的结构C。 [0163] FIG. 7C illustrates comprising a tetracoordinate structure Zn atom and four tetracoordinate Zn atom adjacent 0 atoms C. 在结构C中,上半部中存在一个四配位0原子以及下半部存在三个四配位0原子。 In the structure C in the presence of the upper half there are three tetracoordinate atom a tetracoordinate 0 0 atoms and a lower half. 作为备选,在结构C中,上半部中可以存在三个四配位0原子以及下半部可以存在一个四配位0原子。 Alternatively, in the structure C, the upper half may be three tetracoordinate 0 atoms and may be present in the lower half of a tetracoordinate 0 atoms. 在结构C的小基团中,电荷是0。 In a small group of the structure C, the charge is zero.

[0164] 图7D图示包含一个六配位Sn原子和邻接Sn原子的六个四配位0原子的结构D。 Structure [0164] FIG 7D illustrates a hexacoordinate comprising Sn atom and Sn atom adjacent six tetracoordinate 0 atoms D. 在结构D中,上半部和下半部的每个一半部分中各存在三个四配位0原子。 In the D configuration, each half of the upper and lower halves of each present three tetracoordinate 0 atoms. 在结构D的小基团中, 电荷是+1。 In a small group structure D, the charge is +1.

[0165] 图7E图示包含两个Zn原子的结构E。 [0165] Figure 7E illustrates a structure containing two Zn atoms E. 在结构E中,上半部和下半部的每个一半部分中各存在一个四配位0原子。 In the E configuration, each half of the upper and lower halves of each present a tetracoordinate 0 atoms. 在结构E的小基团中,电荷是-1。 The group E in a small structure, the charge is -1.

[0166] 在本实施例中,多个小基团形成中等基团,以及多个中等基团形成大基团(也称为单位晶胞)。 [0166] embodiment, a plurality of small groups form a medium group, and a plurality of groups form a large middle group (also referred to as a unit cell) in the present embodiment.

[0167] 现在,将描述小基团之间的键合规则。 [0167] Now, description will be between the small groups bonded rules.

[0168] 图7A中相对于六配位In原子的上半部的三个0原子沿着向下方向各具有三个邻接的In原子,下半部中的三个0原子沿着向上方向各具有三个邻接的In原子。 In atom [0168] with respect to FIG. 7A half hexacoordination 0 In atom three atoms each having three adjoining in the downward direction, in the lower half of each three atoms in the upward direction 0 in three contiguous atom. 图7B中相对于五配位Ga原子的上半部的一个0原子沿着向下方向各具有一个邻接的Ga原子,下半部中的一个0原子沿着向上方向各具有一个邻接的Ga原子。 7B, the upper half with respect to the five-coordinated Ga atoms each having one 0 atom adjacent to a Ga atom in the downward direction, a lower half each having a 0 atom adjacent to the upward direction of the Ga atoms . 图7C中相对于四配位Zn原子的上半部的一个〇原子沿着向下方向具有一个邻接的Zn原子,下半部中的三个0原子沿着向上方向各具有三个邻接的Zn原子。 Atoms with respect to a square four-coordinated Zn atom upper half of FIG. 7C having a downward direction adjacent to a Zn atom, a lower half of the 0 atoms each having three three contiguous Zn upward direction atom.

[0169] 以此方式,金属原子上方的四配位0原子的数量等于邻接四配位0原子中每个四配位0原子且位于其下方的金属原子的数量。 [0169] In this manner, the number of above four coordinated metal atom adjacent 0 atoms is tetracoordinate 0 atoms in each of the four coordinating atoms and 0 the number of metal atoms located below it. 相似地,金属原子上方的四配位0原子的数量等于邻接四配位〇原子中每个四配位〇原子且位于其上方的金属原子的数量。 Similarly, the number of above four coordinated metal atom adjacent 0 atoms is tetracoordinate atom per billion square tetracoordinate atoms and the number of metal atoms located thereabove.

[0170] 因为四配位0原子的配位数量是4,所以邻接该0原子且位于其下方的金属原子的数量与邻接该〇原子且位于其上方的金属原子的数量之和是4。 [0170] Since the number of coordinating atoms and four-coordinate 0 is 4, the number of the adjacent 0 atoms and metal atoms located below and adjacent to the square of the number of atoms and lies above the metal atom is 4.

[0171] 相应地,当金属原子上方的四配位0原子的数量与另一个金属原子下方的四配位0 原子的数量之和是4时,包含这些金属原子的两个类型的小基团能够被键合。 [0171] Accordingly, when the number of the number four coordinated metal atom is above 0 atoms and the other below the four-coordinated metal atom, and 0 atom is 4, comprising two types of these metal atoms is small group It can be bonded.

[0172] 例如,在下半部中通过三个四配位0原子键合六配位金属(In或Sn)原子的情况中, 将其键合到五配位金属(Ga或In)原子或四配位金属(Zn)原子。 [0172] For example, in the lower half through three tetracoordinate 0 atoms bonded to a metal case hexacoordinate (In or Sn) atom, which is bonded to the five-coordinate metal (Ga or In) atom or tetrakis coordinating metal (Zn) atoms.

[0173] 沿着c轴方向,通过四配位0原子将配位数量是4、5或6的金属原子键合到另一个金属原子。 [0173] along the c-axis direction, by a tetracoordinate 0 the number of coordinating atoms is 4, 5 or 6 metal atom is bonded to another metal atom. 除了上文以外,可以通过将多个小基团组合以使分层结构的总电荷是0来以不同的方式形成中等基团。 In addition to the above, it can be prepared by a combination of a plurality of small groups so that the total charge of the hierarchical structure is formed Average 0 groups in a different manner.

[0174] 图8A图示In-Sn-Zn-O基材料中包含的中等基团A的模型。 [0174] FIG. 8A illustrates a model of In-Sn-Zn-O-based material contained in the group A medium. 图8B图示包含三个中等基团的大基团B。 8B illustrates three medium containing a large group of group B.

[0175] 注意,图8C图示从c轴方向观察图8B中的分层结构的情况中的原子排列。 [0175] Note that FIG. 8C illustrates observe the atomic arrangement of the hierarchical structure in FIG. 8B in the c-axis direction.

[0176] 在中等基团A中,省略三配位0原子,并以圆图示四配位0原子;圆中的数字示出四配位0原子的数量。 [0176] In group A in the middle, three coordinate 0 atoms are omitted, and a circle shown tetracoordinate 0 atoms; the number in the circle indicates the number of tetracoordinate 0 atoms. 例如,圆圈住的3表示各存在于相对于Sn原子的上半部和下半部的每个一半部分中的三个四配位〇原子。 For example, each circle indicates the presence of live 3 with respect to the three tetracoordinate half portion of each Sn atom and lower halves of the square atoms. 相似地,在中等基团A中,圆圈住的1表示各存在于相对于In原子的上半部和下半部的每个一半部分中的一个四配位0原子。 Similarly, the group A in the middle, a circle indicates a live present in each ligand relative to each half of a four-section on In atom and lower halves of the 0 atoms.

[0177] 中等基团A还图示在下半部中邻接一个四配位0原子以及在上半部中邻接三个四配位0原子的Zn原子,和在上半部中邻接一个四配位0原子和在下半部中邻接三个四配位0 原子的Zn原子。 [0177] A further group of medium illustrated adjacent a tetracoordinate 0 atoms in the lower half a Zn atom and the adjacent three tetracoordinate 0 atoms in the upper half, and a tetracoordinate adjacent in upper half 0 atom and the adjacent three tetracoordinate 0 atoms in the lower half of the Zn atom.

[0178] 在In-Sn-Zn-O基材料的分层结构中包含的中等基团A中,按从顶部起的顺序,上半部和下半部中每一半部分中邻接三个四配位〇原子的Sn原子通过四配位0原子键合到在上半部和下半部中每一半部分中邻接一个四配位0原子的In原子。 [0178] A medium included in the group hierarchy In-Sn-Zn-O-based material in order from the top, the upper and lower halves each half portion adjacent to three tetracoordinate bit square Sn atom by atom tetracoordinate 0 atom is bonded to adjacent atoms in a tetracoordinate 0 atoms in each half portion of the upper and lower halves. 注意,在Sn原子与In原子之间的总共4个四配位0原子(由圆圈住的1和3示出)中,一个四配位0原子被Sn原子和In原子共有。 Note that, in a total of four tetracoordinate 0 atoms (live by circles 1 and 3 show) between Sn and In atoms atom, a tetracoordinate 0 atoms and Sn atoms are shared In atoms. 这同样适用于其他金属-氧-金属键合。 The same applies to other metal - oxide - metal bonding.

[0179] 通过一个四配位0原子将In原子键合到在上半部中邻接三个四配位0原子的Zn原子。 [0179] By a tetracoordinate 0 atoms of In atom is bonded to three contiguous Zn atoms is tetracoordinate 0 atoms in the upper half. Zn原子通过相对于Zn原子的下半部中的一个四配位0原子键合到在上半部和下半部中每一半部分中邻接三个四配位〇原子的In原子。 By Zn atoms relative to the lower half of a tetracoordinate Zn atoms in the 0 atom is bonded to three atoms adjacent In tetracoordinate atoms per square half portion of the upper and lower halves. 通过一个四配位0原子,In原子键合到包含两个Zn原子的小基团,并邻接上半部中的一个四配位0原子。 By a tetracoordinate 0 atoms, In atoms bonded to a group containing the small two Zn atoms, and abuts on a tetracoordinate 0 atoms halves.

[0180] 此含Zn的小基团通过相对于该小基团的下半部中的一个四配位0原子键合到在上半部和下半部中每一半部分中邻接三个四配位〇原子的Sn原子。 [0180] This small group containing Zn by a tetracoordinate relative to the lower half of the small group of 0 atom is bonded to each of the halves of the upper and lower halves abut three tetracoordinate billion bits atoms Sn atom. 键合多个此类中等基团,从而形成大基团。 Bonding a plurality of groups of such medium, to form a large group. 此处,三配位〇原子的电荷和四配位〇原子的一个键的电荷可以分别假定为-0.667和-0.5。 Here, the charge tridentate billion atoms and atoms tetracoordinate charge a square key can be assumed -0.667 and -0.5, respectively.

[0181] 例如,(六配位或五配位)In原子的电荷、(四配位)Zn原子的电荷和(五配位或六配位)Sn原子的电荷分别是+3、+2和+4。 [0181] For example, (hexacoordinated or five ligands) charge In atom, (tetracoordinate) charge of Zn atoms, and (e coordinated or hexa-coordinated) charge Sn atom are +3, +2, and +4. 相应地,含Sn原子的小基团中的电荷是+1。 Accordingly, a small group of atoms containing Sn +1 charge. 因此,需要抵销+1的-1电荷来形成含Sn原子的分层结构。 Accordingly, it is necessary to offset the charge of +1 -1 form a layered structure containing a Sn atom.

[0182] 与具有-1电荷的结构一样,可以提供如结构E中所示的含两个Zn的小基团。 [0182] As with the structure having a charge of -1, it may be provided with two small group of Zn as shown in the E configuration. 例如, 利用含两个Zn原子的一个小基团,可以抵销含Sn原子的一个小基团的电荷,以使分层结构的总电荷可以为0。 For example, by using a small group containing two Zn atoms, a charge can be offset a small group-containing Sn atom, so that the total charge of the hierarchical structure may be zero.

[0183] 当重复大基团B时,可以获得In-Sn-Zn-O基晶体(In2SnZn3O8)。 [0183] When repeating a large group B, can be obtained In-Sn-Zn-O-based crystals (In2SnZn3O8).

[0184] 注意,所获得的In-Sn-Zn-O基晶体的分层结构可以表示为组成式,In2SnZn2〇7 (ZnO)ioCffl是0或自然数)。 [0184] Note that the layered structure of In-Sn-ZnO-based crystal obtained by the composition formula may be expressed as, In2SnZn2〇7 (ZnO) ioCffl is 0 or a natural number).

[0185] 这同样适用于使用In-Sn-Zn-O基材料以外的氧化物半导体的情况。 [0185] The same applies to the use of an oxide semiconductor other than the In-Sn-Zn-O-based material.

[0186] 例如,图9A图示In-Ga-Zn-O基材料的分层结构中包含的中等基团L的模型。 [0186] For example, L medium model group hierarchy 9A illustrates a In-Ga-Zn-O-based material contained.

[0187] 在In-Ga-Zn-O基材料的分层结构中包含的中等基团L中,按从顶部起的顺序,通过一个四配位〇原子,在上半部和下半部中每一半部分中邻接三个四配位〇原子的In原子键合到上半部中邻接一个四配位0原子的Zn原子。 [0187] Secondary groups contained in the hierarchy of In-Ga-Zn-O-based material L in the order from the top, through a tetracoordinate billion atoms, in the upper and lower halves three tetracoordinate adjacent atoms per square halves of in atom is bonded to a Zn atom adjacent to the upper half of a tetracoordinate 0 atoms.

[0188] Zn原子通过相对于Zn原子的下半部中的三个四配位0原子键合到在上半部和下半部中每一半部分中邻接一个四配位0原子的Ga原子。 [0188] with respect to a Zn atom by three tetracoordinate Zn atoms in the lower half of the 0 atom is bonded to each of the half portions adjacent a tetracoordinate 0 atoms, Ga atoms in the upper and lower halves. Ga原子通过相对于Ga原子的下半部中的一个四配位〇原子键合到在上半部和下半部中每一半部分中邻接三个四配位〇原子的In 原子。 With respect to Ga atom through a tetracoordinate Ga atoms in the lower half of the square adjacent In atom is bonded to three atoms tetracoordinate atoms per square half portion of the upper and lower halves. 键合多个此类中等基团,从而形成大基团。 Bonding a plurality of groups of such medium, to form a large group.

[0189] 图9B图示包含三个中等基团的大基团M。 [0189] FIG 9B illustrates a large group comprising three middle groups M.

[0190] 注意,图9C图示从c轴方向观察图9B中的分层结构的情况中的原子排列。 [0190] Note that FIG 9C illustrates the case of observation of an atomic arrangement in the hierarchy of FIG. 9B from the c-axis direction. 此处,因为(六配位或五配位)In原子的电荷、(四配位)Zn原子的电荷和(五配位)Ga原子的电荷分别是+3、+2和+3,所以含有In原子、Zn原子和Ga原子中任一个的小基团的电荷是0。 Here, since (five or six-coordinated ligand) charge of In atom, (tetracoordinate) and a charge of Zn atoms (pentacoordinate) charge Ga atoms are +3, +2 and +3, thus comprising in atom, a Zn atom and the charge of any one of a small group of Ga atoms is 0.

[0191] 因此,具有此类小基团的组合的中等基团的总电荷总是为0。 Average total charge group [0191] Thus, compositions having such small groups is always 0. 为了形成In-Ga-Zn-O 基材料的分层结构,可以不仅使用中等基团L而且使用其中In原子、Ga原子和Zn原子的排列不同于中等基团L的排列的中等基团来形成大基团。 In order to form a layered structure In-Ga-Zn-O-based material, not only with medium wherein group L and the use of the arrangement of In atoms, Ga atoms, and Zn atoms is different from the group L medium arranged to form a middle group bulky groups.

[0192] 当重复图9B所示的大基团时,可以获得In-Ga-Zn基氧化物的晶体。 [0192] When a large group represented by FIG. 9B is repeated, the crystal can be obtained In-Ga-Zn-based oxide. 注意,所获得的In-Ga-Zn基氧化物的分层结构可以表示为组成式,InGa〇3 (ZnO) η (η是自然数)。 Note that the layered structure based In-Ga-Zn oxide can be obtained as a composition represented by the formula, InGa〇3 (ZnO) η (η is a natural number). 例如,在η = I (InGaZnO4)的情况中,可以获得图IOA所示的晶体结构。 For example, in the case η = I (InGaZnO4), the crystal structure can be obtained as shown in FIG IOA. 注意在图IOA中的晶体结构中,因为Ga原子和In原子各具有如图7B所示的5个配位体,所以可以用In来替代Ga。 Note that in FIG IOA in the crystal structure, since the In atoms and Ga atoms each have five ligands shown in Figure 7B, it is possible to use Ga instead of In.

[0193] 例如,在Ώ = 2(InGaZn2〇5)的情况中,可以获得图IOB所示的晶体结构。 [0193] For example, in the case Ώ = 2 (InGaZn2〇5), the crystal structure can be obtained as shown in FIG. IOB. 注意在图IOB中的晶体结构中,因为Ga原子和In原子各具有如图7B描述的5个配位体,所以可以用In 来替代Ga。 Note that in FIG IOB crystal structure, since the In atoms and Ga atoms each having 5 ligands described in Figure 7B, it is possible to use Ga instead of In.

[0194] 在使用In-Zn-O基材料作为氧化物半导体的情况中,其原子比是In/Zn = 0.5至50,优选地,In/Zn = 1至20,更为优选地,In/Zn = 1.5至15。 [0194] In the case of In-Zn-O-based material as an oxide semiconductor, an atomic ratio In / Zn = 0.5 to 50, preferably, In / Zn = 1 to 20, more preferably, In / Zn = 1.5 to 15. The 当Zn的原子比处于上面优选的范围中时,能够提高上述半导体元件的场效应迀移率。 When the atomic ratio of Zn in the range of the above preferred embodiment, the semiconductor element can be improved field effect Gan shift rate. 此处,当化合物的原子比是I η: Zn: 0 = X:r:Z,满足关系1.5Χ+Γ。 Here, when the atomic ratio of the compound I η: Zn: 0 = X: r: Z, satisfy the relationship 1.5Χ + Γ.

[0195] 注意,优选地,通过减少作为电子施主的杂质(如水份和氢气)来纯化氧化物半导体。 [0195] Note that, preferably, by reducing an impurity as an electron donor (e.g., water and hydrogen) to afford the oxide semiconductor. 具体来说,通过二次离子质谱(SMS)测量的纯化的氧化物半导体中氢的含量是5X IO19 个/cm3或更低,优选为5 X IO18个/cm3或更低,进一步优选为5 X IO17个/cm3或更低,再进一步优选为IX 1〇16个/cm3或更低。 Specifically, by secondary ion mass spectrometry (SMS) content in the purified hydrogen in the oxide semiconductor is measured in a 5X IO19 / cm3 or less, more preferably 5 X IO18 / cm3 or less, more preferably 5 X a IO17 / cm3 or less, still further preferably a 1〇16 IX / cm3 or less. 通过霍尔效应测量测得的该氧化物半导体层的载流子密度小于IX IO14个/cm3,优选为IX IO12个/cm3,进一步优选为IX IO11个/cm3。 Measured by Hall effect measurement of the carrier density of the oxide semiconductor layer is less than a IX IO14 / cm3, more preferably IX IO12 / cm3, more preferably IX IO11 number / cm3.

[0196] 此处,描述该氧化物半导体层中的氢含量分析。 [0196] Here, the hydrogen content of the analysis described in the oxide semiconductor layer. 半导体层的氢含量通过SIMS来测量。 The hydrogen content of the semiconductor layer is measured by SIMS. 众所周知的,理论上要通过SMS分析在使用不同材料形成的叠层之间的样本表面附近或界面的附近获取正确数据是困难的。 Is well known, to analyze theoretically or nearby the interface between the surface of the sample using the laminate of different materials is difficult to obtain the correct data by SMS. 因此,在通过SMS分析氢含量沿着厚度方向在层中的分布的情况中,采用其中值没有很大改变且基本恒定的层区域中的平均值作为氢含量。 Thus, in the case of analyzing the distribution of hydrogen content in the thickness direction in the layer by SMS, the average value is not a great change layer region substantially constant value and wherein as the hydrogen content. 再者,在层的厚度小的情况中,由于相邻层的氢含量的影响,在一些情况中无法找到获取几乎恒定值的区域。 Further, in the case where the small thickness of the layer due to the influence of hydrogen content of the adjacent layers, in some cases can not be found in the region acquiring an almost constant value. 在该情况中,采用氢含量的最大值或最小值作为该层的氢含量。 In this case, the use of hydrogen content as a maximum or minimum value of the hydrogen content of the layer. 而且,在层的区域中不存在最大值或最小值的情况中,采用拐点处的值作为氢含量。 Further, there is no case where the area of ​​the layer of the maximum or minimum value, the value at the inflection point as the hydrogen content.

[0197] 除了靶中的氢含量外,在通过溅射形成氧化物半导体层时,重要的是尽可能地减少溅射室内的水和氢。 [0197] In addition to the hydrogen content in the target, when the oxide semiconductor layer is formed by sputtering, it is important to reduce as much as possible the water and hydrogen sputtering chamber. 具体来说,下面方法是有效的:在沉积之前烘干溅射室的内部;减少溅射室中引入的气体中的水和氢含量;以及防止排气系统中排出的室内的气体回流。 Specifically, the following method is effective: drying before deposition inside of the deposition chamber; and reduce the water content of the hydrogen gas introduced into the sputtering chamber; and preventing backflow of gas discharged from the exhaust system of the chamber.

[0198] 优选地在氧气气氛中通过溅射形成氧化物半导体层。 [0198] Preferably, the oxide semiconductor layer is formed by sputtering in an oxygen atmosphere. 此时,衬底加热温度设为高于或等于100 °C且低于或等于600 °C,优选地高于或等于150 °C且低于或等于550 °C,进一步优选地高于或等于200 °C且低于或等于500 °C。 In this case, the substrate heating temperature is higher than or equal to 100 ° C and lower than or equal to 600 ° C, preferably higher than or equal to 150 ° C and lower than or equal to 550 ° C, more preferably higher than or equal to 200 ° C and lower than or equal to 500 ° C. 氧化物半导体层的厚度大于或等于1 nm且小于或等于40 nm,优选地大于或等于3 nm且小于或等于20 nm。 The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 40 nm, preferably greater than or equal to 3 nm and less than or equal to 20 nm. 获得的氧化物半导体层中的杂质含量随着薄膜形成中衬底加热温度的提高而降低。 Impurity content of the oxide semiconductor layer is obtained with the increase in the substrate heating temperature in film formation is reduced. 再者,氧化物半导体层中的原子排列是顺序的,且其密度被增加,从而可能形成多晶体或CAAC。 Further, the atomic arrangement in the oxide semiconductor layer is sequential, and the density is increased, which may form a polycrystalline or CAAC. 在没有稀有气体而使用氧气气氛时,氧化物半导体层中不包含如稀有气体原子的非必要原子,从而可能形成多晶体或CAAC。 In the absence of a rare gas and oxygen gas atmosphere, the oxide semiconductor layer not comprising the noble gas atoms optionally atoms, which may form a polycrystalline or CAAC. 注意可以使用包含氧气和稀有气体的混合气体气氛。 Note that you can use a mixed gas atmosphere containing oxygen gas and a rare gas. 在该情况中,氧气的百分比高于或等于30 vol.%,优选地高于或等于50 vol.%,进一步优选地高于或等于80 vol.%。 In this case, the percentage of oxygen is greater than or equal to 30 vol.%, Preferably higher than or equal to 50 vol.%, More preferably higher than or equal to 80 vol.%. 注意,随着氧化物半导体层越薄,晶体管的短沟道效应降低。 Note that as the oxide semiconductor layer is thinner, reducing the short channel effect transistor. 但是,当氧化物半导体层太薄时, 界面散射增强;因此,可能降低场效应迀移率。 However, when the oxide semiconductor layer is too thin, the interface scattering enhancement; therefore, possible to reduce the shift of the field effect Gan.

[0199] 在通过溅射方法将In-Ga-Zn-O基材料层形成为氧化物半导体层的情况中,优选地使用具有如下原子比的In-Ga-Zn-O靶:In:Ga:Zn的原子比是1:1:1、4:2:3、3:1:2、1:1:2、2: 1:3或3:1:4。 [0199] In the case where the In-Ga-Zn-O-based material layer formed by a sputtering method as the oxide semiconductor layer, preferably having the following atomic In-Ga-Zn-O target ratio: In: Ga: Zn atomic ratio is 1: 1: 1,4: 2: 3,3: 1: 2,1: 1: 2,2: 1: 3 or 3: 1: 4. 当使用具有前文提到的原子比的In-Ga-Zn-O靶来形成氧化物半导体薄膜时, 容易地形成多晶体层或CAAC-OS层。 When the oxide semiconductor thin film formed using the In-Ga-Zn-O target having an atomic ratio mentioned hereinbefore, the polycrystalline layer or CAAC-OS layer is easily formed.

[0200] 在通过溅射方法将In-Sn-Zn-O基材料层形成为氧化物半导体层的情况中,优选地使用具有如下原子比的In-Sn-Zn-O革El: In:Sn:Zn的原子比是1:1:1、4:2:3、3:1:2、1:1:2、3: 1:4、2:1:3、1:2: 2或20:45: 35。 [0200] In the case where the In-Sn-Zn-O-based material layer formed by a sputtering method as the oxide semiconductor layer, preferably having In-Sn-Zn-O atomic ratio of the gram El follows: In: Sn : Zn atomic ratio is 1: 1: 1,4: 2: 3,3: 1: 2,1: 1: 2,3: 1: 4,2: 1: 3,1: 2: 2 or 20: 45: 35. 当使用具有前文提到的原子比的In-Sn-Zn-O靶来形成氧化物半导体薄膜时,容易地形成多晶体层或CAAC-OS层。 When the oxide semiconductor thin film formed using the In-Sn-Zn-O target having an atomic ratio mentioned hereinbefore, the polycrystalline layer or CAAC-OS layer is easily formed.

[0201] 接下来,执行热处理。 [0201] Next, heat treatment is performed. 热处理在减压气氛中、惰性气体气氛中或氧化气氛中执行。 A heat treatment in a reduced pressure atmosphere, an inert gas atmosphere or in an oxidation atmosphere. 通过热处理,可以减少氧化物半导体层中的杂质含量。 By heat treatment, can reduce the impurity content of the oxide semiconductor layer.

[0202] 热处理优选地以这样的方式来执行:在减压气氛或惰性气体气氛中执行热处理之后,保持温度不变将气氛切换到氧化气氛,并进一步执行热处理。 [0202] heat treatment is preferably performed in such a manner that: after the heat treatment is performed in a reduced pressure atmosphere or an inert gas atmosphere, keeping the temperature constant switching the atmosphere to an oxidative atmosphere and further heat treatment is performed. 在减压气氛中或惰性气体气氛中执行热处理时,能够减少氧化物半导体层中的杂质含量;但是,同时导致氧空位。 Reduced-pressure atmosphere or an inert gas atmosphere during heat treatment is performed, it is possible to reduce the impurity content of the oxide semiconductor layer; however, while causing the oxygen vacancies. 通过在氧化气氛中的热处理,能够减少所导致的氧空位。 By heat treatment in an oxidizing atmosphere, reducing the oxygen vacancies can be caused.

[0203] 通过除了在薄膜形成时加热衬底外对氧化物半导体层执行热处理,能够显著地降低薄膜中的杂质水平。 [0203] In addition to heating the substrate by a thin film is formed at the outer heat treatment is performed on the oxide semiconductor layer can be significantly reduced impurity levels in the film. 由此,能够增加晶体管的场效应迀移率,以接近稍后要描述的理想场效应迀移率。 Accordingly, it is possible to increase the rate of shift of the field effect transistor Gan, Gan to close over the FET to be described later shift rate.

[0204] 〈在氧化物半导体层中形成沟道的晶体管〉 [0204] <channel transistors are formed in the oxide semiconductor layer>

[0205] 将参考图16A至图16D描述在氧化物半导体层中形成沟道的晶体管。 [0205] with reference to FIGS. 16A to 16D described channel transistors are formed in the oxide semiconductor layer. 图16A至图16D 是分别图示晶体管的结构的示例的横截面示意图。 16A to 16D are cross-sectional schematic view illustrating an example of a configuration of each transistor.

[0206] 图16A中所示的晶体管包括导电层601 (a)、绝缘层602 (a)、氧化物半导体层603 (a)、导电层605a (a)、导电层605b (a)和绝缘层606 (a)。 Transistor shown in [0206] FIG 16A includes a conductive layer 601 (a), an insulating layer 602 (a), the oxide semiconductor layer 603 (a), the conductive layer 605a (a), the conductive layer 605b (a) and the insulating layer 606 (a).

[0207] 导电层601 (a)在元件形成层600 (a)上设置。 [0207] conductive layer 601 (a) is formed is provided on the layer 600 (a) in the element. 在元件形成层600 (a)中嵌入嵌入式绝缘体612a (a)和嵌入式绝缘体612b (a)。 Is formed in the element layer 600 (a) embedded in the embedded insulator 612a (a) and embedded insulator 612b (a).

[0208] 绝缘层602 (a)在导电层601 (a)下设置。 [0208] insulating layer 602 (a) disposed on lower conductive layer 601 (a).

[0209] 氧化物半导体层603 (a)与导电层601 (a)叠加,其间设置绝缘层602(a)。 [0209] the oxide semiconductor layer 603 (a) and the conductive layer 601 (a) is superimposed, an insulating layer therebetween 602 (a). 氧化物半导体层603 (a)包括区域604a (a)和区域604b (a)。 The oxide semiconductor layer 603 (a) includes a region 604a (a) and the region 604b (a). 区域604a (a)和区域604b (a)设成彼此隔开,并且是添加掺杂物的区域。 Region 604a (a) and the region 604b (a) arranged to be spaced apart from each other, and the region of dopant is added. 区域604a (a)和区域604b (a)之间的区域用作沟道形成区域。 Region 604a (a) and the region serves as a channel between the region 604b (a) forming region. 区域604a (a)与导电层605a (a)和绝缘层616a (a)叠加,以及604b (a)与导电层605b (a)和绝缘层616b (a)叠加。 Region 604a (a) and the conductive layer 605a (a) and an insulating layer 616a (a) superimposing and 604b (a) and the conductive layer 605b (a) and an insulating layer 616b (a) is superimposed.

[0210]导电层6〇5a (a)和导电层605b (a)与氧化物半导体层603 (a)叠加,并且电连接到氧化物层603 (a)。 [0210] 6〇5a conductive layer (a) and the conductive layer 605b (a) with the oxide semiconductor layer 603 (a) is superimposed, and electrically connected to the oxide layer 603 (a).

[0211] 绝缘层606 (a)在氧化物半导体层603 (a)、绝缘层602 (a)和导电层601 (a)上设置。 [0211] insulating layer 606 (a) in the oxide semiconductor layer 603 (a), an insulating layer 602 (a) and the conductive layer 601 (a) is provided on the.

[0212] 图16B中所示的晶体管包括导电层601 (b)、绝缘层602 (b)、氧化物半导体层603 ⑹、导电层605a (b)、导电层605b (b)和绝缘层606⑹。 Transistor shown in [0212] FIG 16B includes a conductive layer 601 (b), the insulating layer 602 (b), the oxide semiconductor layer 603 ⑹, the conductive layer 605a (b), the conductive layer 605b (b) and the insulating layer 606⑹.

[0213] 导电层601 (b)在元件形成层600⑹上设置。 [0213] conductive layer 601 (b) is provided on the layer formed in 600⑹ element. 嵌入式绝缘体612a⑹和嵌入式绝缘体612b⑹嵌在元件形成层600 (a)中。 612a⑹ insulator embedded and embedded member embedded in the insulator 612b⑹ formation layer 600 (a).

[0214] 绝缘层602⑹在导电层601⑹下设置。 [0214] insulating layer disposed on the lower conductive layer 602⑹ 601⑹.

[0215] 导电层605a (b)和导电层605b⑹各在氧化物半导体层603⑹上设置。 [0215] conductive layer 605a (b) and a conductive layer disposed on each of 605b⑹ the oxide semiconductor layer 603⑹. 氧化物半导体层603⑹包括区域604a⑹和区域604b⑹。 603⑹ region including the oxide semiconductor layer and a region 604a⑹ 604b⑹. 区域604a⑹和区域604b⑹设成彼此隔开, 并且是添加掺杂物的区域。 604a⑹ region and spaced from each other into an area 604b⑹, and adding a dopant region. 区域604a⑹和区域604b⑹之间的区域用作沟道形成区域。 604a⑹ region between the region and the channel formation region as 604b⑹. 区域604a⑹与导电层605a⑹叠加,以及604b⑹与导电层605b⑹叠加。 604a⑹ 605a⑹ region with the conductive layer is superimposed, and the conductive layer 605b⑹ 604b⑹ superimposed.

[0216] 氧化物半导体层603 (b)电连接到导电层605a⑹和导电层605b⑹。 [0216] the oxide semiconductor layer 603 (b) is electrically connected to the conductive layer and the conductive layer 605a⑹ 605b⑹. 氧化物半导体层603⑹与导电层601⑹叠加,其间设置绝缘层602 (b)。 The oxide semiconductor layer and the conductive layer 601⑹ 603⑹ superimposed, an insulating layer therebetween 602 (b).

[0217] 绝缘层606⑹在导电层601⑹上方设置。 [0217] insulating layer disposed over the conductive layer 606⑹ 601⑹.

[0218] 图16C中所示的晶体管包括导电层601 (c)、绝缘层602 (c)、氧化物半导体层603 (c)、导电层605a (c)和导电层605b (c)。 Transistor shown in [0218] FIG 16C includes a conductive layer 601 (c), an insulating layer 602 (c), the oxide semiconductor layer 603 (c), the conductive layer 605a (c) and the conductive layer 605b (c).

[0219] 氧化物半导体层603 (c)包括区域604a (c)和区域604b (c)。 [0219] the oxide semiconductor layer 603 (c) includes a region 604a (c) and region 604b (c). 区域604a (c)和区域604b (c)彼此隔开地来设置,并且是添加掺杂物的区域。 Region 604a (c) and region 604b (c) to be disposed apart from each other, and a region of dopant added. 区域604a (c)和区域604b (c)之间的区域用作沟道形成区域。 Region between the region (c) 604a (c) and region 604b serves as a channel formation region. 氧化物半导体层603 (c)在元件形成层600 (c)上设置。 The oxide semiconductor layer 603 (c) is provided on the formed layer 600 (c) in the element. 区域604a (c) 和区域604b (c)并不一定被设置。 Region 604a (c) and region 604b (c) is not necessarily provided.

[0220] 导电层605a (c)和导电层605b (c)在氧化物半导体层603 (c)上设置并与之电连接。 [0220] conductive layer 605a (c) and the conductive layer 605b (c) is provided on the oxide semiconductor layer 603 (c) and electrically connected thereto. 彼此面对的导电层605a (c)和导电层605b (c)的侧表面是逐渐缩小的形状。 Facing each other conductive layer 605a (c) and the conductive layer 605b (c) the side surfaces are tapered shape.

[0221] 导电层605a (c)叠加区域604a (c)的一部分;但是,本发明并不必然地局限于此结构。 [0221] portion of the conductive layer 605a (c) the overlapping area 604a (c); however, the present invention is not necessarily limited to this structure. 当导电层605a (c)叠加区域604a (c)的一部分时,导电层605a (c)与区域604a (c)之间的电阻可以是低的。 When the partial region 604a (c) a conductive layer 605a (c) superimposed, the resistance between the region 604a (c) a conductive layer 605a (c) and may be low. 作为备选,区域604a (c)可以全部地与导电层605a (c)叠加。 Alternatively, the region 604a (c) may all be superimposed with the conductive layer 605a (c).

[0222] 导电层605b (c)与区域604b (c)的一部分叠加;但是,本实施例并不局限于此。 [0222] conductive layer 605b (c) and a partial region 604b (c) superimposed; however, the present embodiment is not limited thereto. 当导电层605b (c)与区域604b (c)的一部分叠加时,导电层605b (c)与区域604b (c)之间的电阻可以是低的。 When a portion of the superimposed region 604b (c) a conductive layer 605b (c), the resistance between the conductive layer 605b (c) and region 604b (c) may be low. 作为备选,区域604b (c)可以全部地与导电层605b (c)叠加。 Alternatively, the region 604b (c) may all be superimposed with the conductive layer 605b (c).

[0223] 绝缘层602 (c)在氧化物半导体层603 (c)、导电层605a (c)和导电层605b (c)上设置。 [0223] insulating layer 602 (c) in the oxide semiconductor layer 603 (c), the conductive layer 605a (c) and the conductive layer 605b (c) is provided on the.

[0224] 导电层601 (c)与氧化物半导体层603 (c)叠加,其间设置绝缘层602 (c)。 [0224] conductive layer 601 (c) with the oxide semiconductor layer 603 (c) superimposed, an insulating layer disposed therebetween 602 (c). 氧化物半导体层603 (c)中与导电层601 (c)叠加的区域连同其间设置的绝缘层602 (c)用作沟道形成区域。 The oxide semiconductor layer 603 (c) with the conductive layer 601 (c) together with the superimposed region of the insulating layer 602 (c) is provided therebetween serves as a channel formation region.

[0225] 图16D中所示的晶体管包括导电层601 (d)、绝缘层602 (d)、氧化物半导体层603 ⑹、导电层605a⑹和导电层605b⑹。 Transistor shown in [0225] FIG 16D includes a conductive layer 601 (d), an insulating layer 602 (d), the oxide semiconductor layer 603 ⑹, the conductive layer and the conductive layer 605a⑹ 605b⑹.

[0226] 导电层605a (d)和导电层600b⑹在元件形成层600⑹上设置。 [0226] conductive layer 605a (d) and a conductive layer disposed on the layer formed 600b⑹ 600⑹ the element. 彼此面对的导电层605a⑹和导电层605b⑹的侧表面是逐渐缩小的形状。 Facing each other side surface of the conductive layer and the conductive layer 605b⑹ 605a⑹ is tapering shape.

[0227] 氧化物半导体层603 (d)包括区域604a (d)和区域604b (d)。 [0227] the oxide semiconductor layer 603 (d) includes a region 604a (d) and region 604b (d). 区域604a (d)和区域604b⑹彼此隔开地来设置,并且是添加掺杂物的区域。 Region 604a (d) spaced apart from one another and the regions 604b⑹ set, and is a region of dopant added. 区域604a⑹和区域604b⑹之间的区域用作沟道形成区域。 604a⑹ region between the region and the channel formation region as 604b⑹. 氧化物半导体层603 (d)在导电层605a (d)、导电层605b⑹和元件形成层600 (d)上方设置,并且电连接到导电层605a⑹和导电层605b⑹。 The oxide semiconductor layer 603 (d) in the conductive layer 605a (d), the conductive layer 605b⑹ and the element formation layer 600 (d) disposed above, and electrically connected to the conductive layer and the conductive layer 605a⑹ 605b⑹. 区域604a⑹和区域604b (d)并不一定被设置。 604a⑹ region and region 604b (d) is not necessarily provided.

[0228] 区域604a (d)电连接到导电层605a (d)。 [0228] region 604a (d) electrically connected to the conductive layer 605a (d).

[0229] 区域604b (d)电连接到导电层605b (d)。 [0229] region 604b (d) electrically connected to the conductive layer 605b (d).

[0230] 绝缘层602 (d)在氧化物半导体层603 (d)上设置。 [0230] insulating layer 602 (d) is provided on the oxide semiconductor layer 603 (d).

[0231] 导电层601 (d)与氧化物半导体层603⑹叠加,其间设置绝缘层602 (d)。 [0231] conductive layer 601 (d) and the oxide semiconductor layer 603⑹ superimposed, an insulating layer therebetween 602 (d). 氧化物半导体层603 (d)中与导电层601⑹叠加的区域连同设在其间的绝缘层602⑹用作沟道形成区域。 The oxide semiconductor layer 603 (d) in the region of the conductive layer superposed together 601⑹ 602⑹ insulating layer provided therebetween serves as a channel formation region.

[0232] 再者,描述图16A至图16D中所示的组件。 [0232] Further, components shown in FIGS. 16A to 16D described with FIG.

[0233] 例如,元件形成层600 (a)至600⑹可以是绝缘层,具有绝缘表面的衬底等。 [0233] For example, the element formation layer 600 (a) through 600⑹ may be an insulating layer having an insulating surface of a substrate and the like. 再者, 可以使用其上预先形成元件的层作为元件形成层600 (a)至60(Kd)。 Further, the layers of the element can be used to form a layer on which previously 600 (a) to 60 (Kd) is formed as an element.

[0234] 导电层601 (a)至601 (d)各作为晶体管的栅极来实现功能。 [0234] conductive layer 601 (a) through 601 (d) of each transistor is implemented as a gate function. 注意,作为晶体管的栅极来实现功能的层可以称为栅电极或栅接线。 Note that as the gate of the transistor to achieve the function layer may be referred to as a gate electrode or a gate wiring.

[0235] 对于导电层601 (a)至601⑹,例如使用如钼、镁、钛、铬、钽、钨、铝、铜、钕或钪的金属或包含任意这些金属材料作为主要组分的层是可能的。 [0235] For the conductive layer 601 (a) to 601⑹, for example, such as molybdenum, magnesium, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or a metal containing any of these materials as a main component are possible. 导电层601 (a)至601 (d)还可以通过将这些材料的层层叠而形成。 The conductive layer 601 (a) through 601 (d) can also be stacked layers formed of these materials.

[0236] 绝缘层602 (a)至602 (d)的每个绝缘层具有晶体管的栅绝缘层的功能。 [0236] insulating layer 602 (a) through 602 (d) each of the insulating layer has a function of a gate insulating layer of the transistor.

[0237] 每个绝缘层602 (a)至602 (d)可以是例如氧化硅层、氮化硅层、氧氮化硅层、氮化硅氧化硅层、氧化铝层、氮化铝层、氮氧化铝层、氮化铝氧化铝层、氧化铪层或氧化镧层。 [0237] Each of the insulating layer 602 (a) through 602 (d) may be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, aluminum oxynitride layer, an aluminum nitride, aluminum oxide layer, hafnium oxide layer or a lanthanum oxide layer. 绝缘层602 (a)至602⑹还可以通过将这些材料层叠而形成。 An insulating layer 602 (a) to 602⑹ also may be formed by laminating these materials.

[0238] 在前文提到的层中间,优选地使用包含属于13族的元素的那些层。 [0238] first mentioned intermediate layer, those layers are preferably used comprising an element belonging to Group 13. 使用包含13族元素的绝缘层促成绝缘层与氧化物半导体层之间的界面的优选状态。 An insulating layer comprising a Group 13 element contributes to the preferred state of the interface between the oxide semiconductor layer and the insulating layer.

[0239] 包含属于13族的元素的材料的其他示例包括,氧化镓、氧化镓铝和氧化铝镓。 Other examples [0239] material containing an element belonging to Group 13 include gallium oxide, gallium oxide, aluminum oxide and gallium aluminum. 注意,氧化铝镓是指其中按原子百分比计铝的量大于镓的量的物质,以及氧化镓铝是指按原子百分比计镓的量大于或等于铝的量的物质。 Note that, aluminum gallium oxide refers to the amount by which the atomic percentage of aluminum gallium material is greater than, and gallium aluminum oxide refers to gallium atomic percentage is greater than or equal to the amount of aluminum material. 可以使用富氧材料,如Al2OxOc = 3 + a,其中a大于0且小于l)、Ga2〇x (X = 3 + a,其中a大于0且小于1)或GaxAl2-x〇3+a(x大于0且小于2以及a大于O且小于1)表示的材料。 Enriched material may be used, such as Al2OxOc = 3 + a, where a is greater than 0 and less than L), Ga2〇x (X = 3 + a, where a is greater than 0 and less than 1), or GaxAl2-x〇3 + a (x greater than 0 and less than 2 and a material of greater than O and less than 1).

[0240] 作为绝缘层602 (a)至602⑹的叠层结构,表示包含具有不同成分的氧化镓的层叠的两个层。 [0240] As the insulating layer 602 (a) of the multilayer structure 602⑹, showing two stacked layers comprises gallium oxide having a different composition of. 作为备选,可以通过将包含Ga2Ox表示的氧化镓的绝缘层与包含Al2Ox的绝缘层层叠来形成绝缘层602 (a)至602 〇1)还可以通过将这些材料层叠而形成。 Alternatively, the insulating layer 602 (A) to 〇1 602) may be formed may also be formed by laminating these materials by an insulating layer containing gallium oxide represented Ga2Ox comprising Al2Ox insulating layer forming.

[0241] 例如,当晶体管的沟道长度是30 nm时,每个氧化物半导体层603 (a)至603⑹的厚度可以约为5 nm。 [0241] For example, when the channel length of the transistor is 30 nm, each of the oxide semiconductor layer 603 (a) to 603⑹ thickness may be about 5 nm. 在此情况中,如果氧化物半导体层603 (a)至603 (d)是CAAC氧化物半导体层,则能够抑制晶体管中的短沟道效应。 In this case, if the oxide semiconductor layer 603 (a) through 603 (d) is a CAAC oxide semiconductor layer, it is possible to suppress the short channel effect transistors.

[0242] 将掺杂η型或p型导电的掺杂物添加到区域604a (a)至604a (d)以及区域604b (a)至604b (d),这些区域各作为晶体管的源极或漏极来实现功能。 [0242] η doped or p-type dopant added to the conductive areas 604a (a) to 604a (d) and a region 604b (a) to 604b (d), each of these regions as a source or drain of the transistor pole to realize the function. 作为掺杂物,使用例如周期表中13族的一个或多个元素(例如,硼)、周期表中15族的一个或多个元素(例如,氮、磷和砷) 以及稀有气体的一个或多个元素(例如,氦、氩和氙)是可能的。 As the dopant, for example, using one or one or more elements of Group 13 in the periodic table (e.g., boron), a Group 15 of the periodic table or a plurality of elements (e.g., nitrogen, phosphorus and arsenic) and rare gas, a plurality of elements (e.g., helium, argon and xenon) are possible. 注意,作为晶体管的源极来实现功能的区域可以称为源区域,以及作为晶体管的漏极来实现功能的区域可以称为漏区域。 Note that as the source of the transistor region to achieve the function may be called a source region and a drain region of the transistor may be referred to implement the functions of the drain region. 将掺杂物添加到区域604a (a)至604a⑹和区域604b (a)至604b⑹减少了区域604a (a) 至604a⑹与区域604b (a)至604b⑹与导电层之间的接触电阻;相应地,能够缩减晶体管的尺寸。 The dopant is added to the region 604a (a) and to 604a⑹ region 604b (a) to reduce the contact resistance between 604b⑹ region 604a (a) to 604a⑹ region 604b (a) to the conductive layer 604b⑹; accordingly, possible to reduce the size of transistors.

[0243] 导电层605a (a)至605a⑹和导电层605b (a)和605b (d)各作为晶体管的源电极或漏电极来实现功能。 [0243] conductive layer 605a (a) to 605a⑹ and the conductive layer 605b (a) and 605b (d) of each transistor as the source electrode or the drain electrode to implement the functions. 注意,源电极可以称为源极、源极布线,以及漏电极可以称为漏极布线。 Note that the source electrode may be called a source electrode, source wiring, and the drain electrode may be called a drain wiring. [0244] 导电层605a (a)至605a⑹和导电层605b (a)和605b⑹中每一个可以是例如,如铝、镁、铬、铜、钽、钛、钼或钨的金属的层;或包含任意上面的金属材料中作为主要组分的合金的层。 [0244] conductive layer 605a (a) to the conductive layer 605b (a), and each may be, for example, such as aluminum, magnesium, layer of metal chromium, copper, tantalum, titanium, molybdenum, or tungsten 605a⑹ 605b⑹; and or comprising alloy layer is a main component of any metallic material as above. 例如,导电层605a (a)至605a⑹和导电层605b (a)和605Md)中每一个可以使用包含铜、镁和错的合金的层来形成。 For example, the conductive layer 605a (a) to 605a⑹ and the conductive layer 605b (a) and 605Md) can each be formed using copper, magnesium and alloy containing the wrong layer. 作为备选,导电层605a (a)至605a (d)和导电层605b (a)和605b⑹中每一个可以使用这些材料层的层叠来形成。 Alternatively, the conductive layer 605a (a) to 605a (d) and the conductive layer 605b (a) and 605b⑹ each laminate of these materials may be used to form layers. 例如,导电层605a (a)至605a⑹和导电层605b (a)和605b⑹中每一个可以使用包含铜、镁和铝的合金的层与包含铜的层的层叠而形成。 For example, the conductive layer 605a (a) to 605a⑹ layer laminated conductive layer 605b (a) and 605b⑹ each of which may comprise an alloy of copper, magnesium and aluminum and a layer comprising copper is formed.

[0245] 作为备选,导电层605a (a)至605a (d)和导电层605b (a)和605b (d)中每一个可以是包含导电性金属氧化物的层。 [0245] Alternatively, the conductive layer 605a (a) to 605a (d) and the conductive layer 605b (a) and 605b (d) each may be a layer comprising a conductive metal oxide. 导电性金属氧化物的示例是氧化铟、氧化锡、氧化锌、氧化铟-氧化锡以及氧化铟-氧化锌。 Examples of the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium - tin oxide and indium oxide - zinc oxide. 注意,可以在这些导电性金属氧化物中包含氧化硅。 Note that, a silicon oxide may be included in these conductive metal oxides.

[0246] 绝缘层606 (a)和606⑹的每个绝缘层可以是可应用于绝缘层602 (a)至602 (d)的材料的层。 [0246] insulating layer 606 (a), and each of the insulating layer may be 606⑹ layer material may be applied to the insulating layer 602 (a) through 602 (d) of. 作为备选,绝缘层606 (a)和606 (b)的每个绝缘层可以使用可应用于绝缘层606 (a)和606⑹的材料的层层叠而形成。 Can be used as an alternative, the insulating layer 606 (a) and 606 (b) each insulating layer may be applied to the insulating layer 606 (a) and layer laminate material 606⑹ formed. 例如,绝缘层606 (a)和606⑹的每个绝缘层可以是氧化硅层、氧化铝层等。 For example, the insulating layer 606 (a), and each of the insulating layer 606⑹ may be a silicon oxide layer, aluminum oxide layer or the like. 例如,使用氧化铝层作为绝缘层606 (a)和606⑹能够更有效地防止杂质(7』0进入氧化物半导体层603 (a)和603⑹以及有效地防止氧化物半导体层603 (a)和603 ⑹释放氧。 For example, using an aluminum oxide layer as an insulating layer 606 (a) and 606⑹ impurities can be more effectively prevented (7 "0 entering the oxide semiconductor layer 603 (A) and 603⑹ and to effectively prevent the oxide semiconductor layer 603 (A) and 603 ⑹ release oxygen.

[0247] 作为备选,作为沟道保护层实现功能的绝缘层可以形成为具有能够用于实现绝缘层602 (a)至602⑹的材料的叠层结构。 [0247] Alternatively, to realize functions as a channel protective insulating layer may be formed to have a lamination structure can be used to achieve the insulating layer 602 (a) of 602⑹ material.

[0248] 此外,可以在元件形成层600 (a)至600 (d)上形成基底层,以及可以在基底层上形成晶体管。 [0248] Further, the layer 600 (a) through 600 (d) forming a base layer may be formed on the element, and the transistor can be formed on the base layer. 基底层可以是例如可应用于绝缘层602 (a)至602⑹的材料的层。 Base layer may be applied, for example, an insulating layer 602 (a) of the layer material to 602⑹. 作为备选,基底层可以是可应用于绝缘层602 (a)至602 (d)的材料的层的层叠。 Alternatively laminated layer, the base layer may be applied to the insulating layer 602 (a) through 602 (d) of the material. 例如,当基底层是氧化铝层和氧化硅层的层叠时,能够阻止基底层中包含的氧经由氧化物半导体层603 (a)至603⑹释放。 For example, when the base layer is laminated aluminum oxide layer and a silicon oxide layer, it is possible to prevent the oxygen contained in the base layer to the oxide semiconductor layer via a release 603⑹ 603 (a).

[0249] 当与氧化物半导体层603 (a)至603⑹接触的绝缘层包含过量的氧时,容易地将氧提供到氧化物半导体层603 (a)至603 (d)。 [0249] When the insulating layer to 603⑹ contact with the oxide semiconductor layer 603 (a) contain an excess of oxygen, oxygen is easily supplied to the oxide semiconductor layer 603 (a) through 603 (d). 因此,能够减少氧化物半导体层603 (a)至603 (d) 和绝缘层中与每个氧化物半导体层603 (a)至603⑹之间的界面处的氧缺陷,这促成氧化物半导体层603 (a)至603 (d)的载流子浓度进一步降低。 Accordingly, it is possible to reduce the oxide semiconductor layer 603 (A) 603 to (D) and the oxygen defects in the insulating layer and each of the oxide semiconductor layer 603 (A) to the interface between the 603⑹, which led to the oxide semiconductor layer 603 carrier concentration (a) to 603 (d) is further reduced. 即使氧化物半导体层603 (a)至603⑹ 制备成使得其中包含过量氧,与氧化物半导体层603 (a)至603 (d)接触的绝缘层仍能够阻止氧从氧化物半导体层603 (a)至603⑹释放。 Even if the oxide semiconductor layer 603 (A) so prepared to 603⑹ containing excess oxygen, the oxide semiconductor layer 603 (A) 603 to the insulating layer (d) is still possible to prevent the contact of oxygen from the oxide semiconductor layer 603 (A) to 603⑹ release.

[0250] 接下来,将参考图11和图12A至12C描述在氧化物半导体层中形成其沟道的晶体管的理论场效应迀移率。 Theoretical FET Gan [0250] Next, with reference to FIGS. 11 and 12A to 12C described in which the transistor channel is formed in the oxide semiconductor layer shift rate. 由于多种原因,绝缘栅晶体管的实际测量的场效应迀移率可能低于其理论场效应迀移率;此现象不只是出现在使用氧化物半导体的情况中。 Due to various reasons, the actually measured Gan field effect insulated gate transistor may be lower than the theoretical shift ratio shift rate field effect Gan; this phenomenon occurs not only in the case of using an oxide semiconductor. 降低迀移率的原因之一是半导体内的缺陷或半导体与绝缘薄膜之间的界面处的缺陷。 One reason is to reduce the rate of shift Gan defects at the interface between the semiconductor and the insulating film or a defect in a semiconductor. 当使用Levinson模型时,可以在理论上计算基于半导体内不存在缺陷的假定的场效应迀移率。 When a Levinson model may be calculated theoretically on the assumption that the field effect Gan absence of defects within the semiconductor shift rate.

[0251] 假定半导体中存在电位势垒(例如,颗粒边界),则将测量的场效应迀移率μ表示为如下公式⑵。 [0251] assumed that the semiconductor in the presence of a potential barrier (e.g., grain boundaries), the measured field effect Gan shift ratio μ is expressed as the following equation ⑵.

[0252] [公式2] [0252] [Formula 2]

Figure CN102789808BD00231

[0254] 此处,μ表示半导体的理论迀移率,i?表示电位势垒的高度,A表示Bo Itzmann常数, 以及T表示绝对温度。 [0254] Here, [mu] represents the theoretical Gan semiconductor drift rate, I? Represents the potential barrier height, A denotes Bo Itzmann constant, and T represents the absolute temperature.

[0255] 当假定电位势垒归因于缺陷时,电位势垒的高度表示为根据Levinson模型的公式⑶。 [0255] When it is assumed that a potential barrier due to the defect, the height of the potential barrier is represented according to the formula ⑶ Levinson model.

[0256] [公式3] [0256] [Equation 3]

Figure CN102789808BD00232

[0258] 此处,e表示基本电荷,#表示沟道中每单位面积的平均缺陷密度,ε表示半导体的介电常数,Ώ表示沟道中每个单位面积的载流子密度,Cm表示每个单位面积的电容,Kg表示栅极电压以及t表示沟道的厚度。 [0258] Here, e represents the elementary charge, defects in the channel # represents the average density per unit area, [epsilon] represents permittivity of the semiconductor, Ώ represents the channel carrier density per unit area, per unit Cm is expressed capacitance area, Kg represents a gate voltage, and t represents the thickness of the channel. 在氧化物半导体层的厚度小于或等于30 nm的情况中,可以将沟道的厚度视为与氧化物半导体层的厚度相同。 In the case where the thickness of the oxide semiconductor layer is less than or equal to 30 nm, the thickness of the channel can be regarded as the same as the thickness of the oxide semiconductor layer.

[0259] 线性区域中的漏极电流心表示为如下公式(4)。 [0259] Heart drain current in the linear region is expressed as the following equation (4).

[0260] [公式4] [0260] [Formula 4]

Figure CN102789808BD00233

[0262] 此处,L表示沟道长度以及r表示沟道宽度,以及L和r各为10 μπι。 [0262] Here, L represents a channel length, and r represents a channel width, and L and r are each 10 μπι. 此外,心表示漏极电压。 In addition, the heart represents the drain voltage.

[0263] 当将上面的公式(4)两边除以Kg,然后同时对两边取对数,得到如下公式(5)。 [0263] When the above formula (4) by dividing both sides Kg, and then taking the logarithm on both sides simultaneously, to give the following equation (5).

[0264] [公式5] [0264] [Formula 5]

Figure CN102789808BD00234

[0266]公式5的右边是^的函数。 The right [0266] Equation 5 is a function of ^. 由该公式,发现可以由In(LzzYg)为纵坐标以及为横坐标的实际测量的值的绘图的斜率得到缺陷密鹿V。 From this equation, the slope of the plot can be found by actual measurement In (LzzYg) as abscissa and ordinate values ​​obtained defect density deer V. 即,可以由晶体管的Id-Kg特征来对缺陷密度求值。 That is, the transistor characteristics Id-Kg to evaluate a defect density.

[0267] 由此,发现铟(In)对锡(Sn)和锌(Zn)的比率是1:1:1的氧化物半导体的缺陷密鹿V 是约IX IO12 /cm2。 [0267] Thus, it was found indium (In) to tin (Sn) zinc (Zn) and the ratio is 1: 1: 1 the oxide semiconductor deer V defect density of about IX IO12 / cm2.

[0268] 基于以此方式得到的缺陷密度,由公式2和公式3将μ〇计算为120 cm2/Vs,这给出在半导体内以及半导体与绝缘薄膜之间的界面处不存在缺陷的情况下理想氧化物半导体的迀移率为120 cm2/Vs概率。 [0268] Based on the defect density obtained in this way, from the Equations 2 and 3 μ〇 calculated as 120 cm2 / Vs, which is given the case where the interface between the semiconductor and the insulating film and the absence of defects in the semiconductor Gan shift over the oxide semiconductor was 120 cm2 / Vs probability. 包含缺陷的In-Sn-Zn氧化物的测量迀移率是约40 cm2/Vs。 Defect comprising measuring Gan In-Sn-Zn oxide is a shift of about 40 cm2 / Vs.

[0269] 注意即使在氧化物半导体层内不存在缺陷时,沟道与栅绝缘层之间的界面处的散射仍影响晶体管的传输特性。 [0269] Note that even when there is no defect in the oxide semiconductor layer, the scattering at the interface between the channel and the gate insulating layer still affect the transmission characteristics of the transistor. 换言之,相距沟道与栅绝缘层之间的界面距离Z的位置的迀移率%表示为如下公式(6)。 In other words, Gan distance between the channel and the distance from the interface of the gate insulating layer Z position shift rate% represented as follows Equation (6).

[0270] [公式6] [0270] [Equation 6]

Figure CN102789808BD00241

[0272] 此处,β表示栅极方向的电场,以及B和J是常数。 [0272] Here, the gate beta] represents the electric field direction, and B and J are constants. 可以从实际测量结果得到B和八根据上文测量结果,ΰ是4.75Χ107 cm/s以及J是10 nm(界面散射的影响所达到的深度)。 Can be obtained from the actual measurement result from the measurement results B and VIII above, ΰ is 4.75Χ107 cm / s, and J is 10 nm (the influence of the interface scattering depth reached). 当增加加寸(即,当增大栅极电压时),公式6的第二项增加,并且相应地迀移率的降低。 When added inch increase (i.e., when the gate voltage is increased), the second term in equation 6 increases, and correspondingly reduce shift Gan rate.

[0273] 图11示出其沟道包括氧化物半导体层内没有缺陷的理想氧化物半导体的晶体管的迀移率以2的计算结果。 [0273] FIG. 11 shows a transistor including Gan no defects over the oxide semiconductor in the oxide semiconductor layer to calculate a shift of its channel 2 results. 为了计算,使用了Synopsys有限公司制作的装置模拟软件Sentaurus Device,假定氧化物半导体的能隙、电子亲和势、相对介电常数和厚度分别为2.86¥、4.76¥、15和15 11111。 To calculate, using the production apparatus Synopsys Co. simulation software Sentaurus Device, assuming the oxide semiconductor energy gap, electron affinity, the relative permittivity and thickness of 2.86 ¥, 4.76 ¥, 15, and 1,511,111. 假定栅极、源极和漏极的功函数分别为5.56¥、4.66¥和4.6 eV。 It assumed that the work function of the gate, source and drain are respectively 5.56 ¥, 4.66 ¥ and 4.6 eV. 假定栅绝缘层的厚度是100 nm,并且假定其相对介电常数是4.1。 It assumed that thickness of the gate insulating layer is 100 nm, and the relative permittivity of 4.1 is assumed. 沟道长度和沟道宽度各假定为l〇ym,以及假定漏极电压Kci为0.1 V。 Channel length and the channel width of each assumed l〇ym, and assuming Kci drain voltage is 0.1 V.

[0274] 如图11所示,迀移率在稍微高于IV的栅极电压处具有大于100 cm2/Vs的峰值,并且因为界面散射的影响增加而随着栅极电压增大而下降。 [0274] As shown, Gan shift has a peak rate of greater than 11 100 cm2 / Vs at a gate voltage slightly higher than IV, and because of the increased influence of the interface scattering and increases as the gate voltage drops. 注意,为了减少界面散射,期望半导体层的表面在原子级上是平坦的(原子层平坦度)。 Note that, in order to reduce interface scattering, it is desirable the surface of the semiconductor layer is flat (atomic layer flatness) on the atomic level.

[0275] 图12A至12C、图13A至13C以及图14A至14C中示出含具有这种迀移率的氧化物半导体的微小晶体管(minute transistors)的特征的计算结果。 [0275] FIGS. 12A to 12C, 13A to 13C and 14A to the calculation results shown in 14C containing fine transistor characteristics (minute transistors) having a oxide semiconductor such Gan shift rate of FIG. 图15A和图15B图示计算中使用的晶体管的横截面结构。 The cross-sectional structure of the transistor used in the calculations illustrated in FIGS. 15A and 15B. 图15A和图15B中所示的晶体管各包括在氧化物半导体层中具有n+ 型导电性的半导体区域103a和半导体区域103c。 Transistor shown in FIG. 15A and 15B each include having n + conductivity type semiconductor region 103a and the semiconductor region in the oxide semiconductor layer 103c. 半导体区域103a和半导体区域103c的电阻率是2 X 10—3 Ω cm。 Resistance of the semiconductor region of the semiconductor regions 103a and 103c is 2 X 10-3 Ω cm.

[0276] 图15A中所示的晶体管在基底绝缘体101和嵌入式绝缘体102上形成,嵌入式绝缘体102嵌入基底绝缘体101中且由氧化铝形成。 Transistor shown in [0276] FIG. 15A embedded in the insulator 101 and the insulator substrate 102, the embedded insulator 102 is embedded in the substrate 101 and the insulator formed of alumina. 该晶体管包括半导体区域103a、半导体区域103c、用作其间的沟道形成区域的本征半导体区域103b和栅极105。 The transistor includes a semiconductor region 103a, a semiconductor region 103c, as a channel therebetween forming an intrinsic semiconductor region 105 and the gate region 103b. 栅极105的宽度是33 nm〇 Width of the gate 105 is 33 nm〇

[0277] 栅绝缘体104在栅极105与半导体区域103b之间形成。 [0277] The gate insulator 104 is formed between the gate 105 and the semiconductor region 103b. 此外,侧壁绝缘体106a和侧壁绝缘体106b在栅极的两个侧表面上形成,以及绝缘体107在栅极105上形成以便防止栅极105与另一个布线之间的短路。 Furthermore, sidewall insulator sidewall insulators 106a and 106b on the both side surfaces of the gate electrode is formed, and an insulator 107 is formed so as to prevent a short circuit between the gate 105 and the gate electrode 105 on the other wiring. 该侧壁绝缘体具有5 nm的宽度。 The sidewall insulator has a width of 5 nm. 设置源极108a和漏极108b分别与半导体区域l〇3a和半导体区域103c接触。 Source and drain electrodes 108a disposed 108b 103c are in contact with the semiconductor region and the semiconductor region l〇3a. 注意此晶体管的沟道宽度为40 nm。 Note that the transistor channel width is 40 nm.

[0278] 图15B的晶体管与图15A的晶体管相同,因为它在基底绝缘体101和由氧化铝形成的嵌入式绝缘体102上形成,并且它包括半导体区域103a、半导体区域103c、在其间设置的本征半导体区域103b、具有33 nm宽度的栅极105、栅绝缘体104、侧壁绝缘体106a、侧壁绝缘体106b、绝缘体107、源极108a和漏极108b。 [0278] FIG. 15B is the same as FIG. 15A transistor transistor 101 because it is formed and embedded in the insulator 102 formed of an insulating alumina substrate, and which includes a semiconductor region 103a, 103c of the semiconductor region, the intrinsic disposed therebetween semiconductor region 103b, a gate width of 105 33 nm, a gate insulator 104, sidewall insulator 106a, the sidewall insulator 106b, an insulator 107, a source electrode 108a and drain electrode 108b.

[0279]图15A中所示的晶体管与图15B中所示的晶体管不同之处在于侧壁绝缘体106a和侧壁绝缘体106b下方的半导体区域的导电性类型。 [0279] FIG 15A is different from the transistor in the transistor shown in FIG 15B shown that the conductivity type of the semiconductor region below the sidewall insulator sidewall insulators 106a and 106b. 在图15A所示的晶体管中,侧壁绝缘体106a和侧壁绝缘体106b下方的半导体区域是具有n+型导电性的半导体区域103a的一部分以及具有n+型导电性的半导体103c的一部分,而在图15B所示的晶体管中,侧壁绝缘体106a 和侧壁绝缘体106b下方的半导体区域是本征半导体区域103b的一部分。 In the transistor shown in FIG. 15A, the semiconductor region below the sidewall insulator sidewall insulators 106a and 106b having a part of n + conductivity type semiconductor region 103a and a portion of n + type semiconductor having conductivity 103c, and 15B in FIG. transistor illustrated, the semiconductor region below the sidewall insulator sidewall insulators 106a and 106b are part of the intrinsic semiconductor region 103b. 换言之,在图15B的半导体层中,具有Zciff宽度且不与栅极105重叠的区域在本征半导体区域103b中设置。 In other words, in the semiconductor layer of FIG. 15B, having a width not provided Zciff region 105 overlapping the gate electrode in the intrinsic semiconductor region 103b. 此区域称为偏移区域,以及宽度Lff称为偏移长度。 This area is called the offset region, and the width Lff called offset length. 正如从图15B见到的,该偏移长度等于侧壁绝缘体106a (侧壁绝缘体106b)的宽度。 As seen from FIG. 15B, the offset length is equal to the width of the sidewall insulator 106a (the sidewall insulator 106b) of.

[0280]计算中使用的其他参数如上文描述。 Other parameters used in the [0280] calculated as described above. 对于计算,使用了Synopsys有限公司制作的装置模拟软件Sentaurus DeVice。 For the calculation, using the production apparatus Synopsys Co. simulation software Sentaurus DeVice. 图12A至12C示出具有图15A所示的结构的晶体管的漏极电流(Id,实线)的栅极电压(Kg,栅极与源极之间的电位差)相关性以及迀移率(μ,虚线)。 12A to 12C show the drain current as shown in FIG. 15A having a structure of a transistor (Id, solid line) gate voltage (potential difference between Kg, the difference between the gate and the source), and Gan correlation drift rate ( μ, dotted line). 在漏极电压(漏极与源极之间的电位差)是+1 V的假定下计算得到漏极电流Id以及在漏极电压是+0.1 V的假定下计算得到迀移率μ。 Drain voltage (a potential difference between the drain and the source of the difference) is calculated under the assumption that the drain current Id +1 V and drain voltage is calculated under the assumption that obtained Gan +0.1 V shift rate μ.

[0281] 图12Α示出栅绝缘薄膜的厚度是15 nm的情况中的晶体管的栅极电压相关性,图12B示出栅绝缘薄膜的厚度是10 nm的情况中的晶体管的栅极电压相关性,以及图12C示出栅绝缘薄膜的厚度是5 nm的情况中的晶体管的栅极电压相关性。 [0281] FIG 12Α shows a thickness of the gate insulating film is a gate voltage of 15 nm in the case of correlation of the transistor, FIG. 12B shows the thickness of the gate insulating film is a gate voltage of 10 nm in the case where the transistor correlation and FIG. 12C shows the thickness of the gate insulating film is a gate voltage dependency of 5 nm in the case of a transistor. 随着栅绝缘层更薄,尤其截止状态中的漏极电流Id (截止态电流)显著降低。 As the gate insulating layer is thinner, in particular, the drain current Id in the off-state (off-state current) is significantly reduced. 相比之下,迀移率μ的峰值和导通态中的漏极电流Id (导通态电流)的峰值存在可忽略的变化。 In contrast, Gan shift of the drain current Id (on-state current) peak value [mu] and the conduction states of the peaks is negligible changes. 这些曲线图示出在约IV的栅极电压处,漏极电流超过1 〇μΑ,这是存储器元件等中所需的。 The graph shows the gate voltage of about IV drain current more than 1 〇μΑ, which is required for the memory elements and the like.

[0282] 图13Α至13C示出具有图15Β所示的结构的晶体管的漏极电流Id (实线)的栅极电压Kg相关性以及迀移率μ(虚线),其中偏移长度Lciff是5 nm。 [0282] FIG 13C shows a 13Α to FIG 15Β drain current Id of the transistor structure shown (solid line) and the gate voltage Gan Kg correlation drift rate [mu] (dotted line), wherein the offset length is 5 Lciff nm. 在漏极电压是+1 V的假定下计算得到漏极电流Id以及在漏极电压是+0.1 V的假定下计算得到迀移率μ。 Calculated drain current Id at the drain voltage of +1 V is calculated under the assumption that the drain voltage and is assumed to give Gan +0.1 V shift rate μ. 图13A示出栅绝缘薄膜的厚度是15 nm的情况中的晶体管的栅极电压相关性,图13Β示出栅绝缘薄膜的厚度是10 nm的情况中的晶体管的栅极电压相关性,以及图13C示出栅绝缘薄膜的厚度是5 nm的情况中的晶体管的栅极电压相关性。 13A illustrates the thickness of the gate insulating film is a gate voltage of 15 nm in the case of correlation of the transistor, FIG 13Β shows the thickness of the gate insulating film is a gate voltage of 10 nm in the case of correlation of the transistor, and FIG. 13C shows the thickness of the gate insulating film is a gate voltage dependency of 5 nm in the case of a transistor.

[0283] 再者,图14A至14C示出具有图15B所示的结构的晶体管的漏极电流Id (实线)的栅极电压相关性以及迀移率μ(虚线),其中偏移长度Lclff是15 nm。 [0283] Further, FIGS. 14A to 14C show a gate voltage of the drain current Id (solid line) and the correlation drift rate Gan [mu] (dotted line), wherein the offset length Lclff transistor having the structure shown in FIG. 15B is 15 nm. 在漏极电压是+1 V的假定下计算得到漏极电流Id以及在漏极电压是+0.1 V的假定下计算得到迀移率μ。 Calculated drain current Id at the drain voltage of +1 V is calculated under the assumption that the drain voltage and is assumed to give Gan +0.1 V shift rate μ. 图14A示出栅绝缘层的厚度是15 nm的情况中的晶体管的栅极电压相关性,图14Β示出栅绝缘层的厚度是10 nm的情况中的晶体管的栅极电压相关性,以及图14C示出栅绝缘层的厚度是5 nm的情况中的晶体管的栅极电压相关性。 14A illustrates the thickness of the gate insulating layer is a gate voltage of 15 nm in the case of correlation of the transistor, shown in FIG 14Β thickness of the gate insulating layer is a gate voltage of 10 nm in the case of correlation of the transistor, and FIG. 14C shows the thickness of the gate insulating layer is a gate voltage dependency of 5 nm in the case of a transistor.

[0284] 在其中任一种结构中,随着栅绝缘层更薄,截止态电流显著下降,而迀移率μ和导通态电流的峰值没有出现可检测到的变化。 [0284] wherein in either configuration, with the gate insulating layer is thinner, off-state current is significantly decreased, and the peak value of μ Gan shift and on-state current is not detectable change occurs.

[0285] 注意,迀移率μ的峰值在图12Α至12C中约为80 cm2/Vs,在图13Α至13C中约为60 cm2/Vs,以及在图14A至图14C约为40 cm2/Vs,因此,迀移率μ的峰值随着偏移长度Lciff增加而降低。 [0285] Note that the shift rate μ Gan peak in FIG. 12C 12Α to about 80 cm2 / Vs, of approximately 60 cm2 / Vs in 13Α to FIG. 13C, and 14A to 14C in about 40 cm2 / Vs Therefore, Gan shift with peak rate μ Lciff offset length increases. 再者,这同样适用于截止态电流。 Further, the same applies to the off-state current. 导通态电流也随着偏移长度Lclff增加而降低;但是, 导通态电流中的下降远小于截止态电流的下降。 With the on-state current is also decreased offset length Lclff increased; however, the decrease in the on-state current is much smaller than off-state current is decreased. 再者,这些曲线图示出在任一种结构中,在约IV的栅极电压处,漏极电流超过ΙΟμΑ,这是存储器元件等中所需的。 Moreover, the curves illustrated in either configuration, the gate voltage of about IV, the drain current exceeds ΙΟμΑ, which is required for the memory elements and the like.

[0286] 本实施例描述的包含其中形成沟道的氧化物半导体层的晶体管是具有降低了截止态电流的晶体管。 [0286] The present embodiment described embodiment wherein the transistor comprises a channel layer formed of an oxide semiconductor having a reduced off-state current of the transistor. 当将这种晶体管用于本发明的实施例的存储器装置中时,该存储器装置能够长时间地保留数据。 When the memory device such a transistor to an embodiment of the present invention, the memory means to retain data for a long time.

[0287] 当使用包含CAAC-OS的晶体管时,能够实现高于非晶体氧化物半导体的场效应迀移率的场效应迀移率。 [0287] When a transistor comprising CAAC-OS, to achieve the above amorphous oxide semiconductor field-effect field effect Gan Gan shift ratio shift rate. 使用具有高迀移率的这种晶体管,存储器装置能够甚至在自举操作中高速地被驱动。 Gan using such a transistor having a high drift rate, the memory device can even bootstrap operation is driven at high speed.

[0288] 本实施例能够根据情况与任意其他实施例组合。 [0288] According to the present embodiment can be the case in combination with any other embodiments Example.

[0289] 本申请基于2011年5月20日向日本专利局提交的序号为的2011-113949日本专利申请,其整个内容通过引用并入本文。 [0289] The present application is based on the serial number filed with the Japan Patent Office on May 20, 2011 in order to 2011--113949 Japanese patent application, the entire contents of which are incorporated herein by reference.

Claims (25)

1. 一种半导体装置,包括: 电源,用于供应电源电位; 控制器,电连接到所述电源; 晶体管,包括栅极、第一端和第二端,所述栅极电连接到所述控制器; 第一线路,电连接到所述控制器; 延迟电路,电连接到所述第一线路; 第一电容器;以及第二线路,电连接到所述第一端, 其中所述第一电容器的一个电极电连接到所述栅极和所述控制器,以及其中所述第一电容器的另一个电极电连接到所述延迟电路。 1. A semiconductor device, comprising: a power supply for supplying a power supply potential; and a controller electrically connected to said power source; a transistor including a gate, a first end and a second end electrically connected to the gate of the a controller; a first line electrically connected to the controller; delay circuit electrically connected to the first line; a first capacitor; and a second line electrically connected to the first end, wherein the first a capacitor electrode is electrically connected to the gate and the controller, and wherein the other electrode of the capacitor is connected to the first delay circuit.
2. 如权利要求1所述的半导体装置,其中所述控制器配置成将所述电源电位输入到所述栅极。 The semiconductor device according to claim 1, wherein the controller is configured to supply the voltage input to the gate.
3. 如权利要求1所述的半导体装置, 其中所述第一线路配置成将第一信号输入到所述控制器和所述延迟电路,以及其中所述第一信号具有等于所述电源电位的电位。 The semiconductor device according to claim 1, wherein said first line is configured to input a first signal to said controller and said delay circuit, and wherein said first signal equal to said power supply potential potential.
4. 如权利要求1所述的半导体装置, 其中所述第二线路配置成将第二信号输入到所述第一端,以及其中所述第二信号具有等于所述电源电位的电位。 The semiconductor device according to claim 1, wherein the second line is configured to input a second signal to the first end, and wherein said second signal has a potential equal to the power supply potential.
5. 如权利要求1所述的半导体装置,还包括: 读取电路,电连接到所述第二端;以及第三线路,电连接到所述读取电路并配置成将第三信号输入到所述读取电路, 其中所述第三信号具有等于所述电源电位的电位。 The semiconductor device according to claim 1, further comprising: a reading circuit electrically connected to the second terminal; and a third line is electrically connected to the reading circuit and configured to input to the third signal the reading circuit, wherein said third signal has a potential equal to the power supply potential.
6. 如权利要求5所述的半导体装置,还包括: 第二电容器,包括第一电极和第二电极, 其中所述第二电容器的所述第一电极电连接到所述第二端和所述读取电路。 The semiconductor device according to claim 5, further comprising: a second capacitor including a first electrode and a second electrode, wherein the first electrode of the second capacitor is electrically connected to the second end and the said reading circuit.
7. 如权利要求6所述的半导体装置,其中所述第二电容器的所述第二电极接地。 7. The semiconductor device of claim 6, wherein said second electrode of said second capacitor grounding requirements.
8. 如权利要求1所述的半导体装置,其中所述晶体管具有包含氧化物半导体的沟道形成区域。 The semiconductor device as claimed in claim 1, wherein said transistor having a channel formation region comprises an oxide semiconductor.
9. 如权利要求8所述的半导体装置,其中所述氧化物半导体包含铟。 The semiconductor device as claimed in claim 8, wherein the oxide semiconductor comprises indium.
10. 如权利要求1所述的半导体装置,其中所述半导体装置是存储器装置。 10. The semiconductor device according to claim 1, wherein said semiconductor device is a memory device.
11. 一种半导体装置,包括: 电源,用于供应电源电位; 第一晶体管,包括栅极、第一端和第二端; 控制器,包括二极管和第二晶体管,其中, 所述二极管电连接在所述电源与所述第一晶体管的所述栅极之间;以及所述第二晶体管包括栅极、第一端和第二端,所述第二晶体管的所述第二端经由所述二极管电连接到所述电源; 第一电容器,所述第一电容器的一个电极电连接到所述第一晶体管的所述栅极、所述二极管和所述第二晶体管的所述第二端; 第一线路,电连接到所述第二晶体管的所述栅极; 第一延迟电路,电连接在所述第一线路与所述第一电容器的另一个电极之间;以及第二线路,电连接到所述第一晶体管的所述第一端。 A semiconductor device, comprising: a power supply for supplying a power supply potential; electrically connected to a controller, including a diode and a second transistor, wherein said diode; a first transistor including a gate, a first end and a second end between the power source and the gate of the first transistor; and the second transistor includes a gate, a first end and a second end, the second end of the second transistor via the a diode electrically connected to the power source; a first capacitor, a first electrode of the capacitor is connected to the gate of the first transistor, the diode and the second terminal of the second transistor; a first line electrically connected to the gate of the second transistor; a first delay circuit electrically connected between the first line and the other electrode of the first capacitor; and a second line electrically connected to the first terminal of the first transistor.
12. 如权利要求11所述的半导体装置,其中所述第二晶体管的所述第一端接地。 12. The semiconductor device of claim 11 wherein said first end of said second transistor to claim.
13. 如权利要求11所述的半导体装置,其中所述控制器还包括倒相器,所述倒相器电连接在所述第一线路与所述第二晶体管的所述栅极之间。 13. The semiconductor device according to claim 11, wherein said controller further comprises an inverter, the inverter is electrically connected between the first line and the gate of the second transistor.
14. 如权利要求11所述的半导体装置, 其中所述控制器还包括第三晶体管,所述第三晶体管包括栅极、第一端和第二端, 其中所述第三晶体管的所述第一端和所述第二端分别电连接到所述电源和所述二极管, 其中所述第三晶体管的所述栅极电连接到所述第二晶体管的所述栅极,以及其中所述第二晶体管的极性与所述第三晶体管的极性不同。 14. The semiconductor device of claim 11 wherein said third transistor to the first claim, wherein said controller further comprises a third transistor, the third transistor including a gate, a first end and a second end, end and the second end electrically connected to said power source and said diode, wherein the gate of the third transistor is electrically connected to the gate of the second transistor, and wherein said second the polarity of the polarity of the second transistor and the third transistor are different.
15. 如权利要求14所述的半导体装置,还包括倒相器,其中所述倒相器电连接在所述第一线路与所述第二晶体管的所述栅极之间。 15. The semiconductor device according to claim 14, further comprising an inverter, wherein the inverter is electrically connected between the first line and the gate of the second transistor.
16. 如权利要求14所述的半导体装置,其中所述控制器还包括: NOR电路,电连接在所述第二晶体管的所述栅极与所述第一线路之间;以及第二延迟电路,电连接在所述NOR电路与所述第一线路之间。 16. The semiconductor device according to claim 14, wherein said controller further comprises: NOR circuit electrically connected between the gate of the second transistor and the first line; and a second delay circuit electrically connected between the first circuit and the NOR circuit.
17. 如权利要求16所述的半导体装置,其中所述NOR电路电连接到所述第一延迟电路。 17. The semiconductor device according to claim 16, wherein said NOR circuit is electrically connected to the first delay circuit.
18. 如权利要求11所述的半导体装置, 其中所述第一线路配置成将第一信号输入到所述控制器和所述第一延迟电路,以及其中所述第一信号具有等于所述电源电位的电位。 18. The semiconductor device of claim 11, wherein said first line is configured to input a first signal to said controller and said first delay circuit, and wherein said first signal equal to said power supply having potential potential.
19. 如权利要求11所述的半导体装置, 其中所述第二线路配置成将第二信号输入到所述第一晶体管的所述第一端,以及其中所述第二信号具有等于所述电源电位的电位。 19. The semiconductor device of claim 11, wherein the second line is configured to input a second signal to the first terminal of the first transistor, and wherein said second signal is equal to the power supply potential potential.
20. 如权利要求11所述的半导体装置,还包括: 读取电路,电连接到所述第一晶体管的所述第二端;以及第三线路,电连接到所述读取电路并配置成将第三信号输入到所述读取电路, 其中所述第三信号具有等于所述电源电位的电位。 20. The semiconductor device of claim 11, further comprising: a reading circuit electrically connected to the second terminal of the first transistor; and a third line is electrically connected to the reading circuit and configured to the third signal is input to said reading circuit, wherein said third signal has a potential equal to the power supply potential.
21. 如权利要求20所述的半导体装置,还包括: 第二电容器,包括第一电极和第二电极, 其中所述第二电容器的所述第一电极电连接到所述第一晶体管的所述第二端和所述读取电路。 21. The semiconductor device according to claim 20, further comprising: a second capacitor including a first electrode and a second electrode, wherein the second capacitor is electrically connected to the first electrode of the first transistor said second end and said read circuit.
22. 如权利要求21所述的半导体装置,其中所述第二电容器的所述第二电极接地。 The semiconductor device of claim 21 wherein said second electrode of said second capacitor as claimed in claim 22. A ground.
23. 如权利要求11所述的半导体装置,其中所述第一晶体管具有包含氧化物半导体的沟道形成区域。 23. A semiconductor device as claimed in claim 11, wherein the first transistor has a channel formation region comprises an oxide semiconductor.
24. 如权利要求23所述的半导体装置,其中所述氧化物半导体包含铟。 24. The semiconductor device according to claim 23, wherein the oxide semiconductor comprises indium.
25. 如权利要求11所述的半导体装置,其中所述半导体装置是存储器装置。 25. A semiconductor device as claimed in claim 11, wherein said semiconductor device is a memory device.
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