JP2004273732A - Active matrix substrate and its producing process - Google Patents
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- JP2004273732A JP2004273732A JP2003061985A JP2003061985A JP2004273732A JP 2004273732 A JP2004273732 A JP 2004273732A JP 2003061985 A JP2003061985 A JP 2003061985A JP 2003061985 A JP2003061985 A JP 2003061985A JP 2004273732 A JP2004273732 A JP 2004273732A
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- 239000000758 substrate Substances 0.000 title claims abstract description 102
- 239000011159 matrix material Substances 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 39
- 238000000059 patterning Methods 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 150000001875 compounds Chemical class 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 abstract description 14
- 230000003068 static effect Effects 0.000 abstract description 14
- 238000012858 packaging process Methods 0.000 abstract 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 122
- 239000011787 zinc oxide Substances 0.000 description 60
- 238000010438 heat treatment Methods 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- QTBSBXVTEAMEQO-UHFFFAOYSA-N acetic acid Substances CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000005224 laser annealing Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Images
Abstract
Description
【0001】
【発明の属する技術分野】
本発明は、アクティブマトリクス基板およびその製造方法、ならびにアクティブマトリクス基板を備えた液晶表示装置やEL表示装置などの各種表示装置に関する。
【0002】
【従来の技術】
アクティブマトリクス型の液晶表示装置は、画素毎にスイッチング素子を備えているため、高繊細で高品位の表示が可能である。上記スイッチング素子としては、薄膜トランジスタ(以下、「TFT」と称することがある)、ダイオード等の非線形素子が用いられる。なかでも、アモルファスシリコンまたは多結晶シリコンを用いたTFTが広く用いられている。
【0003】
通常、アクティブマトリクス型の液晶表示装置の製造工程には、静電気を生じやすい工程(例えばラビング工程など)が多く含まれている。しかし、TFTに用いられるアモルファスシリコンや多結晶シリコンは、静電気による損傷を受けやすい。従って、液晶表示装置の製造工程において、静電気によって、TFTの特性が変化したり、TFT自体が破壊されたりするので、製品の良品率を低下させるという問題があった。
【0004】
そこで、液晶表示装置の製造工程において生じた静電気からTFTを保護するための種々の手段を備えたアクティブマトリクス基板が提案され、または採用されている。
【0005】
特許文献1は、図7に示すアクティブマトリクス基板を開示している。このアクティブマトリクス基板では、基板の最も外側に導電性ライン(導電性ショートリング)7が形成されており、この導電性ライン7によって基板に設けられた走査線および信号線は全て電気的に接続されている。このような構成により、基板に設けられたいずれかのTFTが帯電した場合でも、この導電性ラインを介して電荷を分散させることができるので、TFTを静電気から保護できる。
【0006】
また、特許文献2には、図8に示すように、高抵抗の半導体層(例えばリンドープのn+アモルファスシリコン)からなるショートリング9を有するアクティブマトリクス基板が開示されている。
【0007】
さらに、特許文献3は、図9に示すアクティブマトリクス基板を開示している。このアクティブマトリクス基板では、複数の走査線のうち互いに隣り合う走査線の間および複数の信号線のうち互いに隣り合う信号線の間にスイッチング素子からなる入力保護回路(2端子素子ショートリング)5がそれぞれ挿入されている。この入力保護回路5により、1つの線(走査線または信号線)に一定以上の静電気が加わると、その線から、入力保護回路5のスイッチング素子を介して、その線の隣に位置する線に過大な電荷を分散させることができる。
【0008】
【特許文献1】
特開昭61−059475号公報
【特許文献2】
特公平5−47813号公報
【特許文献3】
特開平10−20336号公報
【0009】
【発明が解決しようとする課題】
上述したようなアクティブマトリクス基板には、以下のような問題がある。
【0010】
図7のアクティブマトリクス基板は、電荷の分散性は優れているが、駆動用ドライバを実装する前に導電性ショートリングを除去する必要がある。そのため、除去後の実装工程において静電気が生じると、その静電気からTFTを充分に保護することができない。
【0011】
これに対し、図8のアクティブマトリクス基板では、実装工程の前にショートリングを除去する必要はない。しかしながら、特許文献2に例示されたような半導体層(リンドープのn+アモルファスシリコンなど)からなるショートリングは、基本的に電圧に対して直線性抵抗となるため、このショートリングに印加される電圧が低くても微小なリーク電流が生じ、その結果、TFTの駆動に悪影響を与える可能性がある。これを防ぐために、ショートリングはある程度高い抵抗を有する必要がある。そのような高抵抗なショートリングの電荷分散性は、図7の導電性ショートリングの電荷分散性よりも低い。また、ショートリングの抵抗値や駆動ドライバの出力インピーダンスの選択に制約が課されるため、アクティブマトリクス基板やそれを用いた表示パネルの設計の自由度を阻害するという問題もある。さらに、半導体層にアモルファスシリコン、コンタクト層にn+アモルファスシリコンを用いた場合の製造プロセスでは、ソース・ドレイン電極をマスクとしてTFTのギャップ部をエッチングするような短縮プロセスを採用することができないという問題があった。
【0012】
図9のアクティブマトリクス基板は、図7または図8に示すようなショートリングを有するアクティブマトリクス基板と比べて明らかに複雑な構造を有している。そのため、図7や図8のアクティブマトリクス基板の製造技術よりも高い製造技術が要求される。例えば、所定位置にスイッチング素子を不良なく形成する必要がある。また、ガラス基板上に形成される複数のスイッチング素子の特性が、基板内におけるこれらの素子の位置に応じてばらつきやすいという問題もある。このようなばらつきを抑えて、スイッチング素子の特性を均一にするために、例えば基板を大型化できないなどの、より多くの制約が課されている。
【0013】
本発明は、上記事情に鑑みてなされたものであり、その主な目的は、駆動用ドライバの実装工程後も機能し、かつ電荷分散性の高い簡便な構造の短絡部材を備えることにより、低電圧領域においてリーク電流をほとんど生じることなく、静電気からTFTを有効に保護することができるアクティブマトリクス基板を提供することである。
【0014】
【課題を解決するための手段】
本発明によるアクティブマトリクス基板は、基板と、前記基板の上に形成された複数の画素電極と、複数の配線と、それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、バリスタの特性を有する短絡部材であって、前記複数の配線のうち互いに隣接する少なくとも2本の配線を接続する短絡部材とを有することを特徴とし、そのことにより上記目的が達成される。
【0015】
ある好ましい実施形態において、前記複数の配線は、複数の走査線と、前記複数の走査線と交差する複数の信号線とを含み、前記複数のスイッチング素子は、それぞれがゲート電極、ドレイン電極およびソース電極を備え、前記ゲート電極が前記複数の走査線の一つと、前記ドレイン電極が前記複数の画素電極の一つと、前記ソース電極が前記複数の信号線の一つとそれぞれ電気的に接続されており、前記短絡部材は、前記複数の信号線のうち互いに隣接する少なくとも2本の信号線および/または前記走査の信号線のうち互いに隣接する少なくとも2本の走査線を接続する。
【0016】
ある好ましい実施形態において、前記短絡部材は、ZnOまたはZnOを主成分とする化合物を含む。
【0017】
前記短絡部材に含まれる前記ZnOまたはZnOを主成分とする化合物の結晶粒径は、30nm以上であって、前記複数の配線のぞれぞれの線幅以下であることが好ましい。
【0018】
ある好ましい実施形態において、前記スイッチング素子は半導体層を有しており、前記半導体層はZnOまたはZnOを主成分とする化合物を含む。
【0019】
前記半導体層および前記短絡部材はいずれもZnOを含んでおり、前記半導体層に含まれるZnOの結晶粒径は、前記短絡部材に含まれるZnOの結晶粒径よりも小さくてもよい。
【0020】
前記短絡部材のバリスタ電圧は、前記アクティブマトリクス基板を表示装置に適用したときに、表示装置の動作時に、前記少なくとも2本の信号線および/または前記少なくとも2本の走査線の間に生じる電位差の最大値よりも高く、100Vよりも低いことが好ましい。
【0021】
前記短絡部材は、前記基板と前記少なくとも2本の信号線との間に設けられていてもよい。
【0022】
本発明の表示装置は、上記のいずれかのアクティブマトリクス基板を備えたことを特徴とする。
【0023】
本発明の製造方法は、基板と、複数の画素電極と、複数の配線と、それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、前記複数の配線のうち互いに隣接するすくなくとも2本の配線を接続する短絡部材とを備えたアクティブマトリクス基板の製造方法であって、前記短絡部材を形成する工程を包含し、前記短絡部材を形成する工程は、前記基板の上に膜を堆積する工程と、前記膜をパターニングする第1パターニングを行う工程とを含み、前記短絡部材はバリスタ特性を有することを特徴とし、そのことにより上記目的が達成される。
【0024】
ある好ましい実施形態において、前記複数の配線は、複数の走査線および複数の信号線を含み、前記短絡部材は前記複数の走査線のうち互いに隣接するすくなくとも2本の走査線および/または前記複数の信号線のうち互いに隣接する少なくとも2本の信号線を接続する。
【0025】
ある好ましい実施形態において、前記複数のスイッチング素子のそれぞれは半導体層を有しており、前記膜をパターニングする第2パターニングを行うことによって、前記半導体層を形成する工程を含む。
【0026】
前記第1パターニングと前記第2パターニングとを同時に行ってもよい。
【0027】
前記第1パターニングによって第1パターンが得られ、前記短絡部材を形成する工程は、前記第1パターンを第1温度で熱処理する工程を含むことができる。
【0028】
前記第2パターニングによって第2パターンが得られ、前記半導体層を形成する工程は、前記第2パターンを前記第1温度よりも低い第2温度で熱処理する工程を含むことができる。
【0029】
【発明の実施の形態】
本発明では、アクティブマトリクス基板において、例えば酸化亜鉛(ZnO)または酸化亜鉛(ZnO)を主成分とする化合物を用いて形成される薄膜バリスタを用いることによって、走査線同士または信号線同士を短絡させる短絡部材またはショートリングを構成している。なお、本明細書では、「短絡部材」は、2本以上の線(走査線や信号線)を一定条件下で電気的に接続する部材を意味し、バリスタ、抵抗、TFTなどを広く含むものとする。また、図7や図8に示す従来技術のように、短絡部材を介してアクティブマトリックス基板に含まれる全ての線がリング状に接続される場合、そのような短絡部材を特に「ショートリング」と呼ぶことがある。
【0030】
従来から、ZnOは、その結晶粒界に2重ショットキーバリアが形成されることにより、非直線抵抗特性を発現する材料であることが知られている。ZnOを用いて電圧非直線抵抗素子バリスタを形成する技術や、そのようなバリスタを利用する技術は数多く提案されている(例えば特公昭62−36606号公報や特許第2912081号公報など)。しかし、アクティブマトリクス基板にZnOの非直線抵抗特性を利用する試みは行われていない。
【0031】
本発明者らは、液晶表示装置等のアクティブマトリックス基板において、ZnO及びZnOを主成分とする化合物を用いて形成された薄膜バリスタを用いることにより、上記課題を解決できることを見出し、本発明に到達した。
【0032】
以下、図面を参照しながら、本発明によるアクティブマトリックス基板の実施形態を説明する。
【0033】
本実施形態のアクティブマトリクス基板の等価回路図を図1に示す。図1のアクティブマトリクスマトリクス基板は、行および列からなるマトリクス状に配列された複数の画素電極と、それぞれ行方向および列方向に配列された複数の走査線(ゲート配線)2および複数の信号線(ソース配線)6を含む複数の配線とを有している。各走査線2と各信号線6との交点近傍には、例えば薄膜トランジスタなどのスイッチング素子20がそれぞれ形成されている。各スイッチング素子20のゲート電極およびソース電極は、複数の走査線2の一つおよび複数の信号線6の一つとそれぞれ電気的に接続されている。また、各スイッチング素子20のドレイン電極は、複数の画素電極の一つと電気的に接続されている。複数のスイッチング素子20を囲むように、バリスタ特性を有する短絡部材3が形成されている。短絡部材3は、例えばZnOまたはZnOを主成分とする化合物から形成された薄膜である。互いに隣接する走査線2および互いに隣接する信号線6は、それぞれ走査線入力端子部4および信号線入力端子部8近傍で、短絡部材3によって接続されている。
【0034】
本実施形態では、ZnOを用いて短絡部材3を構成しているが、本発明はこれに限定されない。ZnOの代わりに、バリスタ特性を有する他の材料を用いて短絡部材3を構成してもよい。また、互いに隣り合う2本または3本以上の線(走査線2または信号線6)を接続する複数の短絡部材3を構成してもよいし、全ての線を接続する1本の短絡部材3(すなわちショートリング)を構成してもよい。さらに、短絡部材3は、互いに隣り合う走査線2の間と互いに隣り合う信号線6の間との両方に形成されてもよいし、どちらか一方にのみ形成されていてもよい。
【0035】
なお、短絡部材3は、複数の走査線2のうち、互いに隣り合う少なくとも2本の走査線2の間または複数の信号線6のうち互いに隣り合う少なくとも2本の信号線6の間に形成されていればよい。
【0036】
本実施形態では、走査線2または信号線6と短絡部材3とは入力端子部近傍で接続されているが、接続される位置はこれに限られない。例えばZnOまたはZnOを主成分とする化合物を用いて透明な短絡部材3を形成する場合、短絡部材3はアクティブマトリクス基板の表示領域に形成されてもよい。例えば、短絡部材3は画素電極と重なって形成されてもよい。
【0037】
本実施形態では、スイッチング素子20として薄膜トランジスタを用いているが、スイッチング素子20はこれに限定されない。代わりに、MOSFET(Metal−Oxide−Semiconductor Field Effect Transistor)などの他の三端子素子や、MIM(Metal−Insulator―Metal)素子などの二端子素子を用いることもできる。二端子素子を用いる場合、各二端子素子は複数の配線(典型的には信号線)の一つと複数の画素電極の一つとを接続するので、短絡部材3は、複数の配線(信号線)のうち互いに隣接する少なくとも2本を接続するように形成される。
【0038】
(実施形態1)
次に、図2を参照しながら、本実施形態のアクティブマトリクス基板における短絡部材3と信号線との接続部分の構成を説明する。
【0039】
図2(a)および(b)は、本実施形態のアクティブマトリクス基板における信号線入力端子部分の断面図および平面図を示す。図2(a)は図2(b)のA−A’線の断面図である。図2(a)および(b)に示す例では、基板1の上に、ゲート絶縁層11を介して複数の信号線(ソース配線)6が設けられている。複数の信号線6のうち互いに隣接する信号線6は、信号線6の上に形成された短絡部材3を介して接続されている。なお、本実施形態における各短絡部材3は、それぞれ2本の信号線のみを接続しているが、3本以上の信号線を接続していてもよい。
【0040】
続いて、図4を参照しながら、本実施形態のアクティブマトリクス基板の製造方法を説明する。図4(a)〜(d)は、各製造工程における、図1に示すようなアクティブマトリクス基板のうち、走査線入力端子が形成される部分、TFTが形成される部分および信号線入力端子が形成される部分(以下、それぞれ「走査線入力端子部」、「TFT部」および「信号線入力端子部」と称する)の模式的な断面図を示す。なお、走査線入力端子は、走査線2に走査信号を送るための入力端子であり、信号線入力端子は、信号線6にデータ信号を送るための入力端子である。
【0041】
まず、基板1を用意する。基板1は、TFTなどが形成される表面が絶縁性表面であればよく、石英基板、ガラス基板以外に表面が絶縁層で覆われたSi基板や金属基板でもよい。本実施形態では、基板1として、コーニング社製1737ガラスなどの無アルカリガラス基板を用いる。
【0042】
次に、図4(a)に示すように、基板1の上にゲート電極10、走査線(ゲート配線)2、走査線入力端子4および信号線入力端子8を、例えばタンタル(Ta)を用いて以下のような方法で同時に形成する。まず、スパッタ法などにより基板1上にTaを堆積した後、Ta上にゲート電極10、走査線2、走査線入力端子4および信号線入力端子8を規定するパターンを有するフォトレジストを形成する。このフォトレジストをマスクとしてTaをドライエッチングすることによって、Taをパターニングする。この後、フォトレジストを剥離する。
【0043】
続いて、図4(b)に示すように、ゲート絶縁層11、半導体層12およびコンタクト層13を形成する。ゲート絶縁層11は、例えばプラズマCVD法によりSiNxを用いて形成する。TFT部では、ゲート絶縁層11の上に、半導体層12およびコンタクト層13をゲート電極10の少なくとも一部を覆うように形成する。半導体層12およびコンタクト層13の形成は、例えばプラズマCVD法により、アモルファスシリコン(a−Si)およびn+シリコンをゲート絶縁層11上に順次堆積させた後、パターニングすることにより行う。この後、走査線入力端子4および信号線入力端子8上のゲート絶縁層11を、例えばドライエッチングによって除去する。
【0044】
この後、図4(c)に示すように、ソース電極およびドレイン電極14、信号線(ソース配線)6、走査線(ゲート配線)2と短絡部材3とを接続する接続線15を、例えばTaを用いて以下に説明するような方法で形成する。まず、スパッタ法によりTaを堆積した後、Ta上にソース電極およびドレイン電極14、信号線6および接続線15のパターンを有するフォトレジストを形成する。このフォトレジストをマスクとしてTaをドライエッチングすることによって、Taをパターニングする。このパターニングにより、TFT部には、コンタクト層13上にソース電極およびドレイン電極14が形成され、信号線入力端子部には、信号線入力端子8と接続された信号線6が形成され、走査線入力端子部には、走査線2と接続された接続線15が形成される。また、このパターニングの際に、ソース電極とドレイン電極との間に位置するコンタクト層13も同時にエッチングされるので、ソース電極とドレイン電極とは絶縁される。パターニング後、フォトレジストを剥離する。さらに、このパターニングにより、走査線2と信号線6とを電気的に接続する配線も同時に形成できる。
【0045】
次に、図4(d)に示すように、接続線15および信号線6の上に、例えばZnOを用いて短絡部材3を形成する。短絡部材3の形成は、例えば以下のような方法で行う。まず、ZnOターゲットを用いたスパッタリング法によって、ArとO2との混合ガス雰囲気中でZnOを堆積する。この後、500℃以上600℃以下の温度で、酸素又は空気雰囲気中でZnOを熱処理することによって、ZnOを結晶成長させる。あるいは、ZnOにエキシマレーザー等を照射すること(レーザーアニール)によって結晶成長させてもよい。レーザーアニールを行う場合は、ZnOを部分的に結晶成長させることも可能である。このような熱処理(レーザーアニールを含む)により、好ましくは、抵抗率が105Ω・cm以上108Ω・cm以下で、結晶のC軸が基板1の表面に対して垂直に配向したZnOを形成する。次いで、公知のフォトリソグラフィー工程で所定のレジストパターンを形成した後、酢酸を用いてZnOをエッチングする。これにより、短絡部材3(またはショートリング)が得られる。信号線入力端子部では、この短絡部材3によって、信号線6は隣接する信号線と接続される。また、走査線入力端子部では、走査線2は接続線15を介して短絡部材3と接続され、またその走査線2と隣接する走査線も接続線15を介して同一の短絡部材と接続されるので、走査線2と隣接する走査線との接続が確保される。
【0046】
本実施形態では、ZnOを用いて短絡部材3を形成しているが、短絡部材3の材料は、ZnOに限定されず、バリスタ特性を示すものであればよい。例えば、Bi、Mn、Co、Sb、Ti等の酸化物を含有したZnOを用いて短絡部材3を形成すると、より安定したバリスタ特性が得られる。
【0047】
また、多数の短絡部材3がそれぞれ2本の線のみを接続するように形成されていてもよいし、3本以上の線を接続するように形成されていてもよい。あるいは、1本の短絡部材3が全ての線を接続するように形成されていてもよい。1本の短絡部材3が全ての線を接続するように形成される(すなわちショートリングである)場合は、複数の短絡部材を有する場合と比べて、短絡部材3のパターニングの際に要求される位置合わせの精度が低いので、有利である。
【0048】
図6は、本実施形態における短絡部材3のI−V特性を示す図である。図6に示すI−V特性は、抵抗率105Ω・cm、膜厚100nmのZnOを用いて、互いに隣接する信号線(ソース配線)の間に線幅10μm、線長100μmのバリスタ特性を有する短絡部材3を形成し、この信号線間に電圧を印加した場合のI−V特性である。短絡部材3のバリスタ電圧は50Vとしている。
【0049】
信号線6間に印加する電圧がこのバリスタ電圧以下のとき、信号線6間の抵抗値(すなわち短絡部材3の抵抗値)は211Ωとなる。従って、この短絡部材3は、従来のショートリング、例えば図8に示すようなリンドープn+アモルファスシリコンを用いて形成された高抵抗ショートリング(抵抗値:数MΩ)よりも高い絶縁性を有している。そのため、互いに隣接する信号線の間は完全に絶縁されていると考えられる。信号線6間に印加する電圧がバリスタ電圧である50Vを超えると、短絡部材3の抵抗値が急激に低下するので、信号線6間は電気的に接続される。
【0050】
短絡部材3のバリスタ電圧は、短絡部材3を形成するZnOまたはZnOを主成分とする化合物の結晶粒子径、膜厚、線幅、線長などを変えることで任意に設定できる。例えば、本実施形態のアクティブマトリックス基板を表示装置に適用した場合において、走査線電圧Vgh、Vglをそれぞれ15V、−10Vとすると、表示装置の動作時には、互いに隣接する走査線間には最大で25Vの電位差が生じることになる。このような場合のバリスタ電圧は、隣接する走査線間に最大25Vの電位差が生じても互いの信号が影響を受けないように、25Vより大きいことが好ましい。このように、短絡部材3のバリスタ電圧を、表示装置の動作時に互いに隣接する線間に生じる電位差の最大値よりも高く設定することによって、その表示装置の通常の表示動作時には、短絡部材3によって接続された線同士は短絡状態にならないので、駆動ドライバからの信号を各線に与えることが可能になる。一方、TFTのゲート絶縁層を静電気から確実に保護するためには、バリスタ電圧は100V以下であることが好ましい。より好ましいバリスタ電圧は、40V以上70V以下である。
【0051】
(実施形態2)
次に、図3を参照しながら、実施形態2のアクティブマトリクス基板における短絡部材3(またはショートリング3)と信号線との接続部分の構成を説明する。
【0052】
図3(a)および(b)は、本実施形態のアクティブマトリクス基板における信号線入力端子部分の断面図および平面図を示す。図3(a)は図3(b)のB−B’線の断面図である。本実施形態は、図3(a)および(b)に示すように、短絡部材3が信号線(ソース配線)6の下、すなわち信号線6とゲート絶縁層11との間に設けられている点で実施形態1と異なっている。このような構成は、TFTの半導体層をZnOまたはZnOを主成分とする化合物を用いて形成する場合に、短絡部材3とTFTの半導体層とを同時に形成できるので有利である(例えば特開2000−150900号公報に、ZnOまたはその化合物を用いてTFTの半導体層を形成する技術が開示されている)。なお、実施形態1と同様に、短絡部材3は3本以上の信号線を接続するパターンを有していてもよく、例えばショートリングであってもよい。
【0053】
続いて、図5を参照しながら、本実施形態のアクティブマトリクス基板の製造方法を説明する。図5(a)および(b)は、図4と同様に、走査線入力端子部、TFT部および信号線入力端子部における模式的な断面図を示す。
【0054】
まず、実施形態1と同様の工程によって、図5(a)に示すように、基板1の上にゲート電極10、走査線(ゲート配線)2、走査線入力端子4および信号線入力端子8を、例えばTaを用いて同時に形成する。
【0055】
続いて、実施形態1と同様の工程によって、ゲート絶縁層11を例えばSiNxを用いて形成する。この後、ゲート絶縁層11の上に、例えばZnOを用いて半導体層12および短絡部材3を形成する。半導体層12および短絡部材3の形成は、例えば以下のようにして行う。まず、ZnOターゲットを用いたスパッタリング法によって、ArとO2との混合ガス雰囲気中でZnOを堆積する。この後、酸素又は空気雰囲気中でZnOを熱処理することによって、ZnOを結晶成長させる。あるいは、ZnOにエキシマレーザー等を照射すること(レーザーアニール)によって結晶成長させてもよい。熱処理の温度などの好ましい結晶成長条件は、典型的には、堆積させたZnOのうち、半導体層12となる部分と短絡部材3となる部分とで異なる。例えば、ZnOのうち半導体層12となる部分には、200℃以上400℃以下の温度T1で熱処理を行い、ZnOのうち短絡部材3となる部分には、T1よりも高い温度T2(例えばT2は500℃以上600℃以下)で熱処理を行う。これにより、ZnOのうち短絡部材3となる部分の結晶粒径は、半導体層12となる部分の結晶粒径よりも大きくなる。このように部分的にZnOの熱処理条件を変える場合には、レーザーアニールによる熱処理方法が好ましい。あるいは、上記のZnOを堆積する工程において、基板温度を例えば250℃に設定してスパッタリングを行うことにより、結晶状態のZnOを堆積させることができる。この場合、ZnOのうち短絡部材3となる部分にはレーザーアニールなどの熱処理を行うことにより、バリスタ特性を有するようにZnOをさらに結晶成長させ、一方、ZnOのうち半導体層12となる部分には熱処理を施さないことも可能である。
【0056】
上記の熱処理条件は、それぞれ所望の特性を有する半導体層12および短絡部材3が形成されるように適宜選択される。典型的には、結晶粒径が10nm以上30nm未満のZnOは半導体層12としても好適な特性を有し、結晶粒径が30nm以上であるZnOは短絡部材3として好適なバリスタ特性を有する。また、短絡部材3がバリスタ特性を確実に発揮するためには、接続する2本の線の間に結晶粒界が存在する必要があるので、短絡部材3の結晶粒径は、短絡部材3によって接続される走査線または信号線の線幅以下であることが好ましい。さらに、好適な短絡部材3を得るには、ZnOのうち短絡部材3となる部分を、105Ω・cm以上108Ω・cm以下の抵抗率を有し、かつ結晶のC軸が基板1の表面に対して垂直に配向するようにZnOを結晶成長させることが望ましい。
【0057】
次いで、公知のフォトリソグラフィー工程でレジストパターンを形成した後、例えば酢酸を用いてZnOをエッチングすることにより、ZnOをパターニングする。これにより、短絡部材3および半導体層12が同時に形成される。なお、短絡部材3のパターニングと半導体層12のパターニングとを別個の工程で行ってもよい。この後、走査線入力端子4および信号線入力端子8上のゲート絶縁層11を、例えばドライエッチングによって除去する。
【0058】
続いて、実施形態1と同様の方法で、ソース電極およびドレイン電極14、信号線(ソース配線)6、接続線15を、例えばTaを用いて形成する。なお、本実施形態では、TaはZnOに対してオーミックコンタクトが可能であるので、実施形態1のようにコンタクト層13を設ける必要はない。この結果、信号線入力端子部では、この短絡部材3によって、信号線6は隣接する信号線と接続される。また、走査線2は接続線15を介して短絡部材3と接続され、またその走査線2と隣接する走査線も接続線15を介して同一の短絡部材と接続されるので、走査線2と隣接する走査線との接続が確保される。
【0059】
なお、本実施形態における短絡部材3と実施形態1における短絡部材3とは、形成される位置は異なっているが、同様の機能および特性(例えばI−V特性など)を有する。
【0060】
上記実施形態のアクティブマトリクス基板は、上述したような短絡部材を有しているので、短絡部材によって接続された線間の電位差がバリスタ電圧以下では、リーク電流をほとんど生じない。また、本実施形態における短絡部材は電荷分散性が高く、アクティブマトリクス基板のTFTを静電気から確実に保護できる。さらに、本実施形態における短絡部材はアクティブマトリクス基板の駆動を妨げないため、駆動ドライバを実装した後に、短絡部材を除去する必要がない。従って、アクティブマトリクス基板の製造工程において生じる静電気に起因する製品不良を低減することができる。
【0061】
また、本実施形態のアクティブマトリクス基板の製造方法によると、上述したようなアクティブマトリクス基板を簡便に製造できる。特に、TFTの半導体層と短絡部材とを同じ材料を用いて同時に形成すると、製造工程を増加させたり、製造コストを増大させたりする必要がないので有利である。
【0062】
【発明の効果】
アクティブマトリクス基板の実装工程後も機能し、かつ電荷分散性の高い簡便な構造の短絡部材を備えることにより、低電圧領域においてリーク電流をほとんど生じることなく、静電気からTFTを有効に保護することができるアクティブマトリクス基板を提供することができる。
【0063】
本発明は、アクティブマトリクス基板を備えた液晶表示装置やEL表示装置などの各種表示装置に好適に適用される。
【図面の簡単な説明】
【図1】本発明の実施形態によるアクティブマトリクス基板の等価回路を示す図である。
【図2】(a)および(b)は、それぞれ本発明の第1の実施形態のアクティブマトリクス基板における短絡部材を模式的に示す断面図および平面図である。
【図3】(a)および(b)は、それぞれ本発明の第2の実施形態のアクティブマトリクス基板における短絡部材を模式的に示す断面図および平面図である。
【図4】(a)〜(d)は、本発明の第1の実施形態のアクティブマトリクス基板の製造方法を説明するための模式的な断面図である。
【図5】(a)および(b)は、本発明の第2の実施形態のアクティブマトリクス基板の製造方法を説明するための模式的な断面図である。
【図6】本発明の実施形態における短絡部材のI−V特性を示す図である。
【図7】従来の導電性ショートリングを有するアクティブマトリクス基板の等価回路を示す図である。
【図8】従来の高抵抗半導体ショートリングを有するアクティブマトリクス基板の等価回路を示す図である。
【図9】従来の2端子素子からなるショートリングを有するアクティブマトリクス基板の等価回路を示す図である。
【符号の説明】
1 基板
2 走査線
3 短絡部材
4 走査線入力端子
5 入力保護回路
6 信号線
7 導電性ライン
8 信号線入力端子
9 高抵抗半導体ショートリング
10 ゲート電極
11 ゲート絶縁層
12 半導体層
14 ソース電極およびドレイン電極
20 TFT[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix substrate and a method of manufacturing the same, and various display devices such as a liquid crystal display device and an EL display device including the active matrix substrate.
[0002]
[Prior art]
The active matrix type liquid crystal display device includes a switching element for each pixel, so that high-definition and high-quality display can be performed. As the switching element, a non-linear element such as a thin film transistor (hereinafter sometimes referred to as “TFT”) or a diode is used. Above all, TFTs using amorphous silicon or polycrystalline silicon are widely used.
[0003]
Normally, a manufacturing process of an active matrix type liquid crystal display device includes many steps that easily generate static electricity (for example, a rubbing step). However, amorphous silicon and polycrystalline silicon used for TFTs are easily damaged by static electricity. Therefore, in the manufacturing process of the liquid crystal display device, the characteristics of the TFT are changed or the TFT itself is destroyed due to static electricity, and thus there is a problem that the non-defective product rate is reduced.
[0004]
Therefore, an active matrix substrate provided with various means for protecting a TFT from static electricity generated in a manufacturing process of a liquid crystal display device has been proposed or adopted.
[0005]
Patent Document 1 discloses the active matrix substrate shown in FIG. In this active matrix substrate, a conductive line (conductive short ring) 7 is formed on the outermost side of the substrate, and all the scanning lines and signal lines provided on the substrate are electrically connected by the
[0006]
In addition, as shown in FIG. 8,
[0007]
Further,
[0008]
[Patent Document 1]
JP-A-61-059475
[Patent Document 2]
Japanese Patent Publication No. 5-47813
[Patent Document 3]
JP-A-10-20336
[0009]
[Problems to be solved by the invention]
The above-described active matrix substrate has the following problems.
[0010]
Although the active matrix substrate of FIG. 7 has excellent charge dispersion, it is necessary to remove the conductive short ring before mounting the driving driver. Therefore, if static electricity is generated in the mounting process after the removal, the TFT cannot be sufficiently protected from the static electricity.
[0011]
On the other hand, in the active matrix substrate of FIG. 8, it is not necessary to remove the short ring before the mounting process. However, a semiconductor layer (phosphorus-doped n + Since a short ring made of amorphous silicon or the like basically has a linear resistance with respect to a voltage, a small leak current occurs even if the voltage applied to this short ring is low, and as a result, driving of a TFT becomes difficult. May have adverse effects. In order to prevent this, the short ring needs to have a somewhat high resistance. The charge dispersibility of such a high resistance short ring is lower than that of the conductive short ring of FIG. In addition, since the selection of the resistance value of the short ring and the output impedance of the drive driver is restricted, there is a problem that the degree of freedom in designing an active matrix substrate and a display panel using the same is hindered. Further, amorphous silicon is used for the semiconductor layer, and n is used for the contact layer. + In a manufacturing process using amorphous silicon, there is a problem that a shortening process of etching a gap portion of a TFT using a source / drain electrode as a mask cannot be employed.
[0012]
The active matrix substrate of FIG. 9 has a clearly more complicated structure than an active matrix substrate having a short ring as shown in FIG. 7 or FIG. Therefore, a manufacturing technique higher than the manufacturing technique of the active matrix substrate shown in FIGS. 7 and 8 is required. For example, it is necessary to form a switching element at a predetermined position without a defect. Another problem is that the characteristics of a plurality of switching elements formed on a glass substrate tend to vary depending on the positions of these elements in the substrate. In order to suppress such variations and make the characteristics of the switching elements uniform, more restrictions are imposed, for example, the size of the substrate cannot be increased.
[0013]
The present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a short-circuit member having a simple structure that functions even after a driving driver mounting process and has a high charge dispersibility and a simple structure. It is an object of the present invention to provide an active matrix substrate that can effectively protect a TFT from static electricity with almost no leakage current in a voltage region.
[0014]
[Means for Solving the Problems]
An active matrix substrate according to the present invention includes a substrate, a plurality of pixel electrodes formed on the substrate, a plurality of wirings, and at least one of the plurality of pixel electrodes and at least one of the plurality of wirings. A plurality of switching elements to electrically connect, and a short-circuit member having the characteristics of a varistor, comprising a short-circuit member connecting at least two wirings adjacent to each other among the plurality of wirings, Thereby, the above object is achieved.
[0015]
In a preferred embodiment, the plurality of wirings include a plurality of scanning lines and a plurality of signal lines intersecting the plurality of scanning lines, and the plurality of switching elements each include a gate electrode, a drain electrode, and a source. An electrode, wherein the gate electrode is electrically connected to one of the plurality of scanning lines, the drain electrode is electrically connected to one of the plurality of pixel electrodes, and the source electrode is electrically connected to one of the plurality of signal lines. The short-circuit member connects at least two adjacent signal lines of the plurality of signal lines and / or at least two adjacent scan lines of the scan signal lines.
[0016]
In a preferred embodiment, the short-circuit member includes ZnO or a compound containing ZnO as a main component.
[0017]
The ZnO or the compound containing ZnO as a main component contained in the short-circuit member preferably has a crystal grain size of 30 nm or more and a line width of each of the plurality of wirings.
[0018]
In a preferred embodiment, the switching element has a semiconductor layer, and the semiconductor layer contains ZnO or a compound containing ZnO as a main component.
[0019]
Each of the semiconductor layer and the short-circuit member may include ZnO, and a crystal grain size of ZnO included in the semiconductor layer may be smaller than a crystal grain size of ZnO included in the short-circuit member.
[0020]
The varistor voltage of the short-circuit member is, when the active matrix substrate is applied to a display device, a potential difference generated between the at least two signal lines and / or the at least two scan lines during operation of the display device. It is preferably higher than the maximum value and lower than 100V.
[0021]
The short-circuit member may be provided between the substrate and the at least two signal lines.
[0022]
A display device according to the present invention includes any one of the active matrix substrates described above.
[0023]
The manufacturing method of the present invention includes a substrate, a plurality of pixel electrodes, a plurality of wirings, and a plurality of switchings each electrically connecting at least one of the plurality of pixel electrodes and at least one of the plurality of wirings. A method for manufacturing an active matrix substrate, comprising: an element; and a short-circuit member for connecting at least two wirings adjacent to each other among the plurality of wirings, the method including a step of forming the short-circuit member, Forming a film on the substrate, and performing a first patterning patterning the film, wherein the short-circuit member has varistor characteristics, whereby the Objective is achieved.
[0024]
In a preferred embodiment, the plurality of wirings include a plurality of scanning lines and a plurality of signal lines, and the short-circuit member is at least two scanning lines and / or the plurality of scanning lines adjacent to each other among the plurality of scanning lines. At least two signal lines adjacent to each other among the signal lines are connected.
[0025]
In a preferred embodiment, each of the plurality of switching elements has a semiconductor layer, and includes a step of forming the semiconductor layer by performing a second patterning for patterning the film.
[0026]
The first patterning and the second patterning may be performed simultaneously.
[0027]
A first pattern is obtained by the first patterning, and the step of forming the short-circuit member may include a step of heat-treating the first pattern at a first temperature.
[0028]
A second pattern is obtained by the second patterning, and the step of forming the semiconductor layer may include a step of heat-treating the second pattern at a second temperature lower than the first temperature.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the present invention, a scan line or a signal line is short-circuited by using a thin film varistor formed using, for example, zinc oxide (ZnO) or a compound containing zinc oxide (ZnO) as a main component in an active matrix substrate. It constitutes a short-circuit member or a short ring. In this specification, a “short-circuit member” means a member that electrically connects two or more lines (scanning lines and signal lines) under certain conditions, and widely includes a varistor, a resistor, a TFT, and the like. . Further, when all the wires included in the active matrix substrate are connected in a ring shape via a short-circuit member as in the related art shown in FIGS. 7 and 8, such a short-circuit member is particularly referred to as a “short ring”. May be called.
[0030]
Conventionally, ZnO has been known to be a material that exhibits nonlinear resistance characteristics by forming a double Schottky barrier at its crystal grain boundary. Many techniques for forming a voltage non-linear resistance element varistor using ZnO and techniques using such a varistor have been proposed (for example, Japanese Patent Publication No. 62-36606 and Japanese Patent No. 2912081). However, no attempt has been made to use the nonlinear resistance characteristics of ZnO for an active matrix substrate.
[0031]
The present inventors have found that the above problems can be solved by using a thin film varistor formed using ZnO and a compound containing ZnO as a main component in an active matrix substrate such as a liquid crystal display device, and the present invention. did.
[0032]
Hereinafter, an embodiment of an active matrix substrate according to the present invention will be described with reference to the drawings.
[0033]
FIG. 1 shows an equivalent circuit diagram of the active matrix substrate of the present embodiment. The active matrix substrate of FIG. 1 includes a plurality of pixel electrodes arranged in a matrix of rows and columns, a plurality of scanning lines (gate lines) 2 and a plurality of signal lines arranged in the row and column directions, respectively. (Source wiring) 6 and a plurality of wirings. In the vicinity of the intersection between each scanning
[0034]
In the present embodiment, the short-
[0035]
The short-
[0036]
In the present embodiment, the
[0037]
In the present embodiment, a thin film transistor is used as the switching element 20, but the switching element 20 is not limited to this. Alternatively, another three-terminal element such as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or a two-terminal element such as an MIM (Metal-Insulator-Metal) element can be used. When a two-terminal element is used, each two-terminal element connects one of a plurality of wirings (typically, signal lines) and one of a plurality of pixel electrodes. Are formed to connect at least two adjacent to each other.
[0038]
(Embodiment 1)
Next, a configuration of a connection portion between the short-
[0039]
2A and 2B are a cross-sectional view and a plan view of a signal line input terminal portion of the active matrix substrate according to the present embodiment. FIG. 2A is a cross-sectional view taken along line AA ′ of FIG. 2B. In the example shown in FIGS. 2A and 2B, a plurality of signal lines (source lines) 6 are provided on the substrate 1 with a
[0040]
Subsequently, a method for manufacturing the active matrix substrate of the present embodiment will be described with reference to FIG. FIGS. 4A to 4D show, in each manufacturing process, a portion where a scanning line input terminal is formed, a portion where a TFT is formed, and a signal line input terminal of the active matrix substrate as shown in FIG. FIG. 2 is a schematic cross-sectional view of a formed portion (hereinafter, referred to as a “scanning line input terminal portion”, a “TFT portion”, and a “signal line input terminal portion”). The scanning line input terminal is an input terminal for sending a scanning signal to the
[0041]
First, the substrate 1 is prepared. The substrate 1 may be an insulating surface on which a TFT or the like is formed, and may be a Si substrate or a metal substrate whose surface is covered with an insulating layer other than a quartz substrate or a glass substrate. In the present embodiment, a non-alkali glass substrate such as Corning 1737 glass is used as the substrate 1.
[0042]
Next, as shown in FIG. 4A, a
[0043]
Subsequently, as shown in FIG. 4B, a
[0044]
Thereafter, as shown in FIG. 4C, a
[0045]
Next, as shown in FIG. 4D, the short-
[0046]
In the present embodiment, the short-
[0047]
Further, a number of short-
[0048]
FIG. 6 is a diagram illustrating IV characteristics of the short-
[0049]
When the voltage applied between the
[0050]
The varistor voltage of the short-
[0051]
(Embodiment 2)
Next, a configuration of a connection portion between the short-circuit member 3 (or the short ring 3) and the signal line in the active matrix substrate according to the second embodiment will be described with reference to FIG.
[0052]
3A and 3B are a cross-sectional view and a plan view of a signal line input terminal portion of the active matrix substrate according to the present embodiment. FIG. 3A is a cross-sectional view taken along line BB ′ of FIG. In this embodiment, as shown in FIGS. 3A and 3B, the short-
[0053]
Subsequently, a method for manufacturing the active matrix substrate of the present embodiment will be described with reference to FIG. FIGS. 5A and 5B are schematic cross-sectional views of the scanning line input terminal portion, the TFT portion, and the signal line input terminal portion, similarly to FIG.
[0054]
First, as shown in FIG. 5A, a
[0055]
Subsequently, the
[0056]
The above heat treatment conditions are appropriately selected so that the
[0057]
Next, after a resist pattern is formed by a known photolithography process, the ZnO is patterned by etching the ZnO using, for example, acetic acid. Thereby, the short-
[0058]
Subsequently, in the same manner as in the first embodiment, the source and drain
[0059]
The short-
[0060]
Since the active matrix substrate of the above-described embodiment has the short-circuit member as described above, almost no leak current occurs when the potential difference between the lines connected by the short-circuit member is equal to or less than the varistor voltage. In addition, the short-circuit member according to the present embodiment has high charge dispersibility, and can reliably protect the TFT of the active matrix substrate from static electricity. Further, since the short-circuit member in the present embodiment does not hinder the driving of the active matrix substrate, there is no need to remove the short-circuit member after mounting the drive driver. Therefore, it is possible to reduce product defects due to static electricity generated in the manufacturing process of the active matrix substrate.
[0061]
Further, according to the method for manufacturing an active matrix substrate of the present embodiment, the above-described active matrix substrate can be easily manufactured. In particular, it is advantageous to form the TFT semiconductor layer and the short-circuit member at the same time using the same material, because it is not necessary to increase the number of manufacturing steps or increase the manufacturing cost.
[0062]
【The invention's effect】
By providing a short-circuit member that functions even after the mounting process of the active matrix substrate and has a simple structure with high charge dispersibility, TFTs can be effectively protected from static electricity with almost no leakage current in the low voltage region. An active matrix substrate that can be provided.
[0063]
INDUSTRIAL APPLICABILITY The present invention is suitably applied to various display devices such as a liquid crystal display device and an EL display device having an active matrix substrate.
[Brief description of the drawings]
FIG. 1 is a diagram showing an equivalent circuit of an active matrix substrate according to an embodiment of the present invention.
FIGS. 2A and 2B are a cross-sectional view and a plan view, respectively, schematically illustrating a short-circuit member in the active matrix substrate according to the first embodiment of the present invention.
FIGS. 3A and 3B are a cross-sectional view and a plan view schematically showing a short-circuit member in an active matrix substrate according to a second embodiment of the present invention.
FIGS. 4A to 4D are schematic cross-sectional views illustrating a method for manufacturing an active matrix substrate according to the first embodiment of the present invention.
FIGS. 5A and 5B are schematic cross-sectional views illustrating a method for manufacturing an active matrix substrate according to a second embodiment of the present invention.
FIG. 6 is a diagram showing IV characteristics of a short-circuit member according to the embodiment of the present invention.
FIG. 7 is a diagram showing an equivalent circuit of a conventional active matrix substrate having a conductive short ring.
FIG. 8 is a diagram showing an equivalent circuit of a conventional active matrix substrate having a high-resistance semiconductor short ring.
FIG. 9 is a diagram showing an equivalent circuit of a conventional active matrix substrate having a short ring composed of two-terminal elements.
[Explanation of symbols]
1 substrate
2 scan lines
3 Short circuit member
4 Scan line input terminal
5 Input protection circuit
6 signal lines
7 Conductive line
8 Signal line input terminal
9 High resistance semiconductor short ring
10 Gate electrode
11 Gate insulating layer
12 Semiconductor layer
14 Source and drain electrodes
20 TFT
Claims (15)
前記基板の上に形成された複数の画素電極と、
複数の配線と、
それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、
バリスタの特性を有する短絡部材であって、前記複数の配線のうち互いに隣接する少なくとも2本の配線を接続する短絡部材と
を有する、アクティブマトリクス基板。Board and
A plurality of pixel electrodes formed on the substrate,
Multiple wires,
A plurality of switching elements each electrically connecting at least one of the plurality of pixel electrodes and at least one of the plurality of wirings,
An active matrix substrate, comprising: a short-circuit member having characteristics of a varistor, wherein the short-circuit member connects at least two wirings adjacent to each other among the plurality of wirings.
前記複数のスイッチング素子は、それぞれがゲート電極、ドレイン電極およびソース電極を備え、前記ゲート電極が前記複数の走査線の一つと、前記ドレイン電極が前記複数の画素電極の一つと、前記ソース電極が前記複数の信号線の一つとそれぞれ電気的に接続されており、
前記短絡部材は、前記複数の信号線のうち互いに隣接する少なくとも2本の信号線および/または前記走査の信号線のうち互いに隣接する少なくとも2本の走査線を接続する、請求項1に記載のアクティブマトリクス基板。The plurality of wirings include a plurality of scanning lines and a plurality of signal lines intersecting with the plurality of scanning lines,
The plurality of switching elements each include a gate electrode, a drain electrode, and a source electrode, and the gate electrode is one of the plurality of scanning lines, the drain electrode is one of the plurality of pixel electrodes, and the source electrode is Each of which is electrically connected to one of the plurality of signal lines,
2. The short circuit member according to claim 1, wherein at least two adjacent signal lines of the plurality of signal lines and / or at least two adjacent scan lines of the scanning signal lines are connected. 3. Active matrix substrate.
複数の画素電極と、
複数の配線と、
それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、
前記複数の配線のうち互いに隣接するすくなくとも2本の配線を接続する短絡部材と
を備えたアクティブマトリクス基板の製造方法であって、前記短絡部材を形成する工程を包含し、前記短絡部材を形成する工程は、
前記基板の上に膜を堆積する工程と、
前記膜をパターニングする第1パターニングを行う工程と
を含み、前記短絡部材はバリスタ特性を有する、製造方法。Board and
A plurality of pixel electrodes;
Multiple wires,
A plurality of switching elements each electrically connecting at least one of the plurality of pixel electrodes and at least one of the plurality of wirings,
A method of manufacturing an active matrix substrate including a short-circuit member connecting at least two wires adjacent to each other among the plurality of wires, the method including a step of forming the short-circuit member, and forming the short-circuit member. The process is
Depositing a film on the substrate;
Performing a first patterning for patterning the film, wherein the short-circuit member has varistor characteristics.
前記短絡部材は前記複数の走査線のうち互いに隣接するすくなくとも2本の走査線および/または前記複数の信号線のうち互いに隣接する少なくとも2本の信号線を接続する、請求項10に記載のアクティブマトリクス基板の製造方法。The plurality of wirings include a plurality of scanning lines and a plurality of signal lines,
The active device according to claim 10, wherein the short-circuit member connects at least two scanning lines adjacent to each other among the plurality of scanning lines and / or at least two signal lines adjacent to each other among the plurality of signal lines. A method for manufacturing a matrix substrate.
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