JP2004273732A - Active matrix substrate and its producing process - Google Patents

Active matrix substrate and its producing process Download PDF

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Publication number
JP2004273732A
JP2004273732A JP2003061985A JP2003061985A JP2004273732A JP 2004273732 A JP2004273732 A JP 2004273732A JP 2003061985 A JP2003061985 A JP 2003061985A JP 2003061985 A JP2003061985 A JP 2003061985A JP 2004273732 A JP2004273732 A JP 2004273732A
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plurality
short
circuit member
matrix substrate
active matrix
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Japanese (ja)
Inventor
Tatsuya Fujita
Masashi Kawasaki
Hisao Ochi
Hideo Ono
Toshinori Sugihara
英男 大野
雅司 川崎
利典 杉原
達也 藤田
久雄 越智
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Masashi Kawasaki
Hideo Ono
Sharp Corp
シャープ株式会社
英男 大野
雅司 川崎
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain an active matrix substrate in which a TFT is protected effectively against static electricity by providing a short circuit member having a convenient structure of high charge dispersiveness and functioning even after a packaging process thereby substantially eliminating a leak current in a low voltage region. <P>SOLUTION: The active matrix substrate comprises a substrate 1, a plurality of pixel electrodes formed on the substrate 1, a plurality of interconnect lines 2 and 6, a plurality of switching elements 20 each connecting at least one of the plurality of pixel electrodes electrically with at least one of the plurality of interconnect lines 2 and 6, and a short circuit member 3 having the characteristics of a varistor. The short circuit member 3 connects at least two adjacent interconnect lines 2 and 6 out of the plurality of interconnect lines 2 and 6. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、アクティブマトリクス基板およびその製造方法、ならびにアクティブマトリクス基板を備えた液晶表示装置やEL表示装置などの各種表示装置に関する。 The present invention is an active matrix substrate and a manufacturing method thereof, and to various display devices such as liquid crystal display devices and EL display device including the active matrix substrate.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
アクティブマトリクス型の液晶表示装置は、画素毎にスイッチング素子を備えているため、高繊細で高品位の表示が可能である。 Active matrix liquid crystal display device is provided with the switching element for each pixel, it is possible to display a high-definition and high quality. 上記スイッチング素子としては、薄膜トランジスタ(以下、「TFT」と称することがある)、ダイオード等の非線形素子が用いられる。 As the switching element, a thin film transistor (hereinafter sometimes referred to as "TFT"), non-linear element such as a diode may be used. なかでも、アモルファスシリコンまたは多結晶シリコンを用いたTFTが広く用いられている。 Of these, TFT is widely used using amorphous silicon or polycrystalline silicon.
【0003】 [0003]
通常、アクティブマトリクス型の液晶表示装置の製造工程には、静電気を生じやすい工程(例えばラビング工程など)が多く含まれている。 Typically, the manufacturing process of an active matrix type liquid crystal display device, prone to static process (e.g. rubbing process, etc.) is included much. しかし、TFTに用いられるアモルファスシリコンや多結晶シリコンは、静電気による損傷を受けやすい。 However, amorphous silicon or polycrystalline silicon used for the TFT is susceptible to damage from static electricity. 従って、液晶表示装置の製造工程において、静電気によって、TFTの特性が変化したり、TFT自体が破壊されたりするので、製品の良品率を低下させるという問題があった。 Accordingly, in a manufacturing process of a liquid crystal display device, the static electricity may change the characteristics of TFT, since TFT itself or break, there is a problem that lowering the yield rate of the product.
【0004】 [0004]
そこで、液晶表示装置の製造工程において生じた静電気からTFTを保護するための種々の手段を備えたアクティブマトリクス基板が提案され、または採用されている。 Therefore, the active matrix substrate having various means for protecting the TFT from static electricity generated in the manufacturing process of the liquid crystal display device have been proposed or are employed.
【0005】 [0005]
特許文献1は、図7に示すアクティブマトリクス基板を開示している。 Patent Document 1 discloses an active matrix substrate shown in FIG. このアクティブマトリクス基板では、基板の最も外側に導電性ライン(導電性ショートリング)7が形成されており、この導電性ライン7によって基板に設けられた走査線および信号線は全て電気的に接続されている。 In this active matrix substrate, the outermost to the conductive lines (conductive short ring) 7 of the substrate are formed, the scanning lines and signal lines provided on the substrate by the conductive lines 7 are all electrically connected ing. このような構成により、基板に設けられたいずれかのTFTが帯電した場合でも、この導電性ラインを介して電荷を分散させることができるので、TFTを静電気から保護できる。 With this configuration, even if one of the TFT provided on the substrate is charged, it is possible to disperse the charge through the conductive lines, to protect the TFT from static electricity.
【0006】 [0006]
また、特許文献2には、図8に示すように、高抵抗の半導体層(例えばリンドープのn アモルファスシリコン)からなるショートリング9を有するアクティブマトリクス基板が開示されている。 Further, Patent Document 2, as shown in FIG. 8, the active matrix substrate is disclosed having a short ring 9 made of a semiconductor layer of high resistance (e.g., n + amorphous silicon doped with phosphorus).
【0007】 [0007]
さらに、特許文献3は、図9に示すアクティブマトリクス基板を開示している。 Furthermore, Patent Document 3 discloses an active matrix substrate shown in FIG. このアクティブマトリクス基板では、複数の走査線のうち互いに隣り合う走査線の間および複数の信号線のうち互いに隣り合う信号線の間にスイッチング素子からなる入力保護回路(2端子素子ショートリング)5がそれぞれ挿入されている。 In this active matrix substrate, an input protection circuit (2 terminal device shorting ring) 5 made of a switching element between the signal lines adjacent to each other among and between a plurality of signal lines of the scanning lines adjacent to each other among the plurality of scan lines They are inserted respectively. この入力保護回路5により、1つの線(走査線または信号線)に一定以上の静電気が加わると、その線から、入力保護回路5のスイッチング素子を介して、その線の隣に位置する線に過大な電荷を分散させることができる。 The input protection circuit 5, when the static electricity above a certain one line (scanning line or signal line) is applied, from the line, via the switching elements of the input protection circuit 5, a line which is located next to the line it can be dispersed excessive charge.
【0008】 [0008]
【特許文献1】 [Patent Document 1]
特開昭61−059475号公報【特許文献2】 JP 61-059475 JP Patent Document 2]
特公平5−47813号公報【特許文献3】 JP Kokoku 5-47813 [Patent Document 3]
特開平10−20336号公報【0009】 Japanese Unexamined Patent Publication No. 10-20336 [0009]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
上述したようなアクティブマトリクス基板には、以下のような問題がある。 An active matrix substrate as described above, has the following problems.
【0010】 [0010]
図7のアクティブマトリクス基板は、電荷の分散性は優れているが、駆動用ドライバを実装する前に導電性ショートリングを除去する必要がある。 The active matrix substrate of Figure 7, but is superior dispersibility of the charge, it is necessary to remove the conductive short ring before mounting the driving driver. そのため、除去後の実装工程において静電気が生じると、その静電気からTFTを充分に保護することができない。 Therefore, when static electricity is generated in the mounting process after removal, it can not be sufficiently protect the TFT from the static electricity.
【0011】 [0011]
これに対し、図8のアクティブマトリクス基板では、実装工程の前にショートリングを除去する必要はない。 In contrast, in the active matrix substrate of FIG. 8, there is no need to remove the short ring before the mounting process. しかしながら、特許文献2に例示されたような半導体層(リンドープのn アモルファスシリコンなど)からなるショートリングは、基本的に電圧に対して直線性抵抗となるため、このショートリングに印加される電圧が低くても微小なリーク電流が生じ、その結果、TFTの駆動に悪影響を与える可能性がある。 However, short-circuit ring formed of a semiconductor layer as exemplified in Patent Document 2 (including n + amorphous silicon doped with phosphorus), because the linear resistance against essentially voltage, the voltage applied to the short ring and small leakage current even occurs low, and as a result, may adversely affect the driving of the TFT. これを防ぐために、ショートリングはある程度高い抵抗を有する必要がある。 To prevent this, short ring is required to have a relatively high resistance. そのような高抵抗なショートリングの電荷分散性は、図7の導電性ショートリングの電荷分散性よりも低い。 Charge dispersibility of such high resistance short ring is lower than the charge dispersibility of the conductive short-circuit of FIG. また、ショートリングの抵抗値や駆動ドライバの出力インピーダンスの選択に制約が課されるため、アクティブマトリクス基板やそれを用いた表示パネルの設計の自由度を阻害するという問題もある。 Moreover, there is for constraints on the selection of the output impedance of the resistance and driver of the short ring is imposed, a problem that inhibits the flexibility of the display panel of the design using an active matrix substrate and it. さらに、半導体層にアモルファスシリコン、コンタクト層にn アモルファスシリコンを用いた場合の製造プロセスでは、ソース・ドレイン電極をマスクとしてTFTのギャップ部をエッチングするような短縮プロセスを採用することができないという問題があった。 Further, amorphous silicon semiconductor layer, the manufacturing process in the case of using the n + amorphous silicon contact layer, a problem that can not be employed to shorten the process so as to etch the gap portion of the TFT source-drain electrode as a mask was there.
【0012】 [0012]
図9のアクティブマトリクス基板は、図7または図8に示すようなショートリングを有するアクティブマトリクス基板と比べて明らかに複雑な構造を有している。 The active matrix substrate of FIG. 9 has a clearly complex structure as compared with the active matrix substrate having a short ring, as shown in FIG. 7 or 8. そのため、図7や図8のアクティブマトリクス基板の製造技術よりも高い製造技術が要求される。 Therefore, a high manufacturing technique is required than manufacturing technology of an active matrix substrate of FIGS. 7 and 8. 例えば、所定位置にスイッチング素子を不良なく形成する必要がある。 For example, it is necessary to form defect without a switching element in a predetermined position. また、ガラス基板上に形成される複数のスイッチング素子の特性が、基板内におけるこれらの素子の位置に応じてばらつきやすいという問題もある。 Also, characteristics of a plurality of switching elements formed on a glass substrate, is also a problem that tends to vary depending on the position of these elements in the substrate. このようなばらつきを抑えて、スイッチング素子の特性を均一にするために、例えば基板を大型化できないなどの、より多くの制約が課されている。 Suppressing such variation, in order to equalize the characteristics of the switching element, for example such as the inability upsizing the substrate, are more constraints imposed.
【0013】 [0013]
本発明は、上記事情に鑑みてなされたものであり、その主な目的は、駆動用ドライバの実装工程後も機能し、かつ電荷分散性の高い簡便な構造の短絡部材を備えることにより、低電圧領域においてリーク電流をほとんど生じることなく、静電気からTFTを有効に保護することができるアクティブマトリクス基板を提供することである。 The present invention has been made in view of the above circumstances, the main purpose also functions after mounting step of the driving driver, and by providing a short-circuit member charges distributed highly simple structure, low without hardly causing a leakage current in the voltage region, it is to provide an active matrix substrate capable of effectively protecting the TFT from static electricity.
【0014】 [0014]
【課題を解決するための手段】 In order to solve the problems]
本発明によるアクティブマトリクス基板は、基板と、前記基板の上に形成された複数の画素電極と、複数の配線と、それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、バリスタの特性を有する短絡部材であって、前記複数の配線のうち互いに隣接する少なくとも2本の配線を接続する短絡部材とを有することを特徴とし、そのことにより上記目的が達成される。 The active matrix substrate according to the present invention includes a substrate, a plurality of pixel electrodes formed on the substrate, a plurality of wirings, and at least one of the at least one said plurality of lines of each said plurality of pixel electrodes a plurality of switching elements for electrically connecting to a short-circuit member having a characteristic of the varistor, characterized by having a short-circuit member connecting at least two wires adjacent to each other among the plurality of wirings, the objects can be achieved.
【0015】 [0015]
ある好ましい実施形態において、前記複数の配線は、複数の走査線と、前記複数の走査線と交差する複数の信号線とを含み、前記複数のスイッチング素子は、それぞれがゲート電極、ドレイン電極およびソース電極を備え、前記ゲート電極が前記複数の走査線の一つと、前記ドレイン電極が前記複数の画素電極の一つと、前記ソース電極が前記複数の信号線の一つとそれぞれ電気的に接続されており、前記短絡部材は、前記複数の信号線のうち互いに隣接する少なくとも2本の信号線および/または前記走査の信号線のうち互いに隣接する少なくとも2本の走査線を接続する。 In a preferred embodiment, the plurality of wires may include a plurality of scan lines, and a plurality of signal lines intersecting the plurality of scanning lines, the plurality of switching elements, each gate electrode, the drain electrode and the source an electrode, and one of the gate electrodes of the plurality of scan lines, wherein the one of the drain electrodes of the plurality of pixel electrodes, the source electrode are one and respectively electrically connected to the plurality of signal lines , the short member connects at least two scanning lines adjacent to each other of the at least two signal lines and / or the scanning signal lines adjacent to each other among the plurality of signal lines.
【0016】 [0016]
ある好ましい実施形態において、前記短絡部材は、ZnOまたはZnOを主成分とする化合物を含む。 In certain preferred embodiments, the short-circuit member comprises a compound mainly composed of ZnO or ZnO.
【0017】 [0017]
前記短絡部材に含まれる前記ZnOまたはZnOを主成分とする化合物の結晶粒径は、30nm以上であって、前記複数の配線のぞれぞれの線幅以下であることが好ましい。 Crystal grain size of the compound mainly containing the ZnO or ZnO contained in the short-circuit member is preferably a at 30nm or more and less than or equal to the plurality of wirings respectively Each of the line width.
【0018】 [0018]
ある好ましい実施形態において、前記スイッチング素子は半導体層を有しており、前記半導体層はZnOまたはZnOを主成分とする化合物を含む。 In certain preferred embodiments, the switching element has a semiconductor layer, the semiconductor layer comprises a compound containing ZnO as a principal component, or ZnO.
【0019】 [0019]
前記半導体層および前記短絡部材はいずれもZnOを含んでおり、前記半導体層に含まれるZnOの結晶粒径は、前記短絡部材に含まれるZnOの結晶粒径よりも小さくてもよい。 The semiconductor layer and the shorting member includes a ZnO none, the crystal grain size of ZnO contained in the semiconductor layer may be smaller than the crystal grain size of ZnO contained in the short-circuit member.
【0020】 [0020]
前記短絡部材のバリスタ電圧は、前記アクティブマトリクス基板を表示装置に適用したときに、表示装置の動作時に、前記少なくとも2本の信号線および/または前記少なくとも2本の走査線の間に生じる電位差の最大値よりも高く、100Vよりも低いことが好ましい。 Varistor voltage of the short-circuit member, upon application of the active matrix substrate in a display device, during operation of the display device, the potential difference between the at least two signal lines and / or the at least two scan lines higher than the maximum value, preferably lower than 100 V.
【0021】 [0021]
前記短絡部材は、前記基板と前記少なくとも2本の信号線との間に設けられていてもよい。 The short-circuit member may be provided between the substrate and the at least two signal lines.
【0022】 [0022]
本発明の表示装置は、上記のいずれかのアクティブマトリクス基板を備えたことを特徴とする。 Display device of the present invention is characterized by comprising any of the above-referenced active matrix substrate.
【0023】 [0023]
本発明の製造方法は、基板と、複数の画素電極と、複数の配線と、それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、前記複数の配線のうち互いに隣接するすくなくとも2本の配線を接続する短絡部材とを備えたアクティブマトリクス基板の製造方法であって、前記短絡部材を形成する工程を包含し、前記短絡部材を形成する工程は、前記基板の上に膜を堆積する工程と、前記膜をパターニングする第1パターニングを行う工程とを含み、前記短絡部材はバリスタ特性を有することを特徴とし、そのことにより上記目的が達成される。 Production method of the present invention includes a substrate and a plurality of pixel electrodes, a plurality of wirings, respectively, a plurality of switching for electrically connecting the at least one of the at least one said plurality of lines of said plurality of pixel electrodes and the element, a method for manufacturing an active matrix substrate and a circuit member connecting at least two wires adjacent to each other among the plurality of wires, comprising the step of forming the short-circuit member, the short member forming a includes depositing a film on the substrate, and a step of performing first patterning patterning the film, the short-circuit member is characterized by having varistor characteristics, the by its the purpose is achieved.
【0024】 [0024]
ある好ましい実施形態において、前記複数の配線は、複数の走査線および複数の信号線を含み、前記短絡部材は前記複数の走査線のうち互いに隣接するすくなくとも2本の走査線および/または前記複数の信号線のうち互いに隣接する少なくとも2本の信号線を接続する。 In a preferred embodiment, the plurality of wirings, a plurality of scanning lines and includes a plurality of signal lines, the short-circuit member is mutually adjacent at least two scanning lines and / or said plurality of said plurality of scanning lines connecting at least two signal lines adjacent to each other among the signal lines.
【0025】 [0025]
ある好ましい実施形態において、前記複数のスイッチング素子のそれぞれは半導体層を有しており、前記膜をパターニングする第2パターニングを行うことによって、前記半導体層を形成する工程を含む。 In certain preferred embodiments, each of the plurality of switching elements includes a semiconductor layer, by performing a second patterning patterning the film, comprising forming the semiconductor layer.
【0026】 [0026]
前記第1パターニングと前記第2パターニングとを同時に行ってもよい。 And said second patterning said first patterning may be conducted simultaneously.
【0027】 [0027]
前記第1パターニングによって第1パターンが得られ、前記短絡部材を形成する工程は、前記第1パターンを第1温度で熱処理する工程を含むことができる。 The first pattern is obtained by the first patterning step of forming the short-circuit member may include a step of heat treating the first pattern at a first temperature.
【0028】 [0028]
前記第2パターニングによって第2パターンが得られ、前記半導体層を形成する工程は、前記第2パターンを前記第1温度よりも低い第2温度で熱処理する工程を含むことができる。 The second pattern is obtained by the second patterning, the step of forming the semiconductor layer may include a step of heat treating the second pattern at a second temperature lower than said first temperature.
【0029】 [0029]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
本発明では、アクティブマトリクス基板において、例えば酸化亜鉛(ZnO)または酸化亜鉛(ZnO)を主成分とする化合物を用いて形成される薄膜バリスタを用いることによって、走査線同士または信号線同士を短絡させる短絡部材またはショートリングを構成している。 In the present invention, in the active matrix substrate, for example by using a thin film varistor is formed by using a compound whose main component is zinc oxide (ZnO) or zinc oxide (ZnO), shorting scan lines or between the signal line to each other constitute a short-circuit member or a short ring. なお、本明細書では、「短絡部材」は、2本以上の線(走査線や信号線)を一定条件下で電気的に接続する部材を意味し、バリスタ、抵抗、TFTなどを広く含むものとする。 In this specification, "short member" 2 or more lines (scanning lines or signal lines) means a member for electrically connecting under certain conditions, varistor, resistor, intended to broadly include such as a TFT . また、図7や図8に示す従来技術のように、短絡部材を介してアクティブマトリックス基板に含まれる全ての線がリング状に接続される場合、そのような短絡部材を特に「ショートリング」と呼ぶことがある。 Also, as in the prior art shown in FIGS. 7 and 8, when all the lines in the active matrix substrate via the short-circuit member is connected in a ring, in particular "short ring" such short member it may be referred to.
【0030】 [0030]
従来から、ZnOは、その結晶粒界に2重ショットキーバリアが形成されることにより、非直線抵抗特性を発現する材料であることが知られている。 Conventionally, ZnO, by double Schottky barrier on the crystal grain boundary is formed, is known to be a material exhibiting a nonlinear resistance characteristic. ZnOを用いて電圧非直線抵抗素子バリスタを形成する技術や、そのようなバリスタを利用する技術は数多く提案されている(例えば特公昭62−36606号公報や特許第2912081号公報など)。 Technology and forming the voltage non-linear resistance element varistors using ZnO, such varistors utilizing techniques have been proposed (e.g., Japanese Patent Publication 62-36606 Patent Publication and Patent No. 2912081 Publication). しかし、アクティブマトリクス基板にZnOの非直線抵抗特性を利用する試みは行われていない。 However, attempts to use non-linear resistance characteristics of the ZnO active matrix substrate is not performed.
【0031】 [0031]
本発明者らは、液晶表示装置等のアクティブマトリックス基板において、ZnO及びZnOを主成分とする化合物を用いて形成された薄膜バリスタを用いることにより、上記課題を解決できることを見出し、本発明に到達した。 The present inventors have found that in the active matrix substrate such as a liquid crystal display device, by using a thin film varistor is formed by using a compound containing ZnO as a principal component and ZnO, can solve the above problems, arrived at the present invention did.
【0032】 [0032]
以下、図面を参照しながら、本発明によるアクティブマトリックス基板の実施形態を説明する。 Hereinafter, with reference to the drawings, an embodiment of an active matrix substrate according to the present invention.
【0033】 [0033]
本実施形態のアクティブマトリクス基板の等価回路図を図1に示す。 The equivalent circuit diagram of an active matrix substrate of the present embodiment shown in FIG. 図1のアクティブマトリクスマトリクス基板は、行および列からなるマトリクス状に配列された複数の画素電極と、それぞれ行方向および列方向に配列された複数の走査線(ゲート配線)2および複数の信号線(ソース配線)6を含む複数の配線とを有している。 Active matrix-matrix substrate of Figure 1, rows and a plurality of pixel electrodes arranged in a matrix of rows, a plurality of scan lines arranged in the row and column directions, respectively (gate wirings) 2 and a plurality of signal lines and a plurality of wiring including the (source wiring) 6. 各走査線2と各信号線6との交点近傍には、例えば薄膜トランジスタなどのスイッチング素子20がそれぞれ形成されている。 The intersection near the scanning lines 2 and the signal line 6, for example, a switching element 20 such as a thin film transistor are formed. 各スイッチング素子20のゲート電極およびソース電極は、複数の走査線2の一つおよび複数の信号線6の一つとそれぞれ電気的に接続されている。 The gate electrode and the source electrode of each switching element 20, respectively with one of one and a plurality of signal lines 6 of a plurality of scanning lines 2 are electrically connected. また、各スイッチング素子20のドレイン電極は、複数の画素電極の一つと電気的に接続されている。 The drain electrodes of each switching element 20 is one of a plurality of pixel electrodes electrically connected. 複数のスイッチング素子20を囲むように、バリスタ特性を有する短絡部材3が形成されている。 So as to surround the plurality of switching elements 20, the short circuit member 3 having varistor characteristics is formed. 短絡部材3は、例えばZnOまたはZnOを主成分とする化合物から形成された薄膜である。 Short-circuit member 3 is a thin film formed from the compound, for example, as a main component ZnO or ZnO. 互いに隣接する走査線2および互いに隣接する信号線6は、それぞれ走査線入力端子部4および信号線入力端子部8近傍で、短絡部材3によって接続されている。 Signal line 6 adjacent scanning lines 2 and the mutually adjacent to each other, at 4 and the signal line input terminal portion 8 near each scanning line input terminal portion are connected by a short-circuit member 3.
【0034】 [0034]
本実施形態では、ZnOを用いて短絡部材3を構成しているが、本発明はこれに限定されない。 In the present embodiment, constitutes a short-circuit member 3 using ZnO, the present invention is not limited thereto. ZnOの代わりに、バリスタ特性を有する他の材料を用いて短絡部材3を構成してもよい。 Instead of ZnO, other materials may constitute the short-circuit member 3 with having varistor characteristics. また、互いに隣り合う2本または3本以上の線(走査線2または信号線6)を接続する複数の短絡部材3を構成してもよいし、全ての線を接続する1本の短絡部材3(すなわちショートリング)を構成してもよい。 Further, it may be composed a plurality of short-circuit member 3 connecting two or three or more lines (scanning lines 2 or the signal line 6) adjacent to each other, one of the short-circuit member 3 to connect all the lines (ie short ring) may be configured. さらに、短絡部材3は、互いに隣り合う走査線2の間と互いに隣り合う信号線6の間との両方に形成されてもよいし、どちらか一方にのみ形成されていてもよい。 Moreover, short-circuit member 3 may be formed may be formed on both the between the signal line 6 adjacent to each other and between the scanning lines 2 which are adjacent to each other, to either only.
【0035】 [0035]
なお、短絡部材3は、複数の走査線2のうち、互いに隣り合う少なくとも2本の走査線2の間または複数の信号線6のうち互いに隣り合う少なくとも2本の信号線6の間に形成されていればよい。 Incidentally, the short circuit member 3, among the plurality of scanning lines 2 are formed between at least two signal lines 6 adjacent to each other of the at least two between the scanning line 2 or the signal lines 6 adjacent to each other it is sufficient that.
【0036】 [0036]
本実施形態では、走査線2または信号線6と短絡部材3とは入力端子部近傍で接続されているが、接続される位置はこれに限られない。 In the present embodiment, are connected at the input terminal portion near the scan line 2 or the signal line 6 and the short-circuit member 3, the position is not limited thereto connected. 例えばZnOまたはZnOを主成分とする化合物を用いて透明な短絡部材3を形成する場合、短絡部材3はアクティブマトリクス基板の表示領域に形成されてもよい。 For example, in the case of forming a transparent shorting member 3 with a compound mainly composed of ZnO or ZnO, short-circuit member 3 may be formed in the display region of the active matrix substrate. 例えば、短絡部材3は画素電極と重なって形成されてもよい。 For example, short-circuit member 3 may be formed to overlap with the pixel electrode.
【0037】 [0037]
本実施形態では、スイッチング素子20として薄膜トランジスタを用いているが、スイッチング素子20はこれに限定されない。 In the present embodiment uses a thin film transistor as a switching element 20, switching element 20 is not limited thereto. 代わりに、MOSFET(Metal−Oxide−Semiconductor Field Effect Transistor)などの他の三端子素子や、MIM(Metal−Insulator―Metal)素子などの二端子素子を用いることもできる。 Alternatively, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or other three-terminal element such as may be used a two-terminal element such as MIM (Metal-Insulator-Metal) element. 二端子素子を用いる場合、各二端子素子は複数の配線(典型的には信号線)の一つと複数の画素電極の一つとを接続するので、短絡部材3は、複数の配線(信号線)のうち互いに隣接する少なくとも2本を接続するように形成される。 When using a two-terminal element, the two-terminal element is a plurality of wires so (typically signal line) connecting the one one a plurality of pixel electrodes, short-circuit member 3, a plurality of wirings (signal lines) It is formed so as to connect at least two adjacent to each other out of.
【0038】 [0038]
(実施形態1) (Embodiment 1)
次に、図2を参照しながら、本実施形態のアクティブマトリクス基板における短絡部材3と信号線との接続部分の構成を説明する。 Next, referring to FIG. 2, illustrating the configuration of a connection portion between the short-circuit member 3 and the signal line in the active matrix substrate of this embodiment.
【0039】 [0039]
図2(a)および(b)は、本実施形態のアクティブマトリクス基板における信号線入力端子部分の断面図および平面図を示す。 2 (a) and 2 (b) shows a cross-sectional view and a plan view of a signal line input terminal portion in an active matrix substrate of the present embodiment. 図2(a)は図2(b)のA−A'線の断面図である。 2 (a) is a sectional view of line A-A 'in FIG. 2 (b). 図2(a)および(b)に示す例では、基板1の上に、ゲート絶縁層11を介して複数の信号線(ソース配線)6が設けられている。 In the example shown in FIG. 2 (a) and (b), on the substrate 1 with a gate insulating layer 11 a plurality of signal lines (source lines) 6 are provided. 複数の信号線6のうち互いに隣接する信号線6は、信号線6の上に形成された短絡部材3を介して接続されている。 Signal line 6 adjacent to each other among the plurality of signal lines 6 are connected via the shorting member 3 formed on the signal line 6. なお、本実施形態における各短絡部材3は、それぞれ2本の信号線のみを接続しているが、3本以上の信号線を接続していてもよい。 Each short-circuit member 3 in this embodiment is connected to only the respective two signal lines may be connected to three or more signal lines.
【0040】 [0040]
続いて、図4を参照しながら、本実施形態のアクティブマトリクス基板の製造方法を説明する。 Subsequently, with reference to FIG. 4, a method for manufacturing an active matrix substrate of the present embodiment. 図4(a)〜(d)は、各製造工程における、図1に示すようなアクティブマトリクス基板のうち、走査線入力端子が形成される部分、TFTが形成される部分および信号線入力端子が形成される部分(以下、それぞれ「走査線入力端子部」、「TFT部」および「信号線入力端子部」と称する)の模式的な断面図を示す。 Figure 4 (a) ~ (d) are, in each manufacturing step, in the active matrix substrate as shown in FIG. 1, part scan line input terminal is formed, the portion and the signal line input terminal TFT is formed moiety formed (hereinafter, respectively "scan line input terminal portion", "TFT portion" and is referred to as a "signal line input terminal portion") shows a schematic cross-sectional view of. なお、走査線入力端子は、走査線2に走査信号を送るための入力端子であり、信号線入力端子は、信号線6にデータ信号を送るための入力端子である。 The scanning line input terminal is an input terminal for sending a scanning signal to the scanning lines 2, the signal line input terminal is an input terminal for sending data signals to the signal line 6.
【0041】 [0041]
まず、基板1を用意する。 First, a substrate 1. 基板1は、TFTなどが形成される表面が絶縁性表面であればよく、石英基板、ガラス基板以外に表面が絶縁層で覆われたSi基板や金属基板でもよい。 Substrate 1 may be any surface insulating surface such as a TFT is formed, a quartz substrate, the surface other than the glass substrate may be a Si substrate or a metal substrate covered with an insulating layer. 本実施形態では、基板1として、コーニング社製1737ガラスなどの無アルカリガラス基板を用いる。 In the present embodiment, as the substrate 1, an alkali-free glass substrate of Corning 1737 glass.
【0042】 [0042]
次に、図4(a)に示すように、基板1の上にゲート電極10、走査線(ゲート配線)2、走査線入力端子4および信号線入力端子8を、例えばタンタル(Ta)を用いて以下のような方法で同時に形成する。 Next, as shown in FIG. 4 (a), using the gate electrode 10 on the substrate 1, a scanning line (gate wiring) 2, a scanning line input terminal 4 and the signal line input terminal 8, for example, tantalum (Ta) simultaneously formed by the following method Te. まず、スパッタ法などにより基板1上にTaを堆積した後、Ta上にゲート電極10、走査線2、走査線入力端子4および信号線入力端子8を規定するパターンを有するフォトレジストを形成する。 First, after deposition of Ta on the substrate 1 by a sputtering method to form a photoresist having a pattern that defines a gate electrode 10, the scanning lines 2, the scanning line input terminal 4 and the signal line input terminal 8 on Ta. このフォトレジストをマスクとしてTaをドライエッチングすることによって、Taをパターニングする。 The Ta the photoresist as a mask by dry etching to pattern the Ta. この後、フォトレジストを剥離する。 Thereafter, the photoresist is removed.
【0043】 [0043]
続いて、図4(b)に示すように、ゲート絶縁層11、半導体層12およびコンタクト層13を形成する。 Subsequently, as shown in FIG. 4 (b), the gate insulating layer 11, to form the semiconductor layer 12 and contact layer 13. ゲート絶縁層11は、例えばプラズマCVD法によりSiN を用いて形成する。 The gate insulating layer 11 is formed, for example, by using a SiN x by a plasma CVD method. TFT部では、ゲート絶縁層11の上に、半導体層12およびコンタクト層13をゲート電極10の少なくとも一部を覆うように形成する。 The TFT portion on the gate insulating layer 11, to form the semiconductor layer 12 and the contact layer 13 so as to cover at least a portion of the gate electrode 10. 半導体層12およびコンタクト層13の形成は、例えばプラズマCVD法により、アモルファスシリコン(a−Si)およびn シリコンをゲート絶縁層11上に順次堆積させた後、パターニングすることにより行う。 Formation of the semiconductor layer 12 and contact layer 13, for example, by a plasma CVD method, after sequentially depositing an amorphous silicon (a-Si) and n + silicon on the gate insulating layer 11 is performed by patterning. この後、走査線入力端子4および信号線入力端子8上のゲート絶縁層11を、例えばドライエッチングによって除去する。 Thereafter, a gate insulating layer 11 on the scanning line input terminal 4 and the signal line input terminal 8, for example, is removed by dry etching.
【0044】 [0044]
この後、図4(c)に示すように、ソース電極およびドレイン電極14、信号線(ソース配線)6、走査線(ゲート配線)2と短絡部材3とを接続する接続線15を、例えばTaを用いて以下に説明するような方法で形成する。 Thereafter, as shown in FIG. 4 (c), a connecting line 15 connecting the source electrode and the drain electrode 14, the signal line (source line) 6, a scanning line (gate wiring) 2 and the short-circuit member 3, for example, Ta formed by a method as described below with reference to. まず、スパッタ法によりTaを堆積した後、Ta上にソース電極およびドレイン電極14、信号線6および接続線15のパターンを有するフォトレジストを形成する。 First, after depositing a Ta by sputtering, a photoresist having a pattern of the source electrode and the drain electrode 14, the signal line 6 and the connecting line 15 on Ta. このフォトレジストをマスクとしてTaをドライエッチングすることによって、Taをパターニングする。 The Ta the photoresist as a mask by dry etching to pattern the Ta. このパターニングにより、TFT部には、コンタクト層13上にソース電極およびドレイン電極14が形成され、信号線入力端子部には、信号線入力端子8と接続された信号線6が形成され、走査線入力端子部には、走査線2と接続された接続線15が形成される。 By this patterning, the TFT portion, is formed a source electrode and a drain electrode 14 on the contact layer 13, the signal line input terminal portion, the signal line 6 connected to the signal line input terminal 8 is formed, the scan lines the input terminal unit, connecting lines 15 connected to the scanning line 2 is formed. また、このパターニングの際に、ソース電極とドレイン電極との間に位置するコンタクト層13も同時にエッチングされるので、ソース電極とドレイン電極とは絶縁される。 At the time of this patterning, the contact layer 13 located also etched simultaneously between the source electrode and the drain electrode, the source electrode and the drain electrode are insulated. パターニング後、フォトレジストを剥離する。 After the patterning, the photoresist is removed. さらに、このパターニングにより、走査線2と信号線6とを電気的に接続する配線も同時に形成できる。 Furthermore, by this patterning, to electrically connect the scanning line 2 and the signal line 6 lines can also be formed at the same time.
【0045】 [0045]
次に、図4(d)に示すように、接続線15および信号線6の上に、例えばZnOを用いて短絡部材3を形成する。 Next, as shown in FIG. 4 (d), on the connecting line 15 and the signal line 6, to form a short-circuit member 3 by using, for example, ZnO. 短絡部材3の形成は、例えば以下のような方法で行う。 Formation of a short circuit member 3 is carried out, for example, by the following method. まず、ZnOターゲットを用いたスパッタリング法によって、ArとO との混合ガス雰囲気中でZnOを堆積する。 First, by a sputtering method using a ZnO target to deposit a ZnO in a mixed gas atmosphere of Ar and O 2. この後、500℃以上600℃以下の温度で、酸素又は空気雰囲気中でZnOを熱処理することによって、ZnOを結晶成長させる。 Thereafter, at a temperature of 500 ° C. or higher 600 ° C. or less, by heat treatment of ZnO in an oxygen or air atmosphere, it is grown to ZnO. あるいは、ZnOにエキシマレーザー等を照射すること(レーザーアニール)によって結晶成長させてもよい。 Alternatively, it may be crystal-grown by irradiating an excimer laser or the like to ZnO (laser annealing). レーザーアニールを行う場合は、ZnOを部分的に結晶成長させることも可能である。 When performing laser annealing, it is also possible to partially crystalline growth of ZnO. このような熱処理(レーザーアニールを含む)により、好ましくは、抵抗率が10 Ω・cm以上10 Ω・cm以下で、結晶のC軸が基板1の表面に対して垂直に配向したZnOを形成する。 By such a heat treatment (including laser annealing), preferably, the resistivity is not more than 10 5 Ω · cm or more 10 8 Ω · cm, ZnO of C axis of the crystal is oriented perpendicularly to the surface of the substrate 1 Form. 次いで、公知のフォトリソグラフィー工程で所定のレジストパターンを形成した後、酢酸を用いてZnOをエッチングする。 Then, after forming a predetermined resist pattern by a known photolithography process, etching the ZnO with acetic acid. これにより、短絡部材3(またはショートリング)が得られる。 Thus, the short circuit member 3 (or short ring) are obtained. 信号線入力端子部では、この短絡部材3によって、信号線6は隣接する信号線と接続される。 The signal line input terminal portion, by the short-circuit member 3, the signal lines 6 is connected to a signal line adjacent. また、走査線入力端子部では、走査線2は接続線15を介して短絡部材3と接続され、またその走査線2と隣接する走査線も接続線15を介して同一の短絡部材と接続されるので、走査線2と隣接する走査線との接続が確保される。 Further, the scanning line input terminal portion, the scanning lines 2 is connected to the circuit member 3 via the connection line 15, also connected to the same short-circuit member also via the connecting line 15 adjacent scanning lines and the scanning lines 2 Runode, connected between the scan line adjacent to the scanning line 2 is secured.
【0046】 [0046]
本実施形態では、ZnOを用いて短絡部材3を形成しているが、短絡部材3の材料は、ZnOに限定されず、バリスタ特性を示すものであればよい。 In the present embodiment, by using a ZnO forms a short-circuit member 3, the material of the short-circuit member 3 is not limited to ZnO, it is sufficient that shows the varistor characteristic. 例えば、Bi、Mn、Co、Sb、Ti等の酸化物を含有したZnOを用いて短絡部材3を形成すると、より安定したバリスタ特性が得られる。 For example, Bi, Mn, Co, Sb, to form a short-circuit member 3 by using a ZnO containing an oxide of Ti or the like, more stable varistor property can be obtained.
【0047】 [0047]
また、多数の短絡部材3がそれぞれ2本の線のみを接続するように形成されていてもよいし、3本以上の線を接続するように形成されていてもよい。 Further, to a number of short-circuit member 3 may be formed so as to connect only two wires, respectively, may be formed so as to connect three or more lines. あるいは、1本の短絡部材3が全ての線を接続するように形成されていてもよい。 Alternatively, it may be formed as a single short-circuit member 3 to connect all the lines. 1本の短絡部材3が全ての線を接続するように形成される(すなわちショートリングである)場合は、複数の短絡部材を有する場合と比べて、短絡部材3のパターニングの際に要求される位置合わせの精度が低いので、有利である。 If one short-circuit member 3 are formed so as to connect all the lines (i.e., short ring), as compared with the case where a plurality of short-circuit member is required in patterning a short circuit member 3 because of the low alignment accuracy, it is advantageous.
【0048】 [0048]
図6は、本実施形態における短絡部材3のI−V特性を示す図である。 Figure 6 is a diagram showing an I-V characteristic of the short-circuit member 3 in this embodiment. 図6に示すI−V特性は、抵抗率10 Ω・cm、膜厚100nmのZnOを用いて、互いに隣接する信号線(ソース配線)の間に線幅10μm、線長100μmのバリスタ特性を有する短絡部材3を形成し、この信号線間に電圧を印加した場合のI−V特性である。 The I-V characteristic shown in FIG. 6, the resistivity of 10 5 Ω · cm, by using a ZnO film thickness 100 nm, between adjacent signal lines (source lines) from each other linewidths 10 [mu] m, the varistor characteristic of the line length 100μm the short-circuit member 3 is formed with a the I-V characteristic when a voltage is applied between the signal line. 短絡部材3のバリスタ電圧は50Vとしている。 Varistor voltage of a short circuit member 3 is set to 50 V.
【0049】 [0049]
信号線6間に印加する電圧がこのバリスタ電圧以下のとき、信号線6間の抵抗値(すなわち短絡部材3の抵抗値)は2 11 Ωとなる。 When the voltage applied between the signal line 6 is less than the varistor voltage, the resistance value between the signal line 6 (i.e. the resistance of the short-circuit member 3) is 2 11 Omega. 従って、この短絡部材3は、従来のショートリング、例えば図8に示すようなリンドープn アモルファスシリコンを用いて形成された高抵抗ショートリング(抵抗値:数MΩ)よりも高い絶縁性を有している。 Therefore, the short-circuit member 3, the conventional short ring, for example a high resistance short ring formed with a phosphorus-doped n + amorphous silicon as shown in FIG. 8 (resistance value: number M.OMEGA.) Has a high insulating property than ing. そのため、互いに隣接する信号線の間は完全に絶縁されていると考えられる。 Therefore, between adjacent signal lines it is considered to be completely insulated from each other. 信号線6間に印加する電圧がバリスタ電圧である50Vを超えると、短絡部材3の抵抗値が急激に低下するので、信号線6間は電気的に接続される。 When the voltage applied between the signal line 6 is greater than 50V is varistor voltage, the resistance value of the short-circuit member 3 is rapidly lowered, while the signal lines 6 are electrically connected.
【0050】 [0050]
短絡部材3のバリスタ電圧は、短絡部材3を形成するZnOまたはZnOを主成分とする化合物の結晶粒子径、膜厚、線幅、線長などを変えることで任意に設定できる。 Varistor voltage of a short circuit member 3 may be arbitrarily set by changing the crystal grain size of the compound mainly containing ZnO or ZnO forms a short-circuit member 3, the film thickness, line width, line length and the like. 例えば、本実施形態のアクティブマトリックス基板を表示装置に適用した場合において、走査線電圧Vgh、Vglをそれぞれ15V、−10Vとすると、表示装置の動作時には、互いに隣接する走査線間には最大で25Vの電位差が生じることになる。 For example, 25V in the case of applying the active matrix substrate of this embodiment to the display device, the scanning line voltage Vgh, respectively 15V and Vgl, when the -10 V, at the time of operation of the display device, at most between the scanning lines adjacent to each other so that the potential difference occurs. このような場合のバリスタ電圧は、隣接する走査線間に最大25Vの電位差が生じても互いの信号が影響を受けないように、25Vより大きいことが好ましい。 Such varistor voltage when such, as another signal even if a potential difference up to 25V between adjacent scanning lines is not affected, it is preferably greater than 25V. このように、短絡部材3のバリスタ電圧を、表示装置の動作時に互いに隣接する線間に生じる電位差の最大値よりも高く設定することによって、その表示装置の通常の表示動作時には、短絡部材3によって接続された線同士は短絡状態にならないので、駆動ドライバからの信号を各線に与えることが可能になる。 Thus, the varistor voltage of the short-circuit member 3, by setting higher than the maximum value of the potential difference generated between the lines adjacent to each other during operation of the display device, in the normal display operation of the display device, the short-circuit member 3 since connected line between is not a short-circuit state, it is possible to give a signal from the driver to each line. 一方、TFTのゲート絶縁層を静電気から確実に保護するためには、バリスタ電圧は100V以下であることが好ましい。 Meanwhile, in order to reliably protect the gate insulating layer of the TFT from static electricity, it is preferable varistor voltage is less than 100 V. より好ましいバリスタ電圧は、40V以上70V以下である。 More preferred varistor voltage is 40V or more 70V or less.
【0051】 [0051]
(実施形態2) (Embodiment 2)
次に、図3を参照しながら、実施形態2のアクティブマトリクス基板における短絡部材3(またはショートリング3)と信号線との接続部分の構成を説明する。 Next, referring to FIG. 3, the configuration of the connection portion between the short-circuit member 3 (or short ring 3) and the signal line in the active matrix substrate of Embodiment 2 will be described.
【0052】 [0052]
図3(a)および(b)は、本実施形態のアクティブマトリクス基板における信号線入力端子部分の断面図および平面図を示す。 Figure 3 (a) and (b) shows a cross-sectional view and a plan view of a signal line input terminal portion in an active matrix substrate of the present embodiment. 図3(a)は図3(b)のB−B'線の断面図である。 3 (a) is a sectional view of line B-B 'in FIG. 3 (b). 本実施形態は、図3(a)および(b)に示すように、短絡部材3が信号線(ソース配線)6の下、すなわち信号線6とゲート絶縁層11との間に設けられている点で実施形態1と異なっている。 This embodiment is provided between the, as shown in FIG. 3 (a) and (b), under the short-circuit member 3 are signal lines (source lines) 6, i.e. the signal line 6 and the gate insulating layer 11 It is different from the first embodiment in a point. このような構成は、TFTの半導体層をZnOまたはZnOを主成分とする化合物を用いて形成する場合に、短絡部材3とTFTの半導体層とを同時に形成できるので有利である(例えば特開2000−150900号公報に、ZnOまたはその化合物を用いてTFTの半導体層を形成する技術が開示されている)。 Such a configuration, in the case of forming a semiconductor layer of a TFT using a compound mainly composed of ZnO or ZnO, is advantageous because the semiconductor layer of the short-circuit member 3 and the TFT can be formed at the same time (for example, JP-2000 the -150900 discloses a technique of forming a semiconductor layer of a TFT using ZnO or their compounds are disclosed). なお、実施形態1と同様に、短絡部材3は3本以上の信号線を接続するパターンを有していてもよく、例えばショートリングであってもよい。 Similarly to Embodiment 1, the short circuit member 3 may have a pattern that connects three or more signal lines, may be a short ring, for example.
【0053】 [0053]
続いて、図5を参照しながら、本実施形態のアクティブマトリクス基板の製造方法を説明する。 Subsequently, with reference to FIG. 5, illustrating a method for manufacturing an active matrix substrate of the present embodiment. 図5(a)および(b)は、図4と同様に、走査線入力端子部、TFT部および信号線入力端子部における模式的な断面図を示す。 Figure 5 (a) and (b), similar to FIG. 4 shows scanning line input terminal portion, a schematic cross-sectional view of the TFT portion and the signal line input terminal portion.
【0054】 [0054]
まず、実施形態1と同様の工程によって、図5(a)に示すように、基板1の上にゲート電極10、走査線(ゲート配線)2、走査線入力端子4および信号線入力端子8を、例えばTaを用いて同時に形成する。 First, the same process as in Embodiment 1, as shown in FIG. 5 (a), a gate electrode 10 on the substrate 1, a scanning line (gate wiring) 2, a scanning line input terminal 4 and the signal line input terminal 8 , for example, it is formed at the same time using the Ta.
【0055】 [0055]
続いて、実施形態1と同様の工程によって、ゲート絶縁層11を例えばSiN を用いて形成する。 Subsequently, the same process as in Embodiment 1 is formed using a gate insulating layer 11, for example SiN x. この後、ゲート絶縁層11の上に、例えばZnOを用いて半導体層12および短絡部材3を形成する。 Thereafter, on the gate insulating layer 11, to form the semiconductor layer 12 and the short-circuit member 3 by using, for example, ZnO. 半導体層12および短絡部材3の形成は、例えば以下のようにして行う。 Formation of the semiconductor layer 12 and the short-circuit member 3 is carried out, for example, as follows. まず、ZnOターゲットを用いたスパッタリング法によって、ArとO との混合ガス雰囲気中でZnOを堆積する。 First, by a sputtering method using a ZnO target to deposit a ZnO in a mixed gas atmosphere of Ar and O 2. この後、酸素又は空気雰囲気中でZnOを熱処理することによって、ZnOを結晶成長させる。 Thereafter, by heat treatment of ZnO in an oxygen or air atmosphere, it is grown to ZnO. あるいは、ZnOにエキシマレーザー等を照射すること(レーザーアニール)によって結晶成長させてもよい。 Alternatively, it may be crystal-grown by irradiating an excimer laser or the like to ZnO (laser annealing). 熱処理の温度などの好ましい結晶成長条件は、典型的には、堆積させたZnOのうち、半導体層12となる部分と短絡部材3となる部分とで異なる。 Preferred crystal growth conditions such as temperature of the heat treatment is typically among the ZnO deposited differs between portions to be partially a short-circuit member 3 serving as a semiconductor layer 12. 例えば、ZnOのうち半導体層12となる部分には、200℃以上400℃以下の温度T1で熱処理を行い、ZnOのうち短絡部材3となる部分には、T1よりも高い温度T2(例えばT2は500℃以上600℃以下)で熱処理を行う。 For example, the portion serving as the semiconductor layer 12 of ZnO, subjected to heat treatment at 200 ° C. or higher 400 ° C. temperature below T1, the portion serving as short-circuit member 3 of ZnO, the temperature T2 (e.g. T2 higher than T1 performing heat treatment at 500 ° C. or higher 600 ° C. or less). これにより、ZnOのうち短絡部材3となる部分の結晶粒径は、半導体層12となる部分の結晶粒径よりも大きくなる。 Accordingly, the crystal grain size of the portion to be a short-circuit member 3 of ZnO is greater than the grain size of the portion that becomes the semiconductor layer 12. このように部分的にZnOの熱処理条件を変える場合には、レーザーアニールによる熱処理方法が好ましい。 When such partially changing the heat treatment conditions of ZnO, a heat treatment method by laser annealing is preferred. あるいは、上記のZnOを堆積する工程において、基板温度を例えば250℃に設定してスパッタリングを行うことにより、結晶状態のZnOを堆積させることができる。 Alternatively, in the step of depositing the above ZnO, by performing sputtering with the substrate temperature for example to 250 ° C., it can be deposited ZnO crystal state. この場合、ZnOのうち短絡部材3となる部分にはレーザーアニールなどの熱処理を行うことにより、バリスタ特性を有するようにZnOをさらに結晶成長させ、一方、ZnOのうち半導体層12となる部分には熱処理を施さないことも可能である。 In this case, by performing heat treatment such as laser annealing to the portion to be the short-circuit member 3 of ZnO, further crystal growth of ZnO so as to have a varistor characteristic, whereas, in the portion where the semiconductor layer 12 of ZnO is it is also possible to not subjected to heat treatment.
【0056】 [0056]
上記の熱処理条件は、それぞれ所望の特性を有する半導体層12および短絡部材3が形成されるように適宜選択される。 The above heat treatment conditions, the semiconductor layer 12 and the short-circuit member 3 each have the desired characteristics is appropriately selected to be formed. 典型的には、結晶粒径が10nm以上30nm未満のZnOは半導体層12としても好適な特性を有し、結晶粒径が30nm以上であるZnOは短絡部材3として好適なバリスタ特性を有する。 Typically, ZnO is less than the crystal grain size of 10nm or more 30nm have suitable properties even as the semiconductor layer 12, ZnO crystal particle diameter of 30nm or more has suitable varistor characteristics as a short-circuit member 3. また、短絡部材3がバリスタ特性を確実に発揮するためには、接続する2本の線の間に結晶粒界が存在する必要があるので、短絡部材3の結晶粒径は、短絡部材3によって接続される走査線または信号線の線幅以下であることが好ましい。 Further, because the short-circuit member 3 to surely exhibit the varistor characteristics, it is necessary the presence of grain boundaries between the two lines to be connected, the crystal grain size of the short-circuit member 3, the short-circuit member 3 it is preferably not more than the line width of the connected scan lines or signal lines. さらに、好適な短絡部材3を得るには、ZnOのうち短絡部材3となる部分を、10 Ω・cm以上10 Ω・cm以下の抵抗率を有し、かつ結晶のC軸が基板1の表面に対して垂直に配向するようにZnOを結晶成長させることが望ましい。 Furthermore, in order to obtain a suitable short-circuit member 3, a portion to be a short-circuit member 3 of ZnO, having a 10 5 Ω · cm or more 10 8 Ω · cm or less in resistivity, and C-axis substrate 1 of crystal causing crystal growth of the ZnO to orient perpendicular to the surface it is desirable.
【0057】 [0057]
次いで、公知のフォトリソグラフィー工程でレジストパターンを形成した後、例えば酢酸を用いてZnOをエッチングすることにより、ZnOをパターニングする。 Then, after forming a resist pattern by a known photolithography process, for example, by etching the ZnO with acetic acid to pattern the ZnO. これにより、短絡部材3および半導体層12が同時に形成される。 Thus, the short circuit member 3 and the semiconductor layer 12 are formed simultaneously. なお、短絡部材3のパターニングと半導体層12のパターニングとを別個の工程で行ってもよい。 It is also possible to perform the patterning of the short-circuit member 3 of patterning the semiconductor layer 12 in a separate step. この後、走査線入力端子4および信号線入力端子8上のゲート絶縁層11を、例えばドライエッチングによって除去する。 Thereafter, a gate insulating layer 11 on the scanning line input terminal 4 and the signal line input terminal 8, for example, is removed by dry etching.
【0058】 [0058]
続いて、実施形態1と同様の方法で、ソース電極およびドレイン電極14、信号線(ソース配線)6、接続線15を、例えばTaを用いて形成する。 Subsequently, in the same manner as in Example 1, the source electrode and the drain electrode 14, the signal line (source line) 6, a connection line 15, for example formed using Ta. なお、本実施形態では、TaはZnOに対してオーミックコンタクトが可能であるので、実施形態1のようにコンタクト層13を設ける必要はない。 In the present embodiment, Ta is because it is possible ohmic contact to ZnO, it is not necessary to provide the contact layer 13 as in the embodiment 1. この結果、信号線入力端子部では、この短絡部材3によって、信号線6は隣接する信号線と接続される。 As a result, the signal line input terminal portion, by the short-circuit member 3, the signal lines 6 is connected to a signal line adjacent. また、走査線2は接続線15を介して短絡部材3と接続され、またその走査線2と隣接する走査線も接続線15を介して同一の短絡部材と接続されるので、走査線2と隣接する走査線との接続が確保される。 The scanning lines 2 is connected to the circuit member 3 via the connection line 15, also because it is connected to the same short-circuit member also via the connecting line 15 adjacent scanning lines and the scanning lines 2, the scanning line 2 connection between adjacent scan lines is ensured.
【0059】 [0059]
なお、本実施形態における短絡部材3と実施形態1における短絡部材3とは、形成される位置は異なっているが、同様の機能および特性(例えばI−V特性など)を有する。 Note that the short-circuit member 3 in short circuit member 3 of Embodiment 1 of the present embodiment, the position is different to be formed has the same functions and characteristics (e.g., the I-V characteristic, etc.).
【0060】 [0060]
上記実施形態のアクティブマトリクス基板は、上述したような短絡部材を有しているので、短絡部材によって接続された線間の電位差がバリスタ電圧以下では、リーク電流をほとんど生じない。 The active matrix substrate of the embodiment, since it has a short-circuit member as described above, the potential difference between connected by shorting member lines below varistor voltage is hardly leak current. また、本実施形態における短絡部材は電荷分散性が高く、アクティブマトリクス基板のTFTを静電気から確実に保護できる。 Moreover, short-circuit member of this embodiment has high charge dispersibility can reliably protect the active matrix substrate TFT from static electricity. さらに、本実施形態における短絡部材はアクティブマトリクス基板の駆動を妨げないため、駆動ドライバを実装した後に、短絡部材を除去する必要がない。 Further, since the short-circuit member of this embodiment does not interfere with the driving of the active matrix substrate, after mounting the driver, there is no need to remove the short-circuit member. 従って、アクティブマトリクス基板の製造工程において生じる静電気に起因する製品不良を低減することができる。 Therefore, it is possible to reduce product defects caused by static electricity generated in the manufacturing process of the active matrix substrate.
【0061】 [0061]
また、本実施形態のアクティブマトリクス基板の製造方法によると、上述したようなアクティブマトリクス基板を簡便に製造できる。 According to the manufacturing method of the active matrix substrate of this embodiment can easily manufacture the active matrix substrate as described above. 特に、TFTの半導体層と短絡部材とを同じ材料を用いて同時に形成すると、製造工程を増加させたり、製造コストを増大させたりする必要がないので有利である。 In particular, when formed at the same time using the same material and the semiconductor layer and the short-circuit member of TFT, or increasing the manufacturing process, it is advantageous because there is no need or increase the manufacturing cost.
【0062】 [0062]
【発明の効果】 【Effect of the invention】
アクティブマトリクス基板の実装工程後も機能し、かつ電荷分散性の高い簡便な構造の短絡部材を備えることにより、低電圧領域においてリーク電流をほとんど生じることなく、静電気からTFTを有効に保護することができるアクティブマトリクス基板を提供することができる。 After the mounting process of the active matrix substrate also functions, and by providing a short-circuit member charges distributed highly simple structure, without hardly causing a leakage current in the low voltage region, it is possible to effectively protect the TFT from static electricity it is possible to provide an active matrix substrate as possible.
【0063】 [0063]
本発明は、アクティブマトリクス基板を備えた液晶表示装置やEL表示装置などの各種表示装置に好適に適用される。 The present invention is suitably applied to various display devices such as liquid crystal display devices and EL display device including the active matrix substrate.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明の実施形態によるアクティブマトリクス基板の等価回路を示す図である。 1 is a diagram showing an equivalent circuit of an active matrix substrate according to an embodiment of the present invention.
【図2】(a)および(b)は、それぞれ本発明の第1の実施形態のアクティブマトリクス基板における短絡部材を模式的に示す断面図および平面図である。 Figure 2 (a) and (b) is a cross-sectional view and a plan view of the short-circuit member in the active matrix substrate shown schematically in the first embodiment of the present invention, respectively.
【図3】(a)および(b)は、それぞれ本発明の第2の実施形態のアクティブマトリクス基板における短絡部材を模式的に示す断面図および平面図である。 3 (a) and (b) is a cross-sectional view and a plan view schematically showing a short-circuit member in the active matrix substrate of the second embodiment of the present invention, respectively.
【図4】(a)〜(d)は、本発明の第1の実施形態のアクティブマトリクス基板の製造方法を説明するための模式的な断面図である。 [4] (a) ~ (d) are schematic sectional views for explaining a manufacturing method of the active matrix substrate of the first embodiment of the present invention.
【図5】(a)および(b)は、本発明の第2の実施形態のアクティブマトリクス基板の製造方法を説明するための模式的な断面図である。 5 (a) and (b) are schematic sectional views for explaining a method for manufacturing an active matrix substrate of the second embodiment of the present invention.
【図6】本発明の実施形態における短絡部材のI−V特性を示す図である。 6 is a diagram showing an I-V characteristic of the short-circuit member in an embodiment of the present invention.
【図7】従来の導電性ショートリングを有するアクティブマトリクス基板の等価回路を示す図である。 7 is a diagram showing an equivalent circuit of an active matrix substrate having a conventional conductive short-circuit.
【図8】従来の高抵抗半導体ショートリングを有するアクティブマトリクス基板の等価回路を示す図である。 8 is a diagram showing an equivalent circuit of an active matrix substrate having a conventional high-resistance semiconductor short ring.
【図9】従来の2端子素子からなるショートリングを有するアクティブマトリクス基板の等価回路を示す図である。 9 is a diagram showing an equivalent circuit of an active matrix substrate having a short ring of a conventional two-terminal element.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 基板2 走査線3 短絡部材4 走査線入力端子5 入力保護回路6 信号線7 導電性ライン8 信号線入力端子9 高抵抗半導体ショートリング10 ゲート電極11 ゲート絶縁層12 半導体層14 ソース電極およびドレイン電極20 TFT 1 substrate 2 scan line 3 short member 4 scan line input terminal 5 input protection circuit 6 signal line 7 conductive lines 8 signal line input terminal 9 high resistance semiconductor short ring 10 gate electrode 11 gate insulating layer 12 semiconductor layer 14 source electrode and a drain electrode 20 TFT

Claims (15)

  1. 基板と、 And the substrate,
    前記基板の上に形成された複数の画素電極と、 A plurality of pixel electrodes formed on said substrate,
    複数の配線と、 And a plurality of wires,
    それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、 Each, and a plurality of switching elements for electrically connecting the at least one of the at least one said plurality of lines of said plurality of pixel electrodes,
    バリスタの特性を有する短絡部材であって、前記複数の配線のうち互いに隣接する少なくとも2本の配線を接続する短絡部材とを有する、アクティブマトリクス基板。 A short-circuit member having a characteristic of the varistor, and a short circuit member connecting at least two wires adjacent to each other among the plurality of lines, the active matrix substrate.
  2. 前記複数の配線は、複数の走査線と、前記複数の走査線と交差する複数の信号線とを含み、 Wherein the plurality of wires may include a plurality of scan lines, and a plurality of signal lines intersecting the plurality of scanning lines,
    前記複数のスイッチング素子は、それぞれがゲート電極、ドレイン電極およびソース電極を備え、前記ゲート電極が前記複数の走査線の一つと、前記ドレイン電極が前記複数の画素電極の一つと、前記ソース電極が前記複数の信号線の一つとそれぞれ電気的に接続されており、 Wherein the plurality of switching elements, each gate electrode comprises a drain electrode and a source electrode, and one of the gate electrodes of the plurality of scanning lines, and one of the drain electrodes of the plurality of pixel electrodes, the source electrode each and one of said plurality of signal lines are electrically connected,
    前記短絡部材は、前記複数の信号線のうち互いに隣接する少なくとも2本の信号線および/または前記走査の信号線のうち互いに隣接する少なくとも2本の走査線を接続する、請求項1に記載のアクティブマトリクス基板。 The short member connects at least two scanning lines adjacent to each other of the at least two signal lines and / or the scanning signal lines adjacent to each other among the plurality of signal lines, according to claim 1 active matrix substrate.
  3. 前記短絡部材は、ZnOまたはZnOを主成分とする化合物を含む、請求項1または2に記載のアクティブマトリクス基板。 The short-circuit member comprises a compound mainly composed of ZnO or ZnO, the active matrix substrate according to claim 1 or 2.
  4. 前記短絡部材に含まれる前記ZnOまたはZnOを主成分とする化合物の結晶粒径は、30nm以上であって、前記複数の配線のぞれぞれの線幅以下である、請求項3に記載のアクティブマトリクス基板。 Crystal grain size of the compound mainly containing the ZnO or ZnO contained in the short-circuit member is an at 30nm or more and less than or equal to the plurality of wirings respectively Each of the line width, according to claim 3 active matrix substrate.
  5. 前記スイッチング素子は半導体層を有しており、前記半導体層はZnOまたはZnOを主成分とする化合物を含む、請求項2から4のいずれかに記載のアクティブマトリクス基板。 The switching element has a semiconductor layer, the semiconductor layer comprises a compound containing ZnO as a principal component, or ZnO, the active matrix substrate according to any one of claims 2 to 4 in.
  6. 前記半導体層および前記短絡部材はいずれもZnOを含んでおり、前記半導体層に含まれるZnOの結晶粒径は、前記短絡部材に含まれるZnOの結晶粒径よりも小さい、請求項5に記載のアクティブマトリクス基板。 The includes a semiconductor layer and the both short-circuit member is ZnO, the crystal grain size of ZnO contained in the semiconductor layer is smaller than the crystal grain size of ZnO contained in the short-circuit member, according to claim 5 active matrix substrate.
  7. 前記短絡部材のバリスタ電圧は、前記アクティブマトリクス基板を表示装置に適用したときに、表示装置の動作時に、前記少なくとも2本の信号線および/または前記少なくとも2本の走査線の間に生じる電位差の最大値よりも高く、100Vよりも低い、請求項2から6のいずれかに記載のアクティブマトリクス基板。 Varistor voltage of the short-circuit member, upon application of the active matrix substrate in a display device, during operation of the display device, the potential difference between the at least two signal lines and / or the at least two scan lines higher than the maximum value, lower than 100 V, the active matrix substrate according to any of claims 2 to 6.
  8. 前記短絡部材は、前記基板と前記少なくとも2本の信号線との間に設けられている、請求項2から7のいずれかに記載のアクティブマトリクス基板。 The short-circuit member is provided between the at least two signal lines and the substrate, the active matrix substrate according to any one of claims 2 to 7.
  9. 請求項1から8のいずれかに記載のアクティブマトリクス基板を備えた表示装置。 Display device including the active matrix substrate according to any one of claims 1 to 8.
  10. 基板と、 And the substrate,
    複数の画素電極と、 A plurality of pixel electrodes,
    複数の配線と、 And a plurality of wires,
    それぞれが、前記複数の画素電極の少なくとも一つと前記複数の配線の少なくとも一つとを電気的に接続する複数のスイッチング素子と、 Each, and a plurality of switching elements for electrically connecting the at least one of the at least one said plurality of lines of said plurality of pixel electrodes,
    前記複数の配線のうち互いに隣接するすくなくとも2本の配線を接続する短絡部材とを備えたアクティブマトリクス基板の製造方法であって、前記短絡部材を形成する工程を包含し、前記短絡部材を形成する工程は、 A method for manufacturing an active matrix substrate and a circuit member connecting at least two wires adjacent to each other among the plurality of wires, comprising the step of forming the short-circuit member, forming the short-circuit member process,
    前記基板の上に膜を堆積する工程と、 Depositing a film on the substrate,
    前記膜をパターニングする第1パターニングを行う工程とを含み、前記短絡部材はバリスタ特性を有する、製造方法。 And a step of performing a first patterning patterning the film, the short-circuit member comprises a varistor properties, production method.
  11. 前記複数の配線は、複数の走査線および複数の信号線を含み、 Wherein the plurality of wires includes a plurality of scan lines and a plurality of signal lines,
    前記短絡部材は前記複数の走査線のうち互いに隣接するすくなくとも2本の走査線および/または前記複数の信号線のうち互いに隣接する少なくとも2本の信号線を接続する、請求項10に記載のアクティブマトリクス基板の製造方法。 The short member connects at least two signal lines adjacent to each other among at least two scan lines and / or the plurality of signal lines adjacent to each other among the plurality of scan lines, the active of claim 10 method of manufacturing a matrix substrate.
  12. 前記複数のスイッチング素子のそれぞれは半導体層を有しており、前記膜をパターニングする第2パターニングを行うことによって、前記半導体層を形成する工程を含む、請求項11に記載の製造方法。 Wherein each of the plurality of switching elements includes a semiconductor layer, by performing a second patterning patterning the film, comprising forming the semiconductor layer manufacturing method of claim 11.
  13. 前記第1パターニングと前記第2パターニングとを同時に行う、請求項12に記載の製造方法。 Performing a second patterning and the first patterned simultaneously, the manufacturing method according to claim 12.
  14. 前記第1パターニングによって第1パターンが得られ、前記短絡部材を形成する工程は、前記第1パターンを第1温度で熱処理する工程を含む、請求項10から13のいずれかに記載の製造方法。 Wherein the first pattern is obtained by first patterning step of forming the shorting member includes a step of heat treating the first pattern at a first temperature, a manufacturing method according to any of claims 10 13.
  15. 前記第2パターニングによって第2パターンが得られ、前記半導体層を形成する工程は、前記第2パターンを前記第1温度よりも低い第2温度で熱処理する工程を含む、請求項14に記載のアクティブマトリクス基板の製造方法。 The second pattern is obtained by the second patterning, the step of forming the semiconductor layer includes a step of heat treating the second pattern at a second temperature lower than said first temperature, active of claim 14 method of manufacturing a matrix substrate.
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