JP3101109B2 - Thin film transistor array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array used for a liquid crystal display device in which a plurality of display electrodes connected to a thin film transistor are arranged in a matrix, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs)
) And an active matrix type liquid crystal display element (hereinafter, referred to as a TFT-LCD) using a thin film transistor array in which display electrodes are arranged in a matrix. As such a conventional TFT-LCD,
For example, a liquid crystal display device disclosed in JP-A-63-85586 is known, and an equivalent circuit of the TFT array is shown in FIG.

As shown in FIG. 9, a TFT array has
A plurality of address wirings (gate wirings) 2 and data wirings (drain wirings) 3 are arranged on a transparent insulating substrate 1 in a row direction and a column direction so as to cross each other at right angles. A plurality of TFTs 4 each having a gate electrode connected to the address wiring 2 and a drain electrode connected to the data wiring 3 are arranged at intersections with the wiring 3.
A plurality of liquid crystal pixels 5 connected to the source electrode of T4 are arranged in a matrix.

[0004] A short-circuit wire 6 is formed on the outer periphery of the transparent insulating substrate 1 so as to surround the outer periphery of the substrate 1. The short-circuit wire 6 includes the plurality of data wires 2 and the plurality of addresses. The wirings 3 are respectively connected. Also,
A connection element 7 for connecting the gate wiring 2 and the drain wiring 3 to the short-circuit wiring 6 is provided. A connection terminal 8 is formed on the address wiring 2, and a connection terminal 9 is formed on the data wiring 3.

In the absence of the connection element 7 described above, static electricity during the assembling process (for example, a glass substrate cutting process or a driving circuit connecting process) causes dielectric breakdown, disconnection, variation in TFT characteristics, and the like. Although there was a problem of causing display defects and reducing the yield, all the address wirings and data wirings were connected to the short-circuiting wirings 6 of the transparent insulating substrate 1 through the connection elements 7 by the configuration shown in FIG. Since they are connected, they are kept at the same potential, and the occurrence of defects due to static electricity can be suppressed.

However, if the resistance of the connection element 7 is too low, the protection ability against static electricity is large, but the display quality is deteriorated due to crosstalk between the connection terminals, and the power consumption is increased due to leakage current. On the other hand, if the resistance of the connection element 7 is too large, the current flowing in response to the impulse of the static electricity is small, so that the ability to protect against the static electricity becomes insufficient.

In view of such a situation, the resistance value of the connection element 7 is suitably 1 M to 10 MΩ.

[0008]

As described above, in the conventional thin film transistor array, a metal for wiring, a semiconductor, or the like has been used as a resistor material of the connection element. However, when a metal is used as the resistor of the connection element, for example, the sheet resistance is 20 Ω / □ when the resistivity of chromium is 50 μΩ · cm, the film thickness is 250 °, and the width is required to obtain an appropriate resistance value. However, it is necessary to make the pattern shape extremely thin and have an extremely long pattern shape, for example, a width of 5 μm and a length of 250 mm, and occupy a large area. Therefore, it is impossible to form an element having such dimensions between the wirings. .

On the other hand, when a semiconductor material is used as a resistor of the connection element, the sheet resistance becomes 400 MΩ / □ when the resistivity of amorphous silicon to which phosphorus is added is 10 ³ Ω · cm and the film thickness is 250 °. In order to obtain such a pattern, it is necessary to form a pattern having an extremely wide width and an extremely short gap length, for example, a width of 0.4 to 4 mm and a gap length of 10 μm. However, there is a drawback that the element occupies a large area, and in practice, only a connection element having a low ability to protect against static electricity can be obtained.

The present invention eliminates the problems of the connection element for protecting against static electricity as described above, improves the ability to protect against static electricity, prevents display defects of the liquid crystal display device due to static electricity, and occupies the element. An object of the present invention is to provide a thin film transistor array with a small yield and a high yield, and a manufacturing method thereof.

[0011]

According to the present invention, a thin film transistor, a source electrode and a drain of the thin film transistor are provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other. A plurality of display electrodes connected to one of the electrodes and a plurality of display electrodes arranged in a matrix, the address wiring being connected to the gate electrode of the thin film transistor, and the data wiring being connected to the other of the source electrode and the drain electrode. A short-circuit wire outside the display area where the display electrodes are arranged, and the short-circuit wire and the plurality of address wires and the plurality of data wires are connected by a high-resistance two-terminal element using chrome silicide as a resistor; It is characterized by having been done.

A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In a thin film transistor array in which the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, chrome is formed between the adjacent address wiring and the adjacent data wiring. The high-resistance two-terminal element using silicide as a resistor is sequentially connected.

Further, a thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other. In a method of manufacturing a thin film transistor array in which a plurality of gate electrodes of the thin film transistor are connected to the address wiring, and a data wiring is connected to the other of the source electrode and the drain electrode, the address wiring and the data are formed on an insulating transparent substrate. A thin film transistor arranged near each of the intersections with the wiring and having a display electrode connected to one of a drain electrode and a source electrode made of Cr, an address wiring connecting a gate electrode of the thin film transistor, and the display electrode Address wiring connection of the short-circuit wiring arranged outside the A second step of forming a high-resistance two-terminal element using chromium silicide as a resistor near an intersection of the short-circuit wiring and the address wiring and the data wiring; and The data wiring connected to the other of the source electrode and the drain electrode of the second wiring is connected to the data wiring connecting part formed in the first step to form an address wiring connecting part of a short-circuit wiring, and the second wiring is connected to the second wiring. A third step of connecting one terminal of the terminal element to the short-circuit wiring, and connecting the other terminal to the address wiring or the data wiring, respectively.

A thin film transistor and a display electrode connected to one of the source electrode and the drain electrode of the thin film transistor are arranged in a matrix at each intersection of the plurality of address wirings and the plurality of data wirings arranged so as to cross each other. In a method of manufacturing a thin film transistor array in which a plurality of gate electrodes of the thin film transistor are connected to the address wiring, and a data wiring is connected to the other of the source electrode and the drain electrode, the address wiring and the data are formed on an insulating transparent substrate. A thin film transistor arranged near each of the intersections with the wiring and having a display electrode connected to one of a drain electrode and a source electrode made of Cr, an address wiring connecting a gate electrode of the thin film transistor, and the display electrode Connection terminal connected to the address wiring outside the defined area A first step of forming a connection terminal connected to a data line, and a high-resistance two-terminal having a chrome silicide connected between at least one of the adjacent address line and the adjacent data line as a resistor And a second step of forming an element.

The step of forming the thin film transistor and the high-resistance two-terminal element using chromium silicide as a resistor includes forming a gate insulating layer of the thin film transistor, and then forming a Cr layer on the semiconductor film for the thin film transistor on the gate insulating layer. Forming a chromium silicide layer at the interface between the semiconductor film and the Cr layer, and etching the Cr layer on the surface of the chromium silicide layer while leaving both ends of the Cr layer. It is characterized by having.

[0016]

According to the present invention, as described above, a short-circuit wire is provided outside the display area in which the display electrodes are arranged, and the short-circuit wire, the plurality of address wires and the plurality of data wires are formed of chrome silicide. Are connected by a high resistance two-terminal element having a resistor as a resistor. The sheet resistance of this high-resistance two-terminal element is about 20 kΩ / □, and the metal C
It is an intermediate value between 20 Ω / □ for r and 400 MΩ / □ for n ⁺ a-Si. Therefore, the high-resistance two-terminal element can be formed to have the same size as the TFT of the liquid crystal display portion.

In a liquid crystal display device using such a high-resistance two-terminal element, even if a high voltage is applied to one of the wirings due to static electricity generated during the assembling process, the connection element and the short-circuiting wiring are used. A current flows through all address wirings and data wirings, and the gate electrodes and source / drain electrodes of all TFTs are immediately kept at the same potential. Therefore,
It is possible to improve the yield without causing display defects of the liquid crystal display device due to dielectric breakdown at the intersection of the address line and the data line caused by static electricity, fluctuation of the threshold voltage of the TFT, and the like.

On the other hand, in driving the liquid crystal display device, the connection element of the present invention has a sufficiently high resistance, so that a display image is not adversely affected. Instead of the short-circuit wiring, adjacent address wirings and adjacent data wirings are sequentially connected by a high-resistance two-terminal element using chromium silicide as a resistor, and the outside of the display area where the display electrodes are arranged is arranged. It can be a surrounding structure.

In this case, only the mask pattern needs to be changed, and the manufacturing process is the same as that described above.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a schematic configuration of a TFT array according to a first embodiment of the present invention.
In FIG. 1, a TFT array includes a plurality of address wires 12 extending in a row direction and a plurality of data wires 13 extending in a column direction on an insulating transparent substrate 11 such as a glass substrate. Insulated and arranged to cross,
The plurality of address lines 12 and the plurality of data lines 1
3 at each intersection with TFT1 connected to these wirings.
4 and display electrodes 15 connected to each of the TFTs 14, and a plurality of these display electrodes 15 are arranged in the row and column directions to form a display area.

Near the outside of the display area, a short-circuit wiring 18 surrounding the display area is provided with the address wiring 12.
A data line connecting portion 18a of the short-circuit line 18 provided substantially in parallel with the address line 12 is formed on the surface of the substrate 11 to be insulated from and intersect with the data line 13. Address wiring connection portion 1 provided substantially parallel to the data wiring 13 of the wiring 18
8b is formed on a gate insulating film described later. The short-circuit wiring 18 is connected to the address wiring 12 and the data wiring 13 by a high-resistance two-terminal element 19 using chromium silicide as a resistor. Here, 16 is a connection terminal of the address wiring, and 17 is a connection terminal of the data wiring.

The address wiring 12 of this TFT array
FIGS. 2 and 3 show the structure of the TFT 14 and the display electrode 15 arranged at the intersections between the TFT 14 and the data wiring 13. As shown in these figures, the address wiring 12 and the data wiring 1
3 are formed so as to intersect with each other via a gate insulating film and an intersection insulating film 21 which will be described later. At this intersection, a gate electrode 41 is connected to the address wiring 12 and the data wiring 13 is formed.
The TFT 14 connected to the drain electrode 46 is formed, and the source electrode 48 of the TFT 14 is connected to the display electrode 15.

The TFT 14 is configured as follows. A gate electrode 41 protruding from the address wiring 12 and a gate insulating film 42 covering the gate electrode 41 are formed on the substrate 11. A semiconductor film 43 made of amorphous silicon is formed at a position of the gate insulating film 42 corresponding to the gate electrode 41, and an element region is formed. A blocking layer 44 made of silicon nitride is formed in a channel portion of the semiconductor film 43, and a drain electrode 46 is formed on one side of the semiconductor film 43 via an ohmic junction layer 45 made of a semiconductor doped with impurities. The drain electrode 46 is connected to the data wiring 13. On the other side of the semiconductor film 43, a source electrode 48 is formed via an ohmic junction layer 47 made of a semiconductor doped with impurities. The source electrode 48 is connected to the display electrode 15 made of a transparent conductive film. I have. Further, on the TFT 14,
A protection film 49 is formed. In addition, 50 is a pixel area.

A short-circuit wiring 18 arranged to intersect with the address wiring 12 and the data wiring 13, and the short-circuit wiring 18, the address wiring 12 and the data wiring 13.
The high-resistance two-terminal element 19 having chromium silicide as a resistor connected between the two elements is configured as shown in FIGS. That is, an island-shaped semiconductor film 61 made of non-doped amorphous silicon (a-Si) is formed on the gate insulating film 42 covering the address wiring 12 formed on the substrate 11, and an impurity is formed on the semiconductor film 61. Doped (doped with phosphorus) island-like semiconductor film (n ⁺ a-S
i) 62 is formed thereon, and a chromium silicide layer 6 is formed thereon.
3a are sequentially formed.

C at both ends of the chrome silicide layer 63a
Connection conductors 67 and 68 are formed on the r layer 63, and one of the C
The r layer 63 is formed in the contact hole 42 provided in the gate insulating film 42.
a to the address line 12 and the other C
The r layer 63 is connected to the short-circuit wiring 18 through a contact hole (not shown) provided in the gate insulating film 42 by a connection conductor 68, and the high-resistance two-terminal element region using chromium silicide as a resistor is protected by a protective film 49. Covered with.

A method of manufacturing the above-described TFT array will be described below with reference to FIGS. FIG. 6 shows T
FIG. 7 shows a manufacturing process of the FT portion, and FIG. 7 shows a manufacturing process of the high-resistance two-terminal element portion using chromium silicide as a resistor in the order of processes. First, a metal or alloy thin film of Cr, Al, Ta, Ti, W, or the like is deposited on an insulating transparent substrate 11 of glass or the like by a sputtering method, and is selectively etched to form a gate shown in FIG. The electrode 41, the address wiring 12 shown in FIG. 7A, and a lower data wiring connection portion (hereinafter referred to as a lower layer short-circuit wiring) disposed in parallel with the address wiring 12 are formed.

Next, the gate insulating film 4 is formed on the substrate 11 on which the gate electrode 41 and the like are formed by a plasma CVD method.
3 are successively deposited on a silicon nitride film serving as a semiconductor film 43, an amorphous silicon film 43 a serving as a semiconductor film 43, and a silicon nitride film serving as a blocking layer 44. B), unnecessary portions other than the portion corresponding to the channel portion of the TFT 14 and the portion corresponding to the intersection of the address wiring 12 and the upper-layer short-circuit wiring 18b to be described later are removed by etching, and the blocking layer 44 is formed in each part. And an intersection insulating film 21 (see FIG. 4).

The blocking layer 44 on the substrate 11
Over the entire upper surface of the amorphous silicon film on which
Ohmic bonding layers 45, 47,
An amorphous silicon layer to which an impurity of 62 is added is formed, and a Cr layer is sequentially deposited by a continuous sputtering method. Thereafter, the Cr layer, the amorphous silicon layer doped with the impurity, and the non-doped amorphous silicon film doped with the impurity are continuously removed by etching, except for the element region of the TFT 14 and the element region of the two-terminal device. Blocking layer 4
4A and 4B, the metal thin film and the impurity-doped amorphous silicon layer are removed by etching to form a source electrode 4 of the TFT 14 as shown in FIGS.
8, the drain electrode 46, and the two-terminal element region 92 (FIG.
Respectively) are formed. That is, the Cr layer 63 and the amorphous silicon layer (n ⁺ a-
When the Cr layer 63 is formed on the Si) 62, a chromium silicide layer 63a is formed at the interface between them.

Next, a transparent conductive thin film of ITO or the like is deposited on the TFT 14, the two-terminal element region 92, and the gate insulating film 42 on the substrate 11, and the transparent conductive thin film is etched, as shown in FIG. The display electrode 15 connected to the source electrode 48 of the TFT 14 is formed as described above, and subsequently, a silicon nitride film on the connection terminal 16 of the address wiring 12 for connecting the address wiring 12 to a driving circuit, FIG.
As shown in (D), a contact hole 42a is formed in the silicon nitride film on the address wiring 12.

Thereafter, a thin film of a metal or alloy such as Al, Ti, Mo, Cr,
Alternatively, a conductive film composed of a plurality of these metal films is deposited and etched to form the data wiring 13 shown in FIG. At the same time, as shown in FIG. 7E, by removing the Cr layer 63 on the two-terminal element region 92 by etching, a high-resistance two-terminal element using chromium silicide is formed. Connection conductors 67 and 68 connecting to region 92 are formed.

In this step, the connection conductor 6 of the two-terminal connection element
Etching of the Cr layer 63b exposed between 7 and 68 is performed using an etchant such as a cerium ammonium nitrate aqueous solution, and the etchant removes the C on the surface.
Only the r layer 63b is removed, and the chromium silicide layer 63a is removed.
Remain, and a high-resistance two-terminal element 19 using chromium silicide as a resistor can be obtained.

In this step, the TFT 14 has the drain electrode 46 connected to the data wiring 13, and the data wiring 13 is a high-resistance two-terminal element 19 using chromium silicide as a resistor at a portion intersecting with the lower-layer short-circuiting wiring 18 a. And the other electrode is connected to the lower-layer short-circuit wiring 18a.
Connected to. One electrode of the high-resistance two-terminal element 19 having chromium silicide as a resistor disposed at the intersection of the address wiring 12 and the upper-layer short-circuit wiring 18b is connected to the upper-layer short-circuit wiring 18b. Further, the upper-layer short-circuit wiring 18b is connected to the lower-layer short-circuit wiring 18a through a contact hole (not shown) formed in the silicon nitride film on the lower-layer short-circuit wiring 18a, and forms a gate insulating film 42 with the address wiring 12. And a silicon nitride film for forming the blocking layer 44 of the TFT 14.

Finally, the protective film 4 is formed by the plasma CVD method.
By depositing a silicon nitride film to be 9 on the entire surface of the substrate and then etching it, as shown in FIGS. 3 and 5,
A connection terminal portion formed at an end of the address line 12 and the data line 13 for connection to the drive circuit, and a portion of the silicon nitride film corresponding to the pixel region 50 on the display electrode 15 are removed to remove the protective film 49. Is formed.

As described above, the TFT array of this embodiment is composed of the TFT 14 formed on the substrate and the TFT 14
And the high-resistance two-terminal element 19 using chromium silicide as a resistor to form a special film during the process of forming the TFT 14. Instead, a thin film for forming the TFT 14 and an etching process thereof are sequentially formed.

Therefore, a TFT array having the high-resistance two-terminal element 19 using chromium silicide as a resistor can be easily manufactured without increasing the number of steps for forming the high-resistance two-terminal element 19 using chromium silicide as a resistor. Can be manufactured. In the above-described embodiment, the gate electrode 41 and the address wiring 12 are made of Cr, Al, Ta, T
Although the case where the gate electrode 41 and the address wiring 12 are formed of a metal or alloy film such as i and W has been described, the present invention is not limited to this. Alternatively, in order to improve the insulating properties of the gate electrode 41 and the address wiring 12, the surface may be partially or entirely oxidized by anodic oxidation, thermal oxidation, or the like.

FIG. 8 shows a TFT according to a second embodiment of the present invention.
It is an equivalent circuit diagram of an array. As shown in this figure, a plurality of address wirings (gate wirings) 72 and data wirings (drain wirings) 73 are arranged on a transparent insulating substrate 71 in a row direction and a column direction so as to intersect each other at right angles. A plurality of TFTs 74 each having a gate electrode connected to the address wiring 72 and a drain electrode connected to the data wiring 73 are arranged at intersections of the address wirings 72 and the data wirings 73, and a liquid crystal connected to a source electrode of the TFT 74 is provided. A plurality of pixels 75 are formed in a matrix.

The adjacent address wirings 72 and the adjacent data wirings 73 are sequentially connected by a high resistance two-terminal element 77 using chromium silicide as a resistor so as to surround the outer periphery of the liquid crystal pixel 75. That is, the address wiring 7
2, a connection terminal 78 formed simultaneously with the formation of the address wiring is formed, and a connection terminal 79 formed simultaneously with the formation of the data wiring is formed on the data wiring 73. These connection terminals 78 and 79 are respectively formed. A high-resistance two-terminal element 77 using chromium silicide formed in the above-described step as a resistor is disposed between the two terminals, and both ends of the high-resistance two-terminal element 77 are respectively adjacent to each other by a connection conductor 76. Connection terminals 78, 79 and connection terminal 78
And 79.

As described above, in this embodiment, instead of the short-circuiting wiring 18 formed in the first embodiment, the high resistance using chromium silicide as a resistor between the adjacent address wiring 72 and the adjacent data wiring 73 is used. It has a structure in which two terminals 77 are sequentially connected and surrounds the outside of the display area where the display electrodes are arranged. Adjacent address wiring 72 in this embodiment
In order to obtain a structure in which a high-resistance two-terminal element 77 using chromium silicide as a resistor connects between adjacent data wirings 73, only the mask pattern is changed. Is the same as

Here, the high-resistance two-terminal element 77 is formed by forming a Cr layer on a semiconductor film (n ⁺ a-Si film) doped with an impurity, forming chromium silicide on the interface between the two, and then forming a Cr layer on the surface. It is obtained by etching away only the layer to form a resistor made of chromium silicide [FIG.
(C) to (E)]. Therefore, even if the TFT has a structure different from that of the TFT described in the embodiment, n ⁺ a-
If the structure includes a step of forming a Cr layer on a Si film,
Of course, the connection element can be formed simultaneously with the TFT array.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0041]

As described above, according to the present invention, the following effects can be obtained.
A short wiring 18 is formed outside the display area where the display electrodes are arranged so as to surround the display area, and the short wiring 18 and the plurality of address wirings 12 and the plurality of data wirings 13 are formed of chrome silicide. Are connected by the high-resistance two-terminal elements 19 each having a resistor as a resistor, so that a high voltage due to static electricity is applied to either the address wiring 12 or the data wiring 13 to the TFT array after cutting and removing the external short ring. When this occurs, a large current flows, causing a substantial short circuit, resulting in the same potential, and the occurrence of defects such as dielectric breakdown between the two wirings and deterioration of TFT characteristics due to insulation failure between the gate electrode 41 and the drain electrode 46. Generation can be prevented.

In addition, at a normal driving voltage, the high resistance 2
Since the terminal element resistance is sufficiently high and the leakage current flowing between the address wiring, between the data wiring, and between the address wiring and the data wiring is a very small current, the data signal applied to each display electrode 15 is not affected at all. And a clear image can be displayed. In addition, during the process of forming the TFT 14 on the substrate, the high resistance 2 using chromium silicide as a resistor can be used without increasing the number of patterning masks and processes.
The terminal element 19 can be formed.

Further, instead of the short-circuiting wiring 18, a chromium is formed between the adjacent address wiring 72 and the adjacent data wiring 73 so as to surround the outer periphery of the display area outside the display area where the display electrodes are arranged. With the configuration in which the high-resistance two-terminal element 77 using silicide as a resistor is sequentially connected, the same operation and effect as described above can be obtained, and the mounting of the high-resistance two-terminal element can be facilitated. .

In particular, an impurity-doped semiconductor film (n ⁺ a-Si) used as a high-resistance two-terminal device of the present invention is used.
The sheet resistance of chromium silicide formed at the interface between the film and the Cr layer varies depending on the thermal history from the deposition of Cr on the n ⁺ a-Si film to the removal by etching, but is about 20 kΩ / □. , A conventionally used metal Cr
Of 20 Ω / □ and 400 MΩ / □ of n ⁺ a-Si. Therefore, the element area does not increase to obtain an appropriate resistance value of the high-resistance two-terminal element, and a fine pattern is not formed. Therefore, the high-resistance two-terminal element can be formed in substantially the same size as a TFT simultaneously formed on a substrate, and can be formed during the manufacturing process of the TFT.

Therefore, even if a high voltage is applied to one of the wires due to static electricity generated during the liquid crystal display device assembling process, a current flows through all the address wires and data wires through the connection elements and the short-circuit wires. The gate and drain electrodes of all TFTs are immediately kept at the same potential. Therefore, it is possible to improve the yield without causing a display defect of the liquid crystal display device due to a dielectric breakdown at an intersection of an address line and a data line caused by static electricity, a change in a threshold voltage of a TFT, or the like.

On the other hand, when driving the liquid crystal display device, the high resistance 2 using the chromium silicide of the present invention as a resistor is used.
Since the terminal element shows a sufficiently high resistance, there is no possibility that the displayed image will be adversely affected. Further, disconnection and short-circuit of the wiring can be electrically inspected collectively, and the TFT characteristics inside the screen can be easily measured.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a TFT array showing a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pixel portion in the TFT array of FIG. 1;

FIG. 3 is a cross-sectional view showing the TFT structure of FIG. 2 cut along line AA.

FIG. 4 is an enlarged plan view showing a high-resistance two-terminal element portion using chromium silicide as a resistor in the TFT array of FIG. 1;

5 is a cross-sectional view of the high-resistance two-terminal element structure using chromium silicide of FIG. 4 as a resistor, taken along line BB.

6 (A) to 6 (E) are cross-sectional views showing respective manufacturing steps of a TFT portion in the TFT array of the first embodiment shown in FIG.

7A to 7E are manufacturing process diagrams of a high-resistance two-terminal element portion using chromium silicide as a resistor in the TFT array according to the first embodiment shown in FIG. 1, wherein FIGS. It is sectional drawing.

FIG. 8 is an equivalent circuit diagram of a TFT array showing a second embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram showing a conventional TFT array.

[Explanation of symbols]

11, 71 Insulating transparent substrate 12, 72 Address wiring 13, 73 Data wiring 14, 74 TFT 15 Display electrode 18 Short wiring 18a Data wiring connection 18b Address wiring connection 19, 77 High resistance using chrome silicide as a resistor Two-terminal element 21 Intersection insulating film 41 Gate electrode 42 Gate insulating film 42a Contact hole 43, 43a Semiconductor film (amorphous silicon film) 44 Blocking layer 45, 47 Ohmic junction layer made of semiconductor doped with impurities 46 Drain electrode 48 Source Electrode 49 Protective film 50 Pixel region 61 Island-like semiconductor film (amorphous silicon) 62 Island-like semiconductor film (n ⁺ a-Si) doped with impurities (doped with phosphorus) 63, 63b Cr layer 63a Chrome silicide layer 67, 68 connection conductor 75 liquid crystal pixel 7 8,79 connection terminal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-365016 (JP, A) JP-A-5-121435 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/136 H01L 29/78 G09F 9/00-9/46

Claims (6)

(57) [Claims] 1. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In a thin film transistor array in which the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, a short circuit is formed outside the display area where the display electrodes are arranged. A thin-film transistor array having a wiring, wherein the short-circuit wiring and the plurality of address wirings and the plurality of data wirings are connected by a high-resistance two-terminal element using chromium silicide as a resistor. 2. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In the thin film transistor array in which the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, the adjacent address wiring and the adjacent data wiring are chrome. A thin film transistor array, which is sequentially connected by a high-resistance two-terminal element using silicide as a resistor. 3. A two-terminal element comprising a semiconductor film formed in an island shape, a chromium silicide layer having ohmic junction layers formed at both ends thereof, and a connection conductor connected to the ohmic junction layer. The thin film transistor array according to claim 1 or 2, wherein 4. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In the method of manufacturing a thin-film transistor array in which the address wiring is connected to the gate electrode of the thin-film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, (a) an address-transparent substrate is provided on the insulating transparent substrate. A thin film transistor having a display electrode connected to one of a drain electrode and a source electrode made of Cr and arranged near each intersection of the wiring and the data wiring; an address wiring connecting a gate electrode of the thin film transistor; Address wiring connection of the short-circuit wiring arranged outside the area where the electrodes are arranged A first step of forming a continuation,
(B) a second step of forming a high-resistance two-terminal element using chromium silicide as a resistor near an intersection of the short-circuit wiring and the address wiring and the data wiring; and (c) a source electrode and a drain of the thin-film transistor. The data wiring connected to the other electrode of the electrode and the address wiring connecting part formed in the first step are connected to form a data wiring connecting part of a short-circuit wiring, and one of the second terminal elements is formed. A third step of connecting a terminal to the short-circuit wiring and connecting the other terminal to an address wiring or a data wiring, respectively. 5. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In the method of manufacturing a thin-film transistor array in which the address wiring is connected to the gate electrode of the thin-film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, (a) an address-transparent substrate is provided on the insulating transparent substrate. A thin film transistor having a display electrode connected to one of a drain electrode and a source electrode made of Cr and arranged near each of the intersections of the wiring and the data wiring; an address wiring connecting a gate electrode of the thin film transistor; A connection terminal connected to the address wiring outside a region where the electrodes are arranged And a first step of forming a connection terminal connected to the data wiring, and (b) a chromium silicide connected between at least one of the adjacent address wiring and the adjacent data wiring is used as a resistor. And a second step of forming a high-resistance two-terminal element. 6. The step of forming a thin film transistor and a high-resistance two-terminal element using chromium silicide as a resistor includes forming a gate insulating layer of the thin film transistor, and then forming a Cr film on the semiconductor film for the thin film transistor on the gate insulating layer. Forming a layer and forming a chromium silicide layer at the interface between the semiconductor film and the Cr layer; and etching the Cr layer on the surface of the chromium silicide layer while leaving both ends of the Cr layer. The method for manufacturing a thin film transistor array according to claim 4, further comprising: