KR100656900B1 - a thin film transistor array panel for a liquid crystal display having an electrostatic protection structure and a manufacturing method thereof - Google Patents

Abstract

Two isolation gate electrodes are covered with a gate insulating film, on which a semiconductor pattern and an ohmic contact layer pattern are formed. The data line extension, which is formed on the ohmic contact layer pattern and extends from the data pad, is divided into three parts centering on the semiconductor patterns on the two isolation gate electrodes to form signal electrodes of two discharge thin film transistors. The horizontal wiring for discharge is connected to the corresponding signal electrode, and one of the isolation gate electrode and the corresponding signal electrode is connected in a conductive pattern through a contact hole formed in the protective film and the gate insulating film. It functions as a diode connected back-to-back. The thin film transistor substrate having such a structure effectively discharges static electricity generated during the manufacturing process and can easily perform array inspection.

Inspection of discharge wiring, thin film transistor, diode, static electricity, array

Description

A thin film transistor array panel for a liquid crystal display device having an electrostatic discharge structure and a method for manufacturing the same {a thin film transistor array panel for a liquid crystal display having an electrostatic protection structure and a manufacturing method}

1 is a view schematically showing the overall structure of a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention.

FIG. 2 is an enlarged layout view of a structure near the pixel area P and the pad in FIG. 1;

3 and 4 are enlarged layout views illustrating enlarged portions III and IV in FIG. 1, respectively.

5, 6, and 7 are cross-sectional views taken along the lines V-V, VI-VI, and VIII-VIII in FIGS. 2, 3, and 4, respectively.

FIG. 8 is an equivalent circuit diagram of the Q portion of FIG. 4,

FIG. 9 is an equivalent circuit diagram of a portion R of FIG. 15A showing an upper portion of a data pad portion before a pixel electrode is formed.

10A and 11A are schematic views of a first step of manufacturing according to an embodiment of the present invention, respectively.

10B and 11B are cross-sectional views taken along the lines VIIb-VIIb and XIb-XIb in FIGS. 10A and 11A, respectively.

12A and 13A are layout views at the next stage of FIGS. 10A and 11A, respectively;

12B, 12C, 12D, 12E, and 12F are cross-sectional views taken along the line XII-XII in FIG. 12A, illustrating the following steps in the order of the process;

13B, 13C, 13D, 13E, and 13F are cross-sectional views taken along the line XIII-XIII in FIG. 13A, which illustrate the following steps in the order of processing;

14A and 15A are layout views at the next stage of FIGS. 12A and 13A, respectively;

14B and 15B are cross-sectional views taken along the lines XIVb-XIVb and XVb-XVb in FIGS. 14A and 15A, respectively.

FIG. 16 is an enlarged layout view of a structure of a pixel area and a pad near a thin film transistor substrate for a liquid crystal display according to a second embodiment;

17 is an enlarged layout view illustrating a structure of a left side of a gate pad part of a thin film transistor substrate for a liquid crystal display according to a second embodiment.

FIG. 18 is an enlarged layout view of a structure above an data pad part of a thin film transistor substrate for a liquid crystal display according to a second embodiment;

19, 20, and 21 are cross-sectional views taken along the lines X′-X ′, XX-XX, and XXI-XXI in FIGS. 16, 17, and 18, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device having inspection wirings for inspecting pixel defects and short circuits or disconnection defects. will be.

Liquid crystal display is one of the most widely used flat panel display, which consists of two substrates on which electrodes are formed, a liquid crystal layer between the two substrates, and two polarizers attached to the outer surface of each substrate to polarize light. The display device controls the amount of light transmitted by rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode.

Such liquid crystal displays generally have thin film transistors each having electrodes formed on two substrates and switching voltages applied to the electrodes. The thin film transistors are formed on one of two substrates.

On the substrate on which the thin film transistor is formed, a plurality of gate lines and data lines are formed in row and column directions. A pixel electrode is formed in the pixel region defined by the intersection of the gate line and the data line, and the thin film transistor controls the image signal transmitted through the data line according to the scan signal transmitted through the gate line and sends it out to the pixel electrode. Outside the display area, which consists of a pixel and a set of wirings surrounding the pixel, a plurality of gate pads and data pads connected to the gate line and the data line, respectively, are formed, and the pads are directly connected to the outside to scan signals and images from the outside. Deliver the signal to the corresponding signal line.

Such thin film transistor substrates are easily exposed to static electricity generated in the process of depositing and patterning a plurality of thin films, and the characteristics of the thin film transistors or the thin film transistors may be destroyed by the static electricity. In order to prevent this, a method of discharging static electricity by connecting each signal line and the like using a discharging wire (shorting bar) has been applied.

On the other hand, after the manufacturing process of the thin film transistor substrate for the liquid crystal display device is completed, an array inspection is performed to inspect pixel defects, short circuits, or disconnection defects in the substrate. It is necessary to electrically separate the connected gate line and the data line from each other.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same, which effectively discharge static electricity and facilitate an array inspection.

In the present invention for achieving this problem, the data pad and the discharging wiring are connected to two discharging thin film transistors formed of two isolated gate electrodes, a semiconductor pattern on top thereof, and a conductor separated on both sides of the semiconductor pattern.

According to the present invention, a gate wiring including a plurality of gate lines for transmitting a scan signal on an insulating substrate, a first gate electrode connected to the gate line, and a gate pad connected to the gate line to receive the scan signal from the outside, Formed. A plurality of data line inspection signal lines and a plurality of second and third gate electrodes are also formed on the substrate, which are separate from the gate wirings. The gate wirings, the data line inspection signal lines, and the second and third gate electrodes are covered with a gate insulating film. First to third semiconductor patterns are formed on the gate insulating layer on the first to third gate electrodes, and the first to third portions are divided into first and second portions separated from each other on the first to third semiconductor patterns, respectively. An ohmic contact layer pattern is formed. On the gate insulating film, data wirings, a plurality of gate line inspection signal lines, and first discharge wirings are formed. The data line is connected to a plurality of data lines and data lines and is formed on the first portion of the first ohmic contact layer pattern and faces the source electrode centering on the source electrode and the gate electrode, and the second of the first ohmic contact layer pattern. A drain electrode is formed on the portion, and a data pad connected to the data line to receive an image signal from the outside. Between the data pad and the first discharge wiring, the first conductor connected to the data pad and the first portion of the second ohmic contact layer pattern, the second portion of the second ohmic contact layer pattern and the third ohmic contact layer pattern A second conductor connected to the first portion, a second portion of the third ohmic contact layer pattern, and a third conductor connected to the first discharge line are formed. The gate line test signal line and the data line test signal line are connected to the gate line and the data line, respectively.

In the present invention, the data pad and the first discharge wiring are connected by two discharge thin film transistors each consisting of the second and third gate electrodes, the second and third semiconductor patterns, and the first to third conductors. In such a structure, when high voltage static electricity flows into the wiring, the two thin film transistors for discharging are turned on to spread the static electricity to the first discharge wiring and each wiring.

Here, the second and third gate electrodes may be connected to each other with the first conductor and the first discharge line, respectively, in which case the two discharge thin film transistors are back-to-back. It is a diode in the forward direction and diode in the reverse direction. Here, when static electricity flows into the wiring, since the static electricity has a voltage higher than the reverse breakdown voltage of the diode, the static electricity is conducted to both diodes and spreads to the data line. On the other hand, when a signal having a magnitude smaller than the forward threshold voltage or the reverse breakdown voltage is applied, such as a test signal, the signal is not transmitted to the first discharge line. As a result, since the data line and the first discharge line are electrically separated and the test signal is applied only to the data line, array inspection is possible.

A second discharging wire may also be formed on the substrate, at which time the gate pad and the second discharging wire may be connected such that static electricity may be transferred to the gate line via the second discharging wire to be discharged. However, the second discharge line and the gate line must be electrically separated during the array inspection, so the connection between the two discharge lines must be broken.

In the method for manufacturing a thin film transistor substrate according to the present invention, first, a gate wiring including a gate line extension, a plurality of data line inspection signal lines, and a plurality of first and second isolated gate electrodes are formed on an insulating substrate. The gate insulating film, the semiconductor layer, the ohmic contact layer, and the first conductor layer are successively deposited thereon. Subsequently, the first conductor layer, the ohmic contact layer, and the semiconductor layer are patterned to form a data line including a data line extension, a plurality of gate line test signal lines, a first discharge line connected to the data line extension, and a resistivity thereunder. The contact layer pattern and the semiconductor pattern are formed. Subsequently, the passivation layer is deposited and patterned to form first to seventh contact holes exposing the drain electrode, the gate line extension, the data line extension, the gate line inspection signal line, the data line inspection signal line, the gate pad, and the data pad, respectively. Next, the second electrode layer is deposited and patterned to cover the drain electrode through the first contact hole, and the first conductive pattern covering the gate line extension and the gate line inspection signal line through the second and fourth contact holes. A second conductive pattern covering the data line extension and the data line inspection signal line is formed through the third and fifth contact holes. Here, the data line extension part and the ohmic contact layer pattern are divided into first to third parts around the first and second isolation gate electrodes, respectively, between the first part and the second part and between the second part and the third part. In the meantime, the semiconductor pattern between the source electrode and the drain electrode is covered with a protective film.

When the passivation layer is patterned, eighth to eleventh contact holes exposing the first and second isolation gate electrodes, the first portion of the data line extension, and the first discharge line may be formed. Next, when forming the pixel electrode, a third conductive pattern connecting the first isolation gate electrode and the first portion of the data line extension through the eighth and tenth contact holes and the second isolation through the ninth and eleventh contact holes. It is preferable to form a fourth conductive pattern connecting the gate electrode and the first discharge wiring.

Meanwhile, when forming the pixel electrode, fifth and sixth conductive patterns covering the gate pad and the data pad may be formed through the second and third contact holes, respectively.

In such a thin film transistor substrate, array inspection may be performed by applying a test signal to a gate line test signal line and a data line test signal line, respectively.

Meanwhile, the second discharge line connected to the gate line extension part may be formed, and an opening that exposes the gate line extension part may be formed in the passivation layer and the gate insulating layer. In this case, the gate line extension part exposed through the opening may be etched.

Next, a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same. do.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be schematically described.

FIG. 1 is a view schematically illustrating an entire structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

First, in the display area D, a plurality of gate lines 200 are formed in a horizontal direction, and a plurality of data lines 600 that are insulated from and cross the gate line 200 are formed in a vertical direction. The plurality of gate lines 200 and the data lines 600 cross each other to define a plurality of pixel regions P, and a thin film transistor TFT and a pixel electrode PE are formed in each pixel region P. have. The thin film transistor TFT receives a scan signal from the gate line 200 to control an image signal transferred from the data line 600 to the pixel electrode PE, and the pixel electrode PE is common to the opposite substrate. Rearrange the liquid crystal molecules between the two together with an electrode (not shown).

Outside the display area D, pads of the gate line 200 and the data line 600, electrostatic discharge elements and wirings, and defect inspection wirings are formed, which will be described in detail.

First, a gate pad 230 connected to each gate line 200 to transmit a scan signal from the outside to the gate line 200, and a gate line extending from the gate pad 230 to the opposite side of the gate line 200. The part 240 is formed. Discharge vertical wires 250 are formed in the vertical direction, and part of the gate line extension part 240 is cut off, so that the discharge vertical wires 250 and the gate lines 200 are electrically separated from each other. Alternatively, the vertical wiring 250 for discharge may be omitted.

In addition, a data pad 630 connected to each data line 600 and transmitting data signals from the outside to the data line 600 and a data line extending from the data pad 630 to the opposite side of the data line 600. The part 640 is formed. Discharge horizontal wires 650 are formed in the horizontal direction, and the discharge horizontal wires 650 and the data pads 630 are connected to the discharge element E. FIG.

Outside the display area D, the first and second gate line inspection signal lines 660 and 670 intersecting the gate line extension 240 and the first to third data lines intersecting the data line extension 640 are also provided. The test signal lines 260, 270, and 280 are formed. The first and second gate line test signal lines 660 and 670 are connected to the odd-numbered and even-numbered gate lines 200 through the gate line extension 240, respectively. The first to third data line test signal lines ( The 260, 270, and 280 are connected to the (3n-2) th, (3n-1) th, and 3nth (n is natural numbers) data lines through the data line extension 640, respectively.

In addition, the discharge vertical wires 250 and the discharge horizontal wires 650 are connected to each other.

The high voltage static electricity generated in the thin film transistor substrate is distributed to each of the wires through the discharge element E, the discharge horizontal wire 650, and the discharge vertical wire 250.

When performing array inspection on a thin film transistor substrate for a liquid crystal display device having such a structure, the first gate line test signal line 660 to which the odd-numbered gate line 200 is connected and the even-numbered gate line 200 are connected to each other. Different signals are respectively applied to the second gate line inspection signal line 670, and the data lines 600 are divided into three groups by using the first to third data line inspection signal lines 260, 270, and 280, respectively. The R, G, and B signals are applied to check for pixel defects in the substrate or short circuits or disconnections between the gate line 200 and the data line 600. At this time, when the test signal is applied, a portion of the gate line extension 240 is cut off, and thus the signal does not pass. The signal does not pass through the discharge element E because the magnitude of the current used is small. Therefore, since the signal used for the array inspection is transmitted only to the corresponding signal line, the array inspection can be performed without cutting the discharge lines 250 and 650.

Next, the structure and manufacturing method of the thin film transistor substrate for a liquid crystal display shown in FIG. 1 will be described in detail.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 1 to 7.

FIG. 2 is an enlarged layout view of the structure of the pixel area P and the pads in FIG. 1, and FIGS. 3 and 4 are enlarged views in detail of the III and IV portions of FIG. 1, respectively, and FIG. 5. 6 and 7 are cross-sectional views taken along the lines V-V, VI-VI, and VIII-VIII in FIGS. 2, 3, and 4, respectively.

1 to 7, the gate wirings 200, 210, 230, and 240 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, tantalum, and the like on the transparent insulating substrate 100 and A plurality of sustain electrodes 220, discharge vertical lines 250, first to third data line test signal lines 260, 270, and 280, and a plurality of first and second isolated gate electrodes 211 and 212 are formed. It is.

The gate wirings include a plurality of gate lines 200 extending in the horizontal direction, a gate electrode 210 which is a branch of the gate line 200, a gate pad 230 connected to the gate line 200, and a gate pad 230. And a gate line extension 240 connected to the gate line extension 240. Here, a part of the gate line extension 240 is cut off.

The vertical discharge line 250 extends in the vertical direction to the left of the gate line extension 240 and is connected to the gate line extension 240, and may be omitted as described above. The first to third data line test signal lines 260, 270, and 280 are positioned above the gate line 200 and extend in the horizontal direction. The first and second isolation gate electrodes 211 and 212 are positioned above the first data line test signal line 260 positioned at the top thereof and are arranged in a line in the vertical direction.

The storage electrode 220 is positioned between the gate lines 200 and crosses the pixel region P in parallel with the gate lines 200. The storage electrode 220 overlaps the conductive pattern 680 for the storage capacitor connected to the pixel electrode 830, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. The pixel electrode 830 and the gate line 200 are formed. If the holding capacity formed by the overlap of is sufficient, it may not be formed.

The gate wirings 200, 210, 230, and 240 and the first and second isolation gate electrodes 211 and 212, the storage electrode 220, the vertical wiring 250 for discharge, and the first to third data line inspection signal lines ( 260, 270, and 280 are covered with a gate insulating film 300 made of silicon nitride or silicon oxide.

Semiconductor patterns 410, 411, 412, 413, 416, 417, and 418 are formed on the gate insulating layer 300, and semiconductor patterns 410, 411, 412, 413, 416, and 417 are formed. On top of each other, resistive contact layer patterns 510, 511, 512, 516, 517, 518, and 520 formed of amorphous silicon doped with an n-type impurity such as phosphorus (P) are formed thereon.

On the ohmic contact layer patterns 510, 511, 512, 516, 517, 518, and 520, the data wires 600, 610, and the like may be formed of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, and tantalum. 620, 630, and 640, horizontal wiring 650 for discharge, first and second gate line inspection signal lines 660 and 670, and conductive pattern 680 for a storage capacitor are formed.

The data line includes a plurality of data lines 600 extending in a vertical direction, a source electrode 610 which is a branch of the data line 600, and a drain electrode 620 facing the source electrode 610 around the gate electrode 210. ), The data pad 630 connected to the data line 600 to receive an image signal from an external source and transmitted to the data line 600, and connected to the data pad 630 and extending in the opposite direction to the data line 600. And a data line extension 640.

The data line extension 640 is divided into three parts around the semiconductor patterns 412 and 413 on the first and second isolation gate electrodes 211 and 212 above the first data line test signal line 260. The signal electrodes 611, 612, 621, and 622 of the two discharge thin film transistors having the patterns 412 and 413 as the channel layers are formed. The signal electrodes on both sides of the semiconductor pattern 412 are referred to as the first discharge source electrode 611 and the drain electrode 621, and the signal electrodes on both sides of the semiconductor pattern 413 are referred to as the second discharge source electrode 612 and The drain electrode 622 is connected to the first discharge drain electrode 621 and the second discharge source electrode 612.

The discharge horizontal wiring 650 is connected to the plurality of second discharge source electrodes 612 and extends in the horizontal direction. The first and second gate line test signal lines 660 and 670 are connected to the gate pad 230. It extends in the vertical direction between the dedicated vertical wirings 250 and intersects with the gate line extension 240.

The conductive pattern 680 for the storage capacitor is formed on the upper portion of the storage electrode 220, and when the storage electrode 220 is not formed, the conductive pattern 680 for the storage capacitor is not formed.

The ohmic contact layer patterns 510, 511, 512, 516, 517, 518, and 520 may include the upper data lines 600, 610, 620, 630, and 640, the horizontal lines 650 for discharge, and the first and second gates. It has the same form as the line inspection signal lines 660 and 670 and the conductive pattern 680 for the storage capacitor.

Meanwhile, the semiconductor patterns 410, 416, 417, and 418 have the same shape as the ohmic contact layer patterns 510, 516, 517, and 518 and the wirings 600, 640, 650, 660, 670, and 680 thereon. The semiconductor pattern 411 is connected to the semiconductor pattern 410 under the source electrode 610 and the drain electrode 620, and the first and second discharge semiconductor patterns 412 and 413 are the first discharge source. The semiconductor pattern 410 is connected to the lower portion of the electrode 611 and the second discharge source electrode 612.

Data wires 600, 610, 620, 630, 640, semiconductor pattern 411, horizontal wiring 650 for discharge, first and second gate line test signal lines 660, 670, and conductive pattern for storage capacitor 680. ), The first and second discharge semiconductor patterns 412 and 413, and the passivation layer 700 are formed on the gate insulating layer 300.

The passivation layer 700 has a contact hole 711 exposing the gate pad 230 together with the gate insulating layer 300, and a contact hole 712 exposing the data pad 630. In addition, the passivation layer 700 has an opening 710 that exposes the gate line extension 240 together with the gate insulating layer 300, and the opening 710 is positioned on a portion where the gate line extension 240 is broken. This opening 710 may not be present. The passivation layer 700 has a contact hole 763 exposing the drain electrode 620, and a contact hole 720 and a data line extension 640 exposing the first and second gate line test signal lines 660 and 670. ) Has a contact hole 780 exposing the contact hole 780 and a contact hole 730 exposing the gate line extension 240 together with the gate insulating film 300 and the first to third data line test signal lines 260, 270, and 280. It has a contact hole 790 to reveal. In addition, the passivation layer 700 has a contact hole 760 exposing the data line extension 640 and a contact hole 740 exposing the horizontal wiring 650 for discharge, and together with the gate insulating film 300, the first and the first contact holes 760. It has contact holes 770 and 750 exposing the second isolated gate electrodes 211 and 212, respectively.

The protective film 700 also has a contact hole (not shown) that exposes the discharge horizontal wiring 650, and has a contact hole (not shown) that exposes the discharge vertical wiring 250 together with the gate insulating film 300. have.

On the passivation layer 700, a pixel electrode 830, an auxiliary gate pad 810, an auxiliary data pad 820, a conductive pattern 840, 841, 842, 850 made of a transparent conductive material such as ITO or a conventional conductive material, 851, 860, 861 are formed. On the protective film 700, a conductive pattern (not shown) for connecting the discharge horizontal wiring 650 and the discharge vertical wiring 250 through a contact hole is formed.

The pixel electrode 830 is formed in the pixel region P, is connected to the drain electrode 620 through the contact hole 763, and the conductive pattern 680 for the storage capacitor through the contact holes 761 and 762. It is connected.

The auxiliary gate pad 810 and the auxiliary data pad 820 are connected to the gate pad 230 and the data pad 630 through contact holes 711 and 712, respectively, which are pads 230 and 630 and external circuits. It is not essential to serve to complement the adhesion with the device and to protect the pads 230, 630.

The conductive patterns 851 and 850 connect the odd-numbered and even-numbered gate line extensions 240 and the first and second gate line test signal lines 660 and 670 through the contact holes 720 and 730, respectively. In addition, the conductive patterns 840, 841, and 842 have (3n-2), (3n-1), and 3nth data line extensions 640 and first to third data lines through the contact holes 780 and 790. The test signal lines 260, 270, and 280 are respectively connected.

The conductive pattern 861 connects the first isolated gate electrode 211 and the first discharge source electrode 611 through the contact holes 760 and 770, and the conductive pattern 860 includes the contact holes 740 and 750. The second isolated gate electrode 212 and the second discharge drain electrode 622 are connected to each other.

Here, the isolation gate electrodes 211 and 212, the gate insulating film 300, the semiconductor patterns 412 and 413, the discharge source electrodes 611 and 612, and the discharge drain electrodes 621 and 622 are disposed therein. A device, that is, a thin film transistor for discharge is formed. By the way, since the isolated gate electrodes 211 and 212, the source electrode 611, and the drain electrode 622 are electrically connected through the conductive patterns 860 and 861, this thin film transistor functions as a diode.

8 shows an equivalent circuit diagram corresponding to the Q portion of FIG. 4.

As shown in FIG. 8, the gate terminals G1 and G2 of the first and second discharge diodes d1 and d2 are connected to the source terminal S1 and the drain terminal D2, respectively, and the first diode d1. Drain terminal (D1) and the source terminal (S2) of the second diode (d2) is connected to form a back-to-back (back-to-back) structure. That is, the direction of the first discharge diode d1 is in the forward direction and the direction of the second discharge diode d2 is in the reverse direction with respect to the positive current from the data line 600 toward the discharge horizontal wiring 650. The second discharge diode d2 is in the forward direction and the first discharge diode d1 is in the reverse direction with respect to the current in the opposite direction.

Here, the gate terminals G1 and G2 are isolated gate electrodes 211 and 212, the source terminals S1 and S2 are source electrodes 611 and 612, and the drain terminals D1 and D2 are drain electrodes 621 and 622. Each corresponds to).

However, since the normal static electricity has a voltage equal to or higher than the reverse breakdown voltage of the discharge diodes d1 and d2, when the static electricity is generated, both diodes d1 and d2 are conducted and the static electricity is distributed to all the data lines 600. However, since the voltage of the signal applied to the first to third data line inspection signal lines 260, 270, and 280 during the array inspection is smaller than the forward threshold voltage or the reverse breakdown voltage of the discharge diodes d1 and d2, the inspection signal is It is not transmitted toward the horizontal wiring 650 for discharge and is only applied to the data line 600.

On the other hand, until the conductive patterns 840, 841, 842, 850, 851, 860, and 861 are formed on the thin film transistor substrate, the thin film transistor for discharge functions not as a diode but as a conventional three-terminal unipolar transistor. . The equivalent circuit at this time is shown in FIG.

9, it is shown that discharge capacitors C1, C2, C3, and C4 are connected between the gate terminals G1 and G2 and the source and drain terminals S1, D1; S2 and D2. In this case, the discharge capacitors C1 and C2 are formed by overlapping the first isolated gate electrode 211, the first discharge source electrode 611, and the drain electrode 621 with the gate insulating layer 300 interposed therebetween in FIG. 4. The discharge capacitors C3 and C4 are formed by overlapping the second isolated gate electrode 212, the second discharge source electrode 612, and the drain electrode 622 with the gate insulating layer 300 interposed therebetween.

At this time, when the static electricity is generated, the potentials of the gate terminals G1 and G2 are changed by the coupling of the capacitors C1 and C2 and the coupling of the capacitors C3 and C4 so that the first and second discharge thin film transistors d1-TFT and d2- are discharged. Since the TFT is turned on, static electricity spreads to the horizontal wiring 650 and the data line 600 for discharge.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 10A to 15B and FIGS. 3, 4, 6, and 7. Elements constituting the display area D are described together with reference to FIGS. 2 and 5.

First, as shown in FIGS. 10A, 11A, 10B, and 11B, a conductor layer for gate wiring is deposited on the insulating substrate 100, and the gate wirings 200, 210, 230, and 240 are formed by using a first photolithography process. The sustain electrode 220, the discharge vertical wiring 250, the first to third data line inspection signal lines 260, 270, and 280, and the first and second isolation gate electrodes 211 and 212 are formed. The discharge vertical interconnection 250 may be cut off or omitted from the gate line extension 240.

Subsequently, as shown in FIGS. 12B and 13B, the gate insulating layer 300, the semiconductor layer 400, and the ohmic contact layer 500 are successively deposited by chemical vapor deposition (CVD), and then the conductor layer 601 for data wiring is deposited. After the deposition by sputtering or the like, the data line 600, 610, 620, 630, 640, the discharge horizontal line 650, and the first and second gate line inspection signal lines 660 using a second photolithography process. 670, the conductive pattern 680 for the storage capacitor is formed. This process is described in detail below.

After the photoresist film is coated on the conductor layer 601, photoresist patterns 112 and 114 having different thicknesses according to positions are formed by using a mask. The mask used at this time has a characteristic that the light transmittance is different depending on the position. Photoresist pattern of portion C of the photoresist patterns 112 and 114 located between the source electrodes 610, 611, and 612 and the drain electrodes 620, 621, and 622 of the thin film transistor and the first and second discharge thin film transistors. Reference numeral 114 denotes a data wiring portion A, that is, a data wiring 600, 610, 620, 630, 640, a horizontal wiring 650 for discharge, and first and second gate line inspection signal lines 660 and 670. The thickness of the capacitor 112 may be thinner than that of the portion 112 on which the conductive pattern 680 is to be formed, and the photosensitive film of the other portion B may be removed or thinner than other portions.

12C and 13C, the exposed conductive layer 601 of the other portion B is removed to expose the underlying ohmic contact layer 500. If there is a thin film on the other part (B), remove it first. In this case, only the source / drain conductor pattern (not shown) of the C portion, the source / drain conductor pattern 602 for discharge, and the conductor pattern 603 of the data wiring portion A remain. The conductor layer 601 of B) is all removed to reveal the underlying ohmic contact layer 500. In this case, the conductor patterns 603 may be connected to the data wires 600, 610, 620, 630 except that the source electrodes 610, 611, 612 and the drain electrodes 620, 621, 622 are connected without being separated. 640, the discharge horizontal wiring 650, the first and second gate line inspection signal lines 660 and 670, and the conductive pattern 680 for the storage capacitor.

Next, as shown in FIGS. 12D and 13D, the exposed ohmic contact layer 500 of the other portion B and the semiconductor layer 400 thereunder are etched to form the ohmic contact layer patterns 502 and 503 and the semiconductors thereunder. Patterns 402 and 403 are formed. In this case, although the ohmic portion 500 and the semiconductor layer 400 of the other portion B may be completely removed to expose the gate insulating layer 300 below, the semiconductor layer 400 may remain slightly. Meanwhile, the photosensitive film pattern 114 of the C portion may or may not remain, but the photosensitive film pattern 112 of the data wiring part A should remain. When the photoresist pattern 114 of the C portion remains, the ashing is removed through ashing. At this time, the photosensitive film pattern 112 of the data wiring portion A is reduced to some extent, but is not removed. This reveals the source / drain conductor patterns and the first and second discharge source / drain conductor patterns 602.

Subsequently, as shown in FIGS. 12E and 13E, the source / drain conductor pattern and the discharge source / drain conductor pattern 602 and the resistive contact layer pattern and the resistive contact layer pattern 502 below. ) To remove it. In this case, a portion of the semiconductor pattern 402 may be removed to reduce the thickness, and the thickness of the photoresist second portion 112 may be etched to some extent. In addition, if the semiconductor layer 400 remains in the other part (B), it should be removed at this time. In this way, the source / drain conductor pattern and the ohmic contact layer pattern are separated, and the discharge source / drain conductor pattern 602 and the ohmic contact layer pattern 502 are separated.

Thus, the data wirings 600, 610, 620, 630, 640, the horizontal wiring 650 for discharge, the 1st and 2nd gate line test signal lines 660, 670, and the conductive pattern 680 for a storage capacitor were completed. Thereafter, as shown in FIGS. 12A, 12F, 13A, and 13F, the photosensitive film 112 remaining in the data wiring portion A is removed.

Subsequently, as shown in FIGS. 14A and 15A, 14B, and 15B, the protective layer 700 is deposited, and the opening 710 and the contact holes 711, 712, 763, 761, 762, and 720 using a third photolithography process. , 730, 740, 750, 760, 770, 780, 790. The opening 710 may not be formed when there is no vertical wiring 250 for discharge or the gate line extension 240 is already broken.

3, 4, 6, and 7, the conductive material is deposited and the pixel electrode 830, the auxiliary gate pad 810, the auxiliary data pad 820, and the conductive material are deposited using a fourth photolithography process. Patterns 840, 841, 842, 850, 851, 860 and 861 are formed.

Finally, the gate line extension 240 exposed through the opening 710 is removed.

As described above, although a thin film transistor substrate for a liquid crystal display device is manufactured using four photolithography processes, it may be manufactured using five photolithography processes.

Next, a thin film transistor substrate for a liquid crystal display device using five photolithography processes and a manufacturing method thereof will be described with reference to FIGS. 16 to 21 as a second embodiment of the present invention.

FIG. 16 is an enlarged layout view of a structure of a pixel area and a pad in a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 17 is an enlarged layout view of a structure of a left side of a gate pad part. 18 is an enlarged layout view of a structure above the data pad unit. 19, 20, and 21 are cross-sectional views taken along the lines X′-X ′, XX-XX, and XXI-XXI in FIGS. 16, 17, and 18, respectively.

16 to 21, the structure of a thin film transistor substrate for a liquid crystal display using five photolithography processes is similar to the embodiment using four photolithography processes. However, the ohmic contact layer 500 and the semiconductor layer 400 are only on the gate electrode 210 and the first and second isolation gate electrodes 211 and 212, and the data line 600 and the horizontal wiring 650 for discharge are provided. ) And the first and second gate line inspection signal lines 660 and 670, the conductive pattern 680 for the storage capacitor, and the lower portion of the vertical wiring 690 for discharge.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device using five photolithography processes will be briefly described.

First, a gate wiring conductor is formed on the insulating substrate 100, and then a first photolithography is performed to form a gate wiring, and the gate insulating film 300, the semiconductor layer 400, and the ohmic contact layer 500 are formed. After deposition, a second photolithography process is performed to form the semiconductor patterns 411, 412, and 413 and the ohmic contact layer patterns 510, 520, 511, 521, and 512. Subsequently, after depositing the data wire conductor, a third photolithography is performed to form data wires, and a part of the data line extension 640 is separated to form the first discharge source electrode 611 and the drain electrode 621. ) And a second discharge source electrode 612 and a drain electrode 622. Subsequently, after the deposition of the passivation layer 700, a fourth photolithography is performed to form the openings 710 and the contact holes 711, 712, 763, 761, 762, 720, 730, 740, 750, 760, 770, 780, 790. ). Subsequently, a fifth photolithography is performed after the deposition of a transparent conductive material such as ITO, and the pixel electrode 830, the auxiliary gate pad 810, the auxiliary data pad 820, and the conductive patterns 840, 841, 842, 850, 851, 860, 861. Subsequently, the gate line extension 240 exposed through the opening 710 is etched.

In the first and second embodiments, three data line inspection signal lines are formed, but only two may be formed.

As described above, in the present invention, an array inspection can be performed to effectively discharge static electricity generated during the manufacture of a thin film transistor substrate for a liquid crystal display device, and to inspect pixel defects, short circuits, or disconnection defects without removing the discharge wiring.

Claims (13)

Insulation board, A gate line formed on the substrate and including a plurality of gate lines transmitting a scan signal, a first gate electrode connected to the gate line, and a gate pad connected to the gate line to receive a scan signal from the outside; A plurality of data line inspection signal lines formed on the substrate and separated from the gate lines; A plurality of second and third gate electrodes formed on and isolated from the substrate, A gate insulating film covering the gate line, the data line test signal line, and the second and third gate electrodes; First to third semiconductor patterns respectively formed on the gate insulating layer on the first to third gate electrodes, First to third ohmic contacts formed on the first to third semiconductor patterns and divided into first and second portions separated from each other, A plurality of data lines formed on the gate insulating layer, source electrodes connected to the data lines and formed on a first portion of the first ohmic contact layer pattern, and facing the source electrode with respect to the gate electrode; A data line including a drain electrode formed on the second portion of the first ohmic contact layer pattern, and a data pad connected to the data line to receive an image signal from the outside; A plurality of gate line inspection signal lines formed on the gate insulating layer and separated from the data lines; A first discharge wiring formed on the gate insulating film, A first conductor connected to the data pad and a first portion of the second ohmic contact pattern; A second conductor connected to the second portion of the second ohmic contact layer pattern and the first portion of the third ohmic contact layer pattern, A third conductor connected to the second portion of the third ohmic contact pattern and the first discharge line Including; The gate line test signal line and the data line test signal line are connected to the gate line and the data line, respectively. Thin film transistor substrate for liquid crystal display device. In claim 1, The first ohmic contact layer pattern is formed under the data line, the gate line test signal line, and the first discharge line, and has the same shape, and the first semiconductor pattern is disposed between the source electrode and the drain electrode. A thin film transistor substrate for a liquid crystal display device having the same shape as the first ohmic contact layer pattern. In claim 1, The thin film transistor substrate for liquid crystal display device further including the 2nd discharge wiring formed on the said board | substrate.  In claim 3, A thin film transistor substrate for a liquid crystal display device, wherein the gate pad and the second discharge line are connected to each other. In claim 3, And the second and third gate electrodes are connected to the first conductor and the first discharge line, respectively. In claim 5, The thin film transistor substrate for liquid crystal display device of which the said 2nd discharge wiring and said gate pad are isolate | separated. A gate wiring including a plurality of gate lines on an insulating substrate, a gate electrode connected to the gate line, a gate pad connected to the gate line to receive a scan signal, and a gate line extension connected to the gate pad; Forming a plurality of data line test signal lines and a plurality of first and second isolated gate electrodes separated from the gate lines; Depositing a gate insulating film covering the gate line, the data line test signal line, and the first and second isolated gate electrodes; Continuously depositing a semiconductor layer, an ohmic contact layer and a first conductor layer on the gate insulating film, Patterning the first conductor layer, the ohmic contact layer, and the semiconductor layer to connect a plurality of data lines, a source electrode connected to the data line, a drain electrode facing the source electrode with respect to the gate electrode, and connected to the data line A data pad receiving an image signal from an external device, a data line including a data line extension connected to the data pad, and a plurality of gate line test signal lines separated from the data line, and connected to the data line extension Forming a first discharge wiring, and an ohmic contact layer pattern and a semiconductor pattern thereunder; Depositing a protective film covering the data line, the gate line test signal line, and the first discharge line; The protective layer is patterned with the gate insulating layer to form first to seventh contact holes that expose the drain electrode, the gate line extension, the data line extension, the gate line test signal line, the data line test signal line, the gate pad, and the data pad, respectively. Forming step, Depositing a second conductor layer covering the passivation layer; A pixel electrode covering the drain electrode through the first contact hole by patterning the second conductor layer, and a first conductive pattern covering the gate line extension part and the gate line inspection signal line through the second and fourth contact holes Forming a second conductive pattern covering the data line extension and the data line test signal line through the third and fifth contact holes; Including; The data line extension part and the ohmic contact layer pattern may be divided into first to third parts around the first and second isolation gate electrodes, respectively, between the first part and the second part and between the second part and the second part. The semiconductor pattern between the three portions and between the source electrode and the drain electrode is covered with the protective film. The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 7, In the step of patterning the protective film, And eighth to eleventh contact holes exposing the first and second isolation gate electrodes, the first portion of the data line extension, and the first discharge wiring, respectively. In claim 8, In the step of forming the pixel electrode, A third conductive pattern connecting the first isolation gate electrode and the first portion of the data line extension through the eighth and tenth contact holes, and a second isolation gate electrode and the second conductive pattern through the ninth and eleventh contact holes. 1 to form a fourth conductive pattern connecting the discharge wiring The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 9, In the step of forming the pixel electrode, And forming fifth and sixth conductive patterns covering the gate pad and the data pad through the second and third contact holes, respectively. In claim 10, And applying a test signal to the gate line test signal line and the data line test signal line, respectively. In claim 10, Forming a second discharging wire connected to the gate line extension part and forming an opening exposing the gate line extension part in the passivation layer and the gate insulating layer; Way. In claim 12, And etching the gate line extension exposed through the opening.

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