JP2000164874A - Thin-film transistor array substrate, manufacturing method for it, and liquid-crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor array substrate, together with its manufacturing method, which is suitable for lowering the resistance of a wiring, while reducing manufacturing cost and construction period. SOLUTION: With a gate wiring consisting of a double interconnection structure which consists of a double interconnection structure comprising a lower layer 6 of a low-resistance metal such as copper and aluminum film and an upper layer 7 of ITO(indium tin oxide) film provided, the ITO film an ITO film which is on the side of gate wiring upper layer 7 and that of a pixel electrode 16 are patterned at the same time. A drain electrode 12 and an auxiliary capacitance electrode/pixel electrode 16 are connected directly, with no contact hole being used for the connection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor array substrate, a method of manufacturing the same, and a liquid crystal display device.
In particular, the present invention relates to a wiring structure using a protective film that does not cause a problem when forming a wiring during a manufacturing process of a thin film transistor array substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 is a cross-sectional view showing a manufacturing process of a thin film transistor array substrate provided with a bottom gate type thin film transistor, gate wiring, source wiring and the like in a conventional general thin film transistor type liquid crystal display device. In this thin film transistor array substrate, a gate wiring and a source wiring are arranged in a matrix on a transparent substrate made of glass or the like, and a region surrounded by the gate wiring and the source wiring becomes one pixel. Is provided with a thin film transistor.

In this thin film transistor, as shown in FIG. 9 (f), a gate electrode 61 integrally formed with a gate wiring is provided on a transparent substrate 60, and a gate insulating film 62 is provided so as to cover the gate electrode 61. ing. Gate electrode 6
1. A semiconductor active film 63 made of amorphous silicon (a-Si) is provided on the gate insulating film 62 above the amorphous silicon (a-S) containing an n-type impurity such as phosphorus.
A source electrode 65 and a drain electrode 66 integrally formed with the source wiring are provided from the semiconductor active film 63 to the gate insulating film 62 via an ohmic contact layer 64 made of i: n ⁺ ). In addition, a passivation film 68 is provided to cover the thin film transistor 67 including the source electrode 65, the drain electrode 66, the gate electrode 61, and the like. On the other hand, a pixel electrode 69 made of a transparent conductive film such as indium tin oxide (hereinafter, referred to as ITO) is provided on a transparent substrate 60,
The pixel electrode 69 and the drain electrode 66 are electrically connected through a contact hole 70 formed in the gate insulating film 62 covering a part of the pixel electrode 69.

The thin film transistor array substrate is manufactured.
First, as shown in FIG.
A conductive film is formed on the substrate 0, and is patterned to form a gate.
An electrode 61 and a gate wiring are formed. Also, the gate arrangement
Pads are formed at the ends of the lines. Next, as shown in FIG.
To form an ITO film on the entire surface
To form a pixel electrode 69. Next, as shown in FIG.
After forming the gate insulating film 62 on the entire surface,
Si film 71, a-Si: n⁺Film 72 is continuously and sequentially formed
Then, the a-Si film 7 is formed using one photomask.
1, a-Si: n ⁺Patterning the film 72 collectively
Thus, the gate insulating film 62 is
The semiconductor active film 63 and the ohmic contact layer 64
Is formed.

Next, as shown in FIG. 9D, patterning is performed to open a part of the gate insulating film 62 on the pixel electrode 69, so that the drain electrode 66 and the pixel electrode 69 to be formed later are connected. Contact hole 70 for connection
To form Next, as shown in FIG. 9E, after a conductive film is formed on the entire surface, this is patterned to form a drain electrode 66, a source electrode 65, and a source wiring made of the conductive film. A on the channel portion of the film 71
The ohmic contact layer 64 including the a-Si: n ⁺ film 72 is formed by removing the -Si: n ⁺ film 72. At this time, the drain electrode 66 and the pixel electrode 69 are connected through the contact hole 70.

[0009] Finally, as shown in FIG. 9 (f), a passivation film 68 is formed on the entire surface and is patterned to form a passivation film 6 on the pixel electrode 69.
A contact hole is formed by opening the passivation film 68 on the pad of the gate wiring and the source wiring while leaving a part of the wiring 8 (so-called terminal connection). Through these steps, a conventional thin film transistor array substrate is completed.

[0007]

According to the above-mentioned method of manufacturing a thin film transistor array substrate, patterning for forming a gate, patterning for forming a pixel electrode, patterning for forming an island portion, patterning for forming a contact hole, and source / source patterning are performed. Patterning for drain formation,
It requires patterning for terminal extraction and six patterning steps, and one process requires six photomasks (hereinafter, referred to as a six-mask process). However, when manufacturing a thin film transistor array substrate,
It is not preferable to use many expensive photomasks and to provide many photolithography steps during the manufacturing process, which causes an increase in manufacturing cost, a long working period, and a low yield. It has been desired to reduce the number of processes as much as possible.

On the other hand, there is a demand to use a metal having a low resistivity, such as copper or aluminum, for the wiring material such as the gate wiring and the source wiring in order to reduce the resistance. However, metals such as copper and aluminum have no resistance to ITO etching. Therefore, for example, when copper or aluminum is applied to the gate wiring material in the above-described manufacturing method, when the ITO film is etched in the pixel electrode patterning step shown in FIG. And aluminum are also etched. Therefore, if it is desired to use copper or aluminum as the gate wiring material, it is necessary to use a protective film for protecting these films from ITO etching. However, in this case, a patterning step of a protective film that covers the wiring is required, so that one more photomask is added, which goes against the request to reduce the number of photomasks by using a seven-mask process. In other words, it is impossible to use low-resistance copper or aluminum as the gate wiring material without increasing the number of photomasks, and it is necessary to reduce manufacturing costs, shorten the construction period, and lower the resistance of gate wiring. There was a problem that can not be.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can reduce the number of photomasks used in the conventional process, thereby reducing the manufacturing cost and the period of work, and reducing the wiring resistance. Another object of the present invention is to provide a structure of a thin film transistor array substrate for a liquid crystal display device and a method for manufacturing the same, which are also suitable for the above.

[0010]

In order to achieve the above object, a thin film transistor array substrate according to the present invention comprises a plurality of source wirings and a plurality of gate wirings having a metal film surface covered with a transparent conductive film on the substrate. Are provided in a matrix, and in each of a plurality of regions surrounded by the source wiring and the gate wiring, a pixel electrode is formed of a transparent conductive film, and a thin film transistor for switchingly driving the pixel electrode is provided. A gate electrode integrally formed with the gate wiring, a semiconductor active layer formed of a semiconductor film on a gate insulating film covering the gate electrode, an ohmic contact layer formed of an impurity semiconductor film thereon, and a gate electrode. The source wiring is partially overlapped with the gate electrode on the stacked body composed of the insulating film, the semiconductor film, and the impurity semiconductor film. A gate which is integrally formed with a source electrode and a drain electrode which partially overlaps the gate electrode, faces the source electrode, and is formed by directly connecting to the pixel electrode, and which is adjacent to a gate wiring for driving each pixel electrode; An auxiliary capacitance electrode directly connected to each pixel electrode is provided so as to form an auxiliary capacitance with the wiring, and a stacked body including an insulating film, a semiconductor film, and an impurity semiconductor film is formed between a gate wiring and the source wiring. It is interposed between the gate wiring and the source wiring at the intersection, and is arranged so as to form a desired auxiliary capacitance below the auxiliary capacitance electrode on the gate wiring separately from the intervening laminate. It is characterized by the following.

As an example of a specific material of each of the above films,
Various metals including copper and aluminum are formed on a metal film forming a gate wiring, ITO is formed on a transparent conductive film which covers the metal film and forms a pixel electrode, a silicon nitride film is formed on a gate insulating film, and a semiconductor active layer is formed. Amorphous silicon can be used for the semiconductor film, and amorphous silicon containing n-type impurities such as phosphorus can be used for the impurity semiconductor film forming the ohmic contact layer. In addition, any metal can be used for the source wiring, the source electrode, and the drain electrode, and the storage capacitor electrode can be formed of the same material as the drain electrode because it needs to be connected to the pixel electrode.
Note that the auxiliary capacitance electrode forms an auxiliary capacitance with a gate wiring adjacent to a gate wiring for driving a pixel electrode connected thereto, but an insulating film, a semiconductor film, and an impurity semiconductor film are provided below the auxiliary capacitance electrode. The capacitance value is set to a desired value depending on the overlapping area between the stacked body and the gate wiring.

In the thin film transistor array substrate of the present invention, in particular, the plurality of gate wirings have a structure in which the surface of the metal film is covered with a transparent conductive film. Therefore, even if copper or aluminum having no resistance to etching of a transparent conductive film such as ITO is used as the metal film material, since the surface is protected by the transparent conductive film,
There is no possibility that the wiring is etched even when the pixel electrode made of the transparent conductive film is etched. for that reason,
By using copper or aluminum, the resistance of the wiring can be reduced without causing a wiring disconnection defect or the like due to the manufacturing process. In addition, not only copper and aluminum but also other various metal materials can be used without concern for etching resistance, and the degree of freedom in selecting a wiring material is improved.

In the above thin film transistor array substrate, an intervening laminated body interposed between the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring, and an insulating layer formed between the gate electrode and the source electrode. A film, a semiconductor film, and a stacked body including an impurity semiconductor film may be integrally formed. That is, in the case of the structure of the thin film transistor array substrate of the present invention, since the metal film which is the main body of the gate wiring is covered with the transparent conductive film, the upper layer side of the gate wiring and the pixel electrode are on the same layer. .
On the other hand, in the structure of the present invention, the contact portion between the drain electrode and the pixel electrode is not a general structure connected through a contact hole formed in an interlayer insulating film between the drain electrode and the pixel electrode. It is directly connected to the pixel electrode without any intervening interlayer insulating film. Therefore, if there is no film at the intersection of the gate line and the source line, the source line formed of the same layer as the drain electrode is short-circuited with the gate line. Therefore, in the structure of the present invention, the intervening laminate is required at the intersection of the gate wiring and the source wiring. The intervening laminate and the laminate constituting the portion of the semiconductor active film of the thin film transistor may be formed separately, or may be formed integrally with the same continuous laminate.

According to the method of manufacturing a thin film transistor array substrate of the present invention, a metal film is formed on a substrate and is patterned to form a plurality of gate wirings connected to each lower layer of a plurality of parallel spaced gate wirings and to each gate wiring. Forming each lower layer of the gate electrode, forming a transparent conductive film on the entire surface, patterning this, forming each upper layer of a plurality of gate wirings and each upper layer of the plurality of gate electrodes, and a pixel electrode corresponding to each gate electrode Are formed, and an insulating film, a semiconductor film, and an impurity semiconductor film to which impurities are added are sequentially formed on the entire surface, and are collectively patterned to form an insulating film, a semiconductor film, and an impurity semiconductor film having the same external shape on the gate electrode and the gate electrode. A stacked body composed of an insulating film, a semiconductor film, and an impurity semiconductor film located below a storage capacitor electrode to be formed later, Separately from this laminate, an intervening laminate composed of an insulating film, a semiconductor film and an impurity semiconductor film is formed between the gate wiring and the source wiring at a portion where each gate wiring and the source wiring intersect. A plurality of parallelly spaced source wirings intersecting a plurality of gate wirings after forming a metal film on the impurity semiconductor film, and connecting to the source wirings and partially overlapping the gate electrode on the impurity semiconductor film. A source electrode, and a drain electrode straddling between the impurity semiconductor film and each pixel electrode so as to partially overlap the gate electrode,
An auxiliary capacitor electrode is formed on a gate wiring connected to each pixel electrode and driving a pixel electrode adjacent to the pixel electrode via an insulating film, a semiconductor film, and an impurity semiconductor film.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the patterning for forming the lower layer side of the gate wiring and the gate electrode, the patterning for forming the upper layer side and the pixel electrode, the insulating film, the semiconductor film and the impurity added impurity are performed. Patterning for forming a stacked body (hereinafter, referred to as an island portion) made of a semiconductor film, patterning for forming a source wiring and a source electrode, a drain electrode, and an auxiliary capacitance electrode are performed four times, that is, four photomasks are required. There is (a four-mask process).
Since a double wiring structure in which the gate wiring is covered with a protective film (transparent conductive film) having etching resistance is required, two photomasks are required in the gate wiring forming step. This is where the number of photomasks is increased by one as compared with the case where a gate wiring is used.

However, in the method of the present invention, a transparent conductive film is used on an upper layer side of the gate wiring and the gate electrode, and the upper layer of the gate wiring and the gate electrode and the pixel electrode are simultaneously patterned. The number of photomasks can be reduced by two as a result of eliminating the step of forming a contact hole that establishes electrical continuity between the drain electrode and the pixel electrode. Can be reduced by one. As a result, it is possible to reduce the manufacturing cost and the construction period. In the actual manufacturing process,
In addition to the patterning step described above, the step of patterning the terminals of the passivation film described in the section of the prior art is added, resulting in a five-mask process.

A guard ring for interconnecting a plurality of gate wirings and a plurality of source wirings to prevent dielectric breakdown of a gate insulating film interposed between the gate wirings and the source wirings is provided with a guard ring made of a transparent conductive film. Patterning may be performed simultaneously with the upper layer side of the gate electrode and the gate wiring and the pixel electrode. In the manufacturing process of the thin film transistor array substrate, a high voltage is applied between the gate wiring and the source wiring opposed to each other with the gate insulating film interposed therebetween due to electrostatic charging of the substrate, which causes dielectric breakdown of the gate insulating film. May occur. Therefore, in the manufacturing process, there is a case where a guard ring is provided in order to release electric charges in the wiring and make the gate wiring and the source wiring have the same potential. In the case of the present invention, the guard ring may be formed of a transparent conductive film.

The reason is that since the upper layer side of the gate wiring is a transparent conductive film, the connection between the guard ring and the gate wiring can be formed without any problem by extending the transparent conductive film as it is. Also, the pad of the terminal part on the source wiring side is formed of a transparent conductive film integrated with the guard ring, and if the source wiring is superimposed on this pad, the contact like the connection point between the drain electrode and the pixel electrode is formed. The guard ring and the source wiring can be directly connected without providing a hole. Since there is an original process of patterning a transparent conductive film to form a pixel electrode on the upper layer side of a gate electrode and a gate wiring, if a guard ring is formed at the same time in this process, a photomask can be provided by providing a guard ring. The number does not increase.

A liquid crystal display device according to the present invention is a liquid crystal display device in which a liquid crystal is sandwiched between a pair of substrates arranged opposite to each other.
One of the substrate pairs is the thin film transistor array substrate of the present invention. According to the present invention, a liquid crystal display device having a high response speed and a low cost can be provided by using the thin film transistor array substrate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. The thin film transistor array substrate of the present embodiment
This is an example in which the gate wiring in the bottom-gate thin film transistor has a double wiring structure, and the manufacturing process is an example in which a five-mask process is used. FIG. 1 (a) to (e)
Are cross-sectional views showing a manufacturing process of the thin film transistor array substrate, FIGS. 2A to 2C, 3A and 3B.
FIG.

As shown in FIGS. 1E and 3B, the thin film transistor 1 is provided with a gate electrode 4 integrally formed with a gate wiring 3 on a glass substrate 2 so as to cover the gate electrode 4. Is provided with a gate insulating film 5 made of a SiN _x film. In the case of the present embodiment, gate wiring 3 and gate electrode 4 have a double wiring structure in which the surface of lower layer 6 made of a copper or aluminum film is covered with upper layer 7 made of an ITO film.

A semiconductor active layer 8 made of amorphous silicon (a-Si, semiconductor film) is provided on a gate insulating film 5 covering the gate electrode 4, and amorphous silicon (a-Si: n) containing an n-type impurity such as phosphorus is provided. ⁺ , An impurity semiconductor film), a source electrode 11 and a drain electrode 12 formed integrally with the source wiring 10 on the semiconductor active layer 8 via an ohmic contact layer 9. The source wiring 10, the source electrode 11, and the drain electrode 12 are made of, for example, a molybdenum (Mo) film, an upper aluminum (Al) film, or a lower Mo film.
1 is formed of a laminated film.

An ohmic contact layer 9 is provided on the semiconductor active layer 8 and has a source line 10 and a source electrode 1.
1 and below the drain electrode 12 in a shape completely overlapping with them. In the case of the present embodiment, a stacked body 13 (a-Si: n ⁺ film forming the ohmic contact layer 9, an a-Si film forming the semiconductor active layer 8, and a SiN _x film forming the gate insulating film 5) are laminated. Hereinafter, the island portion is formed in an L-shape in plan view, is bent from the direction in which the source electrode 11 and the drain electrode 12 extend, and extends to the intersection where the gate wiring 3 and the source wiring 10 intersect ( It is a part called "intervening laminated body" in a claim.)

As shown in FIGS. 3B and 4, the SiN _x film 17 and the a-Si film 1
8. Stack 14 in which a-Si: n ⁺ film 19 is sequentially stacked
(Hereinafter, also referred to as an island portion), and an auxiliary capacitance electrode 15 made of a Mo film or an Al laminated film is provided thereon. The auxiliary capacitance electrode 15 is directly connected to the preceding pixel electrode 16 (the upper pixel electrode shown in FIG. 3B) without interposing a contact hole, and the gate wiring 3 for driving the next pixel electrode 16 is provided. And a storage capacitor is formed between the storage capacitor and the storage capacitor. The a-Si film 18 in the stacked body 14 is the same layer as the a-Si film forming the semiconductor active layer 8, and the a-Si: n ⁺ film 19 forms the a-Si: n forming the ohmic contact layer 9. ^{+ The} same layer as the film,
The iN _x film 17 is the same layer as the SiN _x film constituting the gate insulating film 5. Therefore, the a-Si: n ⁺ film 19 in the stacked body 14 is formed under the auxiliary capacitance electrode 15 in a shape completely overlapping with the auxiliary capacitance electrode 15, similarly to the configuration of the ohmic contact layer 9 of the source electrode 11 and the drain electrode 12. ing. The actual storage capacitor is formed by the overlapping portion of the gate line 3 and the storage capacitor electrode 15.

As shown in FIG. 1E, a pixel electrode 16 made of an ITO film is provided on the side of the thin film transistor 1 on the glass substrate 2, and the drain electrode 12 has an end portion at the pixel electrode 16. It is formed so as to partially ride on the end of the. Therefore, the drain electrode 12 and the pixel electrode 16 are not connected through the contact hole formed in the interlayer insulating film, but are directly connected on the pixel electrode 16 without any intervening interlayer insulating film. The ITO film forming the upper layer 7 of the gate wiring 3 and the gate electrode 4 and the ITO film forming the pixel electrode 16 are the same layer. Further, a passivation film 20 made of SiN _x is provided so as to cover the thin film transistor 1, but the passivation film 20 on the pixel electrode 16 has an opening at a central portion except a peripheral portion in a frame shape. The opening 20a serves as a light transmission area.

FIG. 5B is a plan view of the gate terminal pad 21 at the end of the gate wiring 3 located outside the display area. Each is shown. As shown in these figures, the ITO film 22 on the upper layer 7 side of the gate wiring 3
Extend further from the end portion of the metal film 23 on the lower layer 6 side of the gate wiring 3 to the tip end side to form a rectangular pad 21a. On the other hand, the portion above the break line of the source wiring 10 in FIG. 3B and FIG. 6 show the planar structure and the cross-sectional structure of the source terminal pad portion 24 at the end of the source wiring 10 located outside the display area, respectively. I have. As shown in these figures, the tip of the source wiring 10 is formed so as to partially ride over the end of the pad 24 a made of the ITO film 22 on the upper layer 7 side of the gate wiring 3, and the source wiring 10 and the pad 24 are formed.
a is connected. On both the gate side and the source side, the passivation film 20 on the pads 21a and 24a
The center portion is an opening 20b except for a peripheral portion in a frame shape.

Next, a method of manufacturing the thin film transistor array substrate having the above configuration will be described. First, FIG.
As shown in FIG. 2A and FIG. 2A, a copper or aluminum film (metal film) is formed on a glass substrate 2 and is patterned using a normal photolithography technique using a photomask. The lower layer 6 of the gate wiring 3 and the gate electrode 4 is formed. Next, FIG. 1B and FIG.
As shown in (b), an ITO film is formed on the entire surface and is patterned using a photomask to form a gate wiring 3.
Further, the gate wiring 3 covering the lower layer 6 of the gate electrode 4, the upper layer 7 of the gate electrode 4, and the pixel electrode 16 are formed. As a result, the gate wiring 3 and the gate electrode 4 having a double wiring structure are formed. At this time, a pad 21a of the gate terminal pad portion 21 and a pad 24a (not shown) of the source terminal pad portion 24 are also formed.

Next, as shown in FIG. 1C and FIG. 2C, the SiN _x film 17, the a-Si film 18 (semiconductor film), and the a-Si: n ⁺ film 19 (impurity semiconductor film) ) Is formed successively and sequentially, a photoresist (not shown) is applied thereon, and the photoresist is exposed and developed using a photomask to form a resist pattern, and this resist pattern is used as a mask. The above-mentioned three layers are collectively etched to form a laminate 13 in which three layers of the same shape are laminated,
14 (island portion) is formed. In the island part,
As described above, the semiconductor active layer 8 of the thin film transistor 1
There are two types of patterns, an L-shaped island portion extending from the portion forming the intersection to the intersection of the gate wiring 3 and the source wiring 10, and an island portion located at a storage capacitor forming portion on the gate wiring 3.

Next, as shown in FIGS. 1D and 3A, a Mo film or an Al laminated film 25 (metal film) is formed on the entire surface, and a photoresist (not shown) is formed thereon. After application, the photoresist is exposed and developed using a photomask to form a resist pattern, and the resist pattern is used as a mask to form a Mo film or an Al laminated film 25.
Is further etched, and the a-Si: n ⁺ film 19 is etched using the Mo film or the Al laminated film as a mask.
In this step, the source film 10 and the source electrode 11, the drain electrode 12 and the Mo film or the Al film 25 of the island portion 14 on the gate wiring 3 are assisted from the Mo film or the Al film 25 of the L-shaped island portion 13. A capacitor electrode 15 is formed, and a
The ohmic contact layer 9 is formed from the -Si: n ⁺ film 19. When the Mo film or the Al laminated film 25 is formed in this step, the pixel electrode 16 is exposed without being covered with the gate insulating film 5.
A Mo film or an Al laminated film 25 is directly formed thereon, and the drain electrode 12 and the pixel electrode 1 are formed simultaneously with the formation of the electrodes.
6 and the auxiliary capacitance electrode 1
5 and the pixel electrode 16 are electrically connected.

Finally, as shown in FIG. 1E and FIG. 3B, a passivation film 20 is formed by forming a SiN _x film on the entire surface, and then this is patterned using a photomask to form a gate. The opening 20b of the passivation film 20 on each of the pads 21a and 24a of the terminal pad portion 21 and the source terminal pad portion 24, that is, so-called terminal formation, and the opening 20a of the passivation film 20 on the pixel electrode 16 are formed. Through such steps, the thin film transistor array substrate of this embodiment can be manufactured. Then, while preparing this thin film transistor array substrate, a counter substrate on which a common electrode is formed is prepared, and liquid crystal is sealed between these substrates to complete a liquid crystal display device.

In the thin film transistor array substrate of the present embodiment, the gate wiring 3 has a double wiring structure composed of a low-resistance metal film such as copper or aluminum and an ITO film covering the same, so that the There is no possibility that the gate wiring 3 is etched during the etching. Therefore, the resistance of the gate wiring 3 can be reduced without causing a wiring disconnection failure or the like due to the manufacturing process.

When the thin film transistor array substrate is manufactured, patterning for forming the lower layer side of the gate wiring, patterning for forming the upper layer side and pixel electrode, patterning for forming the island portion, source / drain electrode and auxiliary capacitor Patterning for electrode formation, patterning for terminal connection, and 5 times of patterning, ie, 5
It suffices to use two photomasks. That is, an ITO film is used on the upper layer side of the gate wiring 3, and the upper layer 7 of the gate wiring 3 and the pixel electrode 16 are simultaneously patterned, the connection between the drain electrode 12 and the pixel electrode 16, and the auxiliary capacitance electrode 15 and the pixel electrode 16 are formed. Although a double wiring structure is adopted by adopting a structure in which a contact hole is not used for connection with the semiconductor device, the photolithography is compared with the conventional manufacturing method (six mask process) shown in FIG. The number of masks can be reduced by one. Thereby, it is possible to reduce the manufacturing cost and the construction period.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. The basic configuration of the thin film transistor array substrate according to the present embodiment is the same as that of the first embodiment, and the present embodiment is different from the first embodiment in that the gate insulating film is insulated during the manufacturing process. The only difference is that a guard ring is provided to prevent destruction.
Therefore, in the present embodiment, only the configuration of the guard ring portion will be described, and other description will be omitted.

As shown in FIG. 7, also in the case of the present embodiment, the structure of the gate wiring 30 itself composed of the lower layer 35 and the upper layer 36, the gate terminal pad portion 31 of the gate wiring 30 and the source terminal pad of the source wiring 32 The configuration of the unit 33 itself is the same as in the first embodiment. However, in this embodiment, in order to prevent the gate insulating film from being broken down due to electrostatic charging of the substrate during the manufacturing process, the electric charge in the wiring is released and the gate wiring 30 and the source wiring 32 are set to the same potential. A guard ring 34 is provided for the purpose. Therefore,
An upper layer 36 of each gate wiring 30, a gate terminal pad 37,
The gate-side guard resistor 38, the guard ring 34, the source-side guard resistor 39, and the source terminal pad 40 are all integrally formed of an ITO film, and the width of the guard ring 34 and each of the gate lines 30 and each of the source lines 32 are different. Are electrically connected via guard resistors 38 and 39 having a narrow width.

In the case of this embodiment, as shown in FIG.
The guard ring 34 can be electrically connected to the gate wiring 30 and the source wiring 32 without providing any contact hole. As described in the first embodiment, since there is a patterning process of the upper layer 36 of the gate wiring 30 and the ITO film at the time of forming the pixel electrode during the manufacturing process, the guard ring 34 may be formed at the same time in this process. Since the guard ring 34 is provided, the number of photomasks does not increase.

When there is a demand for performing an operation test of the thin film transistor array with the guard ring 34 connected, the operation test can be actually performed because the guard resistance made of the ITO film is high, which is advantageous.

[Third Embodiment] Hereinafter, an example of a TFT type liquid crystal display device using the thin film transistor array substrate of the above embodiment will be described. In the liquid crystal display device of the present embodiment, as shown in FIG. 8, a pair of transparent substrates 43 and 44 are arranged to face each other, and one of these transparent substrates is one of the thin film transistor array substrate and the other substrate. 4
4 is a counter substrate. The pixel electrode 16 is provided on the opposite surface side of the thin film transistor array substrate 43, and the common electrode 45 is provided on the opposite surface side of the opposite substrate 44. Further, alignment films 46 and 47 are provided on each of the pixel electrode 16 and the common electrode 45, and a liquid crystal layer 48 is provided between the alignment films 46 and 47. Further, first and second polarizing plates 49 and 50 are provided outside the transparent substrates 43 and 44, respectively, and a backlight 51 is attached outside the first polarizing plate 50.

In the TFT type liquid crystal display device of the present embodiment, since the gate wiring resistance of the thin film transistor array substrate 43 is low, a liquid crystal display device having a high response speed can be realized. Further, the manufacturing cost can be reduced.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the planar pattern shape and the like of the thin film transistor array substrate described in the above embodiment can be appropriately changed in design. For example, in the above embodiment, the island part to be provided at the intersection of the gate wiring and the source wiring and the island part of the thin film transistor part are formed integrally, but these island parts may be formed separately. Further, it is needless to say that specific materials and the like of each film can be appropriately changed.

[0040]

As described above in detail, according to the present invention, a double wiring structure comprising a low resistance metal film such as copper or aluminum and a transparent conductive film covering the same on the gate wiring of the thin film transistor array substrate. Therefore, there is no possibility that the gate wiring is etched when the pixel electrode is formed. Therefore, the resistance of the gate wiring can be reduced without causing a wiring disconnection defect or the like due to the manufacturing process. In addition, a transparent conductive film is used on the upper layer side of the gate wiring, and a contact hole is formed in the connection between the drain electrode and the pixel electrode and the connection between the auxiliary capacitance electrode and the pixel electrode in that the upper layer of the gate wiring and the pixel electrode are simultaneously patterned. By devising a structure that is not used, it is possible to reduce the number of photomasks as compared with the conventional manufacturing method while adopting a double wiring structure. By using this thin film transistor array substrate, it is possible to reduce the manufacturing cost and the construction period of the liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a thin film transistor array substrate according to a first embodiment of the present invention.
2A is a sectional view taken along line AA in FIG.
FIG. 1B is a sectional view taken along the line BB of FIG.
FIG. 1C is a cross-sectional view taken along line CC of FIG.
FIG. 1D is a sectional view taken along line DD of FIG.
FIG. 3E is a sectional view taken along line EE in FIG. 3B.

FIG. 2 is a plan view of the same.

FIG. 3 is a continuation of the plan view.

FIG. 4 is a cross-sectional view taken along line FF of FIG. 3B, showing the configuration of the auxiliary capacitance section of the thin film transistor array substrate.

FIG. 5 is a cross-sectional view taken along the line GG of FIG. 3B, showing a configuration of a gate terminal pad portion of the thin film transistor array substrate.

FIG. 6 is a cross-sectional view taken along the line HH of FIG. 3B, showing a configuration of a source terminal pad section of the thin film transistor array substrate.

FIG. 7 is a plan view illustrating a configuration of a guard ring of a thin film transistor array substrate according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating an example of a manufacturing process of a conventional thin film transistor array substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Thin film transistor 2 Glass substrate 3, 30 Gate wiring 4 Gate electrode 5 Gate insulating film 6, 36 Lower layer (of gate wiring and gate electrode) 7, 35 Upper layer (of gate wiring and gate electrode) 8 Semiconductor active layer 9 Ohmic contact layer 10 , 32 Source wiring 11 Source electrode 12 Drain electrode 13, 14 Stacked body 15 Auxiliary capacitance electrode 16 Pixel electrode 34 Guard ring

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuyuki Arai 3-31, Meido, Izumi-ku, Sendai, Miyagi Prefecture Inside Frontec Co., Ltd. No. 31 F-term in Frontec Co., Ltd. (Reference) 2H092 JA24 JA26 JA34 JA37 JA41 JA46 JA47 JB57 JB67 KA05 KB24 LA02 MA12 MA13 NA05 NA15 NA17 NA27 NA28 PA01 PA11 PA13 5F110 AA01 AA16 AA22 CC07 EE02 EE03 EE07 EG15 HK03 HK02 HL03 HL04 HL06 HL11 HM18 NN02 NN24 NN71 NN73 QQ01 QQ08

Claims (5)

[Claims] A plurality of source wirings and a plurality of gate wirings each having a metal film surface covered with a transparent conductive film are provided in a matrix on a substrate, and a plurality of gate wirings surrounded by the source wirings and the gate wirings are provided. In each of the regions, a pixel electrode is formed of a transparent conductive film, and a thin film transistor for switchingly driving the pixel electrode is provided. The thin film transistor includes a gate electrode formed integrally with the gate wiring, and a gate covering the gate electrode. A semiconductor active layer composed of a semiconductor film on an insulating film, an ohmic contact layer composed of an impurity semiconductor film thereon, and a lamination composed of the insulating film, the semiconductor film, and the impurity semiconductor film formed other than on the gate electrode A source electrode which is formed on the body and is partly overlapped with the gate electrode and integrally formed with the source wiring; A drain electrode formed overlapping and facing the source electrode and directly connected to the pixel electrode, and forming an auxiliary capacitance between the drain electrode and a gate line adjacent to a gate line driving each pixel electrode. As described above, an auxiliary capacitance electrode directly connected to each of the pixel electrodes is provided, and a stacked body including the gate insulating film, the semiconductor film, and the impurity semiconductor film is formed at an intersection of the gate wiring and the source wiring. It is interposed between the gate line and the source line, and is arranged so as to form a desired auxiliary capacitance below the auxiliary capacitance electrode on the gate line separately from the intervening laminate. Thin film transistor array substrate. 2. The interposed laminated body and a laminated body formed between the gate electrode and the source electrode and composed of the insulating film, the semiconductor film, and the impurity semiconductor film are integrally formed. A thin film transistor array substrate characterized by the above-mentioned. 3. A metal film is formed on a substrate and patterned to form a plurality of lower layers of a plurality of parallelly spaced gate wirings and a plurality of lower layers of a plurality of gate electrodes connected to the respective gate wirings. A transparent conductive film is formed on the entire surface and patterned to form an upper layer of each of the plurality of gate wirings and an upper layer of each of the plurality of gate electrodes, and a plurality of pixel electrodes corresponding to each gate electrode are formed. A film, a semiconductor film and an impurity semiconductor film to which impurities are added are sequentially formed and then collectively patterned to form an insulating film, a semiconductor film and an impurity semiconductor film having the same outer shape on the gate electrode and partially on the gate wiring. A plurality of parallelly spaced source wirings intersecting the plurality of gate wirings after patterning a metal film over the entire surface, and connecting the gate wirings to the source wirings. A source electrode disposed on the impurity semiconductor film so as to partially overlap with a pole, a drain electrode which extends between the impurity semiconductor film and each of the pixel electrodes so as to partially overlap with the gate electrode, and The insulating film, the auxiliary capacitance electrode via the semiconductor film and the impurity semiconductor film on the gate wiring that connects and drives the pixel electrode adjacent to the pixel electrode, the insulating film below the auxiliary capacitance electrode, The insulating film, the semiconductor film, and the impurity semiconductor are separated from a stacked body including the semiconductor film and the impurity semiconductor film and between a gate wiring and a source wiring at a portion where each of the gate wiring and the source wiring intersect. A method for manufacturing a thin film transistor array substrate, comprising: forming an intervening laminate comprising a film. 4. A guard ring for interconnecting said plurality of gate wirings and said plurality of source wirings to prevent dielectric breakdown of a gate insulating film interposed between said gate wirings and said source wirings, said guard ring comprising: 4. The method of manufacturing a thin film transistor array substrate according to claim 3, wherein the gate electrode and the gate wiring are formed simultaneously with the upper layer side and the pixel electrode by patterning a conductive film. 5. A liquid crystal display device in which a liquid crystal is sandwiched between a pair of substrates disposed opposite to each other, wherein one of the substrate pairs is the thin film transistor array substrate according to claim 1 or 2. apparatus.