JP3213067B2 - Thin film transistor array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array used for a liquid crystal display device in which a plurality of display electrodes connected to a thin film transistor are arranged in a matrix, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs) have been used.
And an active matrix type liquid crystal display element (hereinafter, referred to as TFT-LCD) using a thin film transistor array in which display electrodes are arranged in a matrix. As such a conventional TFT-LCD,
For example, a liquid crystal display device disclosed in Japanese Unexamined Patent Publication No. 59-169684 is known, and an equivalent circuit of the TFT array is shown in FIG.

As shown in FIG. 11, a TFT array is arranged on a transparent insulating substrate 1 such that a plurality of address wirings 2 and data wirings 3 cross each other at right angles in a row direction and a column direction, respectively. At the intersections of these address wirings 2 and data wirings 3, the gate electrodes are respectively connected to the address wiring 2,
A plurality of thin film transistors 4 whose drain electrodes are connected to the data lines 3 are arranged, and a plurality of display electrodes 5 connected to the source electrodes of the thin film transistors 4 are arranged in a matrix. On the outer periphery of the transparent insulating substrate 1,
A short ring 6 is formed so as to surround the outer periphery of the substrate 1, and the plurality of data wirings 2 and the plurality of address wirings 3 are connected to the short ring 6, respectively.

After finishing the TFT array, the TFT array is joined to a counter substrate (not shown) on which the opposing electrodes are formed with a predetermined gap with a sealing material, and the substrate 1 is cut along a cutting line 7 indicated by a broken line. Cut along. Then, a liquid crystal material is sealed between these substrates to complete a liquid crystal display device. In this conventional TFT array, during the manufacturing process, since all the address wirings 2 and the data wirings 3 are connected to the short ring 6, respectively, the potentials of all the address wirings 2 and the data wirings 3 become equal, The occurrence of defects such as dielectric breakdown and short-circuit due to discharge of static electricity generated during the manufacturing process of the TFT array between the electrodes is suppressed.

[0005]

However, in a conventional liquid crystal display device using a TFT array, during the manufacturing process of the liquid crystal display device, the TFT array and the substrate facing each other are bonded via a sealing material, and then the short circuit is caused. In order to cut and remove the ring 6 along the cutting line 7, static electricity generated in a manufacturing process such as pasting of a polarizing plate and connection of a driving circuit causes dielectric breakdown, disconnection, change in TFT characteristics, and the like, resulting in a liquid crystal display. There has been a problem that the display defect of the element occurs and the yield is reduced.

According to the present invention, there is provided a thin film transistor array which is capable of reliably preventing display defects due to static electricity of the liquid crystal display element as described above and improving the yield, and which is easy to manufacture and has a simplified structure. It is an object of the present invention to provide a manufacturing method thereof.

[0007]

According to the present invention, in order to achieve the above object, a thin film transistor and a source electrode of the thin film transistor are provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other. A thin film transistor array in which a plurality of display electrodes connected to either one of the drain electrode are arranged in a matrix, the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode. A short-circuit wiring is formed outside a display area in which the display electrodes are arranged, and an island-shaped semiconductor film and both ends thereof are formed.
And two electrodes formed in direct contact with each other.
The holes and electrons in the double implantation two-terminal device to which the voltage-current characteristic defined by the space charge limited current flow between the electrodes, before
The short-circuit wiring, the plurality of address wirings, and the plurality of
It is characterized by being connected to data wiring .

A gate electrode is connected to the address wiring at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other, and one of a source electrode and a drain electrode is connected to the address wiring. and the data line and the respective thin film transistors connected, a display electrode connected to the other electrode of the source electrode and the drain electrode of the thin film transistor in the method of manufacturing the thin-film transistor array that is arrayed in a matrix on a transparent substrate, wherein Get
A first step of forming a over gate electrode and said address lines, and the data line connection of the short-circuit wiring along the address line outside the region display electrodes Ru is formed, the gate
The thin film transistor and the display electrode are formed on the gate electrode.
The vicinity of the address wiring outside the region
In the vicinity of the data wiring connection, an island-shaped semiconductor film and its both ends
And two electrodes formed in direct contact with
A second step of forming a plurality of holes and electrons in the double implantation two-terminal device to which the voltage-current characteristic defined by the space charge limited current flow between the electrodes, one collector of a plurality of the thin film transistor
A data line connecting the poles and the display electrode are formed;
Are arranged along the data line outside the region, and forming a first address line connecting unit step in forming the data line connecting portion and connected to the short-circuit wiring was the
One terminal of the two-terminal element is connected to the address of the short-circuit wiring.
Line connection or data wiring connection portion, characterized in that the other terminal and a third step of connecting each to the A <br/> address lines or data lines.

[0009]

According to the present invention, as described above, even after the step of cutting and removing the short ring during the manufacturing process of the liquid crystal display, the short-circuit wiring formed so as to surround the outside of the display area of the liquid crystal display. And the plurality of address wirings and the plurality of data wirings are connected to a space charge limited current (Space Charge Limited Curr).
ent) are connected by a hole-electron double-injection type two-terminal element (hereinafter referred to as an SCLC element) whose voltage-current characteristics are defined. The element resistance is sufficiently high at normal driving voltage, and when a high voltage is applied by static electricity, a large current flows and a substantial short circuit occurs.
After the short ring is cut and removed, it is possible to prevent a defect caused by static electricity in the TFT array.

In particular, since the element is a double-injection type two-terminal element of holes and electrons, the current is very small due to the high resistance of the semiconductor layer on the low electric field side, and shows ohmic voltage-current characteristics. On the electric field side, as the voltage increases, electrons and holes are trapped in localized levels in the band gap of amorphous silicon to form space charges, and as a result,
Since the Fermi level is displaced to the conduction band side, the density of conduction electrons increases, and the current rapidly increases without being proportional to the voltage. When a high electric field is further applied, holes pass through the element, and the injection of carriers increases. The injection becomes more dominant than the recombination, and the SCLC characteristic of the double injection of holes and electrons becomes the current. It becomes easier to flow.

Therefore, when a high voltage is applied to the address wiring and the data wiring due to static electricity, a large current flows and the state can be immediately shifted to a substantial short-circuit state. Further, according to the present invention, in the process of forming a TFT array on a substrate, the SCL having a non-linear voltage-current characteristic can be provided without increasing the number of patterning masks and processes.
A C element can be formed.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a schematic configuration of a TFT array according to a first embodiment of the present invention.
In FIG. 1, a TFT array is arranged such that a plurality of address wirings 12 extending in a row direction on a substrate 11 and a plurality of data wirings 13 extending in a column direction are insulated from each other and intersect. And a plurality of these address lines 1
2 and a plurality of data lines 13, a TFT 14 connected to these lines and a display electrode 15 connected to each of the TFTs 14 are provided, and these display electrodes 15 are arranged in the row and column directions. And a plurality of display areas are formed.

A short ring 16 made of a conductive film is formed on an outer peripheral edge of the substrate 11, and the plurality of address wirings 12 and the plurality of data wirings 13 extend from the display area, respectively. It is connected to the. The short ring 16 is formed after a TFT array manufacturing process is completed or after a substrate facing the TFT array is joined during a process of forming a liquid crystal cell.
It is cut and removed along a cutting line indicated by a broken line 17 in FIG.

In the vicinity of the outside of the display area and inside the cutting line 17, a short-circuit wiring 18 surrounding the display area is formed so as to be insulated from and intersect with the address wiring 12 and the data wiring 13. , This short-circuit wiring 18
A data wiring connection portion 18a provided substantially parallel to the address wiring 12 is formed on the surface of the substrate 11, and an address wiring connection portion 18b provided substantially parallel to the data wiring 13 of the short-circuit wiring 18 will be described later. It is formed on the gate insulating film 42. And this short-circuit wiring 1
8 and the address wiring 12 and the data wiring 13 are connected to a space charge limiting current (Space Charge Limit).
ted Current) defines voltage-current characteristics,
Double injection of holes and electrons with nonlinear voltage-current characteristics 2
Terminal elements (SCLC elements) 19 are connected to each other.

The address wiring 12 of the TFT array
FIGS. 2 and 3 show the structure of the TFT 14 and the display electrode 15 arranged at the intersections between the TFT 14 and the data wiring 13. As shown in these figures, the address wiring 12 and the data wiring 1
3 are formed so as to intersect with each other via a gate insulating film 42 and an intersecting portion insulating film 21 which will be described later.
TFTs 14 each having a drain electrode 46 connected to the TFT 3
Are formed, and the source electrode 48 of the TFT 14 is connected to the display electrode 15.

The TFT 14 is configured as follows. A gate electrode 41 protruding from the address wiring 12 and a gate insulating film 42 covering the gate electrode 41 are formed on the substrate 11. A semiconductor film 43 made of amorphous silicon is formed at a position of the gate insulating film 42 corresponding to the gate electrode 41, and an element region is formed. A blocking layer 44 made of silicon nitride is formed in a channel portion of the semiconductor film 43, and a drain electrode 46 is formed on one side of the semiconductor film 43 via an ohmic junction layer 45 made of a semiconductor doped with impurities. The drain electrode 46 is connected to the data wiring 13. On the other side of the semiconductor film 43, a source electrode 48 is formed via an ohmic junction layer 47 made of a semiconductor doped with impurities, and the source electrode 48 is connected to the display electrode 15 made of a transparent conductive film. I have. Further, on the TFT 14,
A protection film 49 is formed.

A short-circuit wiring 18 disposed to intersect the address wiring 12 and the data wiring 13 respectively, and the short-circuit wiring 18 and the address wiring 12 and the data wiring 13
The hole-electron double injection type SCLC element 19 connected between these elements is configured as shown in FIGS.
That is, an island-shaped semiconductor film 91 is formed on the gate insulating film 42 covering the address wiring 12 formed on the substrate 11, and two electrodes are separated on the semiconductor film 91 to form the semiconductor film 91. A semiconductor protection layer 92 for protection is formed. On both sides of the semiconductor film 91 with the semiconductor protection layer 92 interposed therebetween, a connection electrode 97 of the hole and electron double injection type SCLC element 19 and an address wiring connection portion The connection electrode 18d of the hole and electron double injection type SCLC element 19 connected to the gate insulating film 4 is connected to the connection electrode 18d.
2 is connected to the address wiring 12 or directly to the data wiring 13 through a contact hole 42a provided in the second connection electrode 18d.
Are connected to the short-circuit wiring 18 through a contact hole 42b (see FIG. 9D).

The hole and electron double injection type SCLC device 19 shown in FIGS. 4 and 5 has a structure in which no ohmic junction layer is interposed between its electrodes, so that both electrons and holes serve as carriers. Injected. That is, it is a double injection type. In particular, as shown in FIG.
On the high electric field side, as the voltage increases, electrons and holes are trapped in localized levels in the band gap of amorphous silicon to form space charges, and as a result,
Since the Fermi level is displaced to the conduction band side, the density of conduction electrons increases, and the current rapidly increases without being proportional to the voltage.

Further, when a high electric field is applied, holes pass through the device, the injection of carriers increases, and the injection becomes more dominant than the recombination.
It becomes CLC characteristic, and current flows more easily. Therefore, when a high voltage is applied to the address wiring and the data wiring due to static electricity, a large current flows and the state can be shifted to a substantial short-circuit state quickly.

As described above, as the applied voltage increases, the excess electrons injected into the amorphous silicon are trapped by the localized levels in the band gap of the amorphous silicon, and the space charges are released. Form. As a result, since the Fermi level is displaced toward the conductor, the density of conduction electrons increases, and the current rapidly increases without being proportional to the voltage. Such a current is called a space charge limited current, and a semiconductor having a localized level, such as amorphous silicon, exhibits a large non-linear voltage-current characteristic.

By arranging such SCLC elements as shown in FIG. 1, a high voltage is applied to one of the address wirings or data wirings by static electricity after the short ring is cut off in the substrate cutting step. Even if the current flows through the SCLC element, all the address wirings and data wirings are immediately maintained at the same potential. In this embodiment, near the outside of the display area and inside the cutting line, a short-circuit wiring 18 surrounding the display area is provided.
The short-circuit wiring 18 and the address wiring 12 and the data wiring 13 are formed of an SCLC having a large non-linear voltage-current characteristic as described above. Element 1
9, the short ring 16 is cut and removed along the cutting line 17 after the substrate facing the TFT array is joined after the manufacturing process of the TFT array or the manufacturing process of the liquid crystal cell. After that, when a high voltage due to static electricity is applied to either or both of the address wiring 12 and the data wiring 13, a large current flows through the SCLC element 19, and the address wiring 12 and the data wiring 13 are kept at the same potential. Dripping. Therefore, after the short ring 16 is cut and removed, a high voltage due to static electricity is applied to the address wiring 12 or the data wiring 13.
Is applied between these wirings 12 and 13 and the TFT.
There is no deterioration or insulation breakdown between the gate electrode 41 and the drain electrode 46 of the fourteenth embodiment, and no change in the threshold value of the TFT.

Since a liquid crystal display using this TFT array is usually driven at a voltage of about 25 V, as shown in FIG.
The resistance of the element 19 is sufficiently high, and the address wiring 12, the data wiring 13, the address wiring 12 and the data wiring 13
Since the leakage current flowing therebetween is a very small current on the order of 10 ^-9 to 10 ^-7 A, a clear image can be displayed without affecting the data signal applied to each display electrode 15 at all. After the short ring 16 is cut off, an electrical inspection for disconnection and short-circuit of the wiring and each T
FT characteristics and the like can also be electrically measured.

Hereinafter, a method of manufacturing the above-described TFT array will be described with reference to FIGS. FIG. 7 shows TF
8 shows the manufacturing process of the T portion, FIG. 8 shows the manufacturing process of the SCLC element portion, and FIG. 9 shows the manufacturing process of the intersection of the address wiring 12 and the data wiring connecting portion 18a formed in the upper layer and the upper and lower layers of the short-circuit wiring 18. The manufacturing process of the bonding portion 18c between the data wiring connecting portion 18a and the address wiring connecting portion 18b is shown in the order of processes.

First, a metal or alloy thin film such as Cr, Al, Ta, Ti, W or the like is deposited on a transparent insulating substrate 11 such as glass by a sputtering method, and is selectively etched. 8A and FIG. 9
An address wiring 12 shown in FIG. 9A and a lower data wiring connection portion 18a (hereinafter referred to as a lower layer short-circuit wiring) arranged in parallel with the address wiring 12 shown in FIG. 9 are formed. In this step, the short ring 16 on the outer peripheral portion of the substrate 11 shown in FIG. 1 is also formed at the same time.

Next, the gate insulating film 4 is formed on the substrate 11 on which the gate electrode 41 and the like are formed by a plasma CVD method.
3 are successively deposited on the silicon nitride film serving as the second semiconductor film 43, the amorphous silicon film 43a serving as the semiconductor film 43, and the silicon nitride film serving as the blocking layer 44. FIG. 8B shows a portion corresponding to the channel portion of the TFT 14 shown in FIG.
An unnecessary portion other than a portion corresponding to the semiconductor protective layer 92 of the C element 19 and a portion corresponding to an intersection between the address wiring 12 shown in FIG. Blocking layer 4 on each part
4. The semiconductor protective layer 92 and the inter-wiring insulating film 21 are formed respectively.

The blocking layer 44 on the substrate 11
Over the entire upper surface of the amorphous silicon film on which
Ohmic bonding layers 45, 47,
An amorphous silicon layer to which impurities of 93 and 95 are added is formed, and Cr is continuously formed by sputtering.
Etc. are sequentially deposited. Then, after the metal thin film and the amorphous silicon layer to which the impurity is added are removed by etching the portion of the TFT 14 other than the device region, the amorphous silicon film 43a other than the TFT 14 and the SCLC device 19 is continuously etched. At the same time, the metal thin film and the amorphous silicon layer to which the impurity is added are removed by etching on the blocking layer 44 of the TFT, and the TFT is removed as shown in FIGS.
As shown in FIG. 9C, a source electrode 48 and a drain electrode 46 of the TFT 14 are formed, respectively.
As shown in (C), the amorphous silicon film 43a is removed except for the intersection of the address wiring 12 and the upper-layer short wiring 18b.
Is removed.

Next, the TFT 14 on the substrate 11, the SCLC
A transparent conductive thin film such as ITO is deposited on the element 19 and the gate insulating film 42, and the transparent conductive thin film is etched to form the source electrode 4 of the TFT 14 as shown in FIG.
8 (D), a display electrode 15 connected to the address line 8 is formed, and a silicon nitride film on a terminal of the address line (not shown) for connecting the address line 12 to a drive circuit.
9B, a contact hole 42a is formed in the silicon nitride film on the address wiring 12, and a contact hole 42 is formed in the silicon nitride film on the lower-layer shorting wiring 18a as shown in FIG.
b is formed.

Thereafter, a thin film of a metal or alloy such as Al, Ti, Mo, Cr or the like, or a laminated film composed of a plurality of such metal films is deposited on the TFT by sputtering.
After etching, the data wiring 13 shown in FIG.
A connection electrode 97 for connecting the address wiring 12 and the SCLC element 19 shown in FIG. 9E, and an upper layer arranged in parallel with the data wiring 13 of the short-circuit wiring 18 shown in FIGS. Short-circuit wiring section (hereinafter referred to as upper layer short-circuit wiring)
18b.

In this step, the drain electrode 46 of the TFT 14 is connected to the data line 13, and the data line 13 is connected to the lower layer short-circuiting line 18 a at the portion where the SCL is connected.
One electrode of the C element 19 is connected, and the other electrode is connected to the lower layer short-circuit wiring 18a. Also, address wiring 1
2 arranged at the intersection of the upper layer short-circuit wiring 18b
One end of the LC element 19 is connected to the upper-layer short-circuit wiring 18b (electrode). Further, the upper-layer short-circuit wiring 18b is connected to the lower-layer short-circuit wiring 18a through a contact hole 42b formed in the silicon nitride film on the lower-layer short-circuit wiring 18a, and is connected to the address wiring 12 for forming the gate insulating film 42. Silicon nitride film, amorphous silicon film 4
3a and the silicon nitride film for forming the blocking layer 44 of the TFT 14.

Finally, the protective film 4 is formed by the plasma CVD method.
By depositing a silicon nitride film to be 9 on the entire surface of the substrate and then etching it, as shown in FIGS. 3 and 5,
Terminal portions formed at the ends of the address wiring 12 and the data wiring 13 for connection to the drive circuit;
The protective film 49 is formed by removing the silicon nitride film in a portion corresponding to the upper pixel region 50.

As described above, the TFT array of this embodiment includes a TFT 14 formed on a substrate and a TFT 14 formed on the substrate.
Are connected to the address wiring 12, the data wiring 13 and the SCLC element 19 connecting these wirings.
A thin film for forming the TFT 14 and an etching process thereof are sequentially formed without forming any special film during the process of forming the TFT 14. Therefore, the SCLC element 19
It is possible to easily manufacture a TFT array including the hole-electron double injection type SCLC element 19 without increasing the number of steps for forming the TFT.

In the embodiment described above, the gate electrode 4
1 and the address wiring 12 are made of Cr, Al, Ta, Ti,
The case where the gate electrode 41 and the address wiring 12 are formed of a metal or alloy film such as W has been described. However, the gate electrode 41 and the address wiring 12 are not limited thereto, and a stacked film formed by sequentially depositing a plurality of the metals or the like may be used. In order to improve the insulating properties of the gate electrode 41 and the address wiring 12, the surface may be partially or entirely oxidized by anodic oxidation, thermal oxidation, or the like.

Next, a second embodiment will be described with reference to FIG. The second embodiment is different from the SCLC element 1 described above.
In this embodiment, a plurality of circuits 9 are connected between the address wiring 12 and the data wiring 13 and the short-circuit wiring 18. In FIG.
The SCLC element 19 is connected in parallel between the
And two are also connected in parallel with the data wiring 13.

According to the second embodiment, the SCLC element 1
When the switch 9 is turned on, the current carrying capacity of the parallel circuit of the SCLC element 19 is doubled, and the protection effect against static electricity can be improved. The present invention is not limited to the case where two SCLC elements 19 are connected in parallel as in the third embodiment described above, but a plurality of SCLC elements 19 may be connected in parallel.

The present invention is not limited to the second embodiment, and although not shown, the SCLC element 19 is connected to the address line 1.
Two or more may be connected in series between the two and two, and two or more may be connected in series with the data wiring 13. In this case, the off-resistance of the series circuit of the SCLC element 19 is increased, and the leakage current flowing between the address wiring 12 and the data wiring 13 and the leakage current flowing between the address wiring 12 and the data wiring 13 can be suppressed. . And, as detailed, SCLC
Even when a TFT array is formed by connecting a plurality of elements 19, a special film can be formed during the process of forming the TFT array on the substrate in the same manner as in the first embodiment. Also, without going through a special etching process,
A plurality of SCLC elements 19 can be formed by connecting to the address wiring 12 and the data wiring 13.

As described above, in each of the film elements constituting the SCLC element, the semiconductor layer is formed of the n ^- a-Si layer of the TFT, and the first and second upper electrodes which are in direct contact with the semiconductor layer are formed of the TFT. Of data wiring. Therefore,
Materials and processes required for manufacturing an SCLC device are as follows:
All are included in the process of manufacturing the above-described TFT array pixel portion, and unnecessary ohmic junction layers are simultaneously removed at the time of processing the source and drain electrodes.
There is no additional process, and the SCLC element is formed simultaneously with the TFT array.

Even when an unnecessary ohmic junction layer is removed, even if etching damage is given to the semiconductor protective layer, the characteristics of the SCLC element are not affected, and the semiconductor film or gate not covered by the semiconductor protective layer is removed. Even when the insulating film is damaged such as a pinhole, since no other electrode is formed under the gate insulating film, defects such as short circuits are increased, and the manufacturing yield of the TFT array is reduced. Nothing.

When the underlayer is made of glass, the characteristics of the high-resistance semiconductor layer may fluctuate due to fluctuations in the quality of the glass surface, thereby deteriorating the characteristics of the SCLC element. Is a SiN film formed continuously with the high-resistance semiconductor layer, so that the characteristics of the high-resistance semiconductor layer do not depend on the underlayer. It should be noted that the present invention is not limited to the above embodiments, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0039]

As described above in detail, according to the present invention, the short-circuit wiring 18 is formed outside the display area of the liquid crystal display so as to surround this display area. Since the plurality of address wirings 12 and the plurality of data wirings 13 are respectively connected by the hole and electron double injection type SCLC element 19 having a non-linear voltage-current characteristic, after the short ring 16 is cut and removed, Address lines 12 and the data lines 1
When a high voltage due to static electricity is applied to any one of 3, a large current flows and a substantial short-circuit occurs, resulting in the same potential, dielectric breakdown between both wirings, and insulation between the gate electrode 41 and the drain electrode 46. It is possible to prevent defects such as deterioration of TFT characteristics due to failure.

In addition, the element resistance is sufficiently high at a normal driving voltage, and the leakage current flowing between the address wiring, between the data wiring and between the address wiring and the data wiring is a very small current. Can display a clear image without any effect. Further, during the process of forming the TFT 14 on the substrate, the hole and electron double injection type two-terminal device 19 having a simplified non-linear voltage-current characteristic without increasing the number of patterning masks and processes. Can be formed.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a TFT array showing a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pixel portion in the TFT array of FIG. 1;

FIG. 3 is a cross-sectional view showing the TFT structure of FIG. 2 cut along line AA.

FIG. 4 is an enlarged plan view showing an SCLC element portion in the TFT array of FIG. 1;

FIG. 5 is a cross-sectional view illustrating the SCLC element structure of FIG. 4 cut along line BB.

FIG. 6 is a diagram showing an example of a voltage-current characteristic of an SCLC element used in the TFT array of the present invention.

7A to 7E are cross-sectional views showing respective manufacturing steps of a TFT portion in the TFT array of the first embodiment shown in FIG.

8A to 8E are manufacturing process diagrams of the SCLC element portion in the TFT array according to the first embodiment shown in FIG.
Are cross-sectional views showing respective manufacturing steps.

9A and 9B are manufacturing process diagrams of intersections between address wires and upper-layer short-circuit wires and connection portions between upper-layer short-circuit wires and lower-layer short-circuit wires in the TFT array of the first embodiment shown in FIG. FIGS. 4A to 4E are cross-sectional views showing the respective manufacturing steps taken along the line CC along the upper-layer short-circuit wiring.

FIG. 10 is an equivalent circuit diagram of a TFT array showing a second embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram showing a conventional TFT array.

[Explanation of symbols]

11 Substrate 12 Address Wiring 13 Data Wiring 14, 24 TFT 15 Display Electrode 16 Short Ring 18 Short Wiring 18a Data Wiring Connection (Lower Short Wiring) 18b Address Wiring Connection (Upper Short Wiring) 18c Junction 18d Connection Electrode 19,29 Double-hole and electron-injection type two-terminal element (S
CLC element) 21 Intersection insulating film (inter-wiring insulating film) 41 Gate electrode 42 Gate insulating film 42a, 42b Contact hole 43, 91 Semiconductor film 43a Amorphous silicon film 44 Blocking layer 45, 47, 93, 95 Ohmic junction layer 46 Drain Electrode 48 Source electrode 49 Protective film 50 Pixel region 92 Semiconductor protective layer 94, 96 Electrode 97 Connection electrode

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Sasaki 2951-5 Ishikawacho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Laboratory (72) Inventor Hiroyuki Okimoto 2951-5 Ishikawacho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Institute (56) References JP-A-2-106722 (JP, A) JP-A-62-187885 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) G02F 1/1362 G02F 1/1345 H01L 29/78

Claims (4)

(57) [Claims] 1. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are arranged in a matrix at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to cross each other. In a thin film transistor array in which the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, a short circuit is formed outside the display area where the display electrodes are arranged. wiring
Is formed, and the island-shaped semiconductor film is directly contacted with both ends.
And two electrodes formed Te, the holes and electrons in the double implantation two-terminal device in which the voltage-current characteristic defined by the air <br/> between charge limited current flow between the electrodes, for the short wiring
And the plurality of address lines and the plurality of data lines
Is connected to the thin film transistor array. 2. The short-circuit wiring is formed on a transparent substrate.
Data wiring connection and insulation covering the data wiring connection
With the address wiring connection formed above the film.
The data wiring connection part and the address wiring connection part
The thin film transistor array according to claim 1, wherein each of both ends, characterized in that it is connected to the other wiring connections. 3. A gate electrode is connected to the address wiring at each intersection of a plurality of address wirings and a plurality of data wirings arranged so as to intersect each other, and one of a source electrode and a drain electrode is connected to the address wiring. A method of manufacturing a thin film transistor array in which a plurality of thin film transistors each connected to a data wiring and a plurality of display electrodes connected to the other of the source electrode and the drain electrode of the thin film transistor are arranged in a matrix. to the a to the outside of the gate electrode and the address lines, and the area where the display electrodes Ru is formed
A first step of forming a data wiring connection portion of the short-circuit wiring along the dress wiring ; (b) a thin film transistor on the gate electrode;
Of the address wiring outside the region where the display electrodes are formed.
In the vicinity and in the vicinity of the data wiring connection portion, an island-shaped semiconductor
A membrane and two electrodes formed in direct contact with both ends
Comprising a, a hole and electron double implantation two-terminal device to which the voltage-current characteristic defined by the space charge limited current between said electrodes
A second step of forming a plurality , and (c) connecting one electrode of the plurality of thin film transistors
A data wiring line, outside of said display electrodes are formed regions
And the address wiring connection part of the short-circuit wiring connected to the data wiring connection part formed in the first step and arranged along the data wiring, and the two-terminal element is formed.
One of the terminals is connected to the address wiring connection portion of the short-circuit wiring.
Or the data line connection section, the third step in the method of manufacturing the thin film transistor array comprising the for respectively connecting the other terminal to the address lines or data lines. 4. The method according to claim 1, wherein the third step is performed on the transparent substrate.
The data wiring connection part, and the data wiring connection part
The address wiring connection formed above the insulating film to be covered;
And the other end of each part to the other end of the wiring connection.
Method of manufacturing a thin film transistor array according to claim 3, wherein Rukoto provided with that process.