JP3231410B2 - Thin film transistor array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array used for a liquid crystal display device in which a plurality of display electrodes connected to a thin film transistor are arranged in a matrix, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs) have been used.
) And an active matrix type liquid crystal display element (hereinafter, referred to as a TFT-LCD) using a thin film transistor array in which display electrodes are arranged in a matrix. As such a conventional TFT-LCD,
For example, a liquid crystal display device disclosed in Japanese Unexamined Patent Publication No. 59-169684 is known, and an equivalent circuit of the TFT array is shown in FIG.

As shown in FIG. 13, a TFT array is arranged on a transparent insulating substrate 1 such that a plurality of address wirings 2 and data wirings 3 cross each other at right angles in a row direction and a column direction, respectively. At the intersections of these address wirings 2 and data wirings 3, the gate electrodes are respectively connected to the address wiring 2,
A plurality of thin film transistors 4 whose drain electrodes are connected to the data lines 3 are arranged, and a plurality of display electrodes 5 connected to the source electrodes of the thin film transistors 4 are arranged in a matrix. On the outer periphery of the transparent insulating substrate 1,
A short ring 6 is formed so as to surround the outer periphery of the substrate 1, and the plurality of data wirings 2 and the plurality of address wirings 3 are connected to the short ring 6, respectively.

After finishing the TFT array, the TFT array is joined to a counter substrate (not shown) on which the opposing electrodes are formed with a predetermined gap with a sealing material, and the substrate 1 is cut along a cutting line 7 indicated by a broken line. Cut along. Then, a liquid crystal material is sealed between these substrates to complete a liquid crystal display device. In this conventional TFT array, during the manufacturing process, since all the address wirings 2 and the data wirings 3 are connected to the short ring 6, respectively, the potentials of all the address wirings 2 and the data wirings 3 become equal, The occurrence of defects such as dielectric breakdown and short-circuit due to discharge of static electricity generated during the manufacturing process of the TFT array between the electrodes is suppressed.

[0005]

However, in a conventional liquid crystal display device using a TFT array, during the manufacturing process of the liquid crystal display device, the TFT array and the substrate facing each other are bonded via a sealing material, and then the short circuit is caused. In order to cut and remove the ring 6 along the cutting line 7, static electricity generated in a manufacturing process such as pasting of a polarizing plate and connection of a driving circuit causes dielectric breakdown, disconnection, change in TFT characteristics, and the like, resulting in a liquid crystal display. There has been a problem that the display defect of the element occurs and the yield is reduced.

It is an object of the present invention to provide a thin film transistor array which can surely prevent a display defect due to static electricity of the liquid crystal display element as described above and improve the yield, and which is easy to manufacture, and a method of manufacturing the same. Aim.

[0007]

According to the present invention, a thin film transistor and a thin film transistor are provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged on a transparent substrate so as to cross each other. A plurality of display electrodes connected to one of the source electrode and the drain electrode are arranged in a matrix, the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode. In the thin film transistor array, the display electrode is formed outside the display region surrounding the arrayed array, and is formed above the data line connection portion formed on the transparent substrate and the insulating film covering the data line connection portion. A short-circuit wire, each end of which is connected to another wire connection portion, and The short-circuit wiring, the plurality of address wirings, and the plurality of data wirings are formed at an intersection of the island-shaped semiconductor film and the ohmic junction layer formed at both ends of the island-shaped semiconductor film and the ohmic junction layer. A plurality of two-terminal elements comprising two electrodes connected to each other and exhibiting a large non-linear voltage-current characteristic due to a space charge limiting current between the electrodes, and one electrode of the two-terminal element is connected to the short-circuit wiring. And the other electrode is connected to one of the address wiring and the plurality of data wirings.

In addition, the gate electrode and the address wire are formed on a transparent substrate, and a data wire connection portion of a short-circuit wire is formed along the address wire outside a region where the display electrode is formed. a first step, the vicinity of the on the gate electrode to form a thin film transistor having a gate insulating film and the semiconductor film and the source electrode and the drain electrode, the outer side of the region where the display electrodes Ru formed the address lines, the Near the data wiring connection,
A voltage-current characteristic comprising an island-shaped semiconductor film, an ohmic junction layer formed at both ends thereof separated from each other and two electrodes connected to the ohmic junction layer, and having a large non-linearity due to a space charge limited current between the electrodes. A second step of forming a plurality of two-terminal elements, and forming a data line connecting one electrode of the plurality of thin film transistors ;
Wherein the display electrodes are arranged along the data lines on the outside of the forming area, it was connected at both ends of the first lower than the gate insulating film formed in the step of the data wiring connection portion and its respectively forming an address wiring connection portions of the short-circuit wire
And a third step of connecting one terminal of the two-terminal element to an address wiring connection part or a data wiring connection part of the short-circuit wiring, and connecting the other terminal to the address wiring or the data wiring, respectively. It is characterized by having.

[0009]

According to the present invention, as described above, even after the step of cutting and removing the short ring during the manufacturing process of the liquid crystal display, the short-circuit wiring formed so as to surround the outside of the display area of the liquid crystal display. And the plurality of address wirings and the plurality of data wirings are connected to a space charge limited current (Space Charge Limited Curr).
ent) are connected by a two-terminal element (hereinafter referred to as an SCLC element) whose voltage-current characteristic is defined. This two-terminal element has a non-linear voltage-current characteristic, and the element resistance is sufficiently high at a normal driving voltage. When a high voltage is applied due to static electricity, a large current flows and a substantial short circuit occurs.
The occurrence of defects due to static electricity in the array can be prevented.

Further, according to the present invention, it is possible to form the SCLC element having a non-linear voltage-current characteristic without increasing the number of masks and steps for patterning during the step of forming a TFT array on a substrate. .

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a schematic configuration of a TFT array according to a first embodiment of the present invention.
In FIG. 1, a TFT array is arranged such that a plurality of address wirings 12 extending in a row direction on a substrate 11 and a plurality of data wirings 13 extending in a column direction are insulated from each other and intersect. And a plurality of these address lines 1
2 and a plurality of data lines 13, a TFT 14 connected to these lines and a display electrode 15 connected to each of the TFTs 14 are provided, and these display electrodes 15 are arranged in the row and column directions. And a plurality of display areas are formed.

A short ring 16 made of a conductive film is formed on an outer peripheral edge of the substrate 11, and the plurality of address wirings 12 and the plurality of data wirings 13 extend from the display area, respectively. It is connected to the. The short ring 16 is formed after a TFT array manufacturing process is completed or after a substrate facing the TFT array is joined during a process of forming a liquid crystal cell.
It is cut and removed along a cutting line indicated by a broken line 17 in FIG.

In the vicinity of the outside of the display area and inside the cutting line 17, a short-circuit wiring 18 surrounding the display area is formed so as to be insulated from and intersect with the address wiring 12 and the data wiring 13. , This short-circuit wiring 18
A data wiring connection portion 18a provided substantially parallel to the address wiring 12 is formed on the surface of the substrate 11, and an address wiring connection portion 18b provided substantially parallel to the data wiring 13 of the short-circuit wiring 18 will be described later. It is formed on the gate insulating film 42. And this short-circuit wiring 1
8 and the address wiring 12 and the data wiring 13 are connected to a space charge limiting current (Space Charge Limit).
ted Current) defines voltage-current characteristics,
They are connected by two-terminal elements (SCLC elements) 19 having non-linear voltage-current characteristics.

The address wiring 12 of this TFT array
FIGS. 2 and 3 show the structure of the TFT 14 and the display electrode 15 arranged at the intersections between the TFT 14 and the data wiring 13. As shown in these figures, the address wiring 12 and the data wiring 1
3 are formed so as to intersect with each other via a gate insulating film 42 and an intersecting portion insulating film 21 which will be described later.
TFTs 14 each having a drain electrode 46 connected to the TFT 3
Are formed, and the source electrode 48 of the TFT 14 is connected to the display electrode 15.

The TFT 14 is configured as follows. A gate electrode 41 protruding from the address wiring 12 and a gate insulating film 42 covering the gate electrode 41 are formed on the substrate 11. A semiconductor film 43 made of amorphous silicon is formed at a position of the gate insulating film 42 corresponding to the gate electrode 41, and an element region is formed. A blocking layer 44 made of silicon nitride is formed in a channel portion of the semiconductor film 43, and a drain electrode 46 is formed on one side of the semiconductor film 43 via an ohmic junction layer 45 made of a semiconductor doped with impurities. The drain electrode 46 is connected to the data wiring 13. On the other side of the semiconductor film 43, a source electrode 48 is formed via an ohmic junction layer 47 made of a semiconductor doped with impurities, and the source electrode 48 is connected to the display electrode 15 made of a transparent conductive film. I have. Further, on the TFT 14,
A protection film 49 is formed.

A short-circuit wiring 18 disposed so as to intersect the address wiring 12 and the data wiring 13, and the short-circuit wiring 18, the address wiring 12 and the data wiring 13.
4 and 5 are connected to the SCLC element 19 connected between
It is configured as shown in FIG. That is, an island-shaped semiconductor film 91 is formed on the gate insulating film 42 covering the address wiring 12 formed on the substrate 11.
A semiconductor protective layer 92 for separating the two electrodes and protecting the semiconductor film 91 is formed on both sides of the semiconductor film 91 with the semiconductor protective layer 92 interposed therebetween. Ohmic junction layer 9 made of
Electrodes 94 and 96 are formed via 3, 95. Then, one electrode 94 is connected to or directly address lines 12 by connecting conductors 97 through the contact holes 42a provided in the gate insulating film 42, the other electrode 96 directly
Or in contact holes (not provided in the gate insulating film 42
Without) through a connection conductor (not shown) by Ru is connected to the short wiring 18. Then, these two-terminal element region is covered with the protective film 49.

In the SCLC element 19 shown in FIGS. 4 and 5, as the voltage applied between the electrodes 94 and 96 increases, excess electrons injected into the amorphous silicon Is trapped by a localized level in the band gap of the semiconductor device to form a space charge.
As a result, the Fermi level is displaced toward the conductor,
The conduction electron density increases, and the current increases rapidly, not in proportion to the voltage. Such a current is called a space charge limiting current,
As shown in FIG. 6, a semiconductor having a localized level, such as amorphous silicon, has a large non-linear voltage-current characteristic.

In this embodiment, near the outside of the display area and inside the cutting line, the short-circuit wiring 18 surrounding the display area is provided with the address wiring 12 and the data wiring 1.
3 is formed so as to be insulated from and intersect with the address wiring 12 and the address wiring 12 and the data wiring 1.
3 are connected to each other by the SCLC elements 19 having the above-described voltage-current characteristics having large nonlinearity.
After the T-array manufacturing process or the liquid crystal cell manufacturing process, after the substrate facing the TFT array is joined and the short ring 16 is cut and removed along the cutting line 17, the address wiring 12 or the data wiring is formed. 1
When a high voltage due to static electricity is applied to any one or both of them, a large current flows through the SCLC element 19, and the address wiring 12 and the data wiring 13 are kept at the same potential. Therefore, even if a high voltage due to static electricity is applied to the address line 12 or the data line 13 after the short ring 16 is cut and removed, these lines 12, 1
3 and the gate electrode 41 and the drain electrode 4 of the TFT 14
There is no deterioration or breakdown of insulation between the TFTs 6 and no change in the threshold value of the TFT.

Since a liquid crystal display using this TFT array is usually driven at a voltage of about 25 V, as shown in FIG.
The resistance of the element 19 is sufficiently high, and the address wiring 12, the data wiring 13, the address wiring 12 and the data wiring 13
Since the leakage current flowing therebetween is a small current of the order of 10 ⁻¹⁰ A, a clear image can be displayed without affecting the data signal applied to each display electrode 15 at all. After the short ring 16 is cut off, electrical inspection for disconnection and short-circuit of the wiring, and characteristics of each TFT can be electrically measured.

The method of manufacturing the TFT array described above will now be described with reference to FIG. 7 乃 optimum Figure 9. FIG. 7 shows TF
The T portion of the manufacturing process, add to 8 SCLC element part of the manufacturing process, Figure 9 is formed on the upper layer and the address lines 12
Intersection of less wiring connection portions 18 b,及 Beauty shorting wire 18
The manufacturing process of the junction portion 18c of the data lines connecting section 18a and the address wiring connecting portion 18b formed under layer and the upper layer is shown in each step order.

First, a thin film of a metal or alloy such as Cr, Al, Ta, Ti, W, etc. is deposited on a transparent insulating substrate 11 such as glass by a sputtering method, and is selectively etched. 8A and FIG. 9
An address wiring 12 shown in FIG. 9A and a lower data wiring connection portion 18a (hereinafter referred to as a lower layer short-circuit wiring) arranged in parallel with the address wiring 12 shown in FIG. 9 are formed. In this step, the short ring 16 on the outer peripheral portion of the substrate 11 shown in FIG. 1 is also formed at the same time.

Next, the gate insulating film 4 is formed on the substrate 11 on which the gate electrode 41 and the like are formed by a plasma CVD method.
3 are successively deposited on the silicon nitride film serving as the second semiconductor film 43, the amorphous silicon film 43a serving as the semiconductor film 43, and the silicon nitride film serving as the blocking layer 44. FIG. 8B shows a portion corresponding to the channel portion of the TFT 14 shown in FIG.
An unnecessary portion other than a portion corresponding to the semiconductor protective layer 92 of the C element 19 and a portion corresponding to an intersection between the address wiring 12 shown in FIG. Blocking layer 4 on each part
4. The semiconductor protective layer 92 and the inter-wiring insulating film 21 are formed respectively.

The blocking layer 44 on the substrate 11
Over the entire upper surface of the amorphous silicon film on which
Ohmic bonding layers 45, 47,
An amorphous silicon layer to which impurities of 93 and 95 are added is formed, and Cr is continuously formed by sputtering.
Etc. are sequentially deposited. Thereafter, the metal thin film, the amorphous silicon layer to which the impurities are added, and the amorphous silicon film in portions other than the device region of the TFT 14 and the device region of the SCLC device 19 are continuously etched and removed, and the blocking layer 44 of the TFT is formed.
The metal thin film and the amorphous silicon layer to which the impurities are added are removed by etching on the upper portion and the semiconductor protective layer 92, and as shown in FIGS. 7C and 8C,
The source electrode 48 and the drain electrode 46 of the FT 14 and S
Two electrodes 94 and 96 of the CLC element 19 are respectively formed, and as shown in FIG.
The amorphous silicon film 43a is removed except for the intersections between the wiring 2 and the upper-layer wiring 18b.

Next, the TFT 14 on the substrate 11, SCLC
A transparent conductive thin film such as ITO is deposited on the element 19 and the gate insulating film 42, and the transparent conductive thin film is etched to form the source electrode 4 of the TFT 14 as shown in FIG.
8 (D), a display electrode 15 connected to the address line 8 is formed, and a silicon nitride film on a terminal of the address line (not shown) for connecting the address line 12 to a drive circuit.
9B, a contact hole 42a is formed in the silicon nitride film on the address wiring 12, and a contact hole 42 is formed in the silicon nitride film on the lower-layer shorting wiring 18a as shown in FIG.
b is formed.

After that, a thin film of a metal or alloy such as Al, Ti, Mo, Cr, or the like, or a laminated film composed of a plurality of such metal films is deposited on the TFT by sputtering.
After etching, the data wiring 13 shown in FIG.
A connection conductor 97 connecting the address wiring 12 and the SCLC element 19 shown in FIG. 8E, and an upper layer arranged in parallel with the data wiring 13 of the short-circuit wiring 18 shown in FIGS. 8E and 9E. Short-circuit wiring section (hereinafter referred to as upper layer short-circuit wiring)
18b.

In this step, the drain electrode 46 of the TFT 14 is connected to the data line 13, and the data line 13 is connected to the SCL at a portion where the data line 13 intersects with the lower-layer short-circuit line 18 a.
One electrode of the C element 19 is connected, and the other electrode is connected to the lower layer short-circuit wiring 18a. Also, address wiring 1
2 arranged at the intersection of the upper layer short-circuit wiring 18b
The LC element 19 has one of its electrodes connected to the upper-layer short-circuit wiring 18.
b. Further, the upper-layer short-circuit wiring 18b is connected to the lower-layer short-circuit wiring 18a through a contact hole 42b formed in the silicon nitride film on the lower-layer short-circuit wiring 18a, and is connected to the address wiring 12 for forming the gate insulating film 42. Silicon nitride film, amorphous silicon film 43
a and a silicon nitride film for forming the blocking layer 44 of the TFT 14.

Finally, the protective film 4 is formed by a plasma CVD method.
By depositing a silicon nitride film to be 9 on the entire surface of the substrate and then etching it, as shown in FIGS. 3 and 5,
Terminal portions formed at the ends of the address wiring 12 and the data wiring 13 for connection to the drive circuit;
The protective film 49 is formed by removing the silicon nitride film in a portion corresponding to the upper pixel region 50.

As described above, the TFT array of this embodiment is composed of the TFT 14 formed on the substrate and the TFT 14
Are connected to the address wiring 12, the data wiring 13 and the SCLC element 19 connecting these wirings.
A thin film for forming the TFT 14 and an etching process thereof are sequentially formed without forming any special film during the process of forming the TFT 14. Therefore, the SCLC element 19
A TFT array including the SCLC element 19 can be easily manufactured without increasing the number of steps for forming the TFT.

In the embodiment described above, the gate electrode 4
1 and the address wiring 12 are made of Cr, Al, Ta, Ti,
The case where the gate electrode 41 and the address wiring 12 are formed of a metal or alloy film such as W has been described. However, the gate electrode 41 and the address wiring 12 are not limited thereto, and a stacked film formed by sequentially depositing a plurality of the metals or the like may be used. In order to improve the insulating properties of the gate electrode 41 and the address wiring 12, the surface may be partially or entirely oxidized by anodic oxidation, thermal oxidation, or the like.

As shown in FIGS. 10 and 11, the present invention provides a TFT having a structure without the blocking layer 44 and the semiconductor protective film 92 and a TFT provided with the SCLC element.
The same applies to arrays. Figure 10 below
A second embodiment will be described with reference to FIG. The same members as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 10 shows a sectional structure of a TFT according to the second embodiment, and FIG. 11 shows a sectional structure of an SCLC element.
In FIG. 10, a TFT 24 has a semiconductor film 43 formed so as to cover a gate electrode 41 via a gate insulating film 42.
A metal film is formed on the substrate through ohmic junction layers 45 and 47, and a drain electrode 46 and a source electrode 48 are formed by the ohmic junction layers 45 and 47 and the metal film. A channel portion is formed in the semiconductor film 43 between 46. The source electrode 48 has a display electrode 15 made of a transparent conductive film.
Are connected, and the data line 13 is connected to the drain electrode 46.

In FIG. 11, the SCLC element 29 has a T
A semiconductor film 91 is formed on a silicon nitride film to be a gate insulating film 42 of the FT 24, and a metal film is laminated on both ends thereof via ohmic junction layers 93 and 95.
4,96 are formed. One electrode 96 of the SCLC element 29 is connected to the upper-layer short-circuit wiring 18b, and the other electrode 94 is connected to the address wiring 12.

In the second embodiment, the TFT 2
4. The arrangement and connection structure of the SCLC element 29 with the data wiring 12, the address wiring 13, and the short-circuit wiring 18 are formed in the same manner as in the first embodiment. The TFT array of the second embodiment is formed in the same manner as in the first embodiment described above in the step of forming the TFT 24 and the SCLC element 29 having the structures shown in FIGS. That is, the TFT 24 and the SCLC element 29 of the second embodiment are
As shown in FIGS. 7 (a), 8 (a) and 9 (a),
After forming the gate electrode 41, the address wiring 12, and the lower-layer short-circuiting wiring 18a on the substrate, the silicon nitride film to be the gate insulating film 42 and the amorphous silicon film to be the semiconductor film 43, the ohmic bonding layer 45, 47,
By continuously forming an amorphous silicon layer to which impurities of 93 and 95 are added and a metal film and continuously etching these laminated films, TFT and SCLC are obtained.
An element region is formed, and the metal film and the amorphous silicon layer to which impurities are added in a portion corresponding to the channel portion of the TFT 24 and a portion corresponding to between the electrodes of the SCLC element 29 are removed by etching.
C element 29 is formed.

In the second embodiment, as in the first embodiment, the address lines 12 and the data lines 13 are connected by SCL.
Since the connection is made by the C element 29, when a high voltage due to static electricity is applied to either or both of the address wiring 12 and the data wiring 13, a large current flows through the SCLC element 29, and the address wiring 12 and the data wiring 13 are connected to each other. The wiring 13 is maintained at a conductive potential. Therefore, even if a high voltage due to static electricity is applied to the address wiring or the data wiring after cutting and removing the short ring, the deterioration or insulation between the wirings 12 and 13 and between the gate electrode 41 and the drain electrode 46 of the TFT 24 is deteriorated. No destruction occurs. Further, the TFT array of this embodiment is composed of TFT2
4 are sequentially formed by a thin film for forming the SCL 4 and its etching process, so that the SCL can be performed without increasing the number of processes.
A TFT array including the C element 29 can be easily manufactured.

Hereinafter, a third embodiment will be described with reference to FIG. In the third embodiment, the SCLC element 1 described above is used.
In this embodiment, a plurality of circuits 9 are connected between the address wiring 12 and the data wiring 13 and the short-circuit wiring 18. In FIG.
The SCLC element 19 is connected in parallel between the
And two are also connected in parallel with the data wiring 13.

According to the third embodiment, the SCLC element 1
When the switch 9 is turned on, the current carrying capacity of the parallel circuit of the SCLC element 19 is doubled, and the protection effect against static electricity can be improved. The present invention is not limited to the case where two SCLC elements 19 are connected in parallel as in the third embodiment described above, but a plurality of SCLC elements 19 may be connected in parallel.

Further, the present invention is not limited to the third embodiment, and although not shown, two or more SCLC elements 19 are connected in series between the address wiring 12 and the data wiring 13. May be connected in series. In this case, the off-resistance of the series circuit of the SCLC element 19 is increased, and the leakage current flowing between the address wiring 12 and the data wiring 13 and the leakage current flowing between the address wiring 12 and the data wiring 13 can be suppressed. . And, as detailed, SC
Even when a plurality of LC elements 19 are connected to form a TFT array, a special film may be formed during the process of forming the TFT array on the substrate in the same manner as in the first embodiment. Also, a plurality of SCLC elements 19 can be formed by connecting to the address wiring 12 and the data wiring 13 without going through a special etching step.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0039]

As described above in detail, according to the present invention, the short-circuit wiring 18 is formed outside the display area of the liquid crystal display so as to surround this display area. The plurality of address wirings 12 and the plurality of data wirings 13 have nonlinear voltage-current characteristics.
Since they are connected by the CLC elements 19, when a high voltage due to static electricity is applied to either the address wiring 12 or the data wiring 13 to the TFT array after cutting and removing the short ring 16, a large current flows, and As a result, it becomes possible to prevent the occurrence of a defect such as deterioration of TFT characteristics due to insulation breakdown between the two wirings and insulation failure between the gate electrode 41 and the drain electrode 46 or the like.

In addition, the element resistance is sufficiently high at a normal driving voltage, and the leakage current flowing between the address wiring, between the data wiring and between the address wiring and the data wiring is a very small current. Can display a clear image without any effect. Further, the SCLC element 19 having a non-linear voltage-current characteristic can be formed without increasing the number of masks and steps for patterning during the process of forming the TFT 14 on the substrate.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a TFT array showing a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pixel portion in the TFT array of FIG. 1;

FIG. 3 is a cross-sectional view showing the TFT structure of FIG. 2 cut along line AA.

FIG. 4 is an enlarged plan view showing an SCLC element portion in the TFT array of FIG. 1;

FIG. 5 is a cross-sectional view illustrating the SCLC element structure of FIG. 4 cut along line BB.

FIG. 6 is a diagram showing an example of a voltage-current characteristic of an SCLC element used in the TFT array of the present invention.

7A to 7E are cross-sectional views showing respective manufacturing steps of a TFT portion in the TFT array of the first embodiment shown in FIG.

8A to 8E are manufacturing process diagrams of the SCLC element portion in the TFT array according to the first embodiment shown in FIG.
Are cross-sectional views showing respective manufacturing steps.

9A and 9B are manufacturing process diagrams of intersections between address wires and upper-layer short-circuit wires and connection portions between upper-layer short-circuit wires and lower-layer short-circuit wires in the TFT array of the first embodiment shown in FIG. FIGS. 4A to 4E are cross-sectional views showing the respective manufacturing steps taken along the line CC along the upper-layer short-circuit wiring.

FIG. 10 is a sectional view showing a structure of a TFT portion used in a TFT array according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a structure of an SCLC element used in a TFT array according to a second embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a TFT array showing a third embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram showing a conventional TFT array.

[Explanation of symbols]

 11 Substrate 12 Address Wiring 13 Data Wiring 14, 24 TFT 15 Display Electrode 16 Short Ring 18 Short Wiring 18a Data Wiring Connection (Lower Short Wiring) 18b Address Wiring Connection (Upper Short Wiring) 18c Junction 19, 29 2-terminal element (SCLC element) 21 Intersection insulating film (inter-wiring insulating film) 41 Gate electrode 42 Gate insulating film 42a, 42b Contact hole 43, 91 Semiconductor film 43a Amorphous silicon film 44 Blocking layer 45, 47, 93, 95 Ohmic Junction layer 46 Drain electrode 48 Source electrode 49 Protective film 50 Pixel region 92 Semiconductor protective layer 94, 96 Electrode 97 Connection conductor

Continued on front page (72) Inventor Hiroyuki Okimoto 2951-5 Ishikawacho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Laboratory (72) Inventor Tsutomu Nomoto 2951-5 Ishikawacho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Laboratory (72) Inventor Shunichi Sato 2951-5 Ishikawacho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Laboratories (56) References JP-A-2-106722 (JP, A) JP-A-63-85586 (JP, A) JP-A-62-187885 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1345 G02F 1/1362 G02F 1/1343 G02F 1/13 101

Claims (2)

(57) [Claims] A display device connected to one of a thin film transistor and a source electrode or a drain electrode of the thin film transistor at each intersection of a plurality of address wirings and a plurality of data wirings arranged on a transparent substrate so as to cross each other; In a thin film transistor array in which a plurality of electrodes are arranged in a matrix, the address wiring is connected to a gate electrode of the thin film transistor, and a data wiring is connected to the other of the source electrode and the drain electrode, a display region in which the display electrodes are arranged. the surrounding is formed on the outside, the consists of a transparent substrate on the formed data line connection portion and the data line connection unit address wiring connection portion formed in a layer above the insulating film covering the both ends each other wirings A short-circuit wire connected to the connection portion; the short-circuit wire, the plurality of address wires, and the plurality of wires. An island-shaped semiconductor film formed at a position where the data wiring intersects each other; an ohmic junction layer formed at both ends of the island-shaped semiconductor film; and two electrodes connected to the ohmic junction layer. A plurality of two-terminal elements exhibiting a large non-linear voltage-current characteristic due to a space charge limiting current, wherein one electrode of the two-terminal element is connected to the short-circuit wiring, and the other electrode is connected to the address wiring and the plurality of electrodes. A thin film transistor array connected to one of the data wirings. 2. A gate electrode is connected to the address wiring at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other on a transparent substrate, and one of a source electrode and a drain electrode is provided. A method for manufacturing a thin film transistor array in which a plurality of thin film transistors each having an electrode connected to the data wiring, and a plurality of display electrodes connected to the other of the source electrode and the drain electrode of the thin film transistor are arranged in a matrix. A first step of forming the gate electrode and the address line on the transparent substrate, and forming a data line connection portion of a short-circuit line along the address line outside a region where the display electrode is formed; (B) a thin film transistor having a gate insulating film, a semiconductor film, a source electrode and a drain electrode on the gate electrode; To form a static, said the vicinity of than the area where the display electrodes Ru is formed outside of said address lines, said adjacent data line connections, the island-like semiconductor film and the ohmic junction formed by spaced both ends A second step of forming a plurality of two-terminal elements comprising a layer and two electrodes connected to the ohmic junction layer, and exhibiting a large non-linear voltage-current characteristic due to a space charge limited current between the electrodes; c) forming a data line connecting one electrode of the plurality of thin film transistors, and being arranged along the data line outside a region where the display electrode is formed;
Forming the address wiring connecting portion at both ends in the wiring short-circuit which is connected to the first lower layer data line connecting portion than said gate insulating film formed in the step and its respectively, and, one of said two-terminal element And a third step of connecting the other terminal to the address wiring connection part or the data wiring connection part of the short-circuit wiring, and connecting the other terminal to the address wiring or the data wiring, respectively. Method.