JP2015115428A - Electrostatic protective element and electrostatic protective circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic protective element suitable for installation in an active matrix display device using a print TFT, and to provide an electrostatic protection circuit.SOLUTION: In an electrostatic protective element consisting of two gate electrodes facing each other, and a semiconductor where the two gate electrodes are connected by the bottom contact, the current-voltage characteristics are nonlinear characteristics. Furthermore, in an electrostatic protective element consisting of two source-drain electrodes facing each other, and a semiconductor where the two source-drain electrodes are connected by the bottom contact, the current-voltage characteristics are nonlinear characteristics.

Description

  The present invention relates to an electrostatic protection element and an electrostatic protection circuit using the same.

  In recent years, thin film transistors (TFTs) manufactured by a printing process have attracted attention (see, for example, Non-Patent Document 1). Here, the printing process refers to a method for producing a semiconductor element without using a vacuum process by coating or a printing method (inkjet, letterpress, intaglio, planographic, stencil, etc.). In the electronics field, which frequently uses vacuum processes, the printing process is promising as an innovative technology for production systems. It has been noticed that TFTs (printing TFTs) manufactured by a printing process have a large area, low cost, low environmental load, low temperature formation, and flexibility.

  When manufacturing an active matrix display device using TFT (for example, an electronic paper display), an electrostatic protection element using the TFT and an electrostatic protection circuit using the same are often provided around the display area (for example, patents). Reference 1).

  In particular, Patent Document 1 proposes an electrostatic protection circuit that does not require a through hole in a gate insulating film or an interlayer insulating film.

Monthly OPTRONICS May 2011 Special Feature

JP 2001-352069 A

  In the production of an active matrix type display device using a printed TFT, when the source / drain electrodes are formed by letterpress printing, the connection between the gate electrode and the source / drain electrodes is attempted through the through hole of the gate insulating film. There was a problem that the yield was lowered due to the occurrence of defects.

  In addition, when the gate electrode and the source / drain electrode are connected by another electrode layer through the interlayer insulating film, the semiconductor cannot be protected from static electricity in the process from the formation of the semiconductor to securing the connection. .

  Furthermore, the through-holeless electrostatic protection circuit disclosed in Patent Document 1 cannot form a protective element for connecting the gate lines, and cannot protect the gate lines.

  The present invention solves the above-described problems and provides an electrostatic protection element suitable for installation in an active matrix display device using a printed TFT and an electrostatic protection circuit using the same.

  In the present invention, the following features are provided alone or in combination as appropriate.

In order to achieve the above object, an invention according to claim 1 of the present invention is an electrostatic protection element comprising two opposing gate electrodes and a semiconductor in which the two gate electrodes are connected by a bottom contact, The electrostatic protection element is characterized in that the current-voltage characteristics exhibit nonlinear characteristics.

  The gate wiring has a structure in which a bottom contact connection is made by a semiconductor (active layer of TFT) (inter-gate wiring protection element).

In order to achieve the above object, the invention of claim 2 of the present invention provides:
An electrostatic protection element comprising a semiconductor having two source / drain electrodes opposed to each other and a bottom contact between the two source / drain electrodes, wherein the current-voltage characteristic exhibits a non-linear characteristic. This is a protective element.

  It has a structure in which a source and a drain electrode are bottom-contact connected by a semiconductor (a protection element between source and drain wiring).

In order to achieve the above object, the invention of claim 3 of the present invention provides:
2. The electrostatic protection element according to claim 1, wherein the two gate electrodes and the semiconductor are formed simultaneously with the TFT in a TFT manufacturing process.

In order to achieve the above object, the invention of claim 4 of the present invention provides:
3. The electrostatic protection element according to claim 2, wherein the two source / drain electrodes and the semiconductor are formed simultaneously with the TFT in a TFT manufacturing process.

In order to achieve the above object, the invention of claim 5 of the present invention provides:
A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the gate wiring via the electrostatic protection element according to claim 1. Is.

  It has a structure in which all adjacent gate wirings are bottom contact connected by a semiconductor (gate wiring protection circuit).

In order to achieve the above object, the invention of claim 6 of the present invention provides:
A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit having a pixel region formed thereon, wherein the adjacent wiring is connected to the drain wiring via the electrostatic protection element according to claim 2. Is.

  It has a structure in which all adjacent drain wirings are bottom contact connected by a semiconductor (source / drain wiring protection circuit).

In order to achieve the above object, the invention of claim 7 of the present invention provides:
A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the gate wiring via the electrostatic protection element according to claim 3. Is.

In order to achieve the above object, the invention of claim 8 of the present invention provides:
A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring 5. An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the drain wiring via the electrostatic protection element according to claim 4. Is.

  With the above configuration (protection element between gate lines), the gate lines can be connected to each other by a bidirectional nonlinear element.

  With the above configuration (protection element between source and drain wirings), the drain wirings can be connected with a bidirectional nonlinear element.

  With the above configuration (gate wiring protection circuit), static electricity generated in the gate wiring can be distributed among the gate wirings, and the antistatic performance can be improved.

  With the above configuration (source / drain wiring protection circuit), static electricity generated in the drain wiring can be distributed among the source wirings, and the antistatic performance can be improved.

  With the above structure, an electrostatic protection circuit for the gate wiring and the drain wiring can be formed without increasing the TFT manufacturing process.

It is layer structure explanatory drawing of the electrostatic protection element and pixel TFT by this invention. It is the figure which showed typically the voltage-current characteristic of the electrostatic protection element by this invention. It is a circuit explanatory drawing of the electrostatic protection circuit by this invention, and a display apparatus using the same. It is layer structure explanatory drawing of the electrostatic protection element and pixel TFT by this invention. It is a circuit explanatory drawing of the electrostatic protection circuit by this invention, and a display apparatus using the same.

<Embodiment 1>
An electrostatic protection element and an electrostatic protection circuit using the same according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a layer structure of an electrostatic protection element and a pixel TFT according to the present invention. The pixel TFT 9 includes a base material 1, a gate electrode wiring 2, a gate insulating layer 3, a source / drain electrode wiring 4, a semiconductor layer 5, a semiconductor protective layer 6, an interlayer insulating layer 7, and a pixel electrode layer 8. With.

The inter-gate wiring protection element 10 includes a base material 1, a gate electrode wiring 2, a semiconductor layer 5, a semiconductor protective layer 6, and an interlayer insulating layer 7. The gate electrode wiring 2 and the semiconductor layer 5 are bottom contact connected.

  The source / drain wiring protection element 11 includes a base material 1, a gate insulating layer 3, a source / drain electrode wiring 4, a semiconductor layer 5, a semiconductor protective layer 6, and an interlayer insulating layer 7. The source / drain electrode wiring 4 and the semiconductor layer 5 are bottom-contact connected.

  Since the layers constituting the gate line protection element 10 and the source line protection element 11 are configured as described above, they are simultaneously formed in the process of manufacturing the corresponding layers of the pixel TFT 9. As a manufacturing method, a conventional technique can be used, and can be exemplified in the following order of steps.

Production Example 1
(Process 1)
A gate electrode wiring 2 for TFT and two gate electrode wirings 2 constituting the inter-gate wiring protection element 10 are formed on the substrate 1.
(Process 2)
A gate insulating layer 3 is formed on the entire surface of the substrate 1. However, the part which comprises the protection element 10 between gate wirings is remove | excluded. In the case of forming by a printing method, a pattern excluding this part is printed by an insulator. In the case of the photolithography method, an insulating layer is formed on the entire surface, and then a resist pattern having an opening at this portion is formed, and the insulating layer is removed by etching.
(Process 3)
A source / drain electrode wiring 4 for TFT and two source / drain electrode wirings 4 constituting the inter-source wiring protection element 11 are formed on the gate insulating layer 3. In step 3, the printing method is preferred.
(Process 4)
A semiconductor layer 5 is formed on the source / drain electrode wiring 4 for the TFT on the base material and the two source / drain electrode wirings 4 constituting the protection element 11 between the source wirings and the protection element 10 between the gate wirings. Form. It is preferable to form by a printing method.
(Process 5)
The semiconductor protective layer 6 is formed on the semiconductor layer 5 (formation of the gate wiring protection element 10 and the source / drain wiring protection element 11).
(Step 6)
An interlayer insulating layer 7 is formed on the entire surface of the gate insulating layer 3.
(Step 7)
A hole for connection with the pixel electrode is formed in the interlayer insulating layer 7.
(Process 8)
The pixel electrode layer 8 is formed on the interlayer insulating layer 7 in a pattern.
Through the above steps, the gate insulating film and the interlayer insulating film can be formed by either a printing method or a photolithography method. Other processes are preferably printed.

  In Production Example 1, the semiconductor parts of the TFT, the source line protection element 11, and the gate line protection element 10 were simultaneously formed in Step 4. However, the inter-gate wiring protection element 10 may be formed before the gate oxide film is formed. The manufacturing method in that case is illustrated below.

Production Example 2
(Process 1)
A gate electrode wiring 2 for TFT and two gate electrode wirings 2 constituting the inter-gate wiring protection element 10 are formed on the substrate 1.
(Process 2)
A semiconductor layer 5 is formed on the two gate electrode wirings 2 constituting the inter-gate wiring protection element 10 on the substrate. It is preferable to form by a printing method.
(Process 3)
A semiconductor protective layer 6 is formed on the semiconductor layer 5 of the two gate electrode wirings 2 on the substrate (formation of the inter-gate wiring protection element 10).
(Process 4)
A gate insulating layer 3 is formed on the entire surface of the substrate 1.
(Process 5)
A source / drain electrode wiring 4 for TFT and two source / drain electrode wirings 4 constituting the inter-source wiring protection element 11 are formed on the gate insulating layer 3.
(Step 6)
A semiconductor layer 5 is formed on the source / drain electrode wiring 4 for TFT on the base material and the two source / drain electrode wirings 4 constituting the inter-source wiring protection element 11. It is preferable to form by a printing method.
(Step 7)
A semiconductor protective layer 6 is formed on the semiconductor layer 5 (formation of the protective element 11 between source / drain wirings).
(Process 8)
An interlayer insulating layer 7 is formed on the entire surface of the gate insulating layer 3.
(Step 9)
A hole for connection with the pixel electrode is formed in the interlayer insulating layer 7.
(Process 10)
The pixel electrode layer 8 is formed on the interlayer insulating layer 7 in a pattern.

  Similar to Manufacturing Example 1, the gate insulating film and the interlayer insulating film can be formed by either a printing method or a photolithography method. Other processes are preferably printed.

  FIG. 2 is a diagram schematically showing voltage-current characteristics of the electrostatic protection element according to the present invention. In this way, nonlinear characteristics are exhibited. The gate line protection element and the source line protection element exhibit non-linear characteristics as shown in the figure bidirectionally through an appropriate manufacturing process. That is, since such a protective element exhibits the same non-linear characteristics regardless of the direction of the applied voltage, this protective element is shown as a circuit in which two diodes are connected in reverse direction in parallel.

  The semiconductor layer according to the electrostatic protection element of the first embodiment is the same as that used for the TFT. In the semiconductor layer used for the TFT, when no gate voltage is applied, the channel is not formed and the transistor is in an OFF state (normally off). When a gate voltage is applied, carriers are accumulated and a channel is formed and turned on. Therefore, since the electrostatic protection element of the present invention does not have a gate electrode, it exhibits high resistance within the range of normal operating voltage (0 to 80V). Since it is non-linear and has high resistance, almost no current flows through the electrostatic protection element within the range of the normal operating voltage. However, abnormal static electricity is generated, and a protective current flows at a high voltage such as 100 V or higher.

  In particular, in the above-described steps, Step 4 in Production Example 1 and Steps 2 and 6 in Production Example 2 are particularly non-linear characteristics in the printing method, so it is preferable to employ the printing method.

FIG. 3 is a diagram for explaining an example of the circuit configuration of the electrostatic protection circuit according to the present invention and a display device using the same.
The image display portion is a normal active matrix type circuit format.
In order to specify a pixel, a gate wiring and a drain wiring are selected.

The gate wiring inputs a drive signal from a gate terminal around one substrate constituting the active matrix display device, and a plurality of gate wirings are wired in parallel.
The drain wiring is located above the gate wiring, is orthogonal to the gate wiring through an insulating film, and inputs a drive signal from a drain terminal around the substrate on which the gate terminal is arranged. Thus, a plurality of wires are wired in parallel.
And it has a pixel region formed corresponding to the intersection of the gate wiring and the drain wiring.
Such a configuration is the premise of the electrostatic protection circuit of this example.
In this example, adjacent gate lines are connected to such a gate line via the inter-gate line protection element 10 of the first embodiment.

  Further, adjacent wirings are connected to the drain wiring via the source-drain wiring protection element 11 of the first embodiment.

As described above, in this example, adjacent gate lines are connected by the protective element 10 between the gate lines, and adjacent drain lines are connected by the protective element 11 between the source and drain lines. With this configuration, static electricity generated in the gate wiring can be distributed among the gate wirings, and static electricity generated in the source wiring can be distributed among the source wirings, thereby improving the anti-static performance.
<Embodiment 2>
In the above embodiment, the adjacent drain wiring is connected using the protection element 11 between the source and drain wirings, but a floating gate TFT type protection element may be used for connecting the drain wiring.

  FIG. 4 is a diagram for explaining the layer structure of the electrostatic protection element and the pixel TFT according to the present invention. The floating gate TFT protection element 12 includes a base material 1, a gate electrode wiring 2, a gate insulating layer 3, a source / drain electrode wiring 4, a semiconductor layer 5, a semiconductor protective layer 6, and an interlayer insulating layer 7. Is provided. The layers 1 to 7 are simultaneously formed in the process of manufacturing the corresponding layers of the pixel TFT 9. For example, in the above manufacturing method, the gate electrode wiring constituting the floating gate TFT type protection element 12 is formed in step 1, and in the subsequent process, the gate electrode wiring is formed in the same process as the source / drain wiring protection element 11. That's fine.

  The floating gate TFT exhibits a non-linear voltage-current characteristic without being manufactured by a printing method.

  FIG. 5 is a diagram for explaining the circuit configuration of an electrostatic protection circuit according to the present invention and a display device using the same. The image display portion is a normal active matrix type circuit format as in the first example. Adjacent gate wirings are connected by an inter-gate wiring protection element 10, and adjacent drain wirings are connected by a floating gate TFT type protection element 12. With this configuration, static electricity generated in the gate wiring can be distributed among the gate wirings, and static electricity generated in the drain wiring can be distributed among the drain wirings, thereby improving the anti-static performance.

  The present invention can be expected to be applied to the electronics field.

DESCRIPTION OF SYMBOLS 1 Base material 2 Gate electrode wiring 3 Gate insulating layer 4 Source / drain electrode wiring 5 Semiconductor layer 6 Semiconductor protective layer 7 Interlayer insulating layer 8 Pixel electrode layer 9 Pixel TFT
10 Protection element between gate wirings 11 Protection element between source / drain wirings 12 Floating gate TFT type protection element

Claims (8)

  An electrostatic protection element comprising two opposing gate electrodes and a semiconductor in which the two gate electrodes are connected by a bottom contact, wherein the current-voltage characteristics exhibit nonlinear characteristics.   An electrostatic protection element comprising a semiconductor having two source / drain electrodes opposed to each other and a bottom contact between the two source / drain electrodes, wherein the current-voltage characteristic exhibits a non-linear characteristic. Protective element.   2. The electrostatic protection element according to claim 1, wherein the two gate electrodes and the semiconductor are formed simultaneously with the TFT in a TFT manufacturing process.   3. The electrostatic protection element according to claim 2, wherein the two source / drain electrodes and the semiconductor are formed simultaneously with the TFT in a TFT manufacturing process.   A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the gate wiring via the electrostatic protection element according to claim 1.   A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the drain wiring via the electrostatic protection element according to claim 2.   A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring An electrostatic protection circuit comprising: a pixel region, wherein the adjacent wiring is connected to the gate wiring via the electrostatic protection element according to claim 3.   A plurality of parallel gate wirings for inputting a driving signal from one peripheral gate terminal of the substrate constituting the active matrix display device, the gate wiring above the gate wiring and perpendicular to the gate wiring through an insulating film, and A plurality of parallel drain wirings for inputting a drive signal from a drain terminal on the periphery different from one periphery of the substrate on which the gate terminal is disposed, and formed corresponding to an intersection of the gate wiring and the drain wiring 5. An electrostatic protection circuit, comprising: a pixel region, wherein the adjacent wiring is connected to the drain wiring via the electrostatic protection element according to claim 4.

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