JP2020064699A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of storing multi-valued data.SOLUTION: A semiconductor device 100 includes a first transistor 101, a second transistor 102, a first capacitor 103, a second capacitor 104, and a third transistor 105. The first and second transistors respectively have an oxide semiconductor layer. A gate of the first transistor is electrically connected to a first word line, one of a source and a drain of the first transistor is electrically connected to a bit line, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and to one of electrodes of the first capacitor. A gate of the second transistor is electrically connected to a second word line, and the other of the source and the drain of the second transistor is electrically connected to a gate of the third transistor and one of electrodes of the second capacitor.SELECTED DRAWING: Figure 1

Description

The present invention relates to an object, a method, or a manufacturing method. In particular, the present invention relates to, for example, a semiconductor device, a display device, a light emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to a semiconductor device, a display device, or a light emitting device including an oxide semiconductor.

Patent Document 1 describes a semiconductor device having a transistor having an oxide semiconductor layer on a semiconductor substrate having a MOS transistor. In addition, Patent Document 2 describes that a transistor including an oxide semiconductor film has an extremely small leak current in an off state.

JP, 2010-141230, A JP 2012-257187 A

An object of one embodiment of the present invention is to provide a semiconductor device that can store multi-valued information.

One object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like with low power consumption. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like including a transparent semiconductor layer. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like including a highly reliable semiconductor layer.

Note that the description of these problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are obvious from the description of the specification, drawings, claims, etc., and other problems can be extracted from the description of the specification, drawings, claims, etc. Is.

One embodiment of the present invention includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a third transistor, and a region where a channel of the first transistor is formed is oxidized. A region in which the channel of the second transistor is formed has an oxide semiconductor layer, and the gate of the first transistor is electrically connected to the first word line;
One of a source and a drain of the transistor is electrically connected to a bit line, and the other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor and one of the first capacitor. The gate of the second transistor is electrically connected to the electrode, the gate of the second transistor is electrically connected to the second word line, and the other of the source and the drain of the second transistor is the gate of the third transistor and the second transistor. Is a semiconductor device electrically connected to one electrode of the capacitive element.

The operation of writing information in the semiconductor device includes a step of accumulating charges from the bit line into the first capacitor element and the second capacitor element and a step of further accumulating charges from the bit line into the first capacitor element. Then, in the operation of reading information, the step of turning on the third transistor by the voltage of the second capacitance element and the step of turning on the second transistor to turn on the first capacitance element and the second capacitance element are performed. And a step of connecting in parallel.

The first capacitor and the second capacitor are connected in parallel, and the third transistor is turned on by the voltage of the first capacitor or the voltage of the second capacitor.

In the semiconductor device which is one embodiment of the present invention, when multi-valued information is stored and read, even if the number of bits is increased, there are few states to be set and states to be discriminated, and a discrimination circuit is not complicated.

One of a source and a drain of the third transistor may be electrically connected to a power supply line and the other may be electrically connected to a bit line.

A semiconductor device which is one embodiment of the present invention further includes a fourth transistor, a region where a channel of the fourth transistor is formed has an oxide semiconductor layer, and a gate of the fourth transistor has a third transistor. The fourth transistor is electrically connected to the word line, and one of the source and the drain of the fourth transistor is connected to the other of the source and the drain of the second transistor, one electrode of the second capacitor and the gate of the third transistor. The fourth transistor is electrically connected and the reference potential is applied to the other of the source and the drain of the fourth transistor.

When the semiconductor device includes the fourth transistor, the operation of reading information includes a step of turning on the third transistor by the voltage of the second capacitor and a step of turning on the fourth transistor of the second capacitor. The method includes a step of lowering the voltage and a step of turning off the fourth transistor and turning on the second transistor to connect the first capacitor element and the second capacitor element in parallel.

In the semiconductor device which is one embodiment of the present invention, when multi-valued information is stored and read, even if the number of bits is increased, there are few states to be set and states to be discriminated, and a discrimination circuit is not complicated.

6 is a circuit diagram of a semiconductor device. FIG. Timing chart. Timing chart. 6 is a circuit diagram of a semiconductor device. FIG. 6 is a circuit diagram of a semiconductor device. FIG. 6 is a circuit diagram of a semiconductor device. FIG. Timing chart. Timing chart. 6 is a circuit diagram of a semiconductor device. FIG. 6 is a circuit diagram of a semiconductor device. FIG. Timing chart. Timing chart. FIG. 3 is a cross-sectional view of a semiconductor device. FIG. 6 is a cross-sectional view of a transistor. Electronics.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. This is because those skilled in the art can easily understand that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In describing the structure of the present invention with reference to the drawings, the same reference numerals are used in different drawings.

In this specification, connection means electrical connection, and corresponds to a state in which current, voltage, or potential can be supplied or transmitted. Therefore, the state of being connected does not necessarily mean a state of being directly connected, and a wiring, a resistor, a diode, a transistor, or the like may be supplied so that current, voltage, or potential can be supplied or transmitted. The state of being electrically connected through a circuit element is also included in the category.

In the drawings attached to this specification, the constituent elements are classified by function and the block diagram is shown as an independent block from each other, but it is difficult to completely separate actual constituent elements by function, and one constituent element May be associated with multiple functions.

Note that the source of a transistor means a source region which is part of a semiconductor film functioning as an active layer or a source electrode electrically connected to the semiconductor film. Similarly, the drain of a transistor means a drain region which is a part of a semiconductor film functioning as an active layer or a drain electrode electrically connected to the semiconductor film. Further, the gate means a gate electrode.

The names of the source and the drain of the transistor are switched depending on the channel type of the transistor and the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain and a terminal to which a high potential is applied is called a source. In this specification, for convenience, the connection relationship of the transistors may be described assuming that the source and the drain are fixed, but in reality, the names of the source and the drain are interchanged according to the above potential relationship. .

Note that the contents described in one embodiment (may be part of the contents) are different contents described in the embodiment (may be part of the contents), and / or one or a plurality of contents. Application, combination, replacement, or the like can be performed with respect to the content (may be part of the content) described in another embodiment.

Note that in the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to that scale.

It should be noted that the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, variations in shape due to manufacturing technology, variations in shape due to errors, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing shift can be included.

Further, the voltage is a certain potential and a reference potential (for example, ground potential (GND) or source potential).
It often indicates the potential difference between Therefore, the voltage can be restated as the potential.

In this specification, even in the case of being expressed as “electrically connected”, there are cases where the actual circuit does not have a physical connection portion and only the wiring extends.

The ordinal numbers given as the first and second are used for convenience and do not indicate the order of steps or the order of stacking. Further, in this specification, specific names are not shown as matters for specifying the invention.

In addition, even when described as “semiconductor”, for example, when the conductivity is sufficiently low, it may have a property as an “insulator”. Further, the boundary between “semiconductor” and “insulator” is ambiguous, and in some cases cannot be strictly distinguished. Therefore, the "semiconductor" described in this specification can be called the "insulator" in some cases. Similarly, the “insulator” in this specification can be referred to as a “semiconductor” in some cases.

Further, even when described as “semiconductor”, for example, when the conductivity is sufficiently high, it may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and in some cases cannot be strictly distinguished. Therefore, the “semiconductor” described in this specification can be referred to as a “conductor” in some cases. Similarly, the “conductor” described in this specification can be referred to as a “semiconductor” in some cases.

In the present specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, a case of -5 ° or more and 5 ° or less is also included. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore,
The case of 85 ° or more and 95 ° or less is also included.

In this specification, trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

(Embodiment 1)
FIG. 1 shows a semiconductor device 100. The semiconductor device 100 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, and a transistor 105. The semiconductor device 100 can store multivalued information.

The regions where the channels of the transistors 101 and 102 are formed have an oxide semiconductor layer. For the region where the channel of the transistor 105 is formed, layers including various materials such as an oxide semiconductor and silicon can be used.

The gate of the transistor 101 is electrically connected to the wiring 112. The wiring 112 can function as a word line.

One of a source and a drain of the transistor 101 is electrically connected to the wiring 113. The wiring 113 can function as a bit line.

The other of the source and the drain of the transistor 101 is electrically connected to one electrode of the capacitor 103. The other of the source and the drain of the transistor 101 is the transistor 10
2 is electrically connected to one of the source and the drain.

One electrode of the capacitor 103 is electrically connected to the other of the source and the drain of the transistor 101. In addition, one electrode of the capacitor 103 is electrically connected to one of a source and a drain of the transistor 102.

The other electrode of the capacitor 103 is electrically connected to the wiring 115.

The gate of the transistor 102 is electrically connected to the wiring 111. The wiring 111 can function as a word line.

The other of the source and the drain of the transistor 102 is electrically connected to one electrode of the capacitor 104. The other of the source and the drain of the transistor 102 is the transistor 10
5 is electrically connected to the gate.

One electrode of the capacitor 104 is electrically connected to the other of the source and the drain of the transistor 102. Further, one electrode of the capacitor 104 is electrically connected to the gate of the transistor 105.

The other electrode of the capacitor 104 is electrically connected to the wiring 114.

Note that the other electrode of the capacitor 103 and the other electrode of the capacitor 104 are electrically connected to different wirings, but may be electrically connected to one wiring. In other words, the capacitive element 1
The other electrode of 03 is electrically connected to the other electrode of the capacitor 104, and may be electrically connected to one wiring. In that case, the number of wirings can be reduced.

One of a source and a drain of the transistor 105 is electrically connected to the terminal 106. The other of the source and the drain of the transistor 105 is electrically connected to the terminal 107.

The operation of writing information to the semiconductor device 100 and the operation of reading the written information will be described. A timing chart is shown in FIGS.

First, an example of the write operation will be described (FIG. 2). As an example of the writing operation, the capacitive element 10
The electric charge such that the potential difference between the four electrodes becomes V1 is accumulated in the capacitor 104,
It will be described that electric charges are accumulated in the capacitor 103 so that the potential difference between the electrodes becomes V2.

The writing operation is divided into step 1 and step 2. In step 1, the potential difference (VC1) between the electrodes of the capacitor 104 is set to V1, and in step 2, the potential difference (V1) between the electrodes of the capacitor 103 (V1).
Change C2) to V2.

(Step 1)
At time t1, a high voltage is applied to the wiring 111 and the wiring 112. Since the wiring 112 is electrically connected to the gate of the transistor 101, the high voltage is applied to the gate of the transistor 101 and the transistor 101 is turned on. The high voltage may be a voltage that can turn on the transistor 101. Similarly, since the wiring 111 is electrically connected to the gate of the transistor 102, a high voltage is applied to the gate of the transistor 102 and the transistor 102 is turned on. The high voltage may be a voltage that can turn on the transistor 102.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104.
In the capacitor 103, electric charge is accumulated and a potential difference (VC2) between the electrodes of the capacitor 103 is generated.
Becomes V1. On the other hand, also in the capacitor 104, electric charge is accumulated, and the potential difference (VC1) between the electrodes of the capacitor 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 105. Note that a low voltage is applied to the wiring 114 and the wiring 115.
The low voltage may be a reference voltage (GND) or a power supply voltage (VDD or VSS).
May be

(Step 2)
At time t2, a low voltage is applied to the wiring 111. A low voltage is applied to the gate of the transistor 102 and the transistor 102 is turned off. Note that the low voltage may be a voltage that can turn off the transistor 102.

The region in which the channel of the transistor 102 is formed has an oxide semiconductor layer, so that the off-state current of the transistor 102 is extremely low. The charge accumulated in the capacitor 104 does not leak through the source and the drain of the transistor 102.

An oxide semiconductor has a band gap that is twice as large as that of silicon. The off-state current of a transistor including an oxide semiconductor is much smaller than that of a transistor including a semiconductor such as silicon or germanium.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, electric charge is further accumulated in the capacitor 103. Electric charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. A low voltage is applied to the gate of the transistor 101 and the transistor 101 is turned off. Note that the low voltage may be a voltage that can turn off the transistor 101. Since the region where the channel of the transistor 101 is formed includes the oxide semiconductor layer, the off-state current of the transistor 101 is extremely low. The charge accumulated in the capacitor 103 does not leak through the source and the drain of the transistor 101. Similarly, there is no leakage through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

From the above, electric charge such that the potential difference between the electrodes of the capacitor 104 is V1 is generated.
Is stored in the capacitor 103, and electric charges that cause a potential difference between the electrodes of the capacitor 103 to be V2 are stored in the capacitor 103.
And the write operation is completed.

Next, an example of an operation of reading the written information by the above writing operation will be described (
(Figure 3).

The read operation is divided into step 1 and step 2. In step 1, V of the capacitive element 104
C1 (V1) is read out, and in step 2, the capacitive element 104 and the capacitive element 103 are connected in parallel,
The voltage (V3) of the combined capacitive element is read.

(Step 1)
Electric charges have already been accumulated in the capacitive element 104, and the voltage VC1 is V1. The voltage V1 is applied to the gate of the transistor 105. The transistor 105 is turned on. At this time, the current (ID) becomes the current I1 corresponding to the voltage V1. As a result, V1 is read.

(Step 2)
At time t4, a high voltage is applied to the wiring 111. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The charge amount (Q2) accumulated in the capacitor 103 and the charge amount (Q2) accumulated in the capacitor 104 (
Q1) is distributed according to the capacitance (C2) of the capacitive element 103 and the capacitance (C1) of the capacitive element 104.

When the voltage of the composite capacitive element is V3, the voltage VC1 is generated when the transistor 102 is turned on.
And the voltage VC2 becomes V3. The voltage V3 is applied to the gate of the transistor 105. It can be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 105.

The current ID flowing through the transistor 105 becomes the current I3 corresponding to the voltage V3. As a result, V3 is read. The voltage V3 is represented by the following formula.

At time t5, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

Through the above steps, the operation of reading the charge accumulated in the capacitor 103 and the capacitor 104 is completed.

When storing and reading multi-valued information in the semiconductor device 100, two steps of step 1 and step 2 can be used.

When 3 bits are stored using the semiconductor device 100, 2 ¹ +2 ² = 6. Therefore, ^two states are provided in step 1, four states are provided in step 2, and six states may be determined. Alternatively, vice versa, four states may be provided in step 1 and two states may be provided in step 2.

For example, to provide the two states in step 1, the voltage VC1 is set to VA or VB. Note that V
A is a voltage different from VB. The current ID is a current corresponding to the voltage VA or VB.

To provide the four states in step 2, the voltage V3 is set to VE, VF, VG or VH. Note that VE, VF, VG, and VH are voltages different from VA and VB.

Further, in the case of 4 bits, 2 ² +2 ² = 8. Therefore, it is only necessary to set four states in step 1, set four states in step 2, and determine eight states.

Further, in the case of 5 bits, 2 ² +2 ³ = 12, so four states are provided in step 1,
Eight states may be provided in step 2 and 12 states may be determined. Alternatively, vice versa, eight states may be provided in step 1 and four states may be provided in step 2.

Next, a conventional semiconductor device 90 including the transistor 101, the capacitor 103, and the transistor 105 will be examined (FIG. 4).

In the semiconductor device 90, the write operation is the accumulation of electric charges in the capacitor 103, and only Step 1 is performed. The read operation is only step 1 in which the charge of the capacitor 103 is applied to the gate of the transistor 105 and the current ID is determined.

When storing and reading multi-valued information in the semiconductor device 90, only step 1 is used.

When 3 bits are stored using the semiconductor device 90, 2 ³ = 8.
It is necessary to set one state and distinguish eight states.

To provide the eight states in step 1, set the voltage VC1 to VA, VB, VE, VF, VG, V.
Must be H, VI or VJ. VA, VB, VE, VF, VG, VH, V
I and VJ are different voltages.

Further, in the case of 4 bits, 2 ⁴ = 16. Therefore, it is necessary to provide 16 states in step 1 and determine the 16 states.

Further, in the case of 5 bits, 2 ⁵ = 32, so 32 states must be provided and the 32 states must be determined in step 1.

When the semiconductor device 90 is used to store and read multi-valued information, when the number of bits increases, the number of states to be set and the number of states to be discriminated increases, and the discrimination circuit becomes complicated. However, in the semiconductor device 100, even if the number of bits increases, the setting state and the determining state are small, and the determining circuit does not become complicated.

Although it is possible to store multi-valued information by using a plurality of semiconductor devices 90, providing a plurality of semiconductor devices 90 increases the number of transistors and capacitors, and increases the installation area of transistors and capacitors.

For example, when two semiconductor devices 90 are provided, the number of transistors is four and the number of capacitive elements is two. However, in the semiconductor device 100, the number of transistors is three, the number of capacitive elements is two, and the number of elements is small. Also, the installation area can be reduced.

When the number of transistors and capacitors of the semiconductor device 100 is increased, the number of steps in writing operation and reading operation can be increased. A semiconductor device 120 illustrated in FIG. 5A includes a transistor 101, a transistor 102, a transistor 116, a capacitor 103, a capacitor 104, a capacitor 117, and a transistor 105. The gate of the transistor 116 is electrically connected to the wiring 118. The other electrode of the capacitor 117 is electrically connected to the wiring 119. The wiring 118 can function as a word line.

A semiconductor device 125 illustrated in FIG. 5B includes a transistor 101, a transistor 102,
The transistor 116, the transistor 121, the capacitor 103, the capacitor 104, the capacitor 117, the capacitor 122, and the transistor 105 are included. The gate of the transistor 121 is electrically connected to the wiring 123. The other electrode of the capacitor 117 is electrically connected to the wiring 124. The wiring 123 can function as a word line.

The semiconductor device 120 and the semiconductor device 125 have more transistors and capacitors than the semiconductor device 100.

When the semiconductor device 120 stores and reads multi-valued information, step 3 can be used in addition to step 1 and step 2, that is, three steps.

When 3 bits are stored using the semiconductor device 120, 2 ¹ +2 ¹ +2 ¹ = 6,
Two states are provided in step 1, two states are provided in step 2, two states are provided in step 3, and six states may be determined.

In the case of 4 bits, 2 ¹ +2 ¹ +2 ² = 8. Therefore, for example, two states are provided in step 1, two states are provided in step 2, four states are provided in step 3, and eight states are determined. do it.

In addition, in the case of storing and reading multi-valued information in the semiconductor device 125, step 4, that is, four steps can be used in addition to step 1, step 2, and step 3.

When 4 bits are stored using the semiconductor device 125, 2 ¹ +2 ¹ +2 ¹ +2 ¹ = 8, so two states are provided in step 1, two states are provided in step 2, and 2 states are provided in step 3. One state may be provided, two states may be provided in step 4, and eight states may be determined.

Note that in the semiconductor device 120, the other electrode of the capacitor 103, the other electrode of the capacitor 104, and the other electrode of the capacitor 117 are electrically connected to different wirings, but electrically connected to one wiring. It may be connected. In other words, the other electrode of the capacitive element 103 is
It may be electrically connected to the other electrode of the capacitor 104 and the other electrode of the capacitor 117 and may be electrically connected to one wiring. In that case, the number of wirings can be reduced.

Note that in the semiconductor device 125, the other electrode of the capacitor 103, the other electrode of the capacitor 104, the other electrode of the capacitor 117, and the other electrode of the capacitor 122 are electrically connected to different wirings. It may be electrically connected to one wiring. In other words, the other electrode of the capacitor 103 is electrically connected to the other electrode of the capacitor 104, the other electrode of the capacitor 117, and the other electrode of the capacitor 122, and is electrically connected to one wiring. May be done. In that case, the number of wirings can be reduced.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
FIG. 6 shows the semiconductor device 130. The semiconductor device 130 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, and a transistor 131. The semiconductor device 130 can store multivalued information.

Compared to the semiconductor device 100 (FIG. 1), the semiconductor device 130 has a p-type transistor 131.
One of a source and a drain of the transistor 131 is electrically connected to the wiring 132, and the other of the source and the drain of the transistor 131 is electrically connected to the wiring 113. The region where the channel of the transistor 131 is formed is an oxide semiconductor,
Layers having various materials such as silicon can be used.

The operation of writing information to the semiconductor device 130 and the operation of reading the written information will be described. Timing charts are shown in FIGS.

First, an example of the write operation will be described (FIG. 7). As an example of the writing operation, the capacitive element 10
The electric charge such that the potential difference between the four electrodes becomes V1 is accumulated in the capacitor 104,
It will be described that electric charges are accumulated in the capacitor 103 so that the potential difference between the electrodes of V is V2.

The writing operation is divided into step 1 and step 2. In step 1, the potential difference (VC1) between the electrodes of the capacitor 104 is set to V1, and in step 2, the potential difference (V1) between the electrodes of the capacitor 103 (V1).
Change C2) to V2.

(Step 1)
First, a high voltage is applied to the wiring 114. The wiring 114 is electrically connected to the other electrode of the capacitor 104. Accordingly, the potential difference (VC1) between the electrodes of the capacitor 104 becomes V0. The voltage V0 is applied to the gate of the transistor 131, which turns off the transistor 131. Note that the voltage V0 may be any voltage that can turn off the transistor 131.

At time t1, a low voltage is applied to the wiring 114 and a high voltage is applied to the wirings 111 and 112. The transistors 101 and 102 are turned on.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104.
In the capacitor 103, electric charge is accumulated and a potential difference (VC2) between the electrodes of the capacitor 103 is generated.
Becomes V1. On the other hand, also in the capacitor 104, electric charge is accumulated, and the potential difference (VC1) between the electrodes of the capacitor 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 131. Note that a low voltage is applied to the wiring 114 and the wiring 115.
The low voltage may be a reference voltage (GND) or a power supply voltage (VDD or VSS).
May be

(Step 2)
At time t2, a low voltage is applied to the wiring 111. A low voltage is applied to the gate of the transistor 102 and the transistor 102 is turned off.

Since the off-state current of the transistor 102 is extremely low, the charge accumulated in the capacitor 104 is
There is no leakage through the source and drain of the transistor 102.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, electric charge is further accumulated in the capacitor 103. Electric charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. The transistor 101 is turned off. Since the off-state current of the transistor 101 is extremely low, the charge stored in the capacitor 103 does not leak through the source and the drain of the transistor 101. Similarly, there is no leakage through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

At time t3, a high voltage is applied to the wiring 114. Thus, the potential difference (VC1) between the electrodes of the capacitor 104 becomes V4. The voltage V4 is applied to the gate of the transistor 131,
The transistor 131 is turned off. Note that the voltage V4 may be any voltage that can turn off the transistor 131 and may be the same as the voltage V0 or higher or lower than the voltage V0.

Note that various voltages can be applied to the wiring 132. Power supply voltage (VDD or VSS
) May be applied. The wiring 132 may function as a power supply line.

From the above, electric charge such that the potential difference between the electrodes of the capacitor 104 is V1 is generated.
Is stored in the capacitor 103, and electric charges that cause a potential difference between the electrodes of the capacitor 103 to be V2 are stored in the capacitor 103.
And the write operation is completed.

Next, an example of an operation of reading the written information by the above writing operation will be described (
(Figure 8).

The read operation is divided into step 1 and step 2. In step 1, V of the capacitive element 104
C1 (V1) is read out, and in step 2, the capacitive element 104 and the capacitive element 103 are connected in parallel,
The voltage (V3) of the combined capacitive element is read.

(Step 1)
Electric charges have already been accumulated in the capacitor 103. The voltage VC1 is V4, and the transistor 131 is off. At this time, the current (ID) becomes the current Ioff.

At time t4, a low voltage is applied to the wiring 114. The potential difference between the electrodes of the capacitor 104 (VC
In 1), the voltage V1 at the time of writing decreases. The transistor 131 is turned on. At this time, the current (ID) becomes the current I1 corresponding to V1. The current I1 is sent to the discrimination circuit via the wiring 113. As a result, V1 is read.

(Step 2)
At time t5, a high voltage is applied to the wiring 111. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The charge amount (Q2) accumulated in the capacitor 103 and the charge amount (Q2) accumulated in the capacitor 104 (
Q1) is distributed according to the capacitance (C2) of the capacitive element 103 and the capacitance (C1) of the capacitive element 104.

When the voltage of the composite capacitive element is V3, the voltage VC1 is generated when the transistor 102 is turned on.
And the voltage VC2 becomes V3. The voltage V3 is applied to the gate of the transistor 131. It can be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 131.

The current ID flowing through the transistor 131 becomes the current I3 corresponding to the voltage V3. As a result, V3 is read. The voltage V3 is represented by the formula shown in the first embodiment.

At time t6, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

At time t6, a high voltage is applied to the wiring 114. Potential difference V between electrodes of the capacitor 104
C1 rises to voltage V5. The voltage V5 is applied to the gate of the transistor 131, and the transistor 131 is turned off. Note that the voltage V5 may be any voltage that can turn off the transistor 131.

Through the above steps, the operation of reading the charge accumulated in the capacitor 103 and the capacitor 104 is completed.

When storing and reading multi-valued information in the semiconductor device 130, two steps, Step 1 and Step 2, can be used. Compared with the case where the semiconductor device 90 is used to store and read multi-valued information, There are few states to be set and states to be discriminated, and the discrimination circuit is not complicated.
Further, in the case of the semiconductor device 130, the number of elements can be reduced as compared with the semiconductor device 90.

Like the semiconductor devices 120 and 125, the semiconductor device 130 can increase the number of transistors and capacitors.

Further, like the semiconductor device 135, instead of the transistor 131, an n-type transistor 1
36 may be provided (FIG. 9). The semiconductor device 135 can be operated as described in Embodiment Mode 1.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
FIG. 10 shows the semiconductor device 140. The semiconductor device 140 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, a transistor 105, and a transistor 14.
Has 1. The semiconductor device 140 can store multivalued information.

The semiconductor device 140 is different from the semiconductor device 100 (FIG. 1) in that it has a transistor 141.

The gate of the transistor 141 is electrically connected to the wiring 142. The wiring 142 can function as a word line.

One of a source and a drain of the transistor 141 is electrically connected to the other of the source and the drain of the transistor 102, one electrode of the capacitor 104, and the gate of the transistor 105.

The other of the source and the drain of the transistor 141 is electrically connected to the wiring 143. Various voltages can be applied to the wiring 143. Reference potential (GND) is applied to the wiring 143.
The power supply voltage (VDD, VSS) may be applied. The voltage of each wiring and each terminal is relative, and it is important whether the voltage is higher or lower than a certain reference. Therefore, even if it is described as GND, it is not limited to 0V. The current may flow from one of the source and the drain of the transistor 141 to the other, and thus may be connected to a power supply line such as VSS or VDD.

A region of the transistor 141 in which a channel is formed has an oxide semiconductor layer. Therefore, the off-state current of the transistor 141 is extremely low.

The operation of writing information to the semiconductor device 140 and the operation of reading the written information will be described. Timing charts are shown in FIGS. The write operation of the semiconductor device 140 is similar to the write operation of the semiconductor device 100 of the first embodiment.

First, an example of the write operation will be described (FIG. 11). As an example of the writing operation, the capacitive element 1
It will be described that the electric charge so that the potential difference between the electrodes of 04 becomes the voltage V1 is stored in the capacitor 104, and the electric charge is stored in the capacitor 103 so that the potential difference between the electrodes of the capacitor 103 becomes the voltage V2.

(Step 1)
At time t1, a high voltage is applied to the wiring 111 and the wiring 112. The transistors 101 and 102 are turned on.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104.
Electric charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V1. On the other hand, also in the capacitor 104, electric charge is accumulated, and the potential difference (VC1) between the electrodes of the capacitor 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 105.

A low voltage is applied to the wiring 142. The low voltage is applied to the gate of the transistor 141 and the transistor 141 is turned off.

(Step 2)
At time t2, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

The region in which the channel of the transistor 102 is formed has an oxide semiconductor layer, so that the off-state current of the transistor 102 is extremely low. The charge accumulated in the capacitor 104 does not leak through the source and the drain of the transistor 102.

In addition, the transistor 141 is off and does not leak through the source and drain of the transistor 141.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, electric charge is further accumulated in the capacitor 103. Electric charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. The transistor 101 is turned off. Since the off-state current of the transistor 101 is extremely low, the charge stored in the capacitor 103 does not leak through the source and the drain of the transistor 101. Similarly, there is no leakage through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

From the above, electric charge such that the potential difference between the electrodes of the capacitor 104 is V1 is generated.
Is stored in the capacitor 103, and electric charges that cause a potential difference between the electrodes of the capacitor 103 to be V2 are stored in the capacitor 103.
And the write operation is completed.

Next, an example of an operation of reading the written information by the above writing operation will be described (
(Fig. 12).

The read operation is divided into step 1, step 2 and step 3. In step 1, VC1 (V1) of the capacitor 104 is read. In step 2, VC1 is changed from V1 to V6. In step 3, the capacitive element 104 and the capacitive element 103 are connected in parallel, and the voltage (V3) of the combined capacitive element is read.

(Step 1)
Electric charges have already been accumulated in the capacitive element 104, and the voltage VC1 is V1. The voltage V1 is applied to the gate of the transistor 105. The transistor 105 is turned on. At this time, the current (ID) becomes the current I1 corresponding to the voltage V1. As a result, V1 is read.

(Step 2)
At time t4, a high voltage is applied to the wiring 142. The high voltage is applied to the gate of the transistor 141, and the transistor 141 is turned on. The high voltage may be a voltage that can turn on the transistor 141.

When the transistor 141 is turned on, the charge accumulated in the capacitor 104 flows through the source and drain of the transistor 141 to the wiring 143, and the charge accumulated in the capacitor 104 is reduced. The potential difference (VC1) between the electrodes of the capacitor 104 is calculated from V1 to the wiring 1
The voltage V6 applied to 43 drops to V6. For example, when 0V is applied to the wiring 143, the voltage V6 is 0V.

The voltage V6 is applied to the gate of the transistor 105, and the current (current
ID) becomes the current I0. For example, when V6 is 0 V and the transistor 105 is a normally-off n-type transistor, the transistor 105 may be turned off.

(Step 3)
At time t5, a low voltage is applied to the wiring 142. The transistor 141 is turned off. The low voltage may be a voltage that can turn off the transistor 141.

Further, a high voltage is applied to the wiring 111 at time t5. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The charge amount (Q2) accumulated in the capacitor 103 and the charge amount (Q2) accumulated in the capacitor 104 (
Q1) is distributed according to the capacitance (C2) of the capacitive element 103 and the capacitance (C1) of the capacitive element 104. When V6 is 0V, Q1 is zero.

When the voltage of the composite capacitive element is V3, the voltage VC1 is generated when the transistor 102 is turned on.
And the voltage VC2 becomes V3. The voltage V3 is applied to the gate of the transistor 105. It can be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 105.

The current ID flowing through the transistor 105 becomes the current I3 corresponding to the voltage V3. As a result, V3 is read. The voltage V3 is represented by the equation shown in the first embodiment with V1 replaced with V6. Especially when V6 = 0V, V3 is represented by the following equation.

When V3 is represented as above, it is not necessary to consider the effects of V1 and V6.

At time t6, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

Through the above steps, the operation of reading the charge accumulated in the capacitor 103 and the capacitor 104 is completed.

When storing and reading multi-valued information in the semiconductor device 140, two steps of step 1 and step 3 can be used.

When 3 bits are stored using the semiconductor device 140, 2 ¹ +2 ² = 6. Therefore, ^two states are provided in step 1, four states are provided in step 3, and six states may be determined. Alternatively, vice versa, four states may be provided in step 1 and two states may be provided in step 3.

Further, in the case of 4 bits, 2 ² +2 ² = 8. Therefore, it is only necessary to set four states in step 1 and four states in step 3 to determine eight states.

In the semiconductor device 140, compared with the case where the semiconductor device 90 is used to store and read multi-valued information, the setting state and the determining state are less and the determining circuit is not complicated.

Further, the semiconductor device 140 can increase the number of transistors and capacitors as in the semiconductor device 120 and the semiconductor device 125.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
An oxide semiconductor which can be applied to the channel of the transistor of Embodiment 1-3 is described.

The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Further, gallium (Ga) is preferably contained in addition to those as a stabilizer for reducing variation in electric characteristics of a transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable that the stabilizer has aluminum (Al). In addition, zirconium (Z
It is preferred to include r).

Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, and the like have excellent electrical characteristics by a sputtering method or a wet method, unlike silicon carbide, gallium nitride, or gallium oxide. It is possible to manufacture a transistor and has an advantage of being excellent in mass productivity. Further, unlike silicon carbide, gallium nitride, or gallium oxide, the above In—Ga—Zn-based oxide can manufacture a transistor with excellent electrical characteristics over a glass substrate. Further, it is possible to cope with the increase in size of the substrate.

In addition, as other stabilizers, lanthanoids such as lanthanum (La) and cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Cerium). Tm), ytterbium (Yb), or lutetium (Lu) may be contained alone or in combination.

For example, as an oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, I
n-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, S
n-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn. System oxides,
Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, I
n-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, In
-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-
Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-H
o-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb
-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-
Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn
A system oxide, an In-Sn-Hf-Zn system oxide, or an In-Hf-Al-Zn system oxide can be used.

Note that, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn does not matter. Further, it may contain a metal element other than In, Ga, and Zn. The In—Ga—Zn-based oxide has a sufficiently high resistance in the absence of an electric field, can reduce off current sufficiently, and has a high mobility.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: G
An In—Ga—Zn-based oxide having an atomic ratio of a: Zn = 2: 2: 1 (= 2/5: 2/5: 1/5) or an oxide near the composition can be used. Alternatively, In: Sn: Zn = 1:
1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1 /)
6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) in the atomic ratio of an In—Sn—Zn-based oxide or its vicinity. It is preferable to use an oxide.

For example, with an In—Sn—Zn-based oxide, high mobility can be relatively easily obtained. However, even with an In-Ga-Zn-based oxide, mobility can be increased by reducing the defect density in the bulk.

The structure of the oxide semiconductor film is described below.

The oxide semiconductor film is roughly classified into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film means an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, or a CAAC-OS (C Axis Aligned Crystalline).
Oxide Semiconductor) film or the like.

The amorphous oxide semiconductor film is an oxide semiconductor film in which atomic arrangement in the film is irregular and which has no crystal component. An oxide semiconductor film having an amorphous structure in which the entire film does not have a crystal part even in a minute region and is complete is typical.

The microcrystalline oxide semiconductor film contains, for example, microcrystals (also referred to as nanocrystals) each having a size of 1 nm to less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of the amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Therefore, CAAC-O
The crystal part included in the S film also includes a case where one side is less than 10 nm, less than 5 nm, or less than 3 nm and fits in a cube. The CAAC-OS film has a feature that the density of defect states is lower than that of the microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film will be described in detail.

The CAAC-OS film is formed using a transmission electron microscope (TEM).
When observed by ron Microscope), a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, CA
It can be said that the AC-OS film is unlikely to have a decrease in electron mobility due to the crystal grain boundaries.

When the CAAC-OS film is observed with a TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape that reflects unevenness of a surface (also referred to as a formation surface) or a top surface of the CAAC-OS film which is to be formed, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film. .

On the other hand, the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TE
(M observation), it can be confirmed that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From cross-sectional TEM observation and planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When the structural analysis of the CAAC-OS film is performed using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film including a crystal of InGaZnO ₄ by the out-of-plane method, A peak may appear near the diffraction angle (2θ) of 31 °. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, the in-pl which makes X-rays incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis
In the analysis by the ane method, a peak may appear near 2θ of 56 °. This peak is assigned to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), ( Six peaks belonging to a crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, 2θ is 5
A clear peak does not appear even when φ scanning is performed with the angle fixed at around 6 °.

From the above, in the CAAC-OS film, the a-axis and the b-axis are randomly oriented between different crystal parts, but they have c-axis orientation and the c-axis is a normal to the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of the metal atoms arranged in layers, which was confirmed by the above-described cross-sectional TEM observation, is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal might not be parallel to the normal vector of the formation surface or the upper surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, a region near the upper surface has higher crystallinity than a region near the formation surface. is there. Also, CAA
When an impurity is added to the C-OS film, the crystallinity of the region to which the impurity is added may change, and a region with different crystallinity may be partially formed.

Note that, in the analysis of the CAAC-OS film including a crystal of InGaZnO ₄ by the out-of-plane method, a peak may appear in the vicinity of 2θ of 36 ° in addition to the peak of 2θ in the vicinity of 31 °. The peak near 2θ of 36 ° indicates that a part of the CAAC-OS film contains a crystal having no c-axis orientation. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

A transistor including a CAAC-OS film has small variation in electric characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film is, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or CA.
A laminated film including two or more of the AC-OS films may be used.

The CAAC-OS film is formed by a sputtering method using a polycrystalline metal oxide target, for example.

In addition, the following conditions are preferably applied to form the CAAC-OS film.

By reducing the mixture of impurities during the film formation, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the processing chamber may be reduced. Further, the concentration of impurities in the deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the substrate heating temperature is 100 ° C. or higher and 740 ° C. or lower, preferably 200 ° C. or higher and 500 ° C. or lower. By increasing the substrate heating temperature during film formation, when flat-plate-like sputtered particles reach the substrate, migration occurs on the substrate,
The flat surface of the sputtered particles adheres to the substrate.

Further, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is 30% by volume or higher, preferably 100% by volume.

Further, the oxide semiconductor layer is not limited to be formed of a single metal oxide film, and may be formed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which first to third metal oxide films are sequentially stacked, the first metal oxide film and the third metal oxide film are
Of at least one of the metal elements constituting the metal oxide film of No. 3, and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, and 0.
The oxide film is 1 eV or higher or 0.15 eV or higher and 2 eV or lower, 1 eV or lower, 0.5 eV or lower, or 0.4 eV or lower, which is close to a vacuum level. Further, it is preferable that the second metal oxide film contains at least indium because carrier mobility becomes high.

When the transistor has the semiconductor film having the above structure, by applying a voltage to the gate electrode,
When an electric field is applied to the semiconductor film, a channel region is formed in the second metal oxide film of the semiconductor film where the energy at the lower end of the conduction band is small. That is, since the third metal oxide film is provided between the second metal oxide film and the gate insulating film, the second metal oxide film separated from the gate insulating film has a channel. Regions can be formed.

In addition, since the third metal oxide film contains at least one of the metal elements that form the second metal oxide film as its constituent elements, the second metal oxide film and the third metal oxide film Interface scattering is unlikely to occur at the interface. Therefore, since the movement of the carrier is less likely to be hindered at the interface,
The field effect mobility of the transistor is increased.

Further, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, a channel region is also formed in a region near the interface, so that the threshold voltage of the transistor varies. Resulting in. However, since the first metal oxide film contains at least one of the metal elements forming the second metal oxide film as its constituent elements, the second metal oxide film and the first metal oxide film An interface level is hard to be formed at the interface. Therefore, with the above structure, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

In addition, it is preferable that a plurality of oxide semiconductor films be stacked so that an interface state which hinders carrier flow is not formed at the interface between the films due to the presence of impurities between the metal oxide films. . If impurities are present between the stacked metal oxide films, the continuity of energy at the bottom of the conduction band between the metal oxide films is lost, and carriers are trapped or regenerated near the interface. This is because they disappear when combined. By reducing the impurities between the films, a continuous junction (here, the energy at the lower end of the conduction band is particularly higher than that of each film is formed) rather than simply stacking a plurality of metal oxide films each containing at least one metal which is a main component. A state having a U-shaped well structure that continuously changes between the two is likely to be formed.

In order to form a continuous bond, it is necessary to successively stack the films using a multi-chamber film forming apparatus (sputtering apparatus) equipped with a load lock chamber without exposing the films to the atmosphere. Each chamber in the sputtering apparatus uses an adsorption-type vacuum exhaust pump such as a cryopump for high vacuum exhaust (1 × 10 ⁻⁴ Pa or more × 5 ×) in order to remove water and the like that are impurities in the oxide semiconductor as much as possible. It is preferable that the pressure is up to about 10 ⁻⁷ Pa). Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow backward from the exhaust system into the chamber.

In order to obtain a highly pure intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum, but also to highly purify the gas used for sputtering. The dew point of oxygen gas or argon gas used as the above gas is −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −
When the temperature is 100 ° C. or lower and the gas used is highly purified, moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

For example, the first metal oxide film or the third metal oxide film contains aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium more than the second metal oxide film. Also, any oxide film containing a high atomic ratio may be used. Specifically, as the first metal oxide film or the third metal oxide film, the above-mentioned elements are 1.5 times or more, preferably 2 times or more, more preferably 3 times as much as the second metal oxide film. It is preferable to use an oxide film which has a higher atomic ratio than twice. Since the above-mentioned element is strongly bonded to oxygen, it has a function of suppressing generation of oxygen vacancies in the oxide film. Therefore, according to the above configuration, the first
The metal oxide film or the third metal oxide film can be an oxide film in which oxygen vacancies are less likely to occur than in the second metal oxide film.

Note that the thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of the second metal oxide film is 3n.
m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

In the semiconductor film having a three-layer structure, the first metal oxide film to the third metal oxide film can be either amorphous or crystalline. However, since the second metal oxide film in which the channel region is formed is crystalline, stable electrical characteristics can be imparted to the transistor; therefore, the second metal oxide film is crystalline. It is preferable.

(Embodiment 5)
An example of the semiconductor device described in Embodiments 1-4 will be described. FIG. 13 illustrates a transistor 102, a transistor 105, and a capacitor 1 included in the semiconductor device 100 illustrated in FIG.
The cross-sectional structure of 04 is shown as an example.

The channel of the transistor 102 has an oxide semiconductor layer. The transistor 102 in which the transistor 102 and the capacitor 104 have a channel formation region in a single crystal silicon substrate
The case where it is formed above is illustrated.

Note that in the transistor 105, a semiconductor film of amorphous, microcrystalline, polycrystalline, or single crystal such as silicon or germanium can be used for the active layer. Alternatively, transistor 1
In 05, an oxide semiconductor may be used for the active layer. In the case where all the transistors use an oxide semiconductor for the active layer, the transistor 102 does not need to be stacked over the transistor 105 and the transistor 102 and the transistor 105 may be formed in the same layer.

In the case where the transistor 105 is formed using thin film silicon, amorphous silicon manufactured by a vapor deposition method such as a plasma CVD method or a sputtering method is irradiated with laser light to crystallize amorphous silicon. It is possible to use crystalline silicon, single crystal silicon obtained by implanting hydrogen ions or the like into a single crystal silicon wafer, and peeling the surface layer portion.

The semiconductor substrate 1400 on which the transistor 105 is formed is, for example, a silicon substrate having n-type or p-type conductivity, a germanium substrate, a silicon germanium substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP). Substrate, GaInAs
P substrate, ZnSe substrate, etc.) can be used. FIG. 13 illustrates the case where a single crystal silicon substrate having n-type conductivity is used.

In addition, the transistor 105 is separated from other transistors by the element isolation insulating film 1401.
It is electrically separated. The element isolation insulating film 1401 is formed by the selective oxidation method (LOCO
An S (Local Oxidation of Silicon) method or a trench isolation method can be used.

Specifically, the transistor 105 is provided between the impurity region 1402 and the impurity region 1403 which function as a source region or a drain region, the gate electrode 1404, the semiconductor substrate 1400, and the gate electrode 1404, which are formed in the semiconductor substrate 1400. Gate insulation film 1
405 and. The gate electrode 1404 overlaps with a channel formation region formed between the impurity regions 1402 and 1403 with the gate insulating film 1405 provided therebetween.

An insulating film 1409 is provided over the transistor 105. An opening is formed in the insulating film 1409. The impurity region 1402 and the impurity region 140 are provided in the opening.
A wiring 1410 and a wiring 1411 which are respectively in contact with 3 are formed, and a wiring 1412 which is electrically connected to the gate electrode 1404 is formed.

The wiring 1410 is electrically connected to the wiring 1415 formed over the insulating film 1409, the wiring 1411 is electrically connected to the wiring 1416 formed over the insulating film 1409, and the wiring 1412. Are electrically connected to a wiring 1417 formed over the insulating film 1409.

An insulating film 1420 and an insulating film 1440 are sequentially stacked over the wirings 1415 to 1417. An opening is formed in the insulating films 1420 and 1440, and a wiring 1421 electrically connected to the wiring 1417 is formed in the opening.

Then, in FIG. 13, the transistor 102 and the capacitor 104 are formed over the insulating film 1440.

The transistor 102 includes a semiconductor film 1430 including an oxide semiconductor over an insulating film 1440,
A conductive film 1432 and a conductive film 1433 which function as a source electrode or a drain electrode over the semiconductor film 1430, a gate insulating film 1431 over the semiconductor film 1430, the conductive film 1432 and the conductive film 1433, and a gate insulating film 1431 , Conductive film 1432 and conductive film 1433
A gate electrode 1434 which overlaps with the semiconductor film 1430 between. In addition,
The conductive film 1433 is electrically connected to the wiring 1421.

In addition, a conductive film 1435 is formed on the gate insulating film 1431 at a position overlapping with the conductive film 1433.
Is provided. The conductive film 1433 and the conductive film 143 with the gate insulating film 1431 provided therebetween.
The portion where 5 overlaps functions as the capacitive element 104.

Note that although FIG. 13 illustrates the case where the capacitor 104 is provided over the insulating film 1440 together with the transistor 102, the capacitor 104 is provided under the insulating film 1440 together with the transistor 105. Is also good.

Then, the insulating film 1441 and the insulating film 1442 are formed over the transistor 102 and the capacitor 104.
Are provided so as to be stacked in order. An opening is provided in the insulating films 1441 and 1442, and a conductive film 1443 which is in contact with the gate electrode 1434 in the opening is provided over the insulating film 1441.

Note that in FIG. 13, in the transistor 102, the gate electrode 1434 is not included in the semiconductor film 1430.
It suffices to have at least one side thereof, but it may have a pair of gate electrodes existing with the semiconductor film 1430 interposed therebetween.

In the case where the transistor 102 has a pair of gate electrodes which are provided with the semiconductor film 1430 provided therebetween, a signal for controlling a conductive state or a non-conductive state is given to one gate electrode and the other gate electrode is provided. The electrodes may be in a state where a potential is applied from the other. In this case, the pair of electrodes may be supplied with the same potential, or only the other gate electrode may be supplied with a fixed potential such as the ground potential. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

In addition, FIG. 13 illustrates the case where the transistor 102 has a single-gate structure including one channel formation region corresponding to one gate electrode 1434. However, the transistor 102 may have a multi-gate structure in which one active layer has a plurality of channel formation regions by having a plurality of gate electrodes electrically connected to each other.

Further, the semiconductor film 1430 is not limited to a single-layer oxide semiconductor, and may be a plurality of stacked oxide semiconductors. For example, FIG. 14A illustrates a structural example of the transistor 1110A in the case where the semiconductor film 1430 is stacked in three layers.

A transistor 1110A illustrated in FIG. 14A includes a semiconductor film 1430 provided over the insulating film 820, a conductive film 832 electrically connected to the semiconductor film 1430, a conductive film 833, and a gate insulating film. 831 and a gate electrode 834 provided over the gate insulating film 831 so as to overlap with the semiconductor film 1430.

In the transistor 1110A, the oxide semiconductor layer 830 is used as the semiconductor film 1430.
a to the oxide semiconductor layer 830c are sequentially stacked from the insulating film 820 side.

The oxide semiconductor layer 830a and the oxide semiconductor layer 830c are the oxide semiconductor layer 830.
At least one of the metal elements forming b is included in the constituent elements thereof, and the energy at the bottom of the conduction band is 0.05 eV or higher, 0.07 eV or higher, 0.1 eV or higher, or 0.15 eV or higher than that of the oxide semiconductor layer 830b. And 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV
Hereinafter, the oxide film is close to the vacuum level. Further, the oxide semiconductor layer 830b preferably contains at least indium because carrier mobility becomes high.

Note that the oxide semiconductor layer 830c includes the conductive film 832 and the conductive film 8 as illustrated in FIG.
Alternatively, the upper layer 33 may be provided so as to overlap with the gate insulating film 831.

(Embodiment 6)
A semiconductor device according to one embodiment of the present invention is an image reproducing device (typically a DVD: Digital Versatile Disc) including a display device, a personal computer, and a recording medium.
Can be used for a device having a display capable of reproducing a recording medium such as the above and displaying an image thereof. In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a video camera, a camera such as a digital still camera, a goggle type Display (head mounted display)
, A navigation system, a sound reproducing device (car audio, digital audio player, etc.), a copying machine, a facsimile, a printer, a printer complex machine, an automatic teller machine (ATM), an automatic vending machine, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 15A illustrates a portable game machine including a housing 5001, a housing 5002, a display portion 5003,
A display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like are included. Note that the portable game machine illustrated in FIG. 15A includes two display portions 5003 and 5004, but the number of display portions included in the portable game machine is not limited to this.

FIG. 15B illustrates a personal digital assistant including a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 561.
02. Then, the first housing 5601 and the second housing 5602 are connected to each other by the connecting portion 56.
05, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connecting portion 5605. The image on the first display portion 5603 is displayed on the connection portion 5605.
The configuration may be switched according to the angle between the first housing 5601 and the second housing 5602 in FIG. Further, a display device in which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. The function as the position input device can be added by providing a touch panel on the display device.
Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in the pixel portion of the display device.

FIG. 15C illustrates a laptop personal computer including a housing 5401 and a display portion 5402.
, A keyboard 5403, a pointing device 5404, and the like.

FIG. 15D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator compartment door 5302, a freezer compartment door 5303, and the like.

FIG. 15E illustrates a video camera, which includes a first housing 5801, a second housing 5802, and a display portion 58.
03, operation keys 5804, a lens 5805, a connection portion 5806, and the like. Operation key 580
The lens 4805 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connecting portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connecting portion 5806. is there. The image on the display portion 5803 is displayed on the connection portion 5806.
The configuration may be switched according to the angle between the first housing 5801 and the second housing 5802 in FIG.

FIG. 15F shows an ordinary automobile including a car body 5101, wheels 5102, and a dashboard 510.
3, light 5104 and the like.

90 semiconductor device 100 semiconductor device 101 transistor 102 transistor 103 capacitance element 104 capacitance element VC1 potential difference between electrodes of capacitance element 104 VC2 potential difference between electrodes of capacitance element 103 transistor 106 terminal 107 terminal 111 wiring 112 wiring 113 wiring 114 wiring 115 wiring 116 transistor 117 capacitor element 118 wiring 119 wiring 120 semiconductor device 121 transistor 122 capacitor element 123 wiring 124 wiring 125 semiconductor device 130 semiconductor device 131 transistor 132 wiring 135 semiconductor device 136 transistor 140 semiconductor device 141 transistor 142 wiring 143 wiring 820 insulating film 832 conductive Film 833 Conductive film 831 Gate insulating film 834 Gate electrode 830a Oxide semiconductor layer 830b Oxide semiconductor layer 8 0c oxide semiconductor layer 1110A transistor 1400 semiconductor substrate 1401 element isolation insulating film 1402 impurity region 1403 impurity region 1404 gate electrode 1405 gate insulating film 1409 insulating film 1410 wiring 1411 wiring 1412 wiring 1415 wiring 1416 wiring 1417 wiring 1420 insulating film 1421 wiring 1430 Semiconductor film 1431 Gate insulating film 1432 Conductive film 1433 Conductive film 1434 Gate electrode 1435 Conductive film 1440 Insulating film 1441 Insulating film 1442 Insulating film 1443 Conductive film 5001 Case 5002 Case 5003 Display 5004 Display 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Body 5102 Wheels 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigerator compartment door 5 303 Freezer compartment door 5401 Case 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Case 5602 Case 5603 Display unit 5604 Display unit 5605 Connection unit 5606 Operation key 5801 Case 5802 Case 5803 Display unit 5804 Operation key 5805 Lens 5806 connection Department

Claims (2)

A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element,
One of a source and a drain of the first transistor is electrically connected to the first wiring,
The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor,
The other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor,
One of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor,
A power supply voltage is applied to the other of the source and the drain of the fourth transistor,
The gate of the fourth transistor is electrically connected to the second wiring,
A first electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor,
A second electrode of the first capacitive element is electrically connected to a third wiring,
The second capacitor is electrically connected to the gate of the third transistor,
A second electrode of the second capacitive element is a semiconductor device electrically connected to a fourth wiring,
The semiconductor device in which the third wiring and the fourth wiring have a period in which the potential is the same and a period in which the potential is different. A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element,
One of a source and a drain of the first transistor is electrically connected to the first wiring,
The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor,
The other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor,
One of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor,
A power supply voltage is applied to the other of the source and the drain of the fourth transistor,
The power supply voltage is applied to one of a source and a drain of the third transistor,
The gate of the fourth transistor is electrically connected to the second wiring,
A first electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor,
A second electrode of the first capacitive element is electrically connected to a third wiring,
The second capacitor is electrically connected to the gate of the third transistor,
A second electrode of the second capacitive element is a semiconductor device electrically connected to a fourth wiring,
The semiconductor device in which the third wiring and the fourth wiring have a period in which the potential is the same and a period in which the potential is different.