JP6298657B2 - Semiconductor device - Google Patents

Description

The present invention relates to an object, a method, or a manufacturing method. In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor, for example.

Patent Document 1 describes a semiconductor device having a transistor having an oxide semiconductor layer over a semiconductor substrate having a MOS transistor. Patent Document 2 describes that a transistor using an oxide semiconductor film has extremely small leakage current in an off state.

JP 2010-141230 A JP 2012-257187 A

An object of one embodiment of the present invention is to provide a semiconductor device capable of storing multilevel information.

An object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like including a transparent semiconductor layer. Another object of one embodiment of the present invention is to provide a semiconductor device or the like including a highly reliable semiconductor layer.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a third transistor, and a region where a channel of the first transistor is formed is oxidized A region in which the channel of the second transistor is formed includes an oxide semiconductor layer, and the gate of the first transistor is electrically connected to the first word line. One of the source and the drain of the first transistor is electrically connected to the bit line, and the other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor and the one electrode of the first capacitor. Electrically connected, the gate of the second transistor is electrically connected to the second word line, and the other of the source and the drain of the second transistor is connected to the third transistor. Over bets, and a semiconductor device which is electrically connected to one electrode of the second capacitor.

The operation of writing information to the semiconductor device includes a step of accumulating charges from the bit line to the first capacitor element and the second capacitor element, and a step of accumulating charges from the bit line to the first capacitor element. In the operation of reading information, the third transistor is turned on by the voltage of the second capacitor, the second transistor is turned on, and the first capacitor and the second capacitor are And connecting them in parallel.

The first capacitor element and the second capacitor element are connected in parallel, and the third transistor is turned on by the voltage of the first capacitor element or the voltage of the second capacitor element.

In the semiconductor device which is one embodiment of the present invention, when multi-value information is stored and read, even when the number of bits is increased, a setting state and a determination state are few, and a determination circuit is not complicated.

One of the source and the drain of the third transistor may be electrically connected to the power supply line, and the other may be electrically connected to the bit line.

The semiconductor device which is one embodiment of the present invention further includes a fourth transistor, the region where the channel of the fourth transistor is formed includes an oxide semiconductor layer, and the gate of the fourth transistor is the third transistor. One of the source and the drain of the fourth transistor is electrically connected to the word line, the other of the source and the drain of the second transistor, the one electrode of the second capacitor, and the gate of the third transistor. A reference potential is applied to the other of the source and the drain of the fourth transistor.

In the case where the semiconductor device includes the fourth transistor, the operation of reading information includes a step of turning on the third transistor with the voltage of the second capacitor, and a step of turning on the fourth transistor and turning on the second capacitor. A step of lowering the voltage, and a step of turning off the fourth transistor and turning on the second transistor to connect the first capacitor element and the second capacitor element in parallel.

In the semiconductor device which is one embodiment of the present invention, when multi-value information is stored and read, even when the number of bits is increased, a setting state and a determination state are few, and a determination circuit is not complicated.

1 is a circuit diagram of a semiconductor device. Timing chart. Timing chart. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. Timing chart. Timing chart. 1 is a circuit diagram of a semiconductor device. 1 is a circuit diagram of a semiconductor device. Timing chart. Timing chart. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a transistor. Electronics.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments given below. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

In this specification, the connection means an electrical connection, and corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily indicate a directly connected state, and a wiring, a resistor, a diode, a transistor, or the like is provided so that current, voltage, or potential can be supplied or transmitted. The state of being electrically connected via a circuit element is also included in the category.

In the drawings attached to the present specification, the components are classified by function, and the block diagram is shown as an independent block. However, it is difficult to completely separate the actual components for each function. May involve multiple functions.

Note that the source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode that is electrically connected to the semiconductor film. Similarly, a drain of a transistor means a drain region that is part of a semiconductor film functioning as an active layer or a drain electrode that is electrically connected to the semiconductor film. The gate means a gate electrode.

The terms “source” and “drain” of a transistor interchange with each other depending on the channel type of the transistor and the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for the sake of convenience, the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .

Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment, and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

Note that the size, the thickness of layers, or regions in drawings is sometimes exaggerated for simplicity. Therefore, it is not necessarily limited to the scale.

The figure schematically shows an ideal example, and is not limited to the shape or value shown in the figure. For example, it is possible to include variation in shape due to manufacturing technology, variation in shape due to error, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential.

In this specification, even when expressed as “electrically connected”, in an actual circuit, there may be no physical connection and the wiring may only extend.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
FIG. 1 shows a semiconductor device 100. The semiconductor device 100 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, and a transistor 105. The semiconductor device 100 can store multi-value information.

A region where a channel of the transistor 101 and the transistor 102 is formed includes an oxide semiconductor layer. For a region where the channel of the transistor 105 is formed, layers including various materials such as an oxide semiconductor and silicon can be used.

A gate of the transistor 101 is electrically connected to the wiring 112. The wiring 112 can function as a word line.

One of a source and a drain of the transistor 101 is electrically connected to the wiring 113. The wiring 113 can function as a bit line.

The other of the source and the drain of the transistor 101 is electrically connected to one electrode of the capacitor 103. The other of the source and the drain of the transistor 101 is electrically connected to one of the source and the drain of the transistor 102.

One electrode of the capacitor 103 is electrically connected to the other of the source and the drain of the transistor 101. One electrode of the capacitor 103 is electrically connected to one of a source and a drain of the transistor 102.

The other electrode of the capacitor 103 is electrically connected to the wiring 115.

A gate of the transistor 102 is electrically connected to the wiring 111. The wiring 111 can function as a word line.

The other of the source and the drain of the transistor 102 is electrically connected to one electrode of the capacitor 104. The other of the source and the drain of the transistor 102 is electrically connected to the gate of the transistor 105.

One electrode of the capacitor 104 is electrically connected to the other of the source and the drain of the transistor 102. One electrode of the capacitor 104 is electrically connected to the gate of the transistor 105.

The other electrode of the capacitor 104 is electrically connected to the wiring 114.

Note that the other electrode of the capacitor 103 and the other electrode of the capacitor 104 are electrically connected to different wirings, but may be electrically connected to one wiring. In other words, the other electrode of the capacitor 103 may be electrically connected to the other electrode of the capacitor 104 and electrically connected to one wiring. In that case, the number of wirings can be reduced.

One of a source and a drain of the transistor 105 is electrically connected to the terminal 106. The other of the source and the drain of the transistor 105 is electrically connected to the terminal 107.

An operation for writing information to the semiconductor device 100 and an operation for reading the written information will be described. FIG. 2-3 shows a timing chart.

First, an example of the write operation will be described (FIG. 2). As an example of the writing operation, a charge that causes the potential difference between the electrodes of the capacitor 104 to be V1 is accumulated in the capacitor 104, and a charge that causes the potential difference between the electrodes of the capacitor 103 to be V2 is accumulated in the capacitor 103. Explain what to do.

The write operation is divided into step 1 and step 2. In step 1, the potential difference (VC1) between the electrodes of the capacitor 104 is set to V1, and in step 2, the potential difference (VC2) between the electrodes of the capacitor 103 is set to V2.

(Step 1)
At time t1, a high voltage is applied to the wiring 111 and the wiring 112. Since the wiring 112 is electrically connected to the gate of the transistor 101, the high voltage is applied to the gate of the transistor 101, and the transistor 101 is turned on. The high voltage may be a voltage that can turn on the transistor 101. Similarly, since the wiring 111 is electrically connected to the gate of the transistor 102, the high voltage is applied to the gate of the transistor 102, and the transistor 102 is turned on. The high voltage may be a voltage that can turn on the transistor 102.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104. Charge is accumulated in the capacitor 103, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V1. On the other hand, charge is accumulated also in the capacitive element 104, and the potential difference (VC1) between the electrodes of the capacitive element 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 105. Note that a low voltage is applied to the wiring 114 and the wiring 115. The low voltage may be a reference voltage (GND) or a power supply voltage (VDD or VSS).

(Step 2)
At time t2, a low voltage is applied to the wiring 111. A low voltage is applied to the gate of the transistor 102, and the transistor 102 is turned off. Note that the low voltage may be any voltage that can turn off the transistor 102.

Since the region where the channel of the transistor 102 is formed includes an oxide semiconductor layer, the off-state current of the transistor 102 is extremely low. The charge accumulated in the capacitor 104 does not leak through the source and drain of the transistor 102.

An oxide semiconductor has a large band gap that is twice or more that of silicon. A transistor including an oxide semiconductor has extremely low off-state current compared to a transistor formed using a semiconductor such as silicon or germanium.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, charge is further accumulated in the capacitor 103. Charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. A low voltage is applied to the gate of the transistor 101, and the transistor 101 is turned off. Note that the low voltage may be any voltage that can turn off the transistor 101. Since the region where the channel of the transistor 101 is formed includes an oxide semiconductor layer, the off-state current of the transistor 101 is extremely low. The charge accumulated in the capacitor 103 does not leak through the source and drain of the transistor 101. Similarly, leakage does not occur through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

As described above, the charge that causes the potential difference between the electrodes of the capacitor 104 to be V1 is accumulated in the capacitor 104, and the charge that causes the potential difference between the electrodes of the capacitor 103 to be V2 is accumulated in the capacitor 103 and written. The operation ends.

Next, an example of an operation for reading out information written by the above writing operation will be described (FIG. 3).

The read operation is divided into step 1 and step 2. In step 1, VC1 (V1) of the capacitive element 104 is read. In step 2, the capacitive element 104 and the capacitive element 103 are connected in parallel to read the voltage (V3) of the combined capacitive element.

(Step 1)
Charge is already accumulated in the capacitor 104, and the voltage VC1 is V1. The voltage V1 is applied to the gate of the transistor 105. The transistor 105 is turned on. At this time, the current (ID) becomes a current I1 corresponding to the voltage V1. As a result, V1 is read.

(Step 2)
At time t4, a high voltage is applied to the wiring 111. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The amount of charge (Q2) accumulated in the capacitor 103 and the amount of charge (Q1) accumulated in the capacitor 104 are distributed according to the capacitance (C2) of the capacitor 103 and the capacitance (C1) of the capacitor 104. The

Assuming that the voltage of the combined capacitor element is V3, when the transistor 102 is turned on, the voltage VC1 and the voltage VC2 are V3. The voltage V3 is applied to the gate of the transistor 105. It can also be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 105.

The current ID flowing through the transistor 105 is a current I3 corresponding to the voltage V3. As a result, V3 is read. The voltage V3 is expressed by the following formula.

At time t5, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

Thus, the operation for reading the charges accumulated in the capacitor 103 and the capacitor 104 is completed.

When the multivalue information is stored and read in the semiconductor device 100, two steps of Step 1 and Step 2 can be used.

When 3 bits are stored using the semiconductor device 100, 2 ¹ +2 ² = 6. Therefore, ^two states are provided in step 1, four states are provided in step 2, and six states may be determined. Or, conversely, four states may be provided in step 1 and two states may be provided in step 2.

For example, to provide two states in step 1, the voltage VC1 is set to VA or VB. Note that VA is a voltage different from VB. The current ID is a current corresponding to the voltage VA or VB.

In order to provide four states in step 2, the voltage V3 is set to VE, VF, VG, or VH. Note that VE, VF, VG, and VH are voltages different from VA and VB.

In the case of 4 bits, 2 ² +2 ² = 8. Therefore, four states are provided in step 1, four states are provided in step 2, and eight states may be determined.

Further, in the case of 5 bits, 2 ² +2 ³ = 12, so that four states are provided in step 1, eight states are provided in step 2, and 12 states may be determined. Or, conversely, eight states may be provided in step 1 and four states may be provided in step 2.

Next, a conventional semiconductor device 90 including the transistor 101, the capacitor 103, and the transistor 105 is considered (FIG. 4).

In the semiconductor device 90, the write operation is accumulation of electric charges in the capacitor 103, and only Step 1 is performed. In the reading operation, only the charge ID of the capacitor 103 is applied to the gate of the transistor 105 and the current ID is determined.

When the multi-value information is stored in the semiconductor device 90 and read out, only step 1 is used.

When 3 bits are stored using the semiconductor device 90, 2 ³ = 8. Therefore, 8 states must be provided in step 1, and the 8 states must be determined.

In order to provide eight states in step 1, the voltage VC1 must be VA, VB, VE, VF, VG, VH, VI or VJ. Note that VA, VB, VE, VF, VG, VH, VI, and VJ are different voltages.

In the case of 4 bits, since 2 ⁴ = 16, 16 states must be provided in step 1 and the 16 states must be determined.

Further, in the case of 5 bits, since 2 ⁵ = 32, 32 states must be provided in step 1 and the 32 states must be determined.

When multi-value information is stored and read using the semiconductor device 90, when the number of bits increases, the state to be set and the state to be determined increase, and the determination circuit becomes complicated. However, in the semiconductor device 100, even if the number of bits is increased, there are few states to be set and states to be determined, and the determination circuit is not complicated.

In addition, although a plurality of semiconductor devices 90 can be used to store multilevel information, when a plurality of semiconductor devices 90 are provided, the number of transistors and capacitors increases, and the installation area of the transistors and capacitors increases.

For example, when two semiconductor devices 90 are provided, the number of transistors is four and the number of capacitor elements is two. However, in the semiconductor device 100, the number of transistors is three, the number of capacitive elements is two, and the number of elements is small. Also, the installation area can be reduced.

Increasing the number of transistors and capacitors in the semiconductor device 100 can increase the number of steps in the write operation and the read operation. A semiconductor device 120 illustrated in FIG. 5A includes a transistor 101, a transistor 102, a transistor 116, a capacitor 103, a capacitor 104, a capacitor 117, and a transistor 105. A gate of the transistor 116 is electrically connected to the wiring 118. The other electrode of the capacitor 117 is electrically connected to the wiring 119. The wiring 118 can function as a word line.

A semiconductor device 125 illustrated in FIG. 5B includes the transistor 101, the transistor 102, the transistor 116, the transistor 121, the capacitor 103, the capacitor 104, the capacitor 117, the capacitor 122, and the transistor 105. A gate of the transistor 121 is electrically connected to the wiring 123. The other electrode of the capacitor 117 is electrically connected to the wiring 124. The wiring 123 can function as a word line.

The semiconductor device 120 and the semiconductor device 125 have more transistors and capacitors than the semiconductor device 100.

In the case where multi-value information is stored and read out in the semiconductor device 120, Step 3, that is, three steps can be used in addition to Step 1 and Step 2.

When 3 bits are stored using the semiconductor device 120, 2 ¹ +2 ¹ +2 ¹ = 6. Therefore, two states are provided in Step 1, two states are provided in Step 2, and two states are provided in Step 3. It is only necessary to distinguish between six states.

In the case of 4 bits, 2 ¹ +2 ¹ +2 ² = 8. For example, two states are provided in step 1, two states are provided in step 2, four states are provided in step 3, and eight states are discriminated. do it.

In addition, when multi-value information is stored and read in the semiconductor device 125, step 4, that is, four steps can be used in addition to step 1, step 2, and step 3.

When storing 4 bits using the semiconductor device 125, 2 ¹ +2 ¹ +2 ¹ +2 ¹ = 8. Therefore, two states are provided in Step 1, two states are provided in Step 2, and 2 in Step 3. One state is provided, two states are provided in step 4, and eight states may be determined.

Note that in the semiconductor device 120, the other electrode of the capacitor 103, the other electrode of the capacitor 104, and the other electrode of the capacitor 117 are electrically connected to different wirings. It may be connected. In other words, the other electrode of the capacitor 103 may be electrically connected to the other electrode of the capacitor 104 and the other electrode of the capacitor 117, and may be electrically connected to one wiring. In that case, the number of wirings can be reduced.

Note that in the semiconductor device 125, the other electrode of the capacitor 103, the other electrode of the capacitor 104, the other electrode of the capacitor 117, and the other electrode of the capacitor 122 are electrically connected to different wirings. It may be electrically connected to one wiring. In other words, the other electrode of the capacitor 103 is electrically connected to the other electrode of the capacitor 104, the other electrode of the capacitor 117, and the other electrode of the capacitor 122, and is electrically connected to one wiring. May be. In that case, the number of wirings can be reduced.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
FIG. 6 shows the semiconductor device 130. The semiconductor device 130 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, and a transistor 131. The semiconductor device 130 can store multi-value information.

In the semiconductor device 130, the transistor 131 is a p-type transistor as compared with the semiconductor device 100 (FIG. 1), one of the source and the drain of the transistor 131 is electrically connected to the wiring 132, and the source and the drain of the transistor 131 are connected. The other is electrically connected to the wiring 113. As a region where a channel of the transistor 131 is formed, layers including various materials such as an oxide semiconductor and silicon can be used.

An operation of writing information to the semiconductor device 130 and an operation of reading the written information will be described. FIG. 7-8 shows a timing chart.

First, an example of the write operation will be described (FIG. 7). As an example of the writing operation, a charge that causes the potential difference between the electrodes of the capacitor 104 to be V1 is accumulated in the capacitor 104, and a charge is accumulated in the capacitor 103 so that the potential difference between the electrodes of the capacitor 103 is V2. Explain what to do.

The write operation is divided into step 1 and step 2. In step 1, the potential difference (VC1) between the electrodes of the capacitor 104 is set to V1, and in step 2, the potential difference (VC2) between the electrodes of the capacitor 103 is set to V2.

(Step 1)
First, a high voltage is applied to the wiring 114. The wiring 114 is electrically connected to the other electrode of the capacitor 104. As a result, the potential difference (VC1) between the electrodes of the capacitor 104 becomes V0. The voltage V0 is applied to the gate of the transistor 131, and the transistor 131 is turned off. Note that the voltage V0 may be any voltage that can turn off the transistor 131.

At time t1, a low voltage is applied to the wiring 114 and a high voltage is applied to the wiring 111 and the wiring 112. The transistors 101 and 102 are turned on.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104. Charge is accumulated in the capacitor 103, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V1. On the other hand, charge is accumulated also in the capacitive element 104, and the potential difference (VC1) between the electrodes of the capacitive element 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 131. Note that a low voltage is applied to the wiring 114 and the wiring 115. The low voltage may be a reference voltage (GND) or a power supply voltage (VDD or VSS).

(Step 2)
At time t2, a low voltage is applied to the wiring 111. A low voltage is applied to the gate of the transistor 102, and the transistor 102 is turned off.

Since the off-state current of the transistor 102 is extremely low, the charge accumulated in the capacitor 104 does not leak through the source and the drain of the transistor 102.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, charge is further accumulated in the capacitor 103. Charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. The transistor 101 is turned off. Since the off-state current of the transistor 101 is extremely low, the charge stored in the capacitor 103 does not leak through the source and the drain of the transistor 101. Similarly, leakage does not occur through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

At time t3, a high voltage is applied to the wiring 114. As a result, the potential difference (VC1) between the electrodes of the capacitor 104 becomes V4. The voltage V4 is applied to the gate of the transistor 131, and the transistor 131 is turned off. Note that the voltage V4 may be any voltage that can turn off the transistor 131, and may be the same as the voltage V0 or may be higher or lower than the voltage V0.

Note that various voltages can be applied to the wiring 132. A power supply voltage (VDD or VSS) may be applied. The wiring 132 may function as a power supply line.

As described above, the charge that causes the potential difference between the electrodes of the capacitor 104 to be V1 is accumulated in the capacitor 104, and the charge that causes the potential difference between the electrodes of the capacitor 103 to be V2 is accumulated in the capacitor 103 and written. The operation ends.

Next, an example of an operation for reading the information written by the write operation will be described (FIG. 8).

The read operation is divided into step 1 and step 2. In step 1, VC1 (V1) of the capacitive element 104 is read. In step 2, the capacitive element 104 and the capacitive element 103 are connected in parallel, and the voltage (V3) of the combined capacitive element is read.

(Step 1)
Charge is already accumulated in the capacitor 103. The voltage VC1 is V4, and the transistor 131 is off. At this time, the current (ID) becomes the current Ioff.

At time t4, a low voltage is applied to the wiring 114. The potential difference (VC1) between the electrodes of the capacitor 104 decreases to the voltage V1 at the time of writing. The transistor 131 is turned on. At this time, the current (ID) is a current I1 corresponding to V1. The current I1 is sent to the discrimination circuit via the wiring 113. As a result, V1 is read.

(Step 2)
At time t5, a high voltage is applied to the wiring 111. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The amount of charge (Q2) accumulated in the capacitor 103 and the amount of charge (Q1) accumulated in the capacitor 104 are distributed according to the capacitance (C2) of the capacitor 103 and the capacitance (C1) of the capacitor 104. The

Assuming that the voltage of the combined capacitor element is V3, when the transistor 102 is turned on, the voltage VC1 and the voltage VC2 are V3. The voltage V3 is applied to the gate of the transistor 131. It can also be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 131.

The current ID flowing through the transistor 131 is a current I3 corresponding to the voltage V3. As a result, V3 is read. Voltage V3 is expressed by the equation shown in the first embodiment.

At time t6, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

At time t6, a high voltage is applied to the wiring 114. The potential difference VC1 between the electrodes of the capacitor 104 increases to the voltage V5. The voltage V5 is applied to the gate of the transistor 131, and the transistor 131 is turned off. Note that the voltage V5 may be any voltage that can turn off the transistor 131.

Thus, the operation for reading the charges accumulated in the capacitor 103 and the capacitor 104 is completed.

When the semiconductor device 130 stores and reads the multi-value information, two steps of Step 1 and Step 2 can be used. Compared to the case where the semiconductor device 90 stores and reads the multi-value information, There are few states to set and states to discriminate, and the discrimination circuit is not complicated. In the case of the semiconductor device 130, the number of elements can be reduced as compared with the semiconductor device 90.

The semiconductor device 130 can increase the number of transistors and capacitor elements like the semiconductor device 120 and the semiconductor device 125.

Further, as in the semiconductor device 135, an n-type transistor 136 may be provided instead of the transistor 131 (FIG. 9). The semiconductor device 135 can be operated as described in Embodiment Mode 1.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
FIG. 10 shows the semiconductor device 140. The semiconductor device 140 includes a transistor 101, a transistor 102, a capacitor 103, a capacitor 104, a transistor 105, and a transistor 141. The semiconductor device 140 can store multi-value information.

The semiconductor device 140 is different from the semiconductor device 100 (FIG. 1) in that the transistor 141 is included.

A gate of the transistor 141 is electrically connected to the wiring 142. The wiring 142 can function as a word line.

One of a source and a drain of the transistor 141 is electrically connected to the other of the source and the drain of the transistor 102, one electrode of the capacitor 104, and the gate of the transistor 105.

The other of the source and the drain of the transistor 141 is electrically connected to the wiring 143. Various voltages can be applied to the wiring 143. A reference potential (GND) and a power supply voltage (VDD, VSS) may be applied to the wiring 143. In addition, the voltage of each wiring and each terminal is a relative voltage, and it is important whether the voltage is higher or lower than a certain standard. Therefore, even if it is described as GND, it is not limited to 0V. Since current only needs to flow from one of the source and the drain of the transistor 141 to the other, the transistor 141 may be connected to a power supply line such as VSS or VDD.

A region where the channel of the transistor 141 is formed includes an oxide semiconductor layer. Therefore, the off-state current of the transistor 141 is extremely low.

An operation for writing information to the semiconductor device 140 and an operation for reading the written information will be described. FIG. 11-12 shows a timing chart. The write operation of the semiconductor device 140 is the same as the write operation of the semiconductor device 100 of the first embodiment.

First, an example of the write operation will be described (FIG. 11). As an example of the writing operation, a charge is accumulated in the capacitor 104 so that the potential difference between the electrodes of the capacitor 104 becomes the voltage V1, and the charge is stored so that the potential difference between the electrodes of the capacitor 103 becomes the voltage V2. Explain that it accumulates.

(Step 1)
At time t1, a high voltage is applied to the wiring 111 and the wiring 112. The transistors 101 and 102 are turned on.

At time t1, the voltage V1 is applied to the wiring 113. Since the transistor 101 and the transistor 102 are on, charge is accumulated in the capacitor 103 and the capacitor 104. Charges are accumulated and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V1. On the other hand, charge is accumulated also in the capacitive element 104, and the potential difference (VC1) between the electrodes of the capacitive element 104 becomes V1. The voltage V1 may be any voltage that can turn on the transistor 105.

A low voltage is applied to the wiring 142. The low voltage is applied to the gate of the transistor 141, and the transistor 141 is turned off.

(Step 2)
At time t2, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

Since the region where the channel of the transistor 102 is formed includes an oxide semiconductor layer, the off-state current of the transistor 102 is extremely low. The charge accumulated in the capacitor 104 does not leak through the source and drain of the transistor 102.

The transistor 141 is off and does not leak through the source and drain of the transistor 141.

At time t2, the voltage V2 is applied to the wiring 113. Since the transistor 101 is on, charge is further accumulated in the capacitor 103. Charges are accumulated, and the potential difference (VC2) between the electrodes of the capacitor 103 becomes V2.

At time t3, a low voltage is applied to the wiring 112. The transistor 101 is turned off. Since the off-state current of the transistor 101 is extremely low, the charge stored in the capacitor 103 does not leak through the source and the drain of the transistor 101. Similarly, leakage does not occur through the source and drain of the transistor 102.

At time t3, a low voltage is applied to the wiring 113.

As described above, the charge that causes the potential difference between the electrodes of the capacitor 104 to be V1 is accumulated in the capacitor 104, and the charge that causes the potential difference between the electrodes of the capacitor 103 to be V2 is accumulated in the capacitor 103 and written. The operation ends.

Next, an example of an operation for reading the information written by the write operation will be described (FIG. 12).

The read operation is divided into Step 1, Step 2, and Step 3. In step 1, VC1 (V1) of the capacitive element 104 is read. In step 2, VC1 is changed from V1 to V6. In step 3, the capacitive element 104 and the capacitive element 103 are connected in parallel, and the voltage (V3) of the combined capacitive element is read.

(Step 1)
Charge is already accumulated in the capacitor 104, and the voltage VC1 is V1. The voltage V1 is applied to the gate of the transistor 105. The transistor 105 is turned on. At this time, the current (ID) becomes a current I1 corresponding to the voltage V1. As a result, V1 is read.

(Step 2)
At time t4, a high voltage is applied to the wiring 142. The high voltage is applied to the gate of the transistor 141, and the transistor 141 is turned on. The high voltage may be any voltage that can turn on the transistor 141.

When the transistor 141 is turned on, the charge accumulated in the capacitor 104 flows to the wiring 143 through the source and drain of the transistor 141, and the charge accumulated in the capacitor 104 decreases. The potential difference (VC1) between the electrodes of the capacitor 104 decreases from V1 to the voltage V6 applied to the wiring 143. For example, when 0 V is applied to the wiring 143, the voltage V6 is 0 V.

The voltage V6 is applied to the gate of the transistor 105, and the current (ID) flowing through the transistor 105 becomes the current I0. For example, when V6 is 0 V and the transistor 105 is a normally-off n-type transistor, the transistor 105 may be turned off.

(Step 3)
At time t5, a low voltage is applied to the wiring 142. The transistor 141 is turned off. The low voltage may be any voltage that can turn off the transistor 141.

Further, a high voltage is applied to the wiring 111 at time t5. The transistor 102 is turned on.

When the transistor 102 is turned on, one electrode of the capacitor 103 and one electrode of the capacitor 104 are electrically connected to each other through the source and the drain of the transistor 102. Therefore, the capacitor 103 and the capacitor 104 are connected in parallel to form a combined capacitor. The amount of charge (Q2) accumulated in the capacitor 103 and the amount of charge (Q1) accumulated in the capacitor 104 are distributed according to the capacitance (C2) of the capacitor 103 and the capacitance (C1) of the capacitor 104. The When V6 is 0V, Q1 is zero.

Assuming that the voltage of the combined capacitor element is V3, when the transistor 102 is turned on, the voltage VC1 and the voltage VC2 are V3. The voltage V3 is applied to the gate of the transistor 105. It can also be said that the voltage VC1 or the voltage VC2 is applied to the gate of the transistor 105.

The current ID flowing through the transistor 105 is a current I3 corresponding to the voltage V3. As a result, V3 is read. Note that the voltage V3 is expressed by a formula in which V1 is replaced with V6 in the formula shown in the first embodiment. In particular, when V6 = 0V, V3 is expressed by the following equation.

When V3 is expressed as described above, it is not necessary to consider the influence of V1 and V6.

At time t6, a low voltage is applied to the wiring 111. The transistor 102 is turned off.

Thus, the operation for reading the charges accumulated in the capacitor 103 and the capacitor 104 is completed.

When the multivalue information is stored in the semiconductor device 140 and read out, two steps of Step 1 and Step 3 can be used.

When 3 bits are stored using the semiconductor device 140, 2 ¹ +2 ² = 6. Therefore, ^two states are provided in Step 1, four states are provided in Step 3, and six states may be determined. Or, conversely, four states may be provided in step 1 and two states may be provided in step 3.

In the case of 4 bits, 2 ² +2 ² = 8. Therefore, four states are provided in step 1, four states are provided in step 3, and the eight states may be determined.

The semiconductor device 140 has fewer states to set and discriminate than the case where the semiconductor device 90 is used to store and read multi-value information, and the discrimination circuit is not complicated.

Further, in the semiconductor device 140, like the semiconductor device 120 and the semiconductor device 125, the number of transistors and capacitors can be increased.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
An oxide semiconductor that can be used for the channel of the transistor in Embodiment 1-3 is described.

An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable that zirconium (Zr) is included as a stabilizer.

Among oxide semiconductors, In—Ga—Zn-based oxides, In—Sn—Zn-based oxides, and the like have excellent electrical characteristics by sputtering or a wet method, unlike silicon carbide, gallium nitride, or gallium oxide. There is an advantage that a transistor can be manufactured and the mass productivity is excellent. Further, unlike silicon carbide, gallium nitride, or gallium oxide, the In—Ga—Zn-based oxide can manufacture a transistor with excellent electrical characteristics over a glass substrate. In addition, it is possible to cope with an increase in the size of the substrate.

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be included.

For example, as an oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg Oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide (also referred to as IGZO), In—Al—Zn oxide, In—Sn—Zn oxide Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr- Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-E -Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga- A Zn-based oxide, an In-Al-Ga-Zn-based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide is used. be able to.

Note that for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be included. In-Ga-Zn-based oxides have sufficiently high resistance when no electric field is applied, and can have a sufficiently low off-state current, and also have high mobility.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1). / 5) atomic ratio In—Ga—Zn-based oxides and oxides in the vicinity of the composition can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or an oxide in the vicinity of the composition. Use it.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Hereinafter, the structure of the oxide semiconductor film is described.

An oxide semiconductor film is classified roughly into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, or the like.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. An oxide semiconductor film which has no crystal part even in a minute region and has a completely amorphous structure as a whole is typical.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, a microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface can have a higher degree of crystallinity than the region near the formation surface. is there. In addition, in the case where an impurity is added to the CAAC-OS film, the crystallinity of a region to which the impurity is added changes, and a region having a different degree of crystallinity may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

The CAAC-OS film is formed by a sputtering method using a polycrystalline metal oxide target, for example.

In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the treatment chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature at the time of film formation, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

In addition, the oxide semiconductor layer is not necessarily composed of a single metal oxide film, and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which first to third metal oxide films are sequentially stacked, the first metal oxide film and the third metal oxide film constitute a second metal oxide film. At least one metal element is included in the component, and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more than the second metal oxide film, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less, which is an oxide film close to a vacuum level. Furthermore, it is preferable that the second metal oxide film contains at least indium because carrier mobility is increased.

In the case where the transistor includes the semiconductor film having the above structure, when an electric field is applied to the semiconductor film by applying a voltage to the gate electrode, a channel is formed in the second metal oxide film having a lower conduction band energy in the semiconductor film. A region is formed. That is, since the third metal oxide film is provided between the second metal oxide film and the gate insulating film, the second metal oxide film separated from the gate insulating film has a channel. Regions can be formed.

In addition, since the third metal oxide film includes at least one of the metal elements constituting the second metal oxide film in its constituent elements, the second metal oxide film and the third metal oxide film Interface scattering is unlikely to occur at the interface. Accordingly, since the movement of carriers at the interface is difficult to be inhibited, the field effect mobility of the transistor is increased.

In addition, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, a channel region is also formed in a region near the interface, so that the threshold voltage of the transistor fluctuates. Resulting in. However, since the first metal oxide film includes at least one of the metal elements constituting the second metal oxide film in its constituent elements, the second metal oxide film and the first metal oxide film It is difficult to form interface states at the interface. Thus, with the above structure, variation in electrical characteristics such as threshold voltage of the transistor can be reduced.

In addition, it is preferable to stack a plurality of oxide semiconductor films so that an interface state that inhibits carrier flow is not formed at the interface between the films due to the presence of impurities between the metal oxide films. . If impurities exist between the stacked metal oxide films, the continuity of the energy at the bottom of the conduction band between the metal oxide films is lost, and carriers are trapped or re-entered near the interface. This is because the bonds disappear. By reducing the impurities between the films, a plurality of metal oxide films having at least one metal as a main component together are not simply stacked. A state of having a U-shaped well structure that continuously changes between them).

In order to form a continuous bond, it is necessary to use a multi-chamber type film forming apparatus (sputtering apparatus) provided with a load lock chamber to continuously laminate each film without exposure to the atmosphere. Each chamber in the sputtering apparatus is subjected to high vacuum exhaustion (1 × 10 ⁻⁴ Pa or more 5 × 5 × 5) using an adsorption-type vacuum exhaust pump such as a cryopump so as to remove water or the like which is an impurity for the oxide semiconductor as much as possible. It is preferable that it is about 10 ⁻⁷ Pa). Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow backward from the exhaust system into the chamber.

In order to obtain a high-purity intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum but also to increase the purity of a gas used for sputtering. The dew point of oxygen gas or argon gas used as the gas is −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, and the oxide semiconductor film is made highly purified by purifying the gas used. It is possible to prevent moisture and the like from being taken into the body as much as possible.

For example, the first metal oxide film or the third metal oxide film is formed using aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium more than the second metal oxide film. As long as the oxide film contains a high atomic ratio. Specifically, as the first metal oxide film or the third metal oxide film, the above-described element is 1.5 times or more, preferably 2 times or more than the second metal oxide film, more preferably 3 times or more. An oxide film including an atomic ratio which is twice or more higher is preferably used. The above element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide film. Therefore, with the above structure, the first metal oxide film or the third metal oxide film can be an oxide film in which oxygen vacancies are less likely to be generated than in the second metal oxide film.

Note that the thicknesses of the first metal oxide film and the third metal oxide film are 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the second metal oxide film is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm.

In the semiconductor film having a three-layer structure, the first metal oxide film to the third metal oxide film can take either amorphous or crystalline forms. However, since the second metal oxide film in which the channel region is formed is crystalline, stable electrical characteristics can be given to the transistor, and thus the second metal oxide film is crystalline. It is preferable.

(Embodiment 5)
An example of the semiconductor device described in Embodiment 1-4 will be described. FIG. 13 illustrates an example of a cross-sectional structure of the transistor 102, the transistor 105, and the capacitor 104 included in the semiconductor device 100 illustrated in FIG.

A channel of the transistor 102 includes an oxide semiconductor layer. The case where the transistor 102 and the capacitor 104 are formed over the transistor 105 having a channel formation region in a single crystal silicon substrate is illustrated.

Note that the transistor 105 can be formed using an amorphous, microcrystalline, polycrystalline, or single crystal semiconductor film such as silicon or germanium for the active layer. Alternatively, the transistor 105 may use an oxide semiconductor for the active layer. In the case where all transistors use an oxide semiconductor for the active layer, the transistor 102 is not necessarily stacked over the transistor 105, and the transistor 102 and the transistor 105 may be formed in the same layer.

In the case where the transistor 105 is formed using thin silicon, amorphous silicon manufactured by a vapor phase growth method such as a plasma CVD method or a sputtering method, and a multicrystal which is crystallized by irradiating laser light on the amorphous silicon. Crystalline silicon, single crystal silicon in which a surface layer portion is separated by implanting hydrogen ions or the like into a single crystal silicon wafer, or the like can be used.

The semiconductor substrate 1400 on which the transistor 105 is formed includes, for example, a silicon substrate having an n-type or p-type conductivity, a germanium substrate, a silicon germanium substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP A substrate, a GaInAsP substrate, a ZnSe substrate, or the like). FIG. 13 illustrates the case where a single crystal silicon substrate having n-type conductivity is used.

The transistor 105 is electrically isolated from other transistors by an element isolation insulating film 1401. For the formation of the element isolation insulating film 1401, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used.

Specifically, the transistor 105 is provided between the impurity region 1402 and the impurity region 1403 which function as a source region or a drain region, the gate electrode 1404, and the semiconductor substrate 1400 and the gate electrode 1404 formed in the semiconductor substrate 1400. And a gate insulating film 1405. The gate electrode 1404 overlaps with a channel formation region formed between the impurity region 1402 and the impurity region 1403 with the gate insulating film 1405 interposed therebetween.

An insulating film 1409 is provided over the transistor 105. An opening is formed in the insulating film 1409. In the opening, wirings 1410 and 1411 that are in contact with the impurity region 1402 and the impurity region 1403, respectively, and a wiring 1412 that is electrically connected to the gate electrode 1404 are formed.

The wiring 1410 is electrically connected to the wiring 1415 formed over the insulating film 1409. The wiring 1411 is electrically connected to the wiring 1416 formed over the insulating film 1409. Are electrically connected to a wiring 1417 formed over the insulating film 1409.

Over the wirings 1415 to 1417, an insulating film 1420 and an insulating film 1440 are stacked in this order. An opening is formed in the insulating film 1420 and the insulating film 1440, and a wiring 1421 electrically connected to the wiring 1417 is formed in the opening.

In FIG. 13, the transistor 102 and the capacitor 104 are formed over the insulating film 1440.

The transistor 102 includes a semiconductor film 1430 including an oxide semiconductor over the insulating film 1440, a conductive film 1432 and a conductive film 1433 functioning as a source electrode or a drain electrode over the semiconductor film 1430, and the semiconductor film 1430 and the conductive film 1432. And a gate insulating film 1431 over the conductive film 1433, and a gate electrode 1434 which is located over the gate insulating film 1431 and overlaps with the semiconductor film 1430 between the conductive film 1432 and the conductive film 1433. Note that the conductive film 1433 is electrically connected to the wiring 1421.

A conductive film 1435 is provided over the gate insulating film 1431 so as to overlap with the conductive film 1433. A portion where the conductive film 1433 and the conductive film 1435 overlap with the gate insulating film 1431 interposed therebetween functions as the capacitor 104.

Note that FIG. 13 illustrates the case where the capacitor 104 is provided over the insulating film 1440 together with the transistor 102; however, the capacitor 104 is provided under the insulating film 1440 together with the transistor 105. Also good.

An insulating film 1441 and an insulating film 1442 are sequentially stacked over the transistor 102 and the capacitor 104. An opening is provided in the insulating film 1441 and the insulating film 1442, and a conductive film 1443 in contact with the gate electrode 1434 in the opening is provided over the insulating film 1441.

Note that in FIG. 13, the transistor 102 only needs to include the gate electrode 1434 at least on one side of the semiconductor film 1430, but may include a pair of gate electrodes that are interposed with the semiconductor film 1430 interposed therebetween. .

In the case where the transistor 102 includes a pair of gate electrodes with the semiconductor film 1430 interposed therebetween, one gate electrode is supplied with a signal for controlling a conductive state or a non-conductive state, and the other gate The electrode may be in a state where a potential is applied from another. In this case, the same potential may be applied to the pair of electrodes, or a fixed potential such as a ground potential may be applied only to the other gate electrode. By controlling the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

FIG. 13 illustrates the case where the transistor 102 has a single gate structure having one channel formation region corresponding to one gate electrode 1434. However, the transistor 102 may have a multi-gate structure in which a plurality of gate electrodes are electrically connected to each other so that a plurality of channel formation regions are included in one active layer.

Further, the semiconductor film 1430 is not necessarily formed of a single oxide semiconductor, and may be formed of a plurality of stacked oxide semiconductors. For example, FIG. 14A illustrates a structure example of the transistor 1110A in the case where the semiconductor film 1430 is stacked in three layers.

A transistor 1110A illustrated in FIG. 14A includes a semiconductor film 1430 provided over an insulating film 820 and the like, a conductive film 832 electrically connected to the semiconductor film 1430, a conductive film 833, and a gate insulating film. 831 and a gate electrode 834 provided over the gate insulating film 831 so as to overlap with the semiconductor film 1430.

In the transistor 1110A, as the semiconductor film 1430, oxide semiconductor layers 830a to 830c are stacked in this order from the insulating film 820 side.

The oxide semiconductor layer 830a and the oxide semiconductor layer 830c each include at least one of metal elements included in the oxide semiconductor layer 830b in its constituent elements, and the energy at the lower end of the conduction band is higher than that of the oxide semiconductor layer 830b. The oxide film has a vacuum level of 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Further, the oxide semiconductor layer 830b preferably contains at least indium because carrier mobility is increased.

Note that as illustrated in FIG. 14B, the oxide semiconductor layer 830c may be provided over the conductive films 832 and 833 so as to overlap with the gate insulating film 831.

(Embodiment 6)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a video camera, a camera such as a digital still camera, or a goggle type Display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. . Specific examples of these electronic devices are shown in FIGS.

FIG. 15A illustrates a portable game machine, which includes a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, speakers 5006, operation keys 5007, a stylus 5008, and the like. Note that although the portable game machine illustrated in FIG. 15A includes two display portions 5003 and 5004, the number of display portions included in the portable game device is not limited thereto.

FIG. 15B illustrates a portable information terminal which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection portion 5605. is there. The video on the first display portion 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 in the connection portion 5605. Further, a display device to which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 15C illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like.

FIG. 15D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, a refrigerator door 5303, and the like.

FIG. 15E illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

FIG. 15F illustrates an ordinary car, which includes a car body 5101, wheels 5102, a dashboard 5103, lights 5104, and the like.

90 Semiconductor Device 100 Semiconductor Device 101 Transistor 102 Transistor 103 Capacitance Element 104 Capacitance Element VC1 Potential Difference Between Electrodes of Capacitance Element 104 VC2 Potential Difference Between Electrodes of Capacitance Element 103 105 Transistor 106 Terminal 107 Terminal 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 transistor 117 capacitor element 118 wiring 119 wiring 120 semiconductor device 121 transistor 122 capacitor element 123 wiring 124 wiring 125 semiconductor device 130 semiconductor device 131 transistor 132 wiring 135 semiconductor device 136 transistor 140 semiconductor device 141 transistor 142 wiring 143 wiring 820 insulating film 832 conductive Film 833 Conductive film 831 Gate insulating film 834 Gate electrode 830a Oxide semiconductor layer 830b Oxide semiconductor layer 8 0c Oxide semiconductor layer 1110A Transistor 1400 Semiconductor substrate 1401 Element isolation insulating film 1402 Impurity region 1403 Impurity region 1404 Gate electrode 1405 Gate insulating film 1409 Insulating film 1410 Wiring 1411 Wiring 1412 Wiring 1415 Wiring 1416 Wiring 1417 Wiring 1420 Insulating film 1421 Wiring 1430 Semiconductor film 1431 Gate insulating film 1432 Conductive film 1433 Conductive film 1434 Gate electrode 1435 Conductive film 1440 Insulating film 1441 Insulating film 1442 Insulating film 1443 Conductive film 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Cold storage door 5 303 Freezer compartment door 5401 Case 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Case 5602 Case 5603 Display unit 5604 Display unit 5605 Connection key 5606 Case 5802 Case 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection Part

Claims (4)

A semiconductor device having a first transistor, a second transistor, a first capacitor, a second capacitor, and a third transistor,
The region where the channel of the first transistor is formed has an oxide semiconductor layer,
The region where the channel of the second transistor is formed includes an oxide semiconductor layer,
A gate of the first transistor is electrically connected to a first word line;
One of a source and a drain of the first transistor is electrically connected to a bit line;
The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the first capacitor,
A gate of the second transistor is electrically connected to a second word line;
The other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor and one electrode of the second capacitor,
The operation of writing information to the semiconductor device is as follows:
Accumulating electric charge from the bit line to the first capacitor element and the second capacitor element;
Further accumulating electric charge from the bit line to the first capacitor element,
The operation of reading the information includes
Turning on the third transistor by the voltage of the second capacitor;
And a step of turning on the second transistor to connect the first capacitor and the second capacitor in parallel. In claim 1 ,
The first capacitor element and the second capacitor element are connected in parallel, and the third transistor is turned on by the voltage of the first capacitor element or the voltage of the second capacitor element. Semiconductor device. A semiconductor device having a first transistor, a second transistor, a first capacitor, a second capacitor, a third transistor, and a fourth transistor,
The region where the channel of the first transistor is formed has an oxide semiconductor layer,
The region where the channel of the second transistor is formed includes an oxide semiconductor layer,
The region where the channel of the fourth transistor is formed has an oxide semiconductor layer,
A gate of the first transistor is electrically connected to a first word line;
One of a source and a drain of the first transistor is electrically connected to a bit line;
The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor and one electrode of the first capacitor,
A gate of the second transistor is electrically connected to a second word line;
The other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor, one of the source and drain of the fourth transistor, and one electrode of the second capacitor. And
A gate of the fourth transistor is electrically connected to a third word line;
A reference potential is applied to the other of the source and the drain of the fourth transistor,
The operation of writing information to the semiconductor device is as follows:
Accumulating electric charge from the bit line to the first capacitor element and the second capacitor element;
Further accumulating electric charge from the bit line to the first capacitor element,
The operation of reading the information includes
Turning on the third transistor by the voltage of the second capacitor;
Turning on the fourth transistor to reduce the voltage of the second capacitor;
A step of turning off the fourth transistor and turning on the second transistor to connect the first capacitor element and the second capacitor element in parallel. apparatus. In claim 3 ,
The first capacitor element and the second capacitor element are connected in parallel, and the third transistor is turned on by the voltage of the first capacitor element or the voltage of the second capacitor element. Semiconductor device.