JP4299913B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device capable of storing an ultra-large capacity of gigabits or more, and more particularly to a nonvolatile semiconductor memory device including a thin film capacitor made of a ferroelectric thin film.
[0002]
[Prior art]
As the integration density of semiconductor memory devices increases and ultra-large storage capacity of gigabits or more becomes necessary, memory cells will become increasingly smaller, and the capacity of conventional storage capacitors using oxide films will be insufficient. It has become like this. Therefore, in recent years, research and development of a storage device using a ferroelectric thin film as a storage capacitor (hereinafter referred to as “ferroelectric memory”) has been actively carried out, and some of them have already been put into practical use. . Ferroelectric memory is non-volatile, and even if the power is turned off, the contents stored in the memory are not lost, and if the film thickness can be formed sufficiently thin, the spontaneous polarization reversal is fast, which is as fast as DRAM. It is possible to write and read data.
[0003]
At present, two types of ferroelectric memories, which are classified into the following, are broadly considered from the usage forms of ferroelectric thin films.
[0004]
The first ferroelectric memory uses a ferroelectric thin film as a ferroelectric capacitor, and reads a charge at the time of polarization inversion of a ferroelectric capacitor composed of a metal / ferroelectric / metal junction. is there. Its advantage is that the ferroelectric capacitor is made separately, so the creation process is relatively easy, and since the two electrodes of the ferroelectric capacitor are equipotential during standby, polarization is easy to maintain, If the minimum processing dimension is F, it is 8F in a 1-cell 1-transistor (1T / 1C) type cell similar to DRAM²4F for NAND type cells and 1T / 1C parallel connection cells (Chain FRAM)²That is, a small memory cell area is possible. Here, assuming that the minimum line width L and the minimum space width S of the pattern constituting the semiconductor memory device, the minimum processing dimension (2F) corresponds to the sum of both (2F = L + S).
[0005]
The second ferroelectric memory uses a ferroelectric thin film as a ferroelectric gate transistor. This is a structure in which a ferroelectric thin film is used as a gate insulating film instead of the gate oxide film of the MOS-FET, and is also called “MFS (metal / ferroelectric / semiconductor) -FET (Field Effect Transistor)”. It is. In this second ferroelectric memory, carriers that compensate the polarization charge of the ferroelectric thin film are induced on the semiconductor surface, so that an inversion layer and a storage layer are formed depending on the polarization direction of the capacitor, and the switching state of the transistor Can be retained.
[0006]
The particular advantage of this device is that it does not read the polarization charge directly, but can amplify and read it as a gain cell. Therefore, the absolute value of the polarization charge amount is not required for memory retention, and scaling with the minimum dimension f is possible as long as the polarization density can be retained. Here, the “minimum dimension f” is a so-called feature size f, and is generally given by L = S = f or L = f, S = 1.5f or the like.
[0007]
[Problems to be solved by the invention]
The first ferroelectric memory using the ferroelectric thin film as a ferroelectric capacitor requires that the amount of remanent polarization of the ferroelectric capacitor is more than a certain absolute amount and is difficult to scale with the minimum dimension f. Is a disadvantage. In reading using the current ferroelectric capacitor, the inverted charge of the capacitor is guided to the bit line capacitance, and sensing is performed as a potential difference of the bit line. With the miniaturization, the capacitor area and the inversion charge amount are F²However, since it is difficult to reduce the bit line capacity almost, there is a problem that scaling limits exist.
[0008]
On the other hand, the second ferroelectric memory using the MFS-FET also has the following first to third disadvantages. The first disadvantage is that the process of forming a ferroelectric thin film directly on Si may be difficult. The reason is that PZT (lead zirconate titanate: PbZr) is formed on Si (silicon) which is easily oxidized._XTi_1-XO_Three), SBT (Strontium bismuth tantalate: SrBi₂Ta₂O₉), BSTO (barium titanate / strontium: Ba_XSr_1-XTiO_ThreeThis is because it is not easy to form a film while maintaining good crystallinity because the oxide ferroelectric thin film such as) is directly formed.
[0009]
In addition, when a ferroelectric thin film is formed, there is a slight amount of SiO at the interface with silicon (Si).₂A layer is produced but SiO₂ Even if the layer is as thin as several nanometers, the dielectric constant is much smaller than that of the ferroelectric thin film, so that a considerable part of the voltage applied to the gate electrode of the MSF-FET is SiO 2.₂ This is because it includes a problem that the operating voltage becomes high due to being eaten by the layers.
[0010]
In addition, the ideal Si / SiO₂ Unlike the interface, the interface state existing at the Si / ferroelectric interface, or the impurity level of heavy metal in the ferroelectric diffused in Si becomes a channel trap of the MFS-FET, and the carrier mobility. It is also considered that the threshold voltage of the MFS-FET is fluctuated in accordance with the interface state density and the impurity state density, as the first disadvantage. These problems become very big problems as a highly integrated LSI.
[0011]
As a second disadvantage, there is a problem of a counter electric field applied to the ferroelectric thin film. In other words, the charge generated by the polarization of the ferroelectric material and the charge induced on the Si surface are ideally equal, so an accumulation layer and a depletion layer or inversion layer are generated depending on the direction of polarization. The shift of the surface potential of Si is added to the ferroelectric thin film as a counter electric field. Since this counter electric field is applied in the direction in which the polarization is reversed, it is difficult to stably maintain the polarization of the MFS-FET.
[0012]
A third disadvantage is that the memory cell size increases. When memory cells made of MFS-FETs are arranged in a matrix form to constitute a semiconductor memory device, a write control transistor and a read are added to one memory cell in addition to an MFS-FET for holding normal information. A control transistor is required. That is, in the case of MFS-FET, one memory cell is composed of three transistors (3T), and 18F²The cell area is as described above, and the memory cell size is larger than that of a ferroelectric memory cell using the first ferroelectric thin film as a ferroelectric capacitor.
[0013]
As described above, the use of either the ferroelectric capacitor in the first memory or the MFS-FET in the second memory has advantages and disadvantages, and a small memory cell configuration, scaling is possible, and ferroelectric polarization is stable. It is not possible to satisfy all the items required for highly integrated semiconductor memory, such as easy holding and process ease.
[0014]
In view of the above problems, an object of the present invention is to provide a semiconductor memory device using a ferroelectric thin film that can be configured in a small memory cell and that can stably maintain ferroelectric polarization.
[0015]
In addition to the above-described object, there is also provided a semiconductor memory device using a ferroelectric thin film that has the feature of being capable of scaling, which is an advantage of MFS-FETs, and can be further integrated. It has other purposes.
[0016]
Another object of the present invention is to provide a semiconductor memory device using a ferroelectric thin film that can be easily manufactured.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to a first basic configuration of the present invention includes a first electrode, a second electrode disposed opposite to the first electrode, and a first of these first electrodes. A storage capacitor comprising at least a ferroelectric thin film sandwiched between second electrodes; a third electrode connected to the first electrode of the storage capacitor; and facing the third electrode A reference capacitor comprising at least a fourth electrode disposed and a dielectric thin film sandwiched between the third and fourth electrodes; a first electrode of the storage capacitor and a third of the reference capacitor A reading transistor having a gate electrode connected to the electrode; and a control transistor for adjusting the potential of the storage node, which is the three connection points of the first electrode, the third electrode, and the gate electrode. It is characterized in that arranged in a plurality matrix of Moriseru. In other words, the semiconductor memory device according to the first basic configuration is such that a plurality of memory cells each including at least a storage capacitor, a reference capacitor, a read transistor, and a control transistor are arranged in a matrix.
[0018]
In the present invention, in the following description, a node serving as all connection points of the first electrode of the storage capacitor, the third electrode of the reference capacitor, and the gate electrode of the read transistor is referred to as a “storage node”. In the first basic configuration of the present invention, the external voltage V is connected across the series circuit of the storage capacitor and the reference capacitor._AIs added, the potential V of this storage node_GIs indicated by the intersection of the polarization-voltage curve (PV curve) of the memory capacitor and the reference capacitor. Since the storage capacitor having the ferroelectric thin film has a ferroelectric hysteresis curve, it can be in a polarization state corresponding to storage of “1” or “0” in advance before the read operation. Depending on the preset polarization state, the PV curve of the storage capacitor differs, and therefore V indicated by the intersection of the PV curves._GCan take different binary values. This different V_GThus, if the read transistor is on / off controlled, a signal corresponding to the storage state of “1” or “0” can be output to the read signal line.
[0019]
In the first basic configuration of the present invention, a control transistor is preferably connected between the first and second electrodes of the storage capacitor. That is, by installing a control transistor in parallel with the storage capacitor, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed. Further, at the time of reading, first, the storage capacitor is short-circuited by the control transistor, a voltage is applied only to the reference capacitor to perform precharging, and then the control transistor is turned off, and the first and second storage capacitors are turned off. It is possible to apply a precharge combined readout method in which a low voltage reverse potential is applied between the electrodes to invert the polarization state. In the present invention, in the following description, a unit including a storage capacitor and a control transistor connected in parallel to the storage capacitor is referred to as a “storage cell”.
[0020]
In the first basic configuration of the present invention, it is preferable to connect a control transistor between the third and fourth electrodes of the reference capacitor. By installing a control transistor in parallel with the reference capacitor, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed. Further, at the time of writing, the third and fourth electrodes of the reference capacitor are short-circuited (passed) by the control transistor, and a voltage is applied only to the storage capacitor, thereby enabling low voltage writing. In the present invention, in the following description, a unit including a reference capacitor and a control transistor connected in parallel to the reference capacitor is referred to as a “reference cell”.
[0021]
Further, in the first basic configuration of the present invention, the first control transistor connected between the first and second electrodes of the storage capacitor and the third and fourth electrodes of the reference capacitor are connected. Preferably, the second control transistor is provided. At the time of reading, first, the first control transistor is turned on, the storage capacitor is short-circuited, the second control transistor is turned off, and voltage is applied only to the reference capacitor for precharging. On the other hand, at the time of writing, the second control transistor is turned on, the third and fourth electrodes of the reference capacitor are short-circuited (passed) by the second control transistor, and the first control transistor Low voltage writing is possible by turning off the transistor and applying a voltage only to the storage capacitor. In addition, by installing the first and second control transistors, the floating / short state of the storage node can be quickly switched between reading and writing and standby to increase the operation speed.
[0022]
According to the first basic configuration of the present invention, it is possible to provide a highly integrated semiconductor memory device that is easy to process, has a small memory cell configuration, and is scalable. In particular, for miniaturization, all of the storage capacitor, the reference capacitor, the control transistor (first / second control transistor), and the gate capacitor of the read transistor are proportionally reduced, so the MFS-FET Full scaling is possible as well.
[0023]
The second basic configuration of the present invention includes a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric sandwiched between the first and second electrodes. A memory cell string (memory cell chain) in which a plurality of memory cells each including a memory capacitor including at least a thin film and a control transistor connected between the first and second electrodes are connected in series; A third electrode electrically joined to the first electrode of the storage capacitor located at the end of the cell row (memory cell chain), and a fourth electrode arranged corresponding to the third electrode; A reference capacitor having at least a dielectric thin film sandwiched between the third and fourth electrodes; a read transistor having a gate electrode electrically connected to the first and third electrodes; Equipped with memory cell The click is characterized in that arranged in a plurality matrix. Here, “electrically coupled” means not only a direct connection but also a circuit configuration in which a short-circuited storage capacitor, storage cell string (storage cell chain), and the like exist between them. It is. In order to randomly access the memory cell column (memory cell chain) in the second basic configuration of the present invention, a block selection transistor may be connected to each memory cell column.
[0024]
In the second basic configuration of the present invention, if the memory cell column is composed of n memory cells connected in series, one memory cell, a block selection transistor, a read transistor, a reference capacitor, and the like are included. In consideration of the area of the block, the memory cell unit is a minimum of 4F.²The size per memory cell is (4 + 20 / n) F.²To (4 + 14 / n) F²It is possible to achieve a high integration density. Furthermore, according to the second feature of the present invention, it is possible to provide a highly integrated semiconductor memory device that can be easily manufactured and can be scaled in pattern dimensions. In particular, for miniaturization, since all of the storage capacitor, the reference capacitor, the control transistor, and the gate capacitor of the read transistor are proportionally reduced, complete scaling similar to that of the MFS-FET becomes possible. In order to select a specific storage capacitor in a memory cell column, a control transistor that is connected in parallel to another storage capacitor to bring the control transistor into a conductive state and is connected in parallel to the specific storage capacitor of interest It is sufficient to turn off only the transistor for use. In this case, when a storage capacitor far from the reference capacitor in the storage cell column is selected, the parasitic capacitance of the control transistor of the storage cell existing between the reference capacitor and the selected storage capacitor is changed to the capacitance of the reference capacitor. Therefore, it may be considered that the operation of reading stored information is affected. In this case, the problem can be solved by adjusting the capacity of the memory cell at each position to be as close to 1: 1 as possible with respect to the sum of the capacity of the reference capacitor and the parasitic capacity of the control transistor. Specifically, the residual polarization amount of the storage capacitor of the storage cell far from the reference capacitor may be gradually increased from the residual polarization amount of the storage capacitor of the storage cell close to the reference capacitor.
[0025]
In the second basic configuration of the present invention, the control transistor connected in parallel to the storage capacitor is referred to as a “first control transistor” and is further connected between the third and fourth electrodes of the reference capacitor. It is preferable to connect a second control transistor. By configuring a reference cell in which a second control transistor is installed in parallel with the reference capacitor, the storage node can be quickly switched between a read / write state and a standby state to increase the operation speed. . Further, at the time of writing, low voltage writing can be performed by short-circuiting (passing) the third and fourth electrodes of the reference capacitor with the second control transistor and applying a voltage only to the storage capacitor. .
[0026]
Note that, although it is a matter common to the first and second basic configurations of the present invention, the amount of charge including a polarization inversion component obtained when a voltage corresponding to the read voltage is applied to the reference capacitor is the storage capacitor. It is preferable that the charge amount is not less than 1/4 and not more than 4 times the amount of charge including a polarization inversion component obtained when a voltage corresponding to a read voltage is applied to. In particular, by making the effective capacitances of the storage ferroelectric capacitor and the reference capacitor substantially equal, the inversion voltage of the ferroelectric capacitor is set to V_CThen, about 2V_GThe ferroelectric capacitor can be inverted at the operating voltage. At the same time, depending on the polarization state of the initial ferroelectric capacitor, V_GSince a voltage difference of a certain degree can be generated, the read transistor can be directly switched by the potential of the storage node.
[0027]
Further, the same applies to both the first and second basic configurations of the present invention, but the dielectric thin film of the reference capacitor may be a paraelectric thin film or a ferroelectric thin film. If the reference capacitor is made of a ferroelectric thin film, the storage capacitor and the reference capacitor can be created at the same time in the same process, which simplifies the process and improves the manufacturing yield. There is.
[0028]
When the semiconductor memory device according to the first and second basic configurations of the present invention is compared with the existing DRAM or FeRAM, the following advantages can be listed. That is,
(1) The minimum memory cell unit is 4F²Is the size of
(2) The absolute value of the accumulated charge is unnecessary and scaling for area reduction is possible.
(3) Since the ferroelectric capacitor can be held at the same potential during standby, it is stable.
(4) It is not sensitive to capacitor leakage or transistor junction leakage.
(5) Random access is possible,
(6) The same operating speed as DRAM can be secured,
(7) Low power consumption due to read / write (R / W) of only cross-point cells,
(8) Since reading is at the bus level, it becomes less sensitive to noise,
(9) The scaling law also applies to the soft error in the bit line mode, and the soft error is not a problem.
(10) Since a read amplifier is included in the block, a sense amplifier for each bit line is unnecessary.
Etc. Further, if the disadvantages are mentioned, there is a concern about the fatigue deterioration of the ferroelectric capacitor due to the destructive readout. Recently, a BSTO ferroelectric capacitor epitaxially grown has been developed, and this fatigue deterioration has been eliminated.
[0029]
Next, a semiconductor device according to the third basic configuration of the present invention includes a plurality of selection MOS transistors connected in series, and a plate electrode facing the storage electrode connected to each common main electrode of the selection transistors. A NAND type storage cell array comprising storage capacitors made of sandwiched dielectric thin films, a reference capacitor electrically coupled to a main electrode of a selection transistor located at an end of the storage cell array, and the selection A plurality of memory cell blocks each including at least a reading transistor having a gate electrode electrically coupled to a connection portion of a main transistor and a reference capacitor are arranged in a matrix.
[0030]
The main point of the third basic configuration is that a NAND type storage cell array using a dielectric capacitor and a reference capacitor are connected in series, and the potential of the storage node which is the connection point between the two is connected to the gate electrode of the read transistor. In addition to reading, each memory cell block is read out. That is, the external voltage V is applied to both ends of a series circuit of one storage capacitor selected by a transistor in the NAND cell string and the reference capacitor._AAdded this storage node N_SPotential V_GIs indicated by the intersection of the polarization-voltage curve (PV curve) of the memory capacitor and the reference capacitor.
[0031]
In the third basic configuration, the storage capacitor having the ferroelectric thin film has a ferroelectric hysteresis curve, and therefore can be in a polarization state corresponding to the storage of “1” or “0” in advance before the read operation. . The PV curve of the storage capacitor differs depending on the preset polarization state, and therefore V indicated by the intersection of the PV curves._GCan take different binary values. This different V_GThus, if the read transistor is on / off controlled, a signal corresponding to the storage state of “1” or “0” can be output to the read signal line.
[0032]
On the other hand, in a storage capacitor having a paraelectric thin film, a charge corresponding to storage of “1” or “0” is stored in the storage capacitor and the selection transistor is turned off, so that the storage state is achieved within the refresh cycle. Can be held. If the selection transistor is turned on at the time of reading and the storage capacitor and the reference capacitor are connected, the storage node N is set according to the charge amount of the storage capacitor accumulated in advance_SVoltage V_GCan take different binary values. This different V_GThus, if the read transistor is on / off controlled, a signal corresponding to the storage state of “1” or “0” can be output to the read signal line.
[0033]
As described above, the NAND type memory cell has a minimum of 4F.²However, in the conventional circuit, the accumulated charge of the dielectric capacitor in the memory cell is read by the bit line capacitance and determined by the sense amplifier, and therefore, the accumulated charge capacitance of a predetermined ratio to the bit line capacitance is For this reason, miniaturization was difficult. On the other hand, according to the semiconductor device according to the third basic configuration of the present invention, the stored charge of the storage capacitor is read by the capacitance of the reference capacitor, and is determined by the read transistor in the block. For this reason, all of the storage capacitor, the reference capacitor, and the transistor gate capacitor can be scaled proportionally, so that it can be completely scaled with respect to the area as in the MFS-FET, and is highly integrated to the gigabit class. An integrated semiconductor memory device can be realized.
[0034]
In addition, since one reference capacitor and one read transistor need only be added to a NAND type memory cell block composed of a large number of memory cells, the total is 4F.²A small memory cell area close to is possible.
[0035]
When the semiconductor memory device according to the third basic configuration of the present invention is compared with the existing DRAM or FeRAM, the following advantages can be listed. That is,
(1) The minimum memory cell unit is 4F²Is the size of
(2) Since the absolute value of the accumulated charge is unnecessary, scaling for area reduction is possible,
(3) Since the ferroelectric capacitor can be held at the same potential during standby, it becomes stable.
(4) If a ferroelectric capacitor is used as a memory capacitor, memory retention becomes insensitive to capacitor leakage and transistor junction leakage, and cell separation becomes easy.
(5) An operation speed comparable to that of DRAM can be secured.
(6) Since reading to the bit line is at the bus level, it is less sensitive to noise,
(7) The scaling law is applied to soft errors, making them insensitive,
(8) Since a read amplifier is included in the block, a sense amplifier for each bit line is not necessary.
(9) Since one of the storage capacitors is commonly connected to the plate electrode, the cell structure and process are easy.
Etc.
[0036]
In addition, the disadvantages are that the random access for each bit cannot be performed because of the NAND structure, and R / W is in block units. Further, although there is a concern about the fatigue deterioration of the ferroelectric capacitor due to destructive readout, a BSTO ferroelectric capacitor that has been epitaxially grown has been developed recently, and is similar to the semiconductor memory device according to the first and second basic configurations. Such a problem of fatigue deterioration has been considerably reduced.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of a semiconductor memory device according to the present invention will be described below in detail with reference to the accompanying drawings. Before describing a specific embodiment, the basic operation of the present invention will be described in more detail with reference to FIGS.
[0038]
In the equivalent circuit diagram shown in FIG. 1, the semiconductor memory device is sandwiched between a first electrode, a second electrode disposed opposite to the first electrode, and the first and second electrodes. Memory capacitor C having at least a ferroelectric thin film_MAnd storage capacitor C_MA third electrode connected to the first electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes. Reference capacitor C provided at least_REFAnd storage capacitor C_MFirst electrode and reference capacitor C_REFRead transistor Q having a gate electrode connected to the third electrode_READAnd storage capacitor C_MFirst electrode and reference capacitor C_REFControl transistor Q having a source or drain connected to a connection point with the third electrode_CAnd at least a memory cell.
[0039]
2 (a) and 2 (b) show the storage capacitor C shown in FIG._MAnd a reference capacitor C using a paraelectric thin film_REFThe operation diagrams of the storage “1” read operation and the storage “0” read operation when an external voltage is applied between the AB terminals of the cells connected in series are shown. Here, in the polarization-voltage curve (PV curve) shown in FIGS. 2A and 2B, the horizontal axis represents voltage (V) and the vertical axis represents dielectric polarization (P). Ferroelectric capacitor C as memory capacitor_MIs the reverse voltage of V_C, Externally applied voltage V_A, Storage node N which is a connection point of both capacitors_SThe potential of V_GAnd Ferroelectric capacitor C_MThe P-V curve has a ferroelectric hysteresis curve as shown in FIGS. FIG. 2A shows a ferroelectric capacitor C._MIs a polarization state corresponding to the storage of “1” in advance before the read operation, and FIG._MShows a case where the polarization state corresponds to the storage of “0”. Reference capacitor C using paraelectric thin film_REFIs represented by a straight line having a slope corresponding to the capacity.
[0040]
External voltage V between the A and B terminals of the cell_AStorage node N_SPotential V_GIs indicated by the intersection of the PV curves of the storage capacitor and the reference capacitor. As can be seen from FIG. 2A and FIG. 2B, since the PV curves are different, the potential V of the storage node when the polarization state corresponding to the storage of “1” is set in advance._G ¹And the potential V of the storage node in the polarization state corresponding to the storage of “0”_G ⁰Is different.
[0041]
Memory capacitor C_MVoltage V for inverting_AIs a reference capacitor C_REFThe capacitance of the reference capacitor C becomes lower as the capacitance of the capacitor is larger (inclination is greater in FIGS. 2A and 2B)._REFIt is desirable to have a larger capacity. On the other hand, V_AV when adding_GΔV depending on the storage state of the voltage read in_G= V_G ¹-V_G ⁰Conversely, the reference capacitor C_REFThe smaller the capacity, the larger. In this respect, it is desirable that the reference capacitor has a small capacitance. Therefore, taking into account both the inversion voltage and the read voltage, the storage capacitor C_MAnd reference capacitor C_REFHave substantially the same capacitance, that is, the storage capacitor C_MThe reversal polarization charge obtained when the reversal voltage is applied to the reference capacitor C_REFIt is desirable that the charge obtained when added to is approximately the same. More broadly, the substantial capacity ratio is allowed to be not less than 1/4 and not more than 4 times.
[0042]
Memory capacitor C_MAnd reference capacitor C_REFWhen the capacity ratio is 1: 1, V_AIs V_GTwice as large as V_GDifference △ V_GIs almost V_CIt becomes the same level as. Therefore, the storage capacitor C having an inversion voltage of 1V is used._MIf you use V_AIs about 2V, △ V_GAs a result, a difference of about 1V is obtained.
[0043]
Next, storage node N_SIncludes a read transistor Q_READConnected to the gate electrode of V_GDifference △ V_GThe memory state is discriminated by. At this time, the read transistor Q_READThe gate capacitance of the storage capacitor C_MAnd reference capacitor C_REFIs connected in parallel to the storage capacitor C_MAs a residual polarization of 10 μC / cm²If a normal ferroelectric capacitor of about a certain size is used, the read transistor Q having the same area is used._READStorage capacity of the storage node N is 1/10 or less._SAlmost no change in the potential. In the above example, V_GDifference △ V_GAs a result, about 1V can be obtained as the read transistor Q._READMOS transistor Q used as a threshold voltage is larger than about 700 mV, and the MOS transistor Q directly by the gate voltage_READReading can be performed by on / off control of the.
[0044]
In addition, the storage capacitor C_MWhen the squareness ratio of the ferroelectric hysteresis curve is good, the reference capacitor C_REFBy reusing the electric charge read out in step (b), rewriting can be continued following the reading operation. That is, as shown in FIG._RAppropriate rewrite voltage V in the opposite direction_WBy adding a storage capacitor C_MCan be returned to the state before the reading operation.
[0045]
FIG. 3A shows a ferroelectric capacitor C._MFIG. 3B shows a case where the polarization state corresponding to the storage of “1” is made in advance before the read operation. FIG._MShows a case where the polarization state corresponds to the storage of “0”. When continuous rewriting is not performed as shown in FIGS. 3A and 3B, as shown in FIG. 7A, the reference capacitor C_REFThe control transistor is connected in parallel, and the control transistor is turned on (on state), and the reference capacitor C_REFIs directly connected to the capacitor C for direct storage._MOnly voltage can be applied to write data.
[0046]
Reference capacitor C_REF1 is not limited to the paraelectric thin film as shown in FIG. 1, and may be a ferroelectric thin film as shown in FIG. Reference capacitor C_REFFirst, a method of reading a memory by using a ferroelectric substance and applying a voltage directly between the A and B terminals in the circuit diagram shown in FIG. 4 will be described. When a ferroelectric capacitor is used as the reference capacitor, it is necessary to polarize the reference capacitor in one direction before reading. In the circuit diagram shown in FIG. 4, the control transistor is turned on, and a negative voltage is applied between the BC terminals to polarize the reference capacitor in one direction. Next, the control transistor is turned off, and a negative read voltage V is connected in series between the storage capacitor and the reference capacitor between the A and B terminals._AAdd
[0047]
FIG. 5A shows a storage capacitor C._MShows an operation diagram in the read operation when “1” is written in the state of “1” in the drawing. Negative read voltage V at terminal B_AStorage node N_SPotential V_GIs indicated by the intersection of the PV curve of the storage capacitor and the PV straight line of the reference capacitor, and the potential at that time is V_G ¹It becomes. FIG. 5B shows an operation diagram in the read operation when the storage capacitor is polarized in the opposite direction, that is, when it is written in the state of “0”. From the same analysis, the storage node potential V_G ⁰Is obtained. Thus, the read voltage V substantially corresponding to the sum of the inverted voltage of the storage capacitor and the reference capacitor_AAs in the case where the paraelectric thin film is used for the reference capacitor, a sufficient voltage difference V at the storage node depending on the storage state._G ¹-V_G ⁰Can be obtained.
[0048]
Next, the reference capacitor C_REFThe readout in the precharge mode when a ferroelectric thin film is used will be described. In the circuit diagram shown in FIG. 4, the positive voltage V is applied to the terminal B while the control transistor is turned on and the terminals A and C are kept at the same potential._{pre e}To invert the reference capacitor and perform a precharge operation. Next, the control transistor is turned off, the precharge voltage is set to 0, and the terminal B is returned to the same potential as the terminals A and C. Operation diagrams at this time are shown in FIGS. 6 (a) and 6 (b). In the case of a ferroelectric capacitor, since the dielectric constant after polarization inversion is small, the charge stored by precharge is small, and the storage capacitor cannot be inverted by only this precharge charge. However, since the PV curve differs depending on the polarization direction of the storage capacitor, the potential difference V of the storage node_G ¹-V_G ⁰Can be obtained as well. This reading method also has an advantage that the ferroelectric capacitor can be read without being inverted while using the ferroelectric capacitor.
[0049]
Storage capacitor C_MPZT system, SBT system (especially SrBi mainly composed of bismuth (Bi))₂Ta₂O₉It is possible to use a thin film capacitor made of an epitaxial BSTO-based ferroelectric thin film having a Ba-rich composition. Of these, epitaxial BSTO capacitors are particularly excellent in terms of stability and film thickness. Reference capacitor C_REFAs silicon oxide (SiO₂), Tantalum oxide (Ta₂O_Five), A paraelectric capacitor using BSTO having a Sr-rich composition, and the above-described ferroelectric capacitor can be used.
[0050]
FIG. 7A to FIG. 7B are circuit diagrams for explaining the basic configuration of the present invention. FIG. 7A shows a reference capacitor C._REFFIG. 6 is a circuit diagram when a control transistor is connected between the third and fourth electrodes. Reference capacitor C_REFStorage node N by installing a control transistor in parallel with_SThe floating / short state can be quickly switched between read / write and standby to increase the operation speed. At the time of writing, the reference capacitor C_REFThe third and fourth electrodes are short-circuited (passed) by the control transistor, and the storage capacitor C_MBy applying a voltage only to this, low voltage writing becomes possible.
[0051]
FIG. 7B shows the storage capacitor C as described above._MA case where a control transistor is connected between the first and second electrodes is shown. Memory capacitor C_MBy installing a control transistor in parallel, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed. At the time of reading, first, the storage capacitor C_MIs short-circuited by the control transistor, and the reference capacitor C_REFPrecharge by applying a voltage only to the capacitor, and then the control transistor is turned off, and the storage capacitor C_MA precharge combined readout method in which a low voltage reverse potential is applied between the first and second electrodes to invert the polarization state becomes possible.
[0052]
FIG. 7C shows the storage capacitor C._MA first control transistor connected between the first and second electrodes and a reference capacitor C_REFFIG. 6 is a circuit diagram in a case where a second control transistor connected between the third and fourth electrodes is provided. At the time of reading, first, the first control transistor is turned on, and the storage capacitor C_MAnd the second control transistor is cut off, and the reference capacitor C_REFPrecharge is performed by applying a voltage only to these. On the other hand, at the time of writing, the second control transistor is turned on, and the reference capacitor C_REFThe third and fourth electrodes are short-circuited (passed) by the second control transistor. Then, the first control transistor is turned off, and the storage capacitor C_MBy applying a voltage only to this, low voltage writing becomes possible. Further, by installing the first and second control transistors, the storage node N_SThe floating / short state can be quickly switched between read / write and standby to increase the operation speed.
[0053]
FIG. 8A and FIG. 8B are circuit diagrams respectively showing specific configurations for further integrating the semiconductor memory device of the present invention. The memory device shown in FIG. 8A includes a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric sandwiched between the first and second electrodes. A plurality of storage capacitors C comprising at least a thin film_M0, C_M1, C_M2, C_M3,... And each storage capacitor C_M0, C_M1, C_M2, C_M3,..., A control transistor Q connected between the first and second electrodes._CA memory cell string (memory cell chain) in which a plurality of memory cells are connected in series; and a storage capacitor C located at an end of the memory cell string (memory cell chain)_M0A third electrode electrically coupled to the first electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes Reference capacitor C having at least_REFA read transistor Q having a gate electrode electrically coupled to the first and third electrodes_READA memory cell block including at least
[0054]
The semiconductor memory device of the present invention has a plurality of memory cell blocks arranged in a matrix. If the memory cell string is composed of n memory cells connected in series, the memory capacitor C located at the other end of the memory cell string (memory cell chain)_Mn-1The second electrode has a selection transistor (block selection transistor) Q_SIs connected. These n memory cells, block selection transistor Q_SRead transistor Q_READ, And reference capacitor C_REFIn consideration of the area of one block including etc., the memory cell unit has a minimum of 4F.²The size per memory cell is (4 + 20 / n) F.²To (4 + 14 / n) F²It is possible to achieve a high integration density. Specific storage capacitor C in the storage cell column_MyIs selected, the word line WL of the control transistor (nMOSFET) connected in parallel to another storage capacitor is set to a high level to be in a conductive state, and is connected in parallel to a specific storage capacitor of interest. Control transistor (nMOSFET) word line WL_yOnly the control transistor (nMOSFET) should be cut off.
[0055]
Further, as shown in FIG. 8B, the storage capacitor C_M0, C_M1, C_M2, C_M3Control transistors Q connected in parallel to each other_CAs a first control transistor and a reference capacitor C_REFThe second control transistor Q between the third and fourth electrodes_C2When connected. Reference capacitor C_REFIn parallel with the second control transistor Q_C2Storage node N by installing_SThe floating / short state can be quickly switched between read / write and standby to increase the operation speed. At the time of writing, the reference capacitor C_REFBetween the third and fourth electrodes of the second control transistor Q_C2Short-circuited (passed) at a specific storage capacitor C_MyBy applying a voltage only to this, writing at a low voltage becomes possible.
[0056]
9 (a) and 9 (b) show the reference capacitor C in FIGS. 8 (a) and 8 (b)._REF2 is a circuit diagram in the case where each is formed of a ferroelectric thin film. That is, FIG. 9B shows the reference capacitor C._REFIn parallel with the second control transistor Q_C2FIG. 9A shows a reference capacitor C._REFParallel to the second control transistor Q_C2This is the case where Reference capacitor C_REFIs made of a ferroelectric thin film, the storage capacitor C_M0, C_M1, C_M2, C_M3, ... and reference capacitor C_REFCan be created at the same time in the same process, which simplifies the process and improves the production yield.
[0057]
FIG. 10 is a circuit diagram for further integration of the semiconductor memory device of the present invention, which is an example in which a ferroelectric capacitor is used as a memory capacitor. That is, a plurality of selection MOS transistors Q connected in series_M0-Q_MN(Q in the figure_M0-Q_M2And a storage capacitor C comprising a ferroelectric thin film sandwiched between a storage electrode connected to each common main electrode of these selection transistors and a plate electrode facing the storage electrode C_M0-C_MN(Similarly, C_M0-C_M2NAND type memory cell column consisting of: and the selection transistor Q located at the end of the memory cell column_M0Reference capacitor C electrically coupled to the main electrode of_REFAnd a straight node N which is a connection portion between the main electrode of the selection transistor and the electrode of the reference capacitor_SRead transistor Q having a gate electrode electrically coupled to_READAnd at least a memory cell block.
[0058]
In this example, the other electrode disposed opposite to the electrode connected to the storage node of the reference capacitor is connected to the plate electrode PE, and the storage node N_SR / W control transistor Q_{R / W}To the bit line BL.
[0059]
Now, the first capacitor C in the memory cell column_M0The read operation will be described. Transistor Q_{R / W}And turn on Q_M0And Q_M1And turn off the reference capacitor C by the bit line BL._REFPrecharge voltage V_PIs applied to perform precharge. Next, transistor Q_{R / W}Transistor Q_M0Is turned on and a read operation is performed.
[0060]
First capacitor C in the NAND type memory cell column_M0After reading the memory contents of the capacitor C, the same sequence is repeated, so that the capacitor C_M1, C_M2, ... C_Mk, ... C_MNThe memory contents of can be read. That is, the capacitor C_MkTo read the memory contents of the transistor Q_{R / W}And Q_M0To Q_Mk-1Turn on all of the transistors, Q,_MkAnd turn off the reference capacitor C by the bit line BL._REFAnd memory capacitor C_M0To C_Mk-1Precharge voltage V_PIs applied to precharge. Next, transistor Q_{R / W}And turn off the transistor Q_M0The read operation is performed with the switch off.
[0061]
At this time, as a characteristic of the NAND cell column, the capacitor C_MkWhen reading the memory contents of, the C of the procedure that has already been read_M0To C_Mk-1It is a problem that the capacitance of the paraelectric component of the capacitor is added as a parasitic capacitance. If this parasitic capacitance becomes too large, the read operation is hindered. Therefore, in order to use a NAND cell string having a large number of memory cells, it is necessary to reduce the parasitic capacitance as much as possible. That is, it is effective to reduce the paraelectric component by increasing the squareness ratio of the memory ferroelectric capacitor.
[0062]
On the other hand, in writing, data is written in order from the capacitor farthest from the bit line in common with the memory having the NAND type memory cell column. Capacitor C_MkTo write to transistor Q_{R / W}And Q_M0To Q_MkTurn on all_{Mk + 1}Is turned off and the write voltage V is applied to the plate electrode by the bit line BL._AIs applied and a voltage higher than the coercive voltage is applied to the ferroelectric capacitor for memory.
[0063]
According to the present invention, various circuit configurations can be added to the basic circuit configuration including the memory cell column, the reference capacitor, and the read transistor. FIG. 15A to FIG. 15D show some examples.
[0064]
In the circuit shown in FIG.
(1) Reference capacitor C_REFStorage node N_SConnected to the plate electrode PE of the other electrode placed opposite to the electrode connected to the R / W control transistor Q_{R / W}To storage node N_SAnd the bit line BL.
[0065]
In this circuit, only a read operation by precharge is possible, but in a write operation, a write voltage can be directly applied to the storage capacitor.
[0066]
In the circuit shown in FIG.
(2) Reference capacitor C_REFStorage node N_SThe other electrode disposed opposite to the electrode connected to the second electrode is connected to a second drive line DL (may be called a drive line or a complementary bit line BL-), and an R / W control transistor Q_{R / W}To storage node N_SAnd the bit line BL.
[0067]
In this circuit, since a potential complementary to the plate electrode potential can be applied between BL and DL during the precharge operation, the operating voltage can be reduced by the large precharge. The operating speed can be increased. In the write operation, a write voltage can be directly applied to the storage capacitor.
[0068]
In the circuit shown in FIG.
(3) Reference capacitor C_REFStorage node N_SThe other electrode disposed opposite to the electrode connected to the bit line BL is connected to the bit line BL, and the R / W control transistor Q_{R / W}Reference capacitor C_REFIn parallel with storage node N_SAnd the bit line BL.
[0069]
In this circuit, only the read operation by applying the read voltage is possible, but in the write operation, the write voltage can be directly applied to the storage capacitor.
[0070]
Furthermore, in the circuit shown in FIG.
(4) Reference capacitor C_REFStorage node N_SThe other electrode disposed opposite to the electrode connected to the bit line BL is connected to the bit line BL, and the first R / W control transistor Q_{R / W1}Reference capacitor C_REFIn parallel with storage node N_SAnd a second R / W control transistor Q between the bit line BL and the bit line BL._{R / W2}To storage node N_SAnd the plate electrode PE.
[0071]
In this circuit, a read operation using precharge is possible, and a write voltage can be directly applied to the storage capacitor.
[0072]
As described above, various read and write modes can be supported by adding some elements to the basic configuration.
[0073]
In the circuit shown in FIG. 15D, the reference capacitor C_REFAs an alternative, a ferroelectric capacitor may be used instead of the paraelectric capacitor. In this case, the first capacitor C of the memory cell column_M0The read operation will be described with reference to FIG. Transistor Q_{R / W1}Q off_{R / W2}And a precharge voltage V equal to or higher than the coercive voltage of the reference ferroelectric capacitor_PIs applied between the plate electrode PE and the bit line BL to polarize the reference capacitor in one direction. Next, the potential of the bit line BL is returned to the same potential as that of the plate electrode PE, and the transistor Q_M0And turn on the reference capacitor C by the bit line BL._REFAnd memory capacitor C_M0In series, the read voltage V in the direction opposite to the precharge voltage with respect to the plate electrode potential_AIs applied to read out data. Storage node N at this time_SIt can be understood that the operation diagram of FIG. 6 basically operates in the same manner as a reference capacitor using a paraelectric material. Depending on the polarization state corresponding to the storage of “1” or “0” of the storage capacitor in advance, different storage nodes N_SVoltage V_G ¹Or V_G ⁰It can be seen that Storage node N_SRead transistor Q with a gate electrode connected to_READThe memory state is discriminated by.
[0074]
In writing, transistor Q_{R / W1}And turn on the transistor Q_{R / W 2}And turn off the transistor Q_M0Is turned on and the storage capacitor C is connected by the bit line BL._M0Write voltage V_AIs directly applied to perform the write operation.
[0075]
Next, a case where an asymmetrical ferroelectric capacitor in which the center of the ferroelectric hysteresis is shifted from 0 V is used as the storage capacitor as shown in FIGS. 11A and 11B will be described. Such asymmetric ferroelectric capacitors are often observed when using epitaxial ferroelectric films (eg, K. Abe, S. Komatsu, N. Yanase, K. Sano and T. Kawakubo: 'Asymmetric Ferroelectricity and Anomalous Current Conduction in Heteroepitaxial BaTiO_Three Thin Films ’, Japan Journal of Applied Physics, Vol. 36, Part 1, No. 9B, pp. 5846-53 (1997)).
[0076]
As shown in FIG. 11A, an asymmetric capacitor cannot be used as a nonvolatile memory because one polarization state is stable and the other polarization state is metastable. However, as shown in FIG. 11B, the voltage V corresponding to the shift of the center of hysteresis._fIs applied, the polarization in two directions can be stably maintained as in the case of a normal ferroelectric capacitor. Therefore, the circuit of the present invention can be used as an SRAM (Static Random Access Memory) that statically holds memory.
[0077]
That is, the transistor Q is in a standby state for holding the memory._M0To Q_MNAll on and capacitor C through bit line etc._M0To C_MNThe voltage V always corresponds to the deviation of the center of hysteresis._fThe memory is stably held by applying. On the other hand, transistor Q_M0To Q_MNAll of the above can be temporarily turned off, and reading / writing can be performed in the same sequence as when the above-described ordinary ferroelectric capacitor is used. In the ferroelectric capacitor whose center voltage is positively shifted as shown in FIGS. 11 (a) and 11 (b), the readout voltage is negative, and conversely, the ferroelectric whose center voltage is negatively shifted is shown. In the capacitor, it is advantageous in terms of circuit operation that the read voltage is a positive voltage.
[0078]
Next, a case where a paraelectric capacitor is used as the storage capacitor will be described. FIG. 12 shows a storage capacitor C in the circuit shown in FIG._MIn this example, a paraelectric capacitor having a nonlinear storage capacity is used instead of a ferroelectric capacitor. In the circuit shown in FIG. 12, the first capacitor C in the memory cell row_M0The read operation will be described with reference to FIG. Transistor Q_{R / W}Transistor Q_M0And turn off the reference capacitor C by the bit line BL._REFPrecharge voltage V_PIs applied to precharge. Next, the potential of the bit line BL is returned to the same potential as the plate electrode PE, and the transistor Q_{R / W}And turn off the transistor Q_M0Is turned on to perform a read operation. Storage node N at this time_SFIG. 13A and FIG. 13B show the operation diagrams of FIG. 13, and it can be understood that the operation is basically similar to that of the storage capacitor using the ferroelectric. Depending on the polarization state corresponding to the storage of “1” or “0” of the storage capacitor in advance, different storage nodes N_SVoltage V_G ¹Or V_G ⁰It can be seen that Storage node N_SRead transistor Q with a gate electrode connected to_READThe memory state is discriminated by.
[0079]
First capacitor C in the NAND type memory cell column_M0After reading the memory contents of the capacitor C, the same sequence is repeated, so that the capacitor C_M1, C_M2, ... C_Mk, ... C_MNThe memory contents of can be read. That is, the capacitor C_MkTo read the memory contents of the transistor Q_{R / W}And transistor Q_M0To Q_{Mk = 1}Turn on all_MkAnd turn off the reference capacitor C by the bit line BL._REFPrecharge voltage V_PIs applied to precharge. Next, transistor Q_{R / W}And turn off the transistor Q_MkIs turned on to perform a read operation.
[0080]
However, as a problem of the NAND cell array using the paraelectric capacitor, the capacitor C_MkWhen reading the memory contents of the previous C,_M0To C_Mk-1The capacitance of the capacitor up to is added as a parasitic capacitance. If this parasitic capacitance becomes too large, the read operation is hindered. Therefore, in order to use a NAND cell string having a large number of memory cells, it is necessary to reduce the parasitic capacitance as much as possible.
[0081]
In a capacitor using a normal silicon oxide film or silicon nitride film, since the dielectric constant is always constant regardless of the bias voltage, the storage capacity when each storage capacitor in the NAND type cell array is used as a memory cell. The parasitic capacitance when acting as a parasitic capacitor on the front side of the memory cell is the same. Therefore, when all the storage capacitors and the reference capacitors have the same capacitance, the total capacitance including the reference capacitor and the parasitic capacitor at the time of reading increases in proportion to the position of the storage capacitor to be read. become. That is, the total capacitance of the read-side capacitor when reading the k-th capacitor is k times the reference capacitor capacitance, and the read voltage decreases almost in inverse proportion to the increase in the total capacitance, so that the read transistor operates. No longer.
[0082]
One way to alleviate this problem is to use a dielectric film with a non-linear capacitance. The dielectric constant is constant because the silicon oxide film and the silicon nitride film are electronically polarizable. However, an ion polarizable dielectric such as a perovskite oxide ferroelectric has a bias voltage dependency of the dielectric constant. Capacitors having nonlinear capacitance characteristics can be created. FIG. 14 shows a large characteristic of a paraelectric capacitor having a large non-linearity measured with an epitaxial BSTO paraelectric film. The capacitance decreases rapidly by applying a bias voltage of ± several V, and is less than a fraction of become. Therefore, when accumulating charges, it is possible to effectively use a region having a large capacitance near 0 V, and when acting as a parasitic capacitor, a bias voltage is applied by precharging and a portion having a small capacitance can be used. Become. By using such a non-linear capacitance capacitor, it becomes possible to use a NAND type memory cell array including many paraelectric capacitor memory cells. Note that, within the operating voltage range, it is desirable that the peak capacitance value is at least twice the minimum capacitance value.
[0083]
The write operation is the same as that of a ferroelectric capacitor. Transistor Q_{R / W}And Q_M0To Q_MkIs turned on and the storage capacitor C is connected by the bit line BL._MkWrite voltage V_AIs directly applied to perform a write operation. As described above, the dielectric film of the reference capacitor may be a paraelectric material or a ferroelectric material. Even a ferroelectric film can be read out in the same manner as a paraelectric film if it is polarized in one direction by precharging in advance before the reading operation. When the storage capacitor is a ferroelectric capacitor, the reference capacitor is also a ferroelectric capacitor, and when the storage capacitor is a paraelectric capacitor, the reference capacitor is also a paraelectric capacitor. Capacitor can be produced in the same process, and the process can be simplified and the production yield can be improved, which has a great advantage.
[0084]
In addition, as described above, when a memory far from the reference capacitor is selected in the NAND type memory cell column, the paraelectric component of the storage capacitor existing between the reference capacitor and the selected storage capacitor is changed to the read mode. Depending on the case, it may be added to the capacity of the reference capacitor or added to the capacity of the selected storage capacitor, which may affect the memory read operation. In this case, the capacitance of the storage capacitor at each position is as close to 1: 1 as possible with respect to the sum of the capacitance of the reference capacitor and the parasitic capacitance composed of the paraelectric component of the storage capacitor according to the read mode. It can be solved by adjusting to. Specifically, the residual polarization amount of the storage capacitor farther from the reference capacitor is gradually increased or decreased depending on the read mode than the residual polarization amount of the storage capacitor close to the reference capacitor. That is.
[0085]
As a ferroelectric capacitor for storage, a thin film made of a ferroelectric curtain of PZT (lead zirconate titanate), SBT (strontium bismuth titanate), or epitaxial BSTO (barium titanate titanate). Although a capacitor can be used, an epitaxial BSTO type capacitor is particularly excellent in terms of stability and film thickness.
[0086]
In addition, it is possible to use a dielectric film such as silicon oxide or tantalum oxide as a paraelectric capacitor for storage, but considering the absolute value of capacitance and the magnitude of nonlinearity, an epitaxial BSTO-based capacitor can be used. Paraelectric capacitors are particularly superior. As a reference capacitor, a paraelectric capacitor using silicon oxide, tantalum oxide, or BSTO, or the above-described ferroelectric capacitor can be used.
[0087]
From the above, the basic matters of the present invention can be understood. Next, first to twelfth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios between the drawings are included.
[0088]
(First embodiment)
FIG. 16 is a diagram showing a circuit configuration of main parts of the semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 16, the semiconductor memory device according to the first embodiment of the present invention includes a plurality of memory capacitors C connected in series._M0, C_M1, C_M2, ..., C_M15And this storage capacitor C_M0, C_M1, C_M2, ..., C_M15Memory cell string (memory cell chain) composed of control transistors connected in parallel to each of the memory cells, and a storage capacitor C located at the end of the memory cell chain_M15Reference capacitor C connected to_REFAnd storage capacitor C_M15And reference capacitor C_REFTransistor Q for reading having a gate electrode connected to a connection point (connection node)_READAnd a storage capacitor C located at the other end of the storage cell chain_M0Selection transistor (block selection transistor) Q connected to_SA memory cell block having at least the above is configured as a basic unit.
[0089]
Each storage capacitor C_M0, C_M1, C_M2, ..., C_M15Each includes at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes. . Reference capacitor C_REFIs a storage capacitor C_M15A third electrode electrically coupled to the first electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes And at least. 8A and 8B are the storage capacitor C._M0, C_M1, C_M2, ..., C_M15Note that the order of the sequences is reversed, but only a matter of order. In the semiconductor memory device according to the first embodiment, a plurality of memory cell blocks are arranged in a matrix. In FIG. 16, two blocks [A] and two blocks [B] are included. Only one is shown. Block selection transistor Q in the upper column of block [A]_SAre connected to the bit line BL0 and are connected to the block selection transistor Q in the lower column of the block [A]._SIs connected to the bit line BL1. The block selection transistor Q in the upper column of the block [B]_SAre connected to the bit line BL0 and the block select transistor Q in the lower column._SIs connected to the bit line BL1.
[0090]
Storage capacitor C of block [A]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^A, WL1^A, WL2^A, ..., WL15^AIs connected. Similarly, the storage capacitor C of the block [B]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^B, WL1^B, WL2^B, ..., WL15^BIs connected. Block selection transistor Q of block [A]_SEach of the gate electrodes of the word line BS of the block selection transistor^AIs the block selection transistor Q of the block [B]._SEach of the gate electrodes of the word line BS of the block selection transistor^BIs connected. Reference capacitor C for block [A]_REFIncludes a reference capacitor control transistor Q on the gate electrode._REFWord line WR^AControl transistor Q connected to_REFIs the reference capacitor C of the block [B]._REFIncludes a word line WR of a reference capacitor control transistor at the gate electrode.^BControl transistor Q connected to_REFIs connected.
[0091]
Read transistor Q of each memory cell block_READOne of the main electrodes of the read power supply line VL^A, VL^BHowever, the other main electrode has a read output line SL.^A, SL^BIs connected. In this embodiment, the read transistor Q_READTwo sets of read output lines SL connected alternately to^AAnd SL^BIs provided. Further, a plate line PL is connected to a connection point between the reference capacitor control transistor of the block [A] and the reference capacitor control transistor of the block [B]. In FIG. 16, the storage capacitor C_M0, C_M1, C_M2, ..., C_M15Control transistor and readout transistor Q connected in parallel with each other_{R EAD}, Block selection transistor Q_S, And reference capacitor control transistor Q_REFIs shown as an nMOSFET, but it can also be constituted by a pMOSFET.
[0092]
FIG. 17 shows a connection diagram including peripheral circuits. Each word line WL0 of block [A]^A, WL1^A, WL2^A, ..., WL15^AThe word line WL0 of the block [B] is sent to the row decoder A402.^B, WL1^B, WL2^B, ..., WL15^BAre connected to a row decoder B401, and each bit line BL0, BL1,... Is connected to a column decoder 411.
[0093]
In the configurations shown in FIGS. 16 and 17, BLx (x = 0, 1) and WLy in block [A]^AIn order to select a desired memory cell designated at the intersection of (y = 0, 1, 2,..., 15), the word line BS^AIs set to “1 (high level)” and the block selection transistor Q_SOn, WLy^AOnly “0 (low level)” and the storage capacitor C_MyTurn off the control transistor connected to the other WL^ATo “1” and constant potential {eg (1/2) V_G} Is applied by applying a potential to BLx. At the time of reading, the word line WR of the reference capacitor control transistor^AOff, write word line WR^ATurn on. Similarly, BLx (x = 0, 1) and WLy in block [B]^BIn order to select a desired memory cell designated at the intersection of (y = 0, 1, 2,..., 15), the word line BS^BBlock select transistor Q_SOn, WLy^BOnly “0” and the storage capacitor C_MyTurn off the control transistor connected to the other WL^BTo “1” and constant potential {eg (1/2) V_G} Is applied by applying a potential to BLx. At the time of reading, the word line WR of the reference capacitor control transistor^BIs set to “0”, the word line WR is written^BSet to “1”.
[0094]
FIG. 18 further shows a read / write sequence when the “precharge read method” is employed. That is, in the precharge readout method, WLy^A, WLy^BBefore selecting the reference capacitor C_REFApply reverse voltage to the capacitor of^A, WLy^BBy selecting a positive voltage after selecting the memory capacitor C_MyThe voltage is substantially reversed by applying a voltage about twice as high.
[0095]
FIG. 19A is a plan view showing a memory cell block, and for simplification, only a lower layer than the level of the A-A ′ line in the cross-sectional view shown in FIG. 19B is shown. In FIG. 19A, n⁺Source / drain regions 21, 22 and a word line BS to be a polysilicon gate electrode^BAnd the block selection transistor Q of the block [B]._SIs configured. Where "n⁺“Source / drain region” means either a source region or a drain region of a MOSFET. Usually, the source region and drain region of the MOSFET are formed symmetrically with the gate electrode as the center, so it is only a matter of naming which is called the source region of the MOSFET or the drain region of the MOSFET. Only. n⁺The source / drain region 21 functions as a “bit line connection portion”. Similarly, n⁺Source / drain regions 22 and 23 and word line WL0 serving as a polysilicon gate electrode^BAnd the storage capacitor C of the block [B]._M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Control transistor connected in parallel to n⁺Source / drain regions 24, 25 and word line WL2^BAnd the storage capacitor C_M2Control transistors connected in parallel to each other,..., N⁺Source / drain regions 26 (not shown), 27 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. n⁺The source / drain regions 23, 25,..._M0, C_M1, C_M2, ..., C_M15The lower electrodes 42, 43,..., 44 functioning as the first electrode or the second electrode are connected. N⁺The source / drain regions 31 and 32 and the polysilicon gate electrode 531, or the regions 32 and 33 and the gate electrode 532, read transistor Q_READIs formed. n⁺The source / drain regions 31 are formed along the column (row) direction and read out output lines SL.^BN⁺The source / drain regions 32 are also formed in the column (row) direction and read power supply line VL.^BDoubles as And n⁺Source / drain regions 28 and 29 and word line WR^BThus, a reference capacitor control transistor is formed. n⁺The source / drain region 29 functions as a “plate line connecting portion” and is connected to the plate line PL. The plate line PL is connected to a reference capacitor C._REFThis also serves as the lower electrode 45 functioning as the fourth electrode. Although the block [B] will be mainly described, the block [A] has the same configuration as the block [B].
[0096]
As shown in FIG. 19A, each of the block selection transistors Q is included in one block [A] or block [B] sandwiched between the bit line connection portion and the plate line connection portion._S, N storage capacitors C_M0, C_M1, C_M2, C_M3, ..., C_M15N control transistors connected in parallel therewith, read transistor Q_READReference capacitor C_REF, And a reference capacitor control transistor. Memory cell size is 4F²The area other than the memory cell including the contact portion per block is 28F.²Therefore, (4 + 28 / n) F per memory cell²become. In the first embodiment, the ferroelectric capacitor is 20 μC / cm.²Therefore, it was found that even if 16 memory cells are connected in series, the device operates stably. Therefore, 5.8F per piece²It became the size of.
[0097]
FIG. 19B is a cross-sectional view along the B-B ′ direction of the plan view shown in FIG. As shown in FIG. 19B, in the semiconductor memory device according to the first embodiment of the present invention, a p-well 12 is formed on a semiconductor substrate 11, and an n-type surface is formed on the surface of the p-well 12.⁺Source / drain regions 21, 22, 23,..., 30 are provided. Then, a word line BS serving as a polysilicon gate electrode is formed on the gate oxide film on the surface of the p-well 12.^B, WL0^B, WL1^B, WL2^B, ..., WL15^B, WR^BAnd WR^Ahave. In the cross-sectional view of FIG. 19B, the cross section of the wiring portion of the polysilicon gate electrode 532 is also exposed. Although FIG. 19B shows a single-layer polysilicon gate electrode, a two-layer structure including a polysilicon gate layer and a W gate layer may be used instead of the single-layer polysilicon gate electrode. In addition to the W gate layer, refractory metals such as Ti, Mo, Co, or WSi₂, TiSi₂, MoSi₂, CoSi₂A refractory metal silicide such as may be used.
[0098]
n⁺Source / drain regions 21, 22 and word line BS^BThe block selection transistor Q_SIs configured. n⁺Source / drain regions 22, 23 and word line WL0^BAnd the storage capacitor C_M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Control transistor connected in parallel to n⁺Source / drain regions 24, 25 and word line WL2^BAnd the storage capacitor C_M2Control transistors connected in parallel to each other,..., N⁺Source / drain regions 26 (not shown), 27 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. And n⁺Source / drain regions 28 and 29 and word line WR^BThus, a reference capacitor control transistor is formed. Word line BS^B, WL0^B, WL1^B, WL2^B, ..., WL15^B, WR^BAnd WR^AOn top of the oxide film (SiO₂Film), a PSG film, a BPSG film, a nitride film (Si3N4 film) and the like, and a first interlayer insulating film 13 is formed on the first interlayer insulating film 13._M0, C_M1, C_M2, C_{M3 3}, ..., C_M15Lower electrodes 42, 43,..., 45 functioning as the first electrode or the second electrode are formed. Further, on the first interlayer insulating film 13, a reference capacitor C that also serves as a plate line PL is provided._REFA lower electrode 45 functioning as the fourth electrode is also formed. The lower electrodes 42, 43,..., And 45 are formed by contact plugs 73, 75, and 80 formed so as to fill contact holes provided in the first interlayer insulating film 13.⁺Source / drain regions 23, 25,..., 29 are connected. These contact plugs may be made of polycrystalline silicon (doped polysilicon) doped with impurities, refractory metal, silicide of refractory metal, or the like. The lower electrode 42 is a storage capacitor C._M0First electrode and storage capacitor C_M1It functions as the second electrode. The lower electrode 43 includes a storage capacitor C_M2First electrode and storage capacitor C_M3It functions as the second electrode. ... the lower electrode 44 is a storage capacitor C_M14First electrode and storage capacitor C_M15It functions as the second electrode. The lower electrodes 42, 43,..., 44, 45 are composed of a lower barrier metal layer made of (Ti, Al) N having a thickness of 10 nm, and SrRuO having a thickness of 20 nm._ThreeWhat is necessary is just to comprise by the two-layer structure with the lower electrode which consists of. Then, ferroelectric thin films 51, 52,..., 53 such as a 25-nm thick Ba-rich composition BSTO thin film may be formed on the lower electrodes 42, 43,. Reference capacitor C_REFOn the lower electrode 45, a paraelectric thin film 54 such as a BSTO thin film of Sr rich composition having a thickness of 25 nm may be formed. Reference capacitor C_REFAs the paraelectric thin film 54 for use, silicon oxide (SiO₂), Tantalum oxide (Ta₂O_FiveEtc.) and a ferroelectric thin film can be used. On the first interlayer insulating film 13 where the ferroelectric thin films 51, 52,..., 53 and the paraelectric thin film 54 are not formed, an oxide film (SiO₂Film), PSG film, BPSG film, nitride film (SI₃N₄A second interlayer insulating film 14 made of a film) is formed, and upper electrodes 61, 62,... 63 are formed on the second interlayer insulating film 14. The upper electrode 61 includes a storage capacitor C_M0It functions as the second electrode. The upper electrode 62 includes a storage capacitor C_M1First electrode and storage capacitor C_M2It functions as the second electrode. ... Upper electrode 63 is a storage capacitor C_M15First electrode and reference capacitor C_REFIt functions as the third electrode. The upper electrodes 61, 62,..., 63 are made of 20 nm thick SrRuO._ThreeThe upper electrodes 61, 62,..., 63, 64 may be formed by a two-layer structure of an upper electrode made of a film and a (Ti, Al) N upper barrier metal layer having a thickness of 10 nm formed thereon. The contact plugs 72, 74, 77, 79 formed so as to fill the contact holes provided through the first interlayer insulating film 13 and the second interlayer insulating film 14⁺The source / drain regions 22, 24,..., 27, 28 are connected. These contact plugs 72, 74, 77, 79 may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. Further, the upper electrode 63 is connected to the read transistor Q via a contact plug 78 provided through the first interlayer insulating film 13 and the second interlayer insulating film 14._READThis is connected to the wiring portion 532 of the polysilicon gate electrode. The wiring portion 532 of the polysilicon gate electrode is patterned thicker than the polysilicon gate electrode of the device portion in order to provide the contact plug 78. On the upper electrodes 61, 62,..., 63, an oxide film (SiO₂Film), PSG film, BPSG film, nitride film (Si₃N₄A third interlayer insulating film 15 made of a film) is formed, and a bit line 16 is formed on the third interlayer insulating film 15. Bit lines 16 and n⁺The source / drain region 21 is connected to each other by a bit line contact plug 71 that penetrates the first to third interlayer insulating films 13, 14, and 15. The bit line contact plug 71 may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. Although not shown, an oxide film (SiO 2) is further formed on the bit line 16.₂Film), PSG film, BPSG film, nitride film (Si₃N₄It is preferable to form a passivation film such as a film) or a polyimide film. Although the block [B] has been mainly described, the block [A] also has a similar configuration, and with such a circuit configuration, the operation of a highly integrated nonvolatile memory could be confirmed.
[0099]
(Second Embodiment)
FIG. 20 shows the circuit configuration of the main part of the semiconductor memory device according to the second embodiment of the present invention, and FIG. 21 shows the main configuration including peripheral circuits as in FIG. The second embodiment has a structure in which an operating voltage is applied between adjacent bit lines without using the plate line shown in the first embodiment.
[0100]
As shown in FIG. 20, the semiconductor memory device according to the second embodiment includes a plurality of memory capacitors C connected in series._M0, C_M1, C_M2, ..., C_M15And this storage capacitor C_M0, C_M1, C_M2, ..., C_M15Memory cell string (memory cell chain) composed of control transistors connected in parallel to each of the memory cells, and “reference cell and selection transistor (block selection transistor) Q connected to one end of the memory cell chain”_SAnd a read transistor Q having a gate electrode connected to the other end of the memory cell chain_READAre formed as basic units. Here, as already defined, the “reference cell” is a reference capacitor C_REFAnd a reference capacitor control transistor. Memory capacitor C_M0, C_M1, C_M2, ..., C_M15Each includes at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes. . Reference capacitor C_REFIncludes at least a third electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes. "Reference cell and selection transistor (block selection transistor) Q"_SThere are two combinations of the “series circuit” and the reference capacitor C_REFThe third electrode of the memory capacitor C_M0And the block selection transistor Q_SIs the storage capacitor C_M0The first electrode may be connected to the first electrode.
[0101]
In the semiconductor device according to the second embodiment, a plurality of the memory cell blocks are arranged in a matrix, but one read transistor Q_READIs divided into two sub-blocks, sub-block [A] on the right and sub-block [B] on the left. In FIG. 20, only four in total, two as sub-block [A] and two as sub-block [B] are shown. The first stage and column sub-block [A] and the second stage column sub-block [B] in FIG._REFThe third electrode of the memory capacitor C_M0Connected to the first electrode. On the other hand, the sub-block [A] in the second column and the sub-block [B] in the first column are connected to the block selection transistor Q._SIs the storage capacitor C_M0Connected to the first electrode. Capacitor C for reference in sub-block [B] in the first column_REFThe fourth electrode is connected to the bit line BL0. Reference capacitor C of sub-block [A] in the second column_REFBlock selection transistor Q of sub-block [A] of the fourth electrode of the first column and first column_SIs connected to the bit line BL1. Further, the reference capacitor C of the sub-block [B] in the second column_REFThe fourth electrode is connected to the bit line BL2.
[0102]
Block selection transistor Q in the first column of sub-block [A]_SAnd the gate electrode of the reference capacitor control transistor in the second column are respectively connected to the word line WR0.^AIs connected. Also, the gate electrode of the reference capacitor control transistor in the first column of the sub-block [A], and the block selection transistor Q in the second column._SIncludes word line WR1 respectively.^AIs connected. On the other hand, the gate electrode of the reference capacitor control transistor in the first column of the sub-block [B], and the block selection transistor Q in the second column._SIncludes word line WR0, respectively.^BIs connected. Then, the block selection transistor Q in the first column of the sub-block [B]_SAnd the gate electrode of the reference capacitor control transistor in the second column are respectively connected to the word line WR1.^BIs connected.
[0103]
Storage capacitor C of sub-block [A]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^A, WL1^A, WL2^A, ..., WL15^AIs connected. Similarly, the storage capacitor C of the sub-block [B]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^B, WL1^B, WL2^B, ..., WL15^BIs connected. Read transistor Q located at the center of sub-block [A] and sub-block [B]_READOne of the main electrodes is connected to a read power supply line VL, and the other main electrode is connected to a read output line SL. In this embodiment, two sets of read output lines SL are prepared and are connected alternately for each column. In FIG. 20, the storage capacitor C_M0, C_M1, C_M2, ..., C_M15Control transistor and readout transistor Q connected in parallel with each other_READ, Block selection transistor Q_S, And the reference capacitor control transistor is shown as an nMOSFET, but can also be configured as a pMOSFET.
[0104]
FIG. 22 shows a read / write sequence of the semiconductor memory device according to the second embodiment. The semiconductor memory according to the second embodiment of the present invention has a structure in which an operating voltage is applied between adjacent bit numbers BLx and BLx + 1 in the circuit configurations shown in FIGS. Therefore, one word line is connected to the block selection transistor Q for each column._SAnd the reference capacitor control transistor are alternately driven.
[0105]
As an example, the bit line and word line WL1 of sub-block [A]^AStorage capacitor C in the second column located at the intersection with_M1Think when you choose. Word line WR0 of sub-block [A]^AAnd WR1^ATo “1”, the reference capacitor control transistor and the block selection transistor Q in the sub-block [A] in the second column._SAre turned on (on). At the same time, the word line WR0 of the sub-block [B]^BIs “1”, and the block selection transistor Q of the sub-block [B] in the second column is_STurn on. At this time, the word line WR1 of the sub-block [B]^BOnly “0” is set. That is, only the reference capacitor control transistor in the sub-block [B] in the second column is cut off (off), and the reference capacitor C_REFSelect. This state is equivalent to the block selection transistor Q shown in FIG._SCorresponds to when ON. Next WL1^AOnly “0”, other WL^AIs “1”, and the storage capacitor C in the second column_M1Select. This state is the equivalent circuit shown in FIG. 1 or FIGS. 7A to 7C, and the storage capacitor C_MThis corresponds to the case where the control transistor connected in parallel with the switch is off. That is, a storage capacitor C including at least a first electrode, a second electrode, and a ferroelectric thin film sandwiched between the first and second electrodes._MAnd storage capacitor C_MA third electrode connected to the first electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes. Reference capacitor C provided at least_REFAnd storage capacitor C_MFirst electrode and reference capacitor C_REFRead transistor Q having a gate electrode connected to the third electrode_READAn equivalent circuit consisting of In this state, a read / write voltage may be applied between the bit lines BL1 and BL2. That is, if the bit line BL1 is set to “1” and the bit line BL2 is set to “0”, the storage capacitor C_M1And reference capacitor C_REFA voltage of “1” can be applied between them.
[0106]
At this time, a voltage is also applied between the bit lines BL0-BL1 and between the bit lines BL2-BL3, but the word line WR1.^BIs “0”, the block selection transistor Q of the sub-block [B] in the first and third columns_SIs in the off state, and storage capacitors C in the first and third columns_M1No voltage is applied to. That is, the block selection transistor Q in the upper and lower columns of the target column._SIs turned off, so that the voltage applied to the bit lines is not applied to these adjacent column blocks.
[0107]
Further, when selecting the memory cell of the sub-block [B], the reference capacitor of the sub-block [A] is selected, and the equivalent circuit shown in FIG. 1 or FIG. 7 (a) to FIG. Memory capacitor C_MIt goes without saying that the case where the control transistor connected in parallel to is turned off is realized.
[0108]
In the semiconductor memory device according to the second embodiment of the present invention, a voltage can be applied between two adjacent bit lines._CThere is an advantage that the voltage can be applied to the cell. In addition, the reference capacitor C is used for the write operation._REFThrough. Others are almost the same as those of the semiconductor memory device according to the first embodiment.
[0109]
FIG. 23A is a plan view showing a memory cell block, and for simplification, only a lower layer than the level of the A-A ′ plane in FIG. 23B is shown. In FIG. 23A, n in the first column⁺Source / drain regions 281, 21 and word line WR0^BThus, the reference capacitor control transistor of the sub-block [B] is formed. n⁺The source / drain region 281 also functions as a connection portion to the bit line BL0. n⁺The source / drain region 21 has a reference capacitor C_REFA lower electrode 66 functioning as the fourth electrode is connected. And n⁺Source / drain regions 21 and 22 and a word line WL1 serving as a polysilicon gate electrode^BThe block selection transistor Q_S1Is configured. Similarly, n⁺Source / drain regions 22 and 23 and word line WL0 serving as a polysilicon gate electrode^BAnd the storage capacitor C_M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Are connected in parallel to each other, and n⁺Source / drain regions 26 (not shown), 27 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. n⁺The source / drain regions 23 and 25 have respective storage capacitors C_M0, C_M1, C_M2, ..., C_M15The lower electrodes 42, 43,..., 44 functioning as the first electrode or the second electrode are connected. N⁺The read transistor Q is composed of the source / drain regions 31 and 32 and the polysilicon gate electrode 531._READIs formed. n⁺The source / drain regions 31 and 32 are formed in parallel to the word line and also serve as the read power supply line VL. Block selection transistor Q in the second column_S0N⁺Source / drain region 282 and n of the reference capacitor control transistor in the third column⁺The source / drain region 283 is connected to each other by a connection electrode (not shown). Although the block [B] has been mainly described, the block [A] has a similar configuration.
[0110]
As shown in FIG. 23 (a), each of the block selection transistors Q is included in the sub-block [A] or the sub-block [B] of each column._S, N storage capacitors C_M0, C_M1, C_M2, ..., C_M15N control transistors connected in parallel therewith, read transistor Q_READReference capacitor C_REF, And a reference capacitor control transistor. The size of one memory cell is 4F²The area other than the memory cell including the contact portion per sub-block is 16F.²Therefore, (4 + 16 / n) F per memory cell²become. In the semiconductor memory device according to the second embodiment, the ferroelectric capacitor is 20 μC / cm.²Therefore, it was found that even if 16 memory cells are connected in series, the device operates stably. Therefore, 5.0F per piece²It became the size of.
[0111]
FIG. 23B is a cross-sectional view along the B-B ′ direction of the plan view shown in FIG. As shown in FIG. 23B, in the semiconductor memory device according to the second embodiment of the present invention, a p-well 12 is formed on a semiconductor substrate 11, and n is formed on the surface of the p-well 12.⁺Source / drain regions 281, 21, 22, 23,..., 27 are provided. Then, a word line WR0 serving as a polysilicon gate electrode is formed on the gate oxide film on the surface of the p-well 12.^B, WR1^B, WL0^B, WL1^B, WL2^B, ..., WL15^Bhave. Note that the cross-sectional view of FIG._READThe cross section of the wiring portion of the polysilicon gate electrode 531 constituting the same is also exposed. Here, instead of these polysilicon gate electrodes, refractory metals such as W, Ti, Mo and Co, or WSi₂, TiSi₂, MoSi₂, CoSi₂A refractory metal silicide such as may be used.
[0112]
n⁺Source / drain regions 281, 21 and word line WR0^BThus, the reference capacitor control transistor of the sub-block [B] is formed. N⁺Source / drain regions 21, 22 and word line WR1^BThe block selection transistor Q_S1Is configured. n⁺Source / drain regions 22, 23 and word line WL0^BAnd the storage capacitor C_M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Control transistor connected in parallel to n⁺Source / drain regions 24, 25 and word line WL2^BAnd the storage capacitor C_M2Control transistors connected in parallel to each other,..., N⁺Source / drain regions 26 (not shown), 27 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. Also, n not exposed on the cross section in the B-B 'direction⁺The read transistor Q is composed of the source / drain regions 31 and 32 and the polysilicon gate electrode 531._READIs formed. Word line WR0^B, WR1^B, WL0^B, WL1^B, WL2^B, ..., WL15^BAn oxide film (SiO 2) is formed on the polysilicon gate electrode 531.₂Film), PSG film, BPSG film, nitride film (Si₃N₄A first interlayer insulating film 13 made of a film) is formed, and a reference capacitor C is formed on the first interlayer insulating film 13._REFLower electrode 66 functioning as the fourth electrode of each, and each storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Lower electrodes 42, 43,..., 44 functioning as the first electrode or the second electrode are formed. The lower electrodes 66, 42, 43,..., 44 are formed by contact plugs 83, 73, 75 formed so as to bury contact holes provided in the first interlayer insulating film 13.⁺The source / drain regions 21, 23, 25 are connected. These contact plugs may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. The lower electrode 66 is a reference capacitor C._REFThe lower electrode 42 is a storage capacitor C._M0Second electrode and storage capacitor C_M1It functions as the first electrode. The lower electrode 43 includes a storage capacitor C_M2Second electrode and storage capacitor C_M3It functions as the first electrode. The lower electrode 44 is a storage capacitor C_M14Second electrode and storage capacitor C_M15It functions as the first electrode. Then, ferroelectric thin films 51, 52,..., 53 such as a BS rich thin film having a Ba-rich composition may be formed on the lower electrodes 42, 43,. Reference capacitor C_REFA paraelectric thin film 55 may be formed on the lower electrode 66. Reference capacitor C_REFThe paraelectric thin film 55 may be formed. Reference capacitor C_REFParaelectric thin films can also be used. On the first interlayer insulating film 13 where the paraelectric thin film 55 and the ferroelectric thin films 51, 52,..., 53 are not formed, an oxide film (SiO₂A second interlayer insulating film 14 is formed, and upper electrodes 65, 61, 62,..., 63 are formed on the second interlayer insulating film 14. The upper electrode 65 is a reference capacitor C_REFIt functions as the fourth electrode. The upper electrode 61 includes a storage capacitor C_{M 0}It functions as the first electrode. The upper electrode 62 includes a storage capacitor C_M1Second electrode and storage capacitor C_M2It functions as the first electrode. The upper electrode 63 is a storage capacitor C_M15It functions as the second electrode. The upper electrodes 65, 61, 62,..., 63 are formed so as to bury contact holes provided through the first interlayer insulating film 13 and the second interlayer insulating film 14. 74, 77, n⁺The source / drain regions 281, 22, 24,. These contact plugs 82, 72, 74, and 77 may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. Further, the upper electrode 63 is connected to the read transistor Q via a contact plug 78 provided through the first interlayer insulating film 13 and the second interlayer insulating film 14._READThis is connected to the wiring portion 531 of the polysilicon gate electrode. On the upper electrodes 65, 61, 62, ..., 63, an oxide film (SiO₂A third interlayer insulating film 15 made of a film) is formed, and a bit line 16 is formed on the third interlayer insulating film 15. The bit line 16 and the upper electrode 65 are connected to each other by a bit line contact plug 84 that penetrates the third interlayer insulating layer 15. The bit line contact plug 84 may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. Although not shown, an oxide film (SiO 2) is further formed on the bit line 16.₂Film), PSG film, BPSG film, nitride film (Si₃N₄It is preferable to form a passivation film such as a film) or a polyimide film.
[0113]
With the circuit configuration as shown in FIG. 23B, which is a cross-sectional view corresponding to the plan view shown in FIG. 23A, the operation of the highly integrated nonvolatile memory could be confirmed.
[0114]
(Third embodiment)
FIG. 24 shows the circuit configuration of the main part of the semiconductor memory device according to the third embodiment of the present invention, and FIG. 25 shows the main part of the semiconductor memory device including the peripheral circuit in detail. In the semiconductor memory device according to the third embodiment, a pair of drive lines (DL^AAnd DL^B) Is divided into two sub-blocks centering on one read transistor.
[0115]
As shown in FIG. 24, the semiconductor memory device according to the third embodiment of the present invention includes a plurality of memory capacitors C connected in series._M0, C_M1, C_M2, C_M3, ..., C_M15And this storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Memory cell string (memory cell chain) composed of control transistors connected in parallel to each of the memory cells, and a storage capacitor C located at the end of the memory cell chain_M15Read transistor Q having a reference cell connected to the reference cell and a gate electrode connected to the reference cell_READAnd a storage capacitor C located at the other end of the storage cell chain_M0Q (block select transistor) connected to_SA memory cell block having at least the above is configured as a basic unit. Here, the “reference cell” is a reference capacitor C_REFAnd a reference capacitor control transistor. Each storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Each includes at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes. .
[0116]
Reference capacitor C_REFIs a storage capacitor C_M15A third electrode electrically coupled to the first electrode, a fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes And at least. In the semiconductor memory device of the present invention, a plurality of memory cell blocks are arranged in a matrix. In FIG. 24, only eight, four as sub-block [A] and four as sub-block [B], are shown. Block selection transistor Q of sub-block [A] in the second column_S, And block selection transistor Q of sub-block [B] in the first column_SAre connected to the bit line BL0. Similarly, the block selection transistor Q of the sub-block [A] in the second column._SAnd the block selection transistor Q of the sub-block [B] in the second column_SIs connected to the bit line BL1. Further, each of the two block selection transistors Q in the third and fourth columns._SAre respectively connected to the bit line BL2 and the bit line BL3. Block selection transistor Q of sub-block [A]_SThe main electrode not connected to the memory cell is the drive line DL^AIn addition, the block selection transistor Q of the sub-block [B]_SThe main electrode not connected to the memory cell is the drive line DL^BIt is connected to the.
[0117]
Storage capacitor C of sub-block [A]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^A, WL1^A, WL2^A, ..., WL15^AIs connected. Similarly, the storage capacitor C of the sub-block [B]_M0, C_M1, C_M2, ..., C_M15A word line WL0 is connected to each gate electrode of the control transistor connected in parallel with each other.^B, WL1^B, WL2^B, ..., WL15^BIs connected. The word electrode WR is connected to the gate electrode of the reference capacitor control transistor of the sub-block [A].^AAre connected, and the word line WR is connected to the gate electrode of the reference capacitor control transistor of the sub-block [B].^BIs connected. Read transistor Q in the first and third columns_READ ^BOne of the main electrodes has a read power supply line VL, and the other main electrode has a read output line SL.^AIs connected. On the other hand, the read transistors Q in the second and fourth columns_READ ^AOne of the main electrodes has a read power supply line VL, and the other main electrode has a read output line SL.^BIs connected. In FIG. 24, the storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Control transistor and read transistor Q connected in parallel to each other_READ ^A, Q_READ ^B, Block selection transistor Q_S, And the reference capacitor control transistor is shown as an nMOSFET, but can also be configured as a pMOSFET.
[0118]
FIG. 26 shows a read / write sequence of the semiconductor memory device according to the third embodiment of the present invention. In the semiconductor memory device according to the third embodiment of the present invention, the number of bits BLx plays a role of selecting a block along a specific column, and the application of the read / write voltage is performed on two adjacent drive lines DL.^AAnd DL^BThrough. A voltage is also applied to the block adjacent to the opposite side, but the word line WR^AOr word line WR^BIf “0” is set to “0” and the reference capacitor control transistor in the block is turned off, no problem occurs.
[0119]
Further, when selecting a memory cell of sub-block [A], a reference capacitor of sub-block [B] is selected, and when selecting a memory cell of sub-block [B], a reference capacitor of sub-block [A] is selected. Select.
[0120]
In the third embodiment, two drive lines DL^AAnd DL^BSince a voltage can be applied during_CThere is an advantage that the voltage can be applied to the cell. The rest is almost the same as in the first embodiment.
[0121]
For example, in the circuit configuration shown in FIG. 24, BL1 and WL1 in sub-block [A]^AMemory cell C in the second column specified by the intersection of_M1Is selected, the bit line BL1 is set to “1” and the block selection transistors Q of the sub-block [A] and the sub-block [B] are selected._SBoth on. Next, the word line WR^AIs “1”, and the reference capacitor C of the sub-block [A]_REFSelect. And WL1 of sub-block [A]^AOnly "0", other WL^AIf only “1” is set to “1”, the memory cell C in the second column_M1Can be selected. And memory cell C_M1With the selected, two drive lines DL^AAnd DL^BIf a voltage is applied between the readout output line SL^AThe signal can be read out.
[0122]
FIG. 27A is a plan view showing a memory cell block, and for simplification, only a lower layer than the level of the A-A ′ plane of FIG. 27B is shown. In FIG. 27A, n⁺The block selection transistor Q of the sub-block [B] is composed of the source / drain regions 321 and 22 and the polysilicon gate electrode 331._SIs configured. n⁺The source / drain region 321 functions as a connection portion with the drive line. N⁺Source / drain regions 22 and 23 and word line WL0 serving as a polysilicon gate electrode^BAnd the storage capacitor C of the sub-block [B]_M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Control transistor connected in parallel to n⁺Source / drain regions 24, 25 and word line WL2^BAnd the storage capacitor C_M2Control transistors connected in parallel to each other,..., N⁺Source / drain regions 26 (not shown), 322 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. n⁺The source / drain regions 23 and 25 have respective storage capacitors C_M0, C_M1, C_M2, C_M3, ..., C_M15The lower electrodes 42, 43,..., 44 functioning as the first electrode or the second electrode are connected. And n⁺Source / drain regions 322 and 323 and word line WR^BThus, a reference capacitor control transistor is formed. N⁺The read transistor Q is composed of the source / drain regions 324 and 325 and the polysilicon gate electrode 332._READIs formed. n⁺A read power supply line VL is connected to the source / drain region 325. The polysilicon gate electrode 334 is a capacitor control transistor Q for reading in the second column._READCorresponding to The polysilicon gate electrode 333 is connected to the block selection transistor Q in the second column._SIn addition, the polysilicon gate electrode 335 is a block selection transistor Q of the third column._SIn addition, the polysilicon gate electrode 337 is a block selection transistor Q in the fourth column._SCorresponding to The same applies to the sub-block [A].
[0123]
As shown in FIG. 27A, each of the block selection transistors Q is included in one sub-block [B]._S, N storage capacitors C_M0, C_M1, C_M2, C_M3, ..., C_M15N control transistors connected in parallel therewith, read transistor Q^B _READReference capacitor C_REF, And a reference capacitor control transistor. Memory cell size is 4F²The area other than the memory cell including the contact portion per block is 22F.²Therefore, (4 + 22 / n) F per memory cell²become. In the third embodiment, the ferroelectric capacitor is 20 μC / cm.²Therefore, it was found that even if 16 memory cells are connected in series, the device operates stably. Therefore, 5.4F per piece²It became the size of.
[0124]
FIG. 27B is a cross-sectional view along the B-B ′ direction of the plan view of the sub-block [B] shown in FIG. As shown in FIG. 27B, in the semiconductor memory device according to the third embodiment of the present invention, a p-well 12 is formed on a semiconductor substrate 11, and an n-type surface is formed on the surface of the p-well 12.⁺Source / drain regions 321, 22, 23, ..., 322, 323 are provided. A polysilicon gate electrode 331 and a word line WL0 are formed on the gate oxide film on the surface of the p well 12.^B, WL1^B, WL2^B, ..., WL15^BAnd a polysilicon gate electrode 332. N⁺Drive line DL connected to source / drain region 321^BExtends in the direction perpendicular to the page.
[0125]
n⁺The source / drain regions 321 and 22 and the polysilicon gate electrode 331 form a block selection transistor Q_SIs configured. N⁺Source / drain regions 22, 23 and word line WL0^BAnd the storage capacitor C_M0Are connected in parallel to each other. N⁺Source / drain regions 23, 24 and word line WL1^BAnd the storage capacitor C_M1Control transistor connected in parallel to n⁺Source / drain regions 24, 25 and word line WL2^BAnd the storage capacitor C_M2Control transistors connected in parallel to each other,..., N⁺Source / drain regions 26 (not shown), 322 and word line WL15^BAnd the storage capacitor C_M15Are connected in parallel to each other. And n⁺Source / drain regions 322 and 323 and word line WR^BThus, a reference capacitor control transistor is formed. Further, since it is not exposed on the cross section in the B-B 'direction, the illustration is omitted.⁺The read transistor Q is composed of the source / drain regions 324 and 325 (see FIG. 27A) and the polysilicon gate electrode 332._READIs formed. Polysilicon gate electrode 331, word line WL0^B, WL1^B, WL2^B, ..., WL15^B, WR^BOn the polysilicon gate electrode 332, an oxide film (SiO₂A first interlayer insulating film 13 made of a film) is formed, and a storage capacitor C is formed on the first interlayer insulating film 13._M0, C_M1, C_M2, C_M3, ..., C_M15Lower electrodes 42, 43,..., 44 functioning as the first electrode or the second electrode, and the reference capacitor C_REFA lower electrode 351 functioning as the fourth electrode is formed. The lower electrodes 42, 43,..., 44, 351 are n by contact plugs 73, 75, 342 formed so as to fill the contact holes provided in the first interlayer insulating film 13.⁺The source / drain regions 23, 25,. Further, the lower electrode 351 is connected to the read transistor Q via a contact plug 343 provided through the first interlayer insulating film 13._READThe polysilicon gate electrode 332 is connected. These contact plugs may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. The lower electrode 42 is a storage capacitor C._M0First electrode and storage capacitor C_M1It functions as the second electrode. The lower electrode 43 includes a storage capacitor C_M2First electrode and storage capacitor C_M3It functions as the second electrode. ... the lower electrode 44 is a storage capacitor C_M14First electrode and storage capacitor C_M15It functions as the second electrode. Then, predetermined ferroelectric thin films 51, 52,..., 53 may be formed on the lower electrodes 42, 43,. Reference capacitor C_REFA paraelectric thin film 352 may be formed on the lower electrode 351. Reference capacitor C_REFInstead of the paraelectric thin film 352, a ferroelectric thin film can be used. On the first interlayer insulating film 13 on which the ferroelectric thin films 51, 52,..., 53 and the paraelectric thin film 352 are not formed, an oxide film (SiO₂The second interlayer insulating film 14 is formed, and upper electrodes 372, 62,..., 353 are formed on the second interlayer insulating film 14. The upper electrode 372 includes a storage capacitor C_M0It functions as the second electrode. The upper electrode 62 includes a storage capacitor C_M1First electrode and storage capacitor C_M2It functions as the second electrode. ... Upper electrode 353 is a storage capacitor C_M15First electrode and reference capacitor C_REFIt functions as the third electrode. The upper electrodes 372, 62,..., 353 are formed by contact plugs 72, 74, 341 formed so as to fill contact holes provided through the first interlayer insulating film 13 and the second interlayer insulating film 14. , N⁺The source / drain regions 22, 24,. These contact plugs 72, 74, 341 may be made of doped polysilicon, refractory metal, refractory metal silicide, or the like. Further, the upper electrodes 372, 62,..., 353, the read output line SL^B, And readout output line SL^AOn top of the oxide film (SiO₂A third interlayer insulating film 15 made of a film is formed, and a bit line is formed on the third interlayer insulating film 15. Although not shown, an oxide film (SiO 2) is formed on the bit line.₂Film), PSG film, BPSG film, nitride film (Si₃N₄Of course, it is preferable to form a passivation film such as a film) or a polyimide film. Although the sub-block [B] has been mainly described, the sub-block [A] has the same configuration. With such a circuit configuration, the operation of a highly integrated nonvolatile memory could be confirmed.
[0126]
(Fourth embodiment)
FIG. 28 is a diagram showing a circuit configuration of a main part of a semiconductor memory device using a memory ferroelectric capacitor according to the fourth embodiment of the present invention. As shown in FIG. 28, the semiconductor memory device according to the fourth embodiment of the present invention includes a plurality of selection MOS transistors Q connected in series._M0, Q_M1, Q_M2, Q_M3, ..., Q_M15And a plurality of memory ferroelectric capacitors C connected to the common main electrode of these selection transistors._M0, C_M1, C_M2, C_M3, ..., C_M15A NAND-type memory cell column and a selection transistor Q located at the end of the memory cell column_M0Reference capacitor C connected to the main electrode of_REFAnd transistor Q for selection_M0And reference capacitor C_REFStorage node N that is the connection point_SRead transistor Q having a gate electrode connected to_READAnd storage node N_SR / W control transistor Q connected to_{R / W}A memory cell block having at least the above is configured as a basic unit.
[0127]
Each storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Respectively, a first electrode connected to the common main electrode of the selection transistor, a second electrode disposed opposite to the first electrode and connected to the plate electrode, and these first and second electrodes And a ferroelectric thin film sandwiched between the electrodes. Reference capacitor C_REFIs storage node N_SA third electrode connected to the third electrode, a fourth electrode disposed opposite to the third electrode and connected to the plate electrode PL, and a dielectric thin film sandwiched between the third and fourth electrodes At least. Also, the R / W control transistor Q_{R / W}One main electrode of the storage node N_SThe other main electrode is connected to the bit line BL.
[0128]
A plurality of NAND memory cell columns are arranged in a matrix, but one reference capacitor C_REF, This read transistor Q_READ,and
Control transistor Q_{R / W}Is divided into two sub-blocks, sub-block [A] on the right and sub-block [B] on the left. In FIG. 28, only two of the blocks [A] and two of the sub-blocks [B] are shown.
[0129]
Selection transistor Q of sub-block [A]_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The word line WL0 is connected to each gate electrode of^A, WL1^A, WL2^A, WL3^A, ..., WL15^AIs connected. Similarly, the selection transistor Q of the sub-block [B]_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The word line WL0 is connected to each gate of^B, WL1^B, WL2^B, WL3^B, ..., WL15^BIs connected. Read transistor Q of each memory cell block_READOne of the main electrodes is connected to a read power supply line VL, and the other main electrode is connected to a read output line SL. R / W control transistor Q for each memory cell block_{R / W}The word line RL of the R / W control transistor is connected to the gate electrode.
[0130]
FIG. 29 shows a connection diagram of peripheral circuits. Each word line WL0A, WL1A, WL2A, WL3A,..., WL15A in the sub-block [A] is supplied to the row decoder A, and each word line WL0B, WL1B, WL2B, WL3B,. To the decoder B, the bit lines BL0, BL1,... Are connected to a column decoder.
[0131]
In the circuit configuration shown in FIGS. 28 and 29, a desired memory cell indicated by the intersection of BLx (x = 0, 1) and WLyA (y = 0, 1, 2,..., 15) in sub-block [A]. Is selected, all word lines from WL0A to WLyA are set to “1 (high level)”._M0To Q_MyAll the selection transistors up to are turned on, the word line WLy + 1A is set to “0 (low level)”, the selection transistor Qmy + 1 is turned off, and the potential is constant (for example, 1 / V_CThis is achieved by applying a potential to BLx with respect to the plate line PL in C). Similarly, in order to select a desired memory cell indicated by the intersection of BLx (x = 0, 1) and WLyB (y = 0, 1, 2,..., 15) in sub-block [B], from WL0B All word lines up to WLyB are set to “1 (high level)”._M0To Q_MyAll the selection transistors up to are turned on, the word line WLy + 1B is set to “0 (low level)”, the selection transistor Qmy + 1 is turned off, and the potential is constant (for example, 1/2 V)_GThis is achieved by applying a potential to BLx with respect to the plate line PL).
[0132]
FIG. 30 shows a read / write sequence when the “precharge combined read / direct write method” is adopted. First, in the precharge combined readout method, WL0^ATo WLy^AOr WL0^BTo WLy^BR / W control transistor Q before selecting_{R / W}Is turned on, and the reference capacitor C is applied to the plate line PL having a constant potential._REFPrecharge is performed by applying a reverse voltage to. Thereafter, the transistor Q for R / W control_{R / W}Off, WL0^ATo WLy^AOr WL0^BTo WLy^BAfter selecting the above, by applying a positive voltage, the storage capacitor C_MyThe voltage is substantially inverted by applying a voltage about twice as high.
[0133]
Next, the storage capacitor C_MyFirst, the R / W control transistor Q is written to_{R / W}Is turned on, a write voltage is applied to the bit line BL, and WL0^ATo WLy^AOr WL0^BTo WLy^BBy selecting up to, the storage capacitor C_MyThe voltage is directly applied to the inversion.
[0134]
FIG. 31A is a plan view of the fourth embodiment of the present invention, and shows only a lower layer than the level A-A ′ in the cross-sectional view shown in FIG. In one block connected to the bit line, two sub-blocks having 16 storage cells, read transistor Q_READ,and
Control transistor Q_{R / W}Is included. Memory cell size is 4F²The area other than the memory cells per block is 26F.²Therefore, (4 + 26/32) F per memory cell²become. In this embodiment, the ferroelectric capacitor is 20 μC / cm.²It was found that even if 32 memory cells were connected in series, the device with stable remanent polarization was used. Therefore, 4.8F per piece²It became the size of.
[0135]
FIG. 31B is a cross-sectional view taken along B-B ′ in the plan view of FIG. An nMOS transistor is formed on a silicon substrate. Each selection transistor Q_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The main electrode region of the capacitor C includes a lower electrode LE, an upper electrode TE, and a ferroelectric film._M0, C_M1, C_M2, C_M3, ..., C_M15Is formed. The selection transistor Q at the end of the NAND cell memory column_M0Similarly, on the other main electrode, a reference capacitor C_REFIs formed. With such a circuit configuration, the operation of a highly integrated nonvolatile memory could be confirmed.
[0136]
(Fifth embodiment)
FIG. 32 shows a circuit configuration of a main part of a semiconductor memory device using a paraelectric storage capacitor according to the fifth embodiment of the present invention. FIG. 33 shows a main part of the semiconductor memory device including a peripheral circuit. It is a figure shown in detail. As shown in FIG. 32, the semiconductor memory device according to the fifth embodiment of the present invention includes a plurality of selection MOS transistors Q connected in series._M0, Q_M1, Q_M2, Q_M3, ..., Q_M15And a plurality of memory ferroelectric capacitors C connected to the common main electrode of these selection transistors._M0, C_M1, C_M2, C_M3, ..., C_M15A NAND-type memory cell column and a selection transistor Q located at the end of the memory cell column_M0Reference capacitor C connected to the main electrode of_REFAnd transistor Q for selection_M0And reference capacitor C_REFStorage node N that is the connection point_SRead transistor Q having a gate electrode connected to_READAnd storage node N_STwo R / W control transistors Q connected to_{R / W1}And Q_{R / W2}A memory cell block having at least the above is configured as a basic unit.
[0137]
Each storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15Respectively, a first electrode connected to the common main electrode of the selection transistor, a second electrode disposed opposite to the first electrode and connected to the plate electrode, and these first and second electrodes And a ferroelectric thin film sandwiched between the electrodes. Reference capacitor C_REFIs interposed between the third electrode connected to the storage node NS, the fourth electrode connected to the third electrode and connected to the bit line BL, and the third and fourth electrodes. And at least a dielectric thin film. The first R / W control transistor Q_{R / W1}One main electrode of the storage node N_SThe other main electrode is connected to the bit line BL. Second R / W control transistor Q_{R / W2}One main electrode of the storage node N_SThe other main electrode is connected to the plate electrode PE.
[0138]
A plurality of NAND memory cell columns are arranged in a matrix, but one reference capacitor C_REFRead transistor Q_READ, And two R / W control transistors Q_{R / W1}And Q_{R / W2}Is divided into two sub-blocks, sub-block [A] on the right and sub-block [B] on the left. In FIG. 32, only two of the blocks [A] and two of the sub-blocks [B] are shown.
[0139]
Selection transistor Q of sub-block [A]_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The word line WL0 is connected to each gate electrode of^A, WL1^A, WL2^A, WL3^A, ..., WL15^AIs connected. Similarly, the selection transistor Q of the sub-block [B]_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The word line WL0 is connected to each gate electrode of^B, WL1^B, WL2^B, WL3^B, ..., WL15^BIs connected. Read transistor Q of each memory cell block_READOne of the main electrodes has a read power supply line VL, and the other main electrode has a read output line SL.^AOr SL^BIs connected. Two R / W control transistors Q in each memory cell block_{R / W1}And Q_{R / W2}The R / W control transistor word line RL is connected to the gate electrode of₁And RL₂Is connected. FIG. 32, the selection transistor Q_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15Read transistor Q_READ, And two R / W control transistors Q_{R / W1}And Q_{R / W2}Is shown as an nMOSFET, but it can also be constituted by a pMOSFET.
[0140]
FIG. 33 shows a connection diagram of peripheral circuits. Each word line WL0 of sub-block [A]^A, WL1^A, WL2^A, WL3^A, ..., WL^15AThe row decoder A supplies each word line WL0 of the sub-block [B].^B, WL1^B, WL2^B, WL3^B, ..., WL15^BAre connected to a row decoder B, and each bit line BL0, BL1,... Is connected to a column decoder.
[0141]
In the circuit configurations shown in FIGS. 32 and 33, BLx (x = 0, 1) and WLy in sub-block [A]^ATo select a desired memory cell indicated by the intersection of (y = 0, 1, 2,..., 15), WL0^ATo WLy^AQ for all the word lines up to "1 (high level)"_M0To Q_MyAll the transistors for selection up to are turned on, word line WLy + 1^ASelect transistor Q with "0 (low level)"_{my + 1}Is turned off and the potential is constant (for example, 1 / 2V_GThis is achieved by applying a potential to BLx with respect to the plate line PL).
[0142]
FIG. 34 further shows a read / write sequence when the “precharge read / direct write method” is employed. That is, in the precharge readout method, WLy^AOr WLy^BBefore selecting the second R / W control transistor Q_{R / W2}Is turned on, and the reference capacitor C is applied to the plate line PL having a constant potential._REFAnd WL0 before the cell to be selected^ATo WLy-1^AOr WL0^BTo WLy-1^BPrecharge is performed by applying a voltage. Thereafter, the transistor Q for R / W control_{R / W}Off, WLy^AOr WLy^BTo select the storage capacitor C_MyIt reads out the charge. Memory capacitor C_MyFirst, the first R / W control transistor Q is written to_{R / W1}Is turned on to supply a write voltage to the bit line BL, and WL0^ATo WLy-1^AOr WL0^BTo WLy-1^BSelect until. Therefore, the storage capacitor C_MyInvert by applying a voltage directly to.
[0143]
FIG. 35A is a plan view of the fifth embodiment of the present invention, and only the lower layer than the level of A-A ′ in the cross-sectional view shown in FIG. In one block connected to the bit line, two sub-blocks each having eight memory cells are read transistor Q._READ, And two R / W control transistors Q_{R / W1}And Q_{R / W2}Is included. Memory cell size is 4F²The area other than the memory cells per block is 22F²Therefore, (4 + 22/16) F per memory cell²become. In this example, the paraelectric capacitor is 20 mF / cm.²Therefore, it was found that even when 16 memory cells are connected in series, the device operates stably. Therefore, 5.4F per piece²It became the size of.
[0144]
FIG. 35B is a cross-sectional view taken along B-B ′ of the plan view of FIG. An nMOS transistor is formed on a silicon substrate. Each selection transistor Q_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15The main electrode region includes a lower electrode LE, an upper electrode TE, and a storage capacitor C made of a ferroelectric film._M0, C_M1, C_M2, C_M3, ..., C_M15Is formed. The selection transistor Q at the end of the NAND cell memory column_M0Similarly, on the other main electrode of FIG._REFIs formed. With such a circuit configuration, the operation of a highly integrated semiconductor memory was confirmed.
[0145]
(Sixth embodiment)
36A to 36D are schematic cross-sectional views in order of steps of the Chain type semiconductor memory device according to the sixth embodiment of the present invention. In each figure, reference numeral 1 is a first conductive type semiconductor substrate, 2 is a second conductive type impurity diffusion layer, 3 is an inter-element isolation insulating film, 4 is a gate oxide film, 5 is a word line, and 6 is a single crystal Si epitaxial growth layer. 7, 8 and 9 are insulating films, 11 and 15 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 23 is an internal wiring, and 24 is a via plug.
[0146]
First, in FIG. 36A, after the transistor portion of the memory cell is formed by a known process, the single crystal Si layer 6 is selectively epitaxially grown and planarized by a chemical mechanical polishing (CMP) method. . At this time, a silicon oxide film was used as the insulating film of the word line 5. In addition, in order to remove a damaged layer on the surface of the electrode on the Si substrate caused by the RIE process, after etching using hydrogen fluoride vapor, the electrode is directly transferred to a CVD chamber in a vacuum and SiH having a pressure of 1 mTorr.₄0.1 mTorr AsH added as gas and donor₃Selective epitaxial growth was performed at 750 ° C. using a gas.
[0147]
Next, as shown in FIG. 36 (b), in order to remove the damaged layer on the surface of the single crystal Si layer 6 generated in the CMP (Chemical and Mechanical Polishing) process, after etching using hydrogen fluoride vapor, a barrier is formed. TiN is laminated as a metal 11 at 600 ° C. by a reactive sputtering method, and subsequently SrTiO 2 is sputtered at 600 ° C. as a lower electrode 12 by a sputtering method._ThreeLaminate a film (hereinafter abbreviated as SRO) and continue BaTiO_ThreeA ferroelectric thin film 13 (hereinafter abbreviated as BTO) is laminated by sputtering to a thickness of 40 nm at 600 ° C., and subsequently as the upper electrode 14, SrTiO 3 is sputtered at 600 ° C. by sputtering._ThreeA film (hereinafter abbreviated as SRO) is laminated, and TiN is subsequently laminated as a barrier metal 15 at 600 ° C. by reactive sputtering. At this time, all of the barrier metal 11, the lower electrode 12, the ferroelectric thin film 13, and the upper electrode 14 were epitaxially grown on the single crystal Si layer 6 to be single crystal.
[0148]
Next, as shown in FIG. 36C, the barrier metal 11, the lower electrode 12, the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the single layer are formed by known lithography and RIE (Reactive Ion Etching) methods. The crystalline Si layer 6 was patterned. Next, the silicon oxide insulating film 7 was conformally formed by plasma CVD using TEOS as a source gas, and the insulating film sidewall of the capacitor was formed by anisotropic etching. Next, a via plug 24 made of tungsten (W) was embedded by a CVD (Chemical Vapor Deposition) method, and planarization was performed by a CMP method using the barrier metal 15 as a stopper.
[0149]
Next, as shown in FIG. 36 (d), an internal wiring 23 made of W is formed by sputtering, and the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the internal are formed by known lithography and RIE. The wiring 23 was patterned. Next, the silicon oxide insulating film 8 was embedded by a plasma CVD method using TEOS as a source gas, and planarized by a CMP method using the internal wiring 23 as a stopper. Further, an interlayer insulating film 9 was formed.
[0150]
After the film was prepared by such a process, the film orientation was measured by an X-ray diffractometer, and it was confirmed that all of the TiN barrier film, the SRO electrode film, and the BTO dielectric film were epitaxially grown in the (001) direction. The lattice constant in the film thickness direction of the BTO film was greatly extended to 0.434 nm. Further, when the dielectric properties of the formed ferroelectric thin film capacitor were measured, the residual polarization quantity was 0.42 C / m.²A large value was obtained, confirming that it functions as a ferroelectric capacitor.
[0151]
(Seventh embodiment)
FIGS. 37A to 37C and FIGS. 38D and 38E are schematic cross-sectional views in order of steps of the Chain type semiconductor memory device according to the seventh embodiment of the present invention. Reference numeral 1 is a first conductive type semiconductor substrate, 2 is a second conductive type impurity diffusion layer, 5 is a word line, 6 is a single crystal Si epitaxial growth layer, 7, 8, 9, and 10 are insulating films, and 11 is a lower barrier metal film. , 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 15 is an upper barrier metal film, 20 is a plate electrode, 21 is a single-crystal Si growth node, 22 is a capacitor contact portion, and 23 is an internal wiring. is there.
[0152]
First, as shown in FIG. 37A, after the plate electrode 20 made of the second conductive type impurity diffusion layer having a depth of about 0.1 μm is formed on the surface of the first conductive type Si (100) substrate 1. Then, (Ti, Al) N having a thickness of 10 nm as the lower barrier metal layer 11 and SRO having a thickness of 20 nm as the lower electrode 12 are continuously grown epitaxially at a substrate temperature of 600 ° C. without being exposed to the atmosphere by RF or DC sputtering. did. Next, patterning is performed until the substrate 1 is reached by etching using lithography and RIE, etc., the inter-element isolation insulating film 3 is buried by plasma CVD using TEOS gas as a raw material, and planarized by CMP using the lower electrode as a stopper. did. Next, after removing the damaged layer caused by the flattening of the lower electrode surface by wet etching or the like, the dielectric film 13 is formed of BaTiO with a thickness of 20 nm._ThreeA thin film, an SRO film having a thickness of 20 nm as the upper electrode 14, and (Ti, Al) N having a thickness of 10 nm as the upper barrier metal layer 15 are continuously formed at a substrate temperature of 600 ° C. without being exposed to the atmosphere by RE or DC sputtering. Then, the first insulating film 7 was formed by a plasma CVD method using TEOS gas as a raw material.
[0153]
Next, as shown in FIG. 37B, the single-crystal Si growth node 21 was formed by etching using lithography and RIE. Next, the second insulating film 8 was formed conformally. Next, by leaving the first insulating film 7 and removing the second insulating film 8 by anisotropic RIE, the insulating film was also left by self-alignment on the side wall portion of the single crystal Si growth node. Next, in order to remove a damaged layer on the Si surface, after etching using hydrogen fluoride vapor, it is directly transferred to a CVD chamber in a vacuum, and SiH having a pressure of 1 mTorr is used.₄0.1 mTorr AsH added as gas and donor₃The single crystal Si layer 6 was formed by selective epitaxial growth from the single crystal Si growth node 21 at 750 ° C. using a gas. Next, the first insulating film 7 was used as a stop layer and planarized by a CMP method (chemical mechanical polishing method).
[0154]
Next, as shown in FIG. 37 (c), the capacitor is patterned using plasma etching such as photolithography and RIE to form a contact hole 26 to the upper electrode, and then photolithography and RIE. The capacitor was patterned using plasma etching or the like to form a contact hole 27 to the upper electrode, and the insulating film 9 was conformally formed. Next, the insulating film 9 was removed by anisotropic RIE while leaving the first insulating film 7, thereby leaving the insulating film on the side wall portion by self-alignment. Next, via plugs 24 and 25 made of tungsten (W) were embedded by CVD, and planarization was performed by CMP using the first insulating film 7 as a stopper.
[0155]
Next, as shown in FIG. 38 (d), a transistor including the impurity diffusion layer 2, the gate oxide film (not shown), and the word line 5 was formed using a known process.
[0156]
Next, as shown in FIG. 38 (e), for example, a poly-Si film containing an N + type impurity is deposited with a film thickness of about 200 nm, and patterning is performed using plasma etching such as photolithography and RIE. Thus, the internal wiring 23 for connecting the via plugs 24 to 25 and the main electrode of the transistor was formed.
[0157]
Through such a process, a chain type memory cell composed of a capacitor and a transistor using a ferroelectric film can be formed, and the operation as an FRAM was confirmed.
[0158]
(Eighth embodiment)
Next, a semiconductor memory device according to an eighth embodiment of the invention will be described with reference to the schematic cross-sectional views in the order of steps shown in FIGS. 39 (a) to 39 (c) and FIGS. 40 (d) (e). In each figure, reference numeral 1 is a first conductivity type semiconductor substrate, 2 is a second conductivity type impurity diffusion layer, 3 is an inter-element isolation insulating layer, 4 is a gate oxide film, 5 is a word line, and 6 is a single crystal Si epitaxial growth layer. 7, 8 are insulating films, 11 and 15 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 20 is a plate electrode, 30 is a contact plug, 31 is a first bonding layer, 32 is a second Si (100) substrate, and 33 is a bonding layer.
[0159]
First, as shown in FIG. 39A, a transistor or element including the impurity diffusion layer 2, the gate oxide film 4, and the word line 5 is formed on the first Si (100) substrate 1 using a known process. An inter-insulating insulating film 3 and a contact plug 30 with a capacitor were formed and planarized by a method such as chemical mechanical polishing (CMP). Next, an Al film was formed on the entire surface as the first bonding layer 31.
[0160]
Next, as shown in FIG. 39B, SrRuO having a thickness of 10 nm (Ti, Al) N as the lower barrier metal layer 11 and a thickness of 20 nm as the lower electrode 12 is formed on the second Si (100) substrate 32._ThreeThe dielectric film 13 is a BSTO thin film having a mole fraction of Ba of 70% and a thickness of 20 nm, and the upper electrode 14 is SrRuO having a thickness of 20 nm._ThreeA (Ti, Al) N film having a thickness of 10 nm was continuously epitaxially grown as an upper barrier metal layer 15 at a substrate temperature of 600 ° C. without being exposed to the atmosphere by RF or DC sputtering. Next, an Al film was formed on the entire surface as the second bonding layer 33.
[0161]
Next, as shown in FIG. 39C, the first bonding layer and the second bonding layer are made to have a degree of vacuum of 3 × 10.^-8The first bonded layer and the second bonded layer are removed without removing the oxidized layer formed on the surface by sputtering of Ar gas in an ultra-high vacuum of Torr or higher to expose a new Al surface. Were pressed and bonded at 400 ° C. for 30 minutes.
[0162]
Next, as shown in FIG. 40D, the bonded second substrate was polished from the back surface by CMP or the like to leave a capacitor layer and an Si layer of about 0.2 μm. Thereafter, alignment was performed using the first substrate, and capacitors were patterned for each memory cell. As an etching condition at this time, an oxide layer may be used as an etching stop layer. Next, the insulating film 7 was formed conformally. Next, the insulating film 7 was removed by anisotropic RIE to leave the insulating film on the capacitor side wall portion by self-alignment. Next, for example, N⁺A via plug 24 was formed by embedding a poly-Si film containing a type impurity in a thickness of about 200 nm and planarizing by a CMP method using the Si layer 32 as a stopper.
[0163]
Next, as shown in FIG. 30E, the internal wiring 23 made of TiN is formed by sputtering, and the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the internal are formed by known lithography and RIE. The wiring 23 was patterned. Next, the silicon oxide insulating film 8 was buried by plasma CVD using TEOS as a source gas, planarized by CMP using the internal wiring 23 as a stopper, and an interlayer insulating film 9 was formed.
[0164]
Through such a process, a memory cell including a capacitor and a transistor using a ferroelectric film can be formed with a high yield, and the operation as an FRAM was confirmed.
[0165]
(Ninth embodiment)
41A to 41C are schematic cross-sectional views in order of the processes of the NAND cell in the semiconductor memory device according to the ninth embodiment of the present invention. In each figure, reference numeral 1 is a first conductive type semiconductor substrate, 2 is a second conductive type impurity diffusion layer, 3 is an inter-element isolation insulating film, 4 is a gate oxide film, 5 is a word line, and 6 is a single crystal Si epitaxial growth layer. 7, 8 and 9 are insulating films, 11 and 14 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, and 20 is a plate electrode.
[0166]
In FIG. 41A, after the transistor portion of the memory cell is formed by a known process, the single crystal Si layer 6 is selectively epitaxially grown and planarized by a chemical mechanical polishing (CMP) method. At this time, a silicon oxide film was used as the insulating film of the word line 5. In addition, in order to remove a damaged layer on the surface of the electrode on the Si substrate caused by the RIE process, after etching using hydrogen fluoride vapor, the electrode is directly transferred to a CVD chamber in a vacuum and SiH having a pressure of 1 mTorr.₄0.1 mTorr AsH added as gas and donor₃Selective epitaxial growth was performed at 750 ° C. using a gas.
[0167]
Next, as shown in FIG. 41B, in order to remove a damaged layer on the surface of the single crystal Si layer 6 generated in the CMP process, reactive sputtering as a barrier metal 11 is performed after etching using hydrogen fluoride vapor. TiN is laminated at 600 ° C. by the method, and subsequently SrTiO 2 is sputtered at 600 ° C. by sputtering as the lower electrode 12._ThreeLaminate a film (hereinafter abbreviated as SRO) and continue BaTiO_ThreeA ferroelectric thin film 13 (hereinafter abbreviated as BTO) is laminated to a thickness of 40 nm at 600 ° C. by a sputtering method, and subsequently SrTiO 2 is sputtered at 600 ° C. by a sputtering method as the upper electrode 14._ThreeA film (hereinafter abbreviated as SRO) is laminated, and TiN is subsequently laminated as a barrier metal 15 at 600 ° C. by reactive sputtering. At this time, all of the barrier metal 11, the lower electrode 12, the ferroelectric thin film 13, and the upper electrode 14 are epitaxially grown on the single crystal Si layer 6 to form a single crystal. All of them grew as polycrystals.
[0168]
Next, as shown in FIG. 41C, the barrier metal 11, the lower electrode 12, the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the single crystal Si layer 6 are formed by known lithography and RIE methods. Patterning was performed. At this time, the insulating film was used as a stopper. The silicon oxide insulating film 7 was buried in the patterned trench by plasma CVD using TEOS as a source gas, and planarized by CMP using barrier metal 15 as a stopper. Thereafter, TiN was laminated as a plate electrode 20 by sputtering, and an interlayer insulating film 8 was formed.
[0169]
After the film was prepared by such a process, the film orientation was measured by an X-ray diffractometer, and it was confirmed that all of the TiN barrier film, the SRO electrode film, and the BTO dielectric film were epitaxially grown in the (001) direction. The lattice constant in the film thickness direction of the BTO film was greatly extended to 0.434 nm. Further, when the dielectric properties of the formed ferroelectric thin film capacitor were measured, the residual polarization quantity was 0.42 C / m.²It was confirmed that it functions as a ferroelectric capacitor.
[0170]
(10th Embodiment)
42 (a) to (c) and FIGS. 43 (d) to (f) are schematic cross-sectional views in order of the processes of the NAND cell in the semiconductor memory device according to the tenth embodiment of the present invention. A paraelectric capacitor was created as a storage capacitor. In each figure, reference numeral 1 is a first conductivity type semiconductor substrate, 2 is a second conductivity type impurity diffusion layer, 5 is a word line, 6 is a single crystal Si epitaxial growth layer, 7, 8, 9, 10 are insulating films, 11 is Lower barrier metal, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 15 is an upper barrier metal film, 20 is a plate electrode, 21 is a single crystal Si growth node, 22 is a capacitor contact portion, and 23 is a capacitor contact portion. Internal wiring.
[0171]
First, as shown in FIG. 42A, after the plate electrode 20 made of the second conductivity type impurity diffusion layer having a depth of about 0.1 μm is formed on the surface of the first conductivity type Si (100) substrate 1. The lower barrier metal layer 11 has a thickness of (Ti, Al) N, the lower electrode 12 has a thickness of 20 nm SRO, and the dielectric film 13 has a thickness of 20 nm (Ba_0.2Sr_0.8) TiO_ThreeA thin film, an SRO film having a thickness of 20 nm as the upper electrode 14, and a (Ti, Al) N film having a thickness of 10 nm as the upper barrier metal layer 15 are continuously formed at a substrate temperature of 600 ° C. without being exposed to the atmosphere by RF or DC sputtering. Then, the first insulating film 7 was formed by a plasma CVD method using TEOS gas as a raw material.
[0172]
Next, as shown in FIG. 42B, the single-crystal Si growth node 21 was formed by etching using lithography and RIE. Next, the second insulating film 8 was formed conformally.
[0173]
Next, as shown in FIG. 42C, the first insulating film 7 is left and the second insulating film 8 is removed by anisotropic RIE, so that the sidewall of the single crystal Si growth node is formed. Also left the insulating film by self-alignment. Next, in order to remove a damaged layer on the Si surface, after etching using hydrogen fluoride vapor, it is directly transferred to a CVD chamber in a vacuum, and SiH having a pressure of 1 mTorr is used.₄0.1 mTorr AsH added as gas and donor₃The single crystal Si layer 6 was formed by selective epitaxial growth from the single crystal Si growth node 21 at 750 ° C. using a gas. Next, the insulating film was used as a stop layer and planarized by CMP (chemical mechanical polishing).
[0174]
Next, as shown in FIG. 43 (d), the capacitor is patterned using plasma etching such as photolithography and RIE, an insulating film is buried, and planarized by CMP to form a capacitor isolation insulating film 9. did.
[0175]
Next, as shown in FIG. 43E, a transistor including the impurity diffusion layer 2, the gate oxide film (not shown), and the word line 5 is formed using a known process.
[0176]
Next, as shown in FIG. 43 (f), the contact portion 22 of the capacitor was opened using plasma etching such as photolithography and RIE. As an etching condition at this time, any one of the upper barrier metal layer 15 to the upper electrode 14 may be used as a stopper and selectively stopped. Next, for example, N⁺A poly-Si film containing a type impurity was deposited to a thickness of about 200 nm, and the entire surface was etched by a method such as CMP and RIE, thereby forming an internal wiring 23 connecting the contact portion 22 and the main electrode of the transistor. Further, an interlayer insulating film 10 was formed.
[0177]
Through such a process, a NAND type memory cell composed of a capacitor and a transistor using a ferroelectric film can be formed, and the operation as a NAND type FRAM was confirmed.
[0178]
(Eleventh embodiment)
A semiconductor memory device according to an eleventh embodiment of the present invention will be described with reference to FIGS. 44A to 44C and FIGS. Reference numeral 1 is a first conductive type semiconductor substrate, 2 is a second conductive type impurity diffusion layer, 3 is an inter-element isolation insulating layer, 4 is a gate oxide film, 5 is a word line, 6 is a single crystal Si epitaxial growth layer, 7 and 8 Is an insulating film, 11 and 14 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 20 is a plate electrode, 30 is a contact plug, 31 is a first bonding layer, and 32 is a second layer. The Si (100) substrate 33 is a second bonding layer.
[0179]
First, as shown in FIG. 44 (a), a transistor or element including the impurity diffusion layer 2, the gate oxide film 4, and the word line 5 is formed on the first Si (100) substrate 1 using a known process. An inter-insulating insulating film 3 and a contact plug 30 with a capacitor were formed and planarized by a method such as chemical mechanical polishing (CMP). Next, an Al film was formed on the entire surface as the first bonding layer 31.
[0180]
Next, as shown in FIG. 44B, SrRuO having a thickness of 10 nm (Ti, Al) N as the lower barrier metal layer 11 and a thickness of 20 nm as the lower electrode 12 is formed on the second Si (100) substrate 32._ThreeThe dielectric film 13 is a BSTO thin film having a mole fraction of Ba of 70% and a thickness of 20 nm, and the upper electrode 14 is SrRuO having a thickness of 20 nm._ThreeA (Ti, Al) N film having a thickness of 10 nm was continuously epitaxially grown as an upper barrier metal layer 15 at a substrate temperature of 600 ° C. without being exposed to the atmosphere by RF or DC sputtering. Next, an Al film was formed on the entire surface as the second bonding layer 33.
[0181]
Next, as shown in FIG. 44 (c), the first bonding layer and the second bonding layer are made to have a degree of vacuum of 3 × 10.^-8The first bonded layer and the second bonded layer are removed without removing the oxide layer formed on the surface by sputtering of Ar gas in an ultra-high vacuum of Torr or higher to expose a new Al surface. Were joined together by pressurizing at 400 ° C. for 30 minutes.
[0182]
Next, as shown in FIG. 45 (d), the bonded second substrate was polished from the back surface by CMP or the like to leave a capacitor layer and an Si layer of about 0.2 μm. Thereafter, alignment was performed using the first substrate, and capacitors were patterned for each memory cell. As an etching condition at this time, an oxide layer may be used as an etching stop layer. Furthermore, after the insulating film 7 was embedded by the plasma CVD method using TEOS gas as a raw material, it was planarized again by the CMP method or the like.
[0183]
Finally, as shown in FIG. 45E, a Ti / TiN / Al layer was formed as the plate electrode 20, and then the insulating layer 8 was covered.
[0184]
Through such a process, a memory cell including a capacitor and a transistor using a ferroelectric film can be formed with a high yield, and the operation as an FRAM was confirmed.
[0185]
(Twelfth embodiment)
46A, 46B and 47C, 47D are schematic cross-sectional views in order of the processes of the NAND cell according to the twelfth embodiment of the present invention. 1 is a first conductivity type semiconductor substrate, 2 is a second conductivity type impurity diffusion layer, 3 is an inter-element isolation insulating layer, 4 is a gate oxide film, 5 is a word line, 6 is a single crystal Si layer, 7, 8, 9 Is an insulating film, 11 is a first barrier metal, 12 is a first electrode, 13 is a dielectric thin film, 14 is a second electrode, 15 is a second barrier metal layer, 20 is a plate electrode, and 30 is a contact plug. , 31 is a first bonding layer, 32 is a second Si (100) substrate, and 33 is a second bonding layer.
[0186]
First, as shown in FIG. 46A, a 10 nm-thick (Ti, Al) N film as the first barrier metal 11 is formed on the first surface of the first conductivity type Si (100) substrate 1. The first electrode 12 has an SRO film with a thickness of 20 nm, the ferroelectric film 13 has a BaTO thin film with a mole fraction of 70% and a thickness of 20 nm, the second electrode 14 has an SRO film with a thickness of 20 nm, and a second barrier metal. A TiN film having a thickness of 10 nm was epitaxially grown as the layer 15 at a substrate temperature of 600 ° C. by RF or DC sputtering, respectively. Further, a TiN film having a thickness of 200 nm was formed as the plate electrode 20 at room temperature. Next, after a BPSG film having a thickness of, for example, about 500 nm was formed as the first bonding insulating film 31, it was planarized by, eg, CMP.
[0187]
Next, a second Si substrate 32 was prepared, and a BPSG layer was formed as a second bonding layer 33 on the surface and planarized. Next, the first bonding insulating film 31 and the second bonding layer 33 were abutted and bonded. Adhesion was performed by a known method, for example, heat treatment at about 900 ° C.
[0188]
Next, as shown in FIG. 46 (b), it is assumed that the polishing is performed from the second surface of the first Si substrate 1, and the description thereof is omitted. A thin silicon layer having a thickness of, for example, about 10 nm is formed using a polishing stopper layer around the cell region. Other methods for forming SOI by bonding or polishing such as smart cut may also be used.
[0189]
Next, a trench for element isolation was opened using plasma etching such as normal photolithography and RIE. As an etching condition at this time, it is preferable to selectively stop using the capacitor dielectric film 13 as a stopper. Next, a buried insulating film 7 was formed and planarized by CMP. Further, after selectively etching the buried insulating film 7 shallowly by RIE or the like, the second conductivity type single crystal silicon layer 6 is formed and planarized again. Examples thereof include a method of forming a silicon layer conformally and then crystallizing from a side wall portion by heat treatment such as RTP to form a single crystal, a method of selectively embedding single crystal silicon by a selective growth CVD method, and the like.
[0190]
Next, as shown in FIG. 47C, a second groove for separating elements was formed by etching using lithography and RIE. At this time, the dielectric film 5 of the capacitor may be used as an etching stop layer. Next, a buried insulating film 8 was formed and planarized by CMP or the like.
[0191]
Finally, as shown in FIG. 47 (d), a transistor including the second conductivity type impurity diffusion layer 2, the gate oxide film 4, and the word line 5 and the interlayer insulating film 9 are formed using a known process. did.
[0192]
Through such a process, a memory cell including a capacitor and a transistor using a ferroelectric film can be formed with a high yield, and the operation as an FRAM was confirmed.
[0193]
(Other embodiments)
As described above, the present invention has been described according to the first to twelfth embodiments. However, it should not be understood that the description and the drawings, which are a part of this disclosure, limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0194]
In the description of the first to twelfth embodiments already described, the nMOSFET is formed in the p well, but the nMOSFET may be formed in the p substrate. Moreover, you may comprise using pMOSFET instead of nMOSFET. When a pMOSFET is used, the polarity of the read / write sequence shown in FIG. 18, FIG. 22, or FIG.
[0195]
Needless to say, the semiconductor memory devices according to the first to 123rd embodiments already described may be formed on an SOI substrate. Further, in FIG. 27B, the bit line is not exposed because it is not exposed on the cross section in the BB ′ direction, but the plane is such that the bit line is exposed on the cross section in the BB ′ direction. Of course, the layout may be acceptable. Conversely, in FIG. 19B and FIG. 23B, it is also possible to adopt a planar layout in which the bit line is not exposed on the cross section.
[0196]
Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Accordingly, the present invention is limited only by the invention and the specified items according to the scope of claims reasonable from this disclosure.
[0197]
According to the embodiment described in detail above, scaling with the minimum dimension f is possible, and a semiconductor memory element having a small memory cell configuration can be provided. In particular, according to the above-described embodiment of the present invention, it is possible to provide a semiconductor memory element that can stably hold ferroelectric polarization and that is highly integrated. In addition, according to the present invention, it is possible to realize an ultra-highly integrated semiconductor memory element that can be easily manufactured, and the industrial value is extremely high.
[0198]
【The invention's effect】
As described above in detail, according to the present invention, scaling according to the initial dimension f is possible, and a semiconductor memory element having a small memory cell configuration can be provided. In addition, despite the fact that the process is easy, an ultra-highly integrated semiconductor memory device has the characteristics that a small memory cell can be grooved and the ferroelectric polarization can be stably maintained and scaled. Therefore, the industrial value of the present invention is extremely large.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a memory cell for explaining a basic configuration of the present invention.
FIGS. 2A and 2B are schematic diagrams illustrating a read operation in (a) storage “1” and (b) storage “0” of the semiconductor memory device of the present invention, respectively.
FIGS. 3A and 3B are schematic diagrams illustrating read / write operations in (a) storage “1” and (b) storage “0” of the semiconductor memory device of the present invention, respectively.
FIG. 4 is a reference capacitor C._REFFIG. 3 is an equivalent circuit diagram of the memory cell of the present invention when is a ferroelectric thin film.
FIGS. 5A and 5B are schematic diagrams illustrating a read operation of (a) storage “1” and (b) storage “0” by a read operation by applying a series voltage in the circuit of FIG.
FIGS. 6A and 6B are schematic diagrams showing a read operation of (a) storage “1” and (b) storage “0” in a precharge mode of a reference ferroelectric capacitor, respectively.
FIG. 7 is an equivalent circuit diagram of a memory cell for explaining each basic configuration (a), (b), and (c) of the present invention.
FIGS. 8A and 8B are circuit diagrams respectively showing specific configurations (a) and (b) for higher integration of the semiconductor memory device of the present invention. FIGS.
FIG. 9: Reference capacitor C_REFFIG. 3 is a circuit diagram showing specific configurations (a) and (b) of the present invention suitable for high integration in a case where is formed of a ferroelectric thin film.
FIG. 10 is an equivalent circuit diagram of a memory cell for explaining the basic configuration of the present invention using a scalable NAND-FRAM.
FIGS. 11A and 11B are schematic diagrams illustrating polarization states (a) and (b) of a ferroelectric capacitor having asymmetric ferroelectric hysteresis, respectively.
12 is an equivalent circuit diagram of a memory cell for explaining a basic configuration when a paraelectric capacitor is used in the circuit of FIG.
FIGS. 13A and 13B are schematic diagrams illustrating read operations (a) and (b) when a paraelectric capacitor is used. FIGS.
FIG. 14 is a schematic diagram for explaining the polarization state of a paraelectric capacitor having nonlinear capacitance characteristics.
FIG. 15 is an equivalent circuit diagram of memory cells for explaining several circuit configurations (a) to (d) of the present invention.
FIG. 16 is a circuit configuration diagram of a main part of the semiconductor memory device according to the first embodiment of the invention.
FIG. 17 is a circuit configuration diagram of a main part including a peripheral circuit of the semiconductor memory device according to the first embodiment.
FIG. 18 is a timing chart showing a read / write sequence of the semiconductor memory device according to the first embodiment.
19A is a plan view and FIG. 19B is a cross-sectional view of the semiconductor memory device according to the first embodiment.
FIG. 20 is a circuit configuration diagram of a main part of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 21 is a circuit configuration diagram of a main part including a peripheral circuit of a semiconductor memory device according to a second embodiment.
FIG. 22 is a timing chart showing a read / write sequence of the semiconductor memory device according to the second embodiment.
23A is a plan view and FIG. 23B is a cross-sectional view of a semiconductor memory device according to a second embodiment.
FIG. 24 is a circuit configuration diagram of a main part of a semiconductor memory device according to a third embodiment of the invention.
FIG. 25 is a circuit configuration diagram of a main part including a peripheral circuit of a semiconductor memory device according to a third embodiment.
FIG. 26 is a timing chart showing a read / write sequence of the semiconductor memory device according to the third embodiment.
27A is a plan view and FIG. 27B is a sectional view of a semiconductor memory device according to a third embodiment.
FIG. 28 is a circuit configuration diagram of a main part of a semiconductor memory device according to a fourth embodiment of the invention.
FIG. 29 is a circuit configuration diagram of a main part including a peripheral circuit of a semiconductor memory device according to a fourth embodiment.
FIG. 30 is a timing chart showing a read / write sequence of the semiconductor memory device according to the fourth embodiment.
31A is a plan view and FIG. 31B is a cross-sectional view of a semiconductor memory device according to a fourth embodiment.
FIG. 32 is a circuit configuration diagram of a main part of a semiconductor memory device according to a fifth embodiment of the invention.
FIG. 33 is a circuit configuration diagram of a main part including a peripheral circuit of a semiconductor memory device according to a fifth embodiment.
FIG. 34 is a timing chart showing a read / write sequence of the semiconductor memory device according to the fifth embodiment.
FIG. 35A is a plan view and FIG. 35B is a cross-sectional view of a semiconductor memory device according to a fifth embodiment.
FIG. 36 is a schematic cross-sectional view in order of steps (a) to (d) of a memory cell of a semiconductor memory device according to a sixth embodiment of the present invention;
FIG. 37 is a schematic cross-sectional view in order of steps (a) to (c) of the memory cell of the semiconductor memory device according to the seventh embodiment of the present invention.
38 is a cross-sectional view showing steps (d) and (e) following FIG. 37 in the seventh embodiment.
FIG. 39 is a schematic cross-sectional view in order of steps (a) to (c) of the memory cell of the semiconductor memory device according to the eighth embodiment of the present invention;
40 is a cross-sectional view showing steps (d) and (e) following FIG. 39 in the seventh embodiment.
FIG. 41 is a schematic cross-sectional view in order of steps (a) to (c) of the memory cell of the semiconductor memory device according to the ninth embodiment of the present invention.
FIG. 42 is a schematic cross-sectional view in order of steps (a) to (c) of the memory cell of the semiconductor memory device according to the tenth embodiment of the present invention;
43 is a cross-sectional view showing steps (d) to (f) following FIG. 42 in the tenth embodiment.
FIG. 44 is a schematic cross-sectional view in order of steps (a) to (c) of the memory cell of the semiconductor memory device according to the eleventh embodiment of the present invention;
45 is a cross-sectional view showing steps (d) and (e) following FIG. 44 in the eleventh embodiment.
FIG. 46 is a schematic cross-sectional view in order of steps (a) and (b) of the memory cell of the semiconductor memory device according to the twelfth embodiment of the present invention;
47 is a sectional view showing steps (d) and (e) following FIG. 46 in the twelfth embodiment. FIG.
[Explanation of symbols]
C_M0~ C_MN  Memory capacitor
C_REF        Reference capacitor
Q_READ        Read transistor
Q_M0~ Q_MN  MOS transistor for selection
Q_C         Control transistor
Q_S         Block selection transistor

Claims (16)

A storage capacitor comprising at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes;
A third electrode connected to the first electrode; a fourth electrode disposed opposite to the third electrode; and a dielectric thin film sandwiched between the third and fourth electrodes. A reference capacitor provided at least;
A read transistor having a gate electrode connected to the first and third electrodes;
Control provided to adjust the potential of the storage node, which is the three connection points of the first electrode of the storage capacitor, the third electrode of the reference capacitor, and the gate electrode of the read transistor Transistors for
A plurality of memory cells having at least
The semiconductor memory device, wherein the control transistor is connected between the first electrode and the second electrode of the storage capacitor.   The semiconductor memory device according to claim 1, wherein the control transistor is connected between the third electrode and the fourth electrode of the reference capacitor. A storage capacitor comprising at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes;
A third electrode connected to the first electrode; a fourth electrode disposed opposite to the third electrode; and a dielectric thin film sandwiched between the third and fourth electrodes. A reference capacitor provided at least;
A read transistor having a gate electrode connected to the first and third electrodes;
Control provided to adjust the potential of the storage node, which is the three connection points of the first electrode of the storage capacitor, the third electrode of the reference capacitor, and the gate electrode of the read transistor Transistors for
A plurality of memory cells including at least a matrix,
The semiconductor memory device, wherein the control transistor is connected between the third electrode and the fourth electrode of the reference capacitor. A storage capacitor comprising at least a first electrode, a second electrode disposed opposite to the first electrode, a ferroelectric film sandwiched between the first and second electrodes, and the first capacitor A memory cell array in which a plurality of memory cells each including a control transistor connected between the first and second electrodes are connected in series;
A third electrode electrically coupled to the first electrode of the memory capacitor located at the end of the memory cell column, a fourth electrode disposed opposite to the third electrode, A reference capacitor comprising at least a dielectric thin film sandwiched between three and fourth electrodes;
A read transistor having a gate electrode electrically coupled to the first and third electrodes;
A semiconductor memory device comprising a plurality of memory cell blocks each including a plurality of memory cell blocks arranged in a matrix. The control transistor connected between the first electrode and the second electrode of the memory cell column is a first control transistor,
The semiconductor memory device according to claim 4, wherein a second control transistor is provided between the third electrode and the fourth electrode of the reference capacitor.   The charge amount including a polarization inversion component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor includes a polarization inversion component obtained when a voltage corresponding to the read voltage is applied to the storage capacitor. 5. The semiconductor memory device according to claim 4, wherein the charge amount is not less than 1/4 and not more than 4 times the charge amount.   5. The semiconductor memory device according to claim 4, wherein the dielectric thin film of the reference capacitor is a paraelectric thin film.   5. The semiconductor memory device according to claim 4, wherein the dielectric thin film of the reference capacitor is a ferroelectric thin film. A NAND comprising: a plurality of selection MOS transistors connected in series; a storage capacitor made of a dielectric film sandwiched between plate electrodes opposed to storage electrodes connected to each common main electrode of the selection MOS transistors; A type memory cell string;
A reference capacitor electrically coupled to a main electrode of a selection transistor located at an end of the memory cell row;
A read transistor having a gate electrode electrically coupled to a connection between a main electrode of the selection MOS transistor and an electrode of the reference capacitor;
A semiconductor memory device comprising a plurality of memory cell blocks each including a plurality of memory cell blocks arranged in a matrix. A control transistor is further provided between a storage node and a bit line which are three connection points of the main electrode of the selection MOS transistor, one electrode of the reference capacitor, and the gate electrode of the read transistor. The semiconductor memory device according to claim 9.   The charge amount including a polarization inversion component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor includes a polarization inversion component obtained when a voltage corresponding to the read voltage of the storage capacitor is applied. The semiconductor memory device according to claim 9, wherein the semiconductor memory device is ¼ or more and four times or less of an amount of charge.   The semiconductor memory device according to claim 9, wherein the dielectric film of the memory capacitor is a ferroelectric film.   10. The storage capacitor according to claim 9, wherein the dielectric film of the storage capacitor is a paraelectric film, and the maximum capacitance value of the storage capacitor within the operating voltage range is twice or more the minimum capacitance value. Semiconductor memory device described   10. The semiconductor memory device according to claim 9, wherein the dielectric film of the reference capacitor is a ferroelectric film.   10. The semiconductor memory device according to claim 9, wherein the dielectric film of the reference capacitor is a paraelectric film.   The charge amount including a polarization inversion component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor includes a polarization inversion component obtained when a voltage corresponding to the read voltage is applied to the storage capacitor. The semiconductor memory device according to claim 9, wherein the charge amount is ¼ or more and four times or less of a charge amount.

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