CN102598266B - The semiconductor device - Google Patents

The semiconductor device Download PDF

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Publication number
CN102598266B
CN102598266B CN 201080051156 CN201080051156A CN102598266B CN 102598266 B CN102598266 B CN 102598266B CN 201080051156 CN201080051156 CN 201080051156 CN 201080051156 A CN201080051156 A CN 201080051156A CN 102598266 B CN102598266 B CN 102598266B
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China
Prior art keywords
electrode
transistor
source
oxide semiconductor
semiconductor device
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CN 201080051156
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Chinese (zh)
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CN102598266A (en
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山崎舜平
小山润
加藤清
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株式会社半导体能源研究所
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Priority to JP2009-264615 priority Critical
Priority to JP2009264615 priority
Application filed by 株式会社半导体能源研究所 filed Critical 株式会社半导体能源研究所
Priority to PCT/JP2010/069647 priority patent/WO2011062067A1/en
Publication of CN102598266A publication Critical patent/CN102598266A/en
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Publication of CN102598266B publication Critical patent/CN102598266B/en

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Abstract

一种半导体装置,其具有新的结构。 A semiconductor device having a new structure. 该半导体装置包括:彼此串联连接的存储单元;以及电容器。 The semiconductor device comprising: memory cells connected in series to each other; and a capacitor. 存储单元之一包括:连接到位线及源极线的第一晶体管;连接到信号线及字线的第二晶体管;以及连接到字线的电容器。 One of the memory cells comprises: a first transistor connected to the bit line and the source line; a signal line connected to the second transistor and the word line; and a capacitor connected to a word line. 第二晶体管包含氧化物半导体层。 A second transistor including an oxide semiconductor layer. 第一晶体管的栅电极、第二晶体管的源电极和漏电极中的一方、以及电容器的电极中的一方彼此连接。 The gate electrode of the first transistor, one electrode of the second transistor, one of a source and drain, and an electrode of the capacitor connected to each other.

Description

半导体装置 The semiconductor device

技术领域 FIELD

[0001] 所公开的发明涉及一种利用半导体元件的半导体装置及其制造方法。 [0001] The disclosed invention relates to a method of manufacturing a semiconductor device using a semiconductor element.

背景技术 Background technique

[0002] 利用半导体元件的存储装置可以粗略地分为两类:当电力供给停止时丢失存储的数据的易失性存储装置和即使在没有电力供给时也保持所存储的数据的非易失性存储装置。 [0002] The storage means using a semiconductor element can be roughly divided into two categories: volatile volatile memory means the stored data is lost when the power supply is stopped, and even when power is not supplied retaining stored data storage means.

[0003] 易失性存储装置的典型例子是DRAM (Dynamic Random Access Memory :动态随机存取存储器)。 Typical examples of [0003] volatile storage device is a DRAM (Dynamic Random Access Memory: Dynamic Random Access Memory). DRAM这样的方式存储数据:存储元件中包含的晶体管被选择并将电荷存储在电容器中。 DRAM stores data in such a manner: a transistor included in the memory element is selected and the charge stored in the capacitor.

[0004] 由于上述原理,在从DRAM读出数据时电容器的电荷丢失,因此,需要再次进行写入以使得在读出数据之后再次存储数据。 [0004] Due to the above principle, the charge of the capacitor when the data is read from the DRAM is lost, therefore, need to be re-written so that the data is read again after the data is stored. 另外,存储元件中所包括的晶体管存在泄漏电流, 并且即使晶体管未被选择时电荷也流入或流出电容器,从而数据保持时间较短。 Further, the presence of the transistor included in the memory element leakage current, even when the transistor is not selected and the charge flows into or out of the capacitor, so that the data holding time is shorter. 为此,需要以预定的间隔进行另一写入操作(刷新操作),并且难以充分降低功耗。 To this end, a further need for a write operation (refresh operation), and it is difficult to sufficiently reduce the power consumption at predetermined intervals. 另外,因为在没有电力供给时存储的内容丢失,因此需要具有利用磁性材料或光学材料的另外的存储装置以实现较长期间的存储保持。 Further, since the stored contents are lost when power is not supplied, thus requiring additional storage means having a magnetic material or an optical material to achieve a longer storage period of holding.

[0005] 易失性存储装置的另一例子是SRAM (Static Random Access Memory :静态随机存取存储器)。 [0005] Another example of a volatile memory device is a SRAM (Static Random Access Memory: SRAM). SRAM使用诸如触发器等电路保持存储的数据,因此不需要刷新操作。 SRAM uses such as data storage flip-flop circuit holds the like and therefore requires no refresh operation. 在这一点上SRAM优越于DRAM。 At this point, SRAM is superior to DRAM. 但是,因为使用诸如触发器等电路,因此单位存储容量的成本变高。 However, since the circuit such as a flip-flop and the like, so the cost per unit storage capacity becomes high. 另外,如DRAM中那样,如果没有电力供给,则SRAM中存储的数据丢失。 Further, as if there is no power supply, the data stored in the DRAM is lost in the SRAM.

[0006] 非易失性存储装置的典型例子是快闪(flash)存储器。 [0006] Typical examples of nonvolatile memory device is a flash (flash) memory. 快闪存储器在晶体管中包括在栅电极和沟道形成区之间的浮置栅极,并通过将电荷保持在该浮置栅极中来存储数据。 The flash memory includes a floating gate between the gate electrode and the channel region is formed in the transistor, and the charge held by the data stored in the floating gate. 因此,快闪存储器具有如下的优点:数据保持时间极长(几乎是永久性的),不需要易失性存储装置中所需的刷新操作(例如,见专利文献1)。 Thus, the flash memory has the following advantages: the data holding time is extremely long (almost permanent), does not require the refresh operation required for easily volatile memory devices (e.g., see Patent Document 1).

[0007] 但是,由于在进行写入时产生的隧穿电流,存储元件中的栅极绝缘层劣化,使得在预定次数的写入之后存储元件不能发挥其功能。 [0007] However, since the tunnel is generated during the writing of the tunneling current, the deterioration of the gate insulating layer of the storage element, such that the storage element can not perform its function after a predetermined number of writes. 为了降低上述问题的不利影响,例如,使用其中使各存储元件的写入次数均衡化的方法。 In order to reduce the adverse effects of the above problems, for example, using a method in which the number of times each storage element write equalization. 但是,为了实现该方法,需要具有复杂的外围电路。 However, to realize this method requires a complicated peripheral circuit. 另外,使用上述方法也不能解决使用寿命的根本问题。 In addition, the fundamental problem with the above method does not solve the life. 换而言之,快闪存储器不合适于其中数据被频繁写入的应用。 In other words, the flash memory is not suitable for applications in which data is frequently written.

[0008] 另外,为了将电荷保持在浮置栅极中或者去除该电荷,需要高电压。 [0008] Further, in order to maintain the charge in the floating gate or removal of the charge, it requires a high voltage. 再者,电荷的保持或去除需要相对较长的时间,并且难以实现写入和擦除的高速化。 Also, charge retention, or removal requires a relatively long time, and it is difficult to achieve high-speed writing and erasing.

[0009] 参考文献 [0009] Reference

[0010] 专利文献1 :日本专利申请公开No. S57-105889 [0010] Patent Document 1: Japanese Patent Application Publication No. S57-105889

发明内容 SUMMARY

[0011] 鉴于上述问题,所公开的发明的一个实施例的目的之一是提供一种具有新的结构的半导体装置,其中即使没有电力供给也能够保持存储的数据并且对写入次数没有限制。 [0011] In view of the above problems, an embodiment of the disclosed embodiment of the invention, the object is to provide a novel semiconductor device having a structure in which power is not supplied even if the stored data can be held and there is no limit on the number of writes.

[0012] 本发明的一个实施例是具有使用氧化物半导体形成的晶体管和使用除氧化物半导体以外的材料形成的晶体管的分层结构的半导体装置。 One embodiment [0012] of the present invention is a semiconductor device having a layered structure of a transistor using an oxide semiconductor and formed using a material other than an oxide semiconductor transistor is formed. 例如,可以采用如下结构。 For example, the following structure may be adopted.

[0013] 本发明的一个实施例是一种半导体装置,包括:源极线;位线;信号线;以及字线。 A [0013] embodiment of the present invention is a semiconductor device, comprising: a source line; bit line; signal line; and a word line. 多个存储单元彼此串联连接在源极线和位线之间,并且所述多个存储单元之一包括:具有第一栅电极、第一源电极以及第一漏电极的第一晶体管;具有第二栅电极、第二源电极以及第二漏电极的第二晶体管;以及电容器。 A plurality of memory cells are connected in series between the source and bit lines and one of said plurality of memory cells comprises: a first gate electrode, a first source electrode of the first transistor and a first drain electrode; a second two gate electrode, a second source electrode and second drain electrode of the second transistor; and a capacitor. 第一晶体管设置在包含半导体材料的衬底上,第二晶体管包含氧化物半导体层。 A first transistor disposed on a substrate comprising a semiconductor material, a second transistor including an oxide semiconductor layer. 第一栅电极、第二源电极和第二漏电极中的一方、以及电容器的一个电极彼此电连接。 A first gate electrode, a second one of the source electrode and the second drain electrode, and one electrode of the capacitor electrically connected to each other. 源极线与第一源电极彼此电连接,位线与第一漏电极彼此电连接, 并且信号线与第二栅电极彼此电连接。 Source line and a first source electrode electrically connected to each other, a first bit line and a drain electrode electrically connected to each other, and the signal line and the second gate electrode electrically connected to each other. 字线、第二源电极和第二漏电极中的另一方、以及电容器的另一电极彼此电连接。 Word line, a second source electrode and a drain electrode of the other of the second, and the other electrode of the capacitor electrically connected to each other.

[0014] 本发明的另一个实施例是一种半导体装置,包括:源极线;位线;信号线;以及字线。 Another [0014] embodiment of the present invention is a semiconductor device, comprising: a source line; bit line; signal line; and a word line. 多个存储单元串联连接在源极线和位线之间,所述多个存储单元之一包括:具有第一栅电极、第一源电极以及第一漏电极的第一晶体管;具有第二栅电极、第二源电极以及第二漏电极的第二晶体管;以及电容器。 A plurality of memory cells are connected in series between the source line and a bit line, one of said plurality of memory cells comprises: a first gate electrode, a first source electrode of the first transistor and a first drain electrode; a second gate electrode of the second transistor, a second source electrode and second drain electrode; and a capacitor. 第一晶体管设置在包含半导体材料的衬底上,第二晶体管包含氧化物半导体层。 A first transistor disposed on a substrate comprising a semiconductor material, a second transistor including an oxide semiconductor layer. 第一栅电极、第二源电极和第二漏电极中的一方、以及电容器的一个电极彼此电连接。 A first gate electrode, a second one of the source electrode and the second drain electrode, and one electrode of the capacitor electrically connected to each other. 源极线与第一源电极彼此电连接,位线与第一漏电极彼此电连接,并且信号线与第二源电极和第二漏电极中的另一方彼此电连接。 Source line and a first source electrode electrically connected to each other, a first bit line and a drain electrode electrically connected to each other, and the signal line and the second source electrode and second drain electrode electrically connected to each other. 字线、第二栅电极、以及电容器的电极中的另一方彼此电连接。 Word line, a second gate electrode, and the other electrode of the capacitor are electrically connected to each other.

[0015] 在上面的说明中,优选的是,半导体装置包括:第一选择线;第二选择线;在栅电极中电连接到第一选择线的第三晶体管;以及在栅电极中电连接到第二选择线的第四晶体管。 [0015] In the above description, it is preferable that the semiconductor device comprising: a first select line; second select line; in the gate electrode of the third transistor is electrically connected to the first select line; and a gate electrode electrically connected a fourth transistor to a second select line. 此外,优选地,位线通过第三晶体管电连接到第一漏电极,并且源极线通过第四晶体管电连接到第一源电极。 In addition, preferably, the bit line is connected to a first power drain electrode through the third transistor, and the source line is connected to the first source electrode through the fourth transistor electrically.

[0016] 在上述说明中,半导体装置中的第一晶体管包括:设置在包含半导体材料的衬底中的沟道形成区域;以夹着沟道形成区域的方式设置的杂质区域;在沟道形成区域上的第一栅极绝缘层;在第一栅极绝缘层上的第一栅电极;以及电连接到所述杂质区域的第一源电极及第一漏电极。 [0016] In the above description, the first transistor in the semiconductor device comprising: a channel disposed in a substrate comprising semiconductor material forming region; impurity region to sandwich a channel forming region is provided embodiment; forming a channel a first insulating layer on the gate region; a first gate electrode on the first gate insulating layer; and a first source electrode electrically connected to the impurity region and the first drain electrode.

[0017] 在上述说明中,第二晶体管包括:在包含半导体材料的衬底上的第二栅电极;在第二栅电极上的第二栅极绝缘层;在第二栅极绝缘层上的氧化物半导体层;以及电连接到所述氧化物半导体层的第二源电极及第二漏电极。 [0017] In the above description, the second transistor comprising: a second gate electrode on a substrate comprising a semiconductor material; a second gate insulating layer on the second gate electrode; on the second gate insulating layer the oxide semiconductor layer; and a second source electrode electrically connected to the oxide semiconductor layer and the second drain electrode.

[0018] 在上述说明中,优选使用单晶半导体衬底或SOI衬底作为所述包含半导体材料的衬底。 [0018] In the above description, it is preferable to use a single crystal semiconductor substrate or an SOI substrate as the substrate comprises a semiconductor material. 尤其是,优选使用硅作为所述半导体材料。 It is particularly preferable to use silicon as the semiconductor material.

[0019] 在上述说明中,所述氧化物半导体层优选使用基于In-Ga-Zn-0的氧化物半导体材料形成。 [0019] In the above description, the oxide semiconductor layer is preferably formed using an oxide semiconductor material based on In-Ga-Zn-0's. 更优选地,所述氧化物半导体层包含In 2Ga2Zn07的晶体。 More preferably, the oxide semiconductor layer containing In 2Ga2Zn07 the crystal. 此外,氧化物半导体层中的氢浓度优选为小于或等于5 X1019原子/cm3。 In addition, the hydrogen concentration in the oxide semiconductor layer is preferably less than or equal to 5 X1019 atoms / cm3. 另外,第二晶体管的截止电流(off-state current)优选为小于或等于1 X 10_13A。 Further, off-state current of the second transistor (off-state current) is preferably less than or equal to 1 X 10_13A.

[0020] 在任何上述结构中,第二晶体管可以设置在与第一晶体管重叠的区域中。 [0020] In any of the above-described structure, the second transistor may be disposed in the overlapping region of the first transistor.

[0021] 注意,在本说明书等中,诸如"上"或"下"之类的术语并不必然表示一个部件被放置在另一部件的"正上"或"正下"。 [0021] Note that in this specification and the like, terms such as "on" or "under" and the like does not necessarily mean a component is placed in the "NOW" another element or "immediately below." 例如,"在栅极绝缘层上的第一栅电极"的表述并不排除其中在栅极绝缘层和第一栅电极之间设置另一部件的情况。 For example, the expression "on the gate insulating layer, a first gate electrode" does not exclude the case where another member is provided between the gate insulating layer and the first gate electrode. 另外,诸如"上"或"下"之类的术语只是为了便于说明而使用的,并且在没有相反的明确说明的情况下,其可以包括部件的关系倒转的情况。 Further, terms such as "on" or "under" and the like are used only for convenience of explanation, and in the absence of explicit contrary instructions, which may include a case where the relationship of reversed member.

[0022] 另外,在本说明书等中,诸如"电极"或"布线"之类的术语并不限制部件的功能。 [0022] Further, in the present specification and the like, as the term "electrode" or "wiring" does not limit the functions of such components. 例如,有时将"电极"用作"布线"的一部分,反之亦然。 For example, sometimes an "electrode" is used as part of a "wiring", and vice versa. 再者,术语"电极"或"布线"可以包括其中以一体的方式形成多个"电极"或"布线"的情况。 Furthermore, the term "electrode" or "wiring" which may include a plurality of integrally formed "electrode" or a "wiring".

[0023] "源极"和"漏极"的功能有时彼此互换,例如,在使用相反极性的晶体管的情况或电路操作中电流方向变化的情况下。 The [0023] "source" and "drain" are sometimes interchanged with one another, e.g., a change in current direction in case of using a transistor of opposite polarity, or in the case of circuit operation. 因此,在本说明书中,术语"源极"和"漏极"可以彼此互换。 Accordingly, in the present specification, the term "source" and "drain" are interchangeable with each other.

[0024] 注意,在本说明书等中,术语"电连接"包括其中部件通过具有某种电作用的物体连接的情况。 [0024] Note that in this specification and the like, the term "electrically connected" includes the case where components are connected through an object having any electric function. 这里,对于具有某种电作用的物体没有特别的限制,只要可以在通过该物体连接的部件之间发送和接收电信号即可。 Here, there is no particular limitation to the object having any electric function, as long as electric signals can be sent and received between the components connected by the object.

[0025] "具有某种电作用的物体"的例子是诸如晶体管等的开关元件、电阻元件、电感器、 电容器、其他具有各种功能的元件等、以及电极和布线。 [0025] Examples of the "object having any electric function" is a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having various functions, and an electrode and a wiring.

[0026] -般来说,术语"SOI衬底"是指其中在绝缘表面上设置有硅半导体层的衬底。 [0026] - In general, the term "SOI substrate" means a substrate which is provided with a silicon semiconductor layer on an insulating surface. 在本说明书等中,术语"SOI衬底"在其类别中还包括在绝缘表面上设置有使用硅以外的材料形成的半导体层的衬底。 In the present specification and the like, the term "SOI substrate" also includes in its category is provided on an insulating surface of the substrate with a layer of a semiconductor material other than silicon is formed. 换言之,"SOI衬底"中所具有的半导体层不限于硅半导体层。 In other words, "SOI substrate" is not limited to the semiconductor layer having a silicon semiconductor layer. "SOI 衬底"中的衬底不限于诸如硅晶片等的半导体衬底,并且可以是诸如玻璃衬底、石英衬底、 蓝宝石衬底、或金属衬底等的非半导体衬底。 "SOI substrate" is not limited to a semiconductor substrate such as a silicon wafer substrate or the like, and may be a non-semiconductor substrate such as a glass substrate, a quartz substrate, a sapphire substrate, a metal substrate, or the like. 换而言之,"SOI衬底"在其类别中还包括设有半导体材料形成的层的绝缘衬底或具有绝缘表面的导电衬底。 In other words, "SOI substrate" also includes in its category a substrate provided with an insulating layer of a semiconductor material or a conductive substrate having an insulating surface. 此外,在本说明书等中,术语"半导体衬底"不但是指仅利用半导体材料形成的衬底,而且是指包含半导体材料的所有衬底。 In the present specification and the like, the term "semiconductor substrate" not only refers to using only the substrate of semiconductor material, and refers to all the substrate including a semiconductor material. 就是说,在本说明书等中,"半导体衬底"在其类别中还包括"S0I衬底"。 That is, like in the present specification, "semiconductor substrate" also includes in its category "SOI substrate."

[0027] 另外,在本说明书等中,氧化物半导体以外的半导体材料可以是任何半导体材料, 只要其是氧化物半导体以外的半导体材料即可。 [0027] Further, a semiconductor material other than the oxide semiconductor of the present specification and the like may be any semiconductor material as long as it is a material other than a semiconductor of an oxide semiconductor. 例如,可以给出硅、锗、硅锗、碳化硅、或砷化镓等。 For example, given a silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like. 另外,可以使用有机半导体材料等。 Further, an organic semiconductor material may be used. 注意,在未特别说明半导体装置等中所包含的材料时,可以使用氧化物半导体材料或者氧化物半导体以外的半导体材料。 Note that, the semiconductor material is not particularly described devices contained, it is possible to use a semiconductor material other than an oxide semiconductor material or an oxide semiconductor.

[0028] 本发明的一个实施例提供了一种半导体装置,其中使用氧化物半导体以外的材料的晶体管放置在下部而包含氧化物半导体的晶体管放置在上部。 [0028] An embodiment of the present invention provides a semiconductor device in which a transistor using a material other than an oxide semiconductor disposed in a lower portion and including an oxide semiconductor transistor placed in the upper.

[0029] 由于包含氧化物半导体的晶体管的截止电流极小,因此通过使用该晶体管可以将所存储的数据储存极长时间。 [0029] Since the off current of a transistor including an oxide semiconductor is extremely small, and therefore the data stored by using the transistor can be stored very long time. 换而言之,由于不需要进行刷新操作,或者,刷新操作的频率可以极低,因此可以充分降低功耗。 In other words, since the frequency does not require a refresh operation, or the refresh operation can be extremely low power consumption can be sufficiently reduced. 另外,即使没有电力供给,也可以较长时间保存存储的数据。 Further, even if power is not supplied, a longer time may be stored in the data store.

[0030] 另外,在该半导体装置中,信息的写入不需要高电压,而且也没有元件劣化的问题。 [0030] Further, in the semiconductor device, writing information does not require high voltage, and there is no problem of deterioration of elements. 例如,因为不需要如现有的非易失性存储器那样将电子注入到浮置栅极和从浮置栅极抽出电子,因此不发生栅极绝缘层的劣化。 For example, it is not necessary as the conventional nonvolatile memory such as electrons are injected into the floating gate, and electrons are extracted from the floating gate, so the deterioration of the gate insulating layer does not occur. 就是说,根据本发明一个实施例的半导体装置对在现有的非易失性存储器中成为问题的写入次数没有限制,而且其可靠性显著提高。 That is, there is no limit on the number of writing a problem in the conventional semiconductor nonvolatile memory device according to one embodiment of the present invention, and its reliability significantly increased. 此外, 根据晶体管的导通状态或截止状态而进行信息写入,从而可以容易地实现高速操作。 Further, according to the conductive state or the OFF state of the transistor and writing information, whereby high-speed operation can be easily realized. 另外, 还有如下的优点:不需要快闪存储器等中所需的用于擦除信息的操作。 Further, there are the following advantages: does not require a flash memory or the like required for the erase operation information.

[0031] 与包含氧化物半导体的晶体管相比,使用氧化物半导体以外的材料的晶体管可以以充分高的速度进行操作,因此,使用该晶体管可以高速地读出存储的数据。 [0031] Compared with a transistor including an oxide semiconductor, a transistor using a material other than an oxide semiconductor can operate at sufficiently high speeds, thus using the transistor of quickly reading out the stored data.

[0032] 通过包括使用氧化物半导体以外的材料的晶体管和使用氧化物半导体的晶体管, 可以实现具有新的特征的半导体装置。 [0032] By using an oxide semiconductor and a transistor including a transistor using an oxide semiconductor material than the semiconductor device having a novel feature can be achieved.

附图说明 BRIEF DESCRIPTION

[0033] 在附图中: [0033] In the drawings:

[0034] 图1是用于说明半导体装置的电路图; [0034] FIG. 1 is a circuit diagram illustrating a semiconductor device;

[0035] 图2A和2B是用于说明半导体装置的截面图及平面图; [0035] Figures 2A and 2B are cross-sectional and plan views showing a semiconductor device;

[0036] 图3A至3H是用于说明半导体装置的制造步骤的截面图; [0036] FIGS. 3A through 3H are cross-sectional views illustrating manufacturing steps for explaining the semiconductor device;

[0037] 图4A至4G是用于说明半导体装置的制造步骤的截面图; [0037] FIGS 4A to 4G are cross-sectional views illustrating manufacturing steps for explaining the semiconductor device;

[0038] 图5A至®是用于说明半导体装置的制造步骤的截面图; [0038] FIGS. 5A to ® is a sectional view for illustrating manufacturing steps of the semiconductor device;

[0039] 图6是包含氧化物半导体的晶体管的截面图; [0039] FIG. 6 is a sectional view of a transistor including an oxide semiconductor;

[0040] 图7是沿图6的A-A'截面的能带图(示意图); [0040] FIG. 7 is taken along A-A 'cross section of an energy band diagram (schematic) 6;

[0041] 图8A是示出将正电压(VP0)施加到栅极(GE1)的状态的图,而图8B是示出将负电压(V e〈0)施加到栅极(GE1)的状态的图; [0041] FIG. 8A is a diagram illustrating the positive voltage (VP0) state is applied to the gate electrode (GE1) of, and FIG 8B is a diagram showing a negative voltage (V e <0) is applied to the state of the gate (GE1) of FIG;

[0042] 图9是示出真空能级和金属的功函数((^)之间以及真空能级和氧化物半导体的电子亲和势(x )之间的关系的图; [0042] FIG. 9 shows a vacuum level and the work function of metal (and a relationship between the oxide semiconductor and the vacuum level of the electron affinity (x) between (^);

[0043] 图10是示出CV特性的图; [0043] FIG. 10 is a graph showing the CV characteristic diagram;

[0044] 图11是示出Vg和(1/C)2的关系的图; [0044] FIG. 11 is a graph showing Vg and the (1 / C) of FIG. 2, the relationship;

[0045] 图12是用于说明半导体装置的截面图; [0045] FIG. 12 is a sectional view for explaining a semiconductor device;

[0046] 图13A和13B每一都是用于说明半导体装置的截面图; [0046] Figures 13A and 13B are each a cross-sectional view of a semiconductor device for explaining;

[0047] 图14A和14B每一都是用于说明半导体装置的截面图; [0047] Figures 14A and 14B are each a cross-sectional view of a semiconductor device for explaining;

[0048] 图15A和15B每一都是用于说明半导体装置的截面图; [0048] FIGS. 15A and 15B are each a cross-sectional view of a semiconductor device for explaining;

[0049] 图16是用于说明半导体装置的电路图; [0049] FIG. 16 is a circuit diagram for explaining a semiconductor device;

[0050] 图17是用于说明半导体装置的模块电路图; [0050] FIG. 17 is a block circuit diagram of a semiconductor device;

[0051] 图18是用于说明半导体装置的电路图; [0051] FIG. 18 is a circuit diagram illustrating a semiconductor device;

[0052] 图19是用于说明半导体装置的电路图; [0052] FIG. 19 is a circuit diagram illustrating a semiconductor device;

[0053] 图20A至20F每一都是用于说明使用半导体装置的电子设备的图。 [0053] FIGS. 20A to 20F are each a diagram for explaining an electronic device using a semiconductor device.

具体实施方式 Detailed ways

[0054] 下面,参照附图说明本发明的实施方式的例子。 [0054] The following describes an example of embodiment with reference to the embodiment of the present invention. 注意,本发明并不限于下面的描述,本领域技术人员可以容易地理解,在此公开的方式和细节可以以各种形式进行修改,而不脱离本发明的宗旨及其范围。 Note that the present invention is not limited to the following description, one skilled in the art can readily appreciate that modes and details herein disclosed can be modified in various forms without departing from the spirit and scope of the invention. 因此,本发明不应被解释为受限于在此所示的实施例的内容。 Accordingly, the present invention should not be construed as limited to the content of the embodiment shown herein.

[0055] 注意,为了便于理解,附图等中所示出的各结构的位置、大小、或范围等有时并未准确地呈现。 [0055] Note that, as shown in order to facilitate understanding, drawings and the like of the position of each structure, size, range, or the like may not be accurately rendered. 因此,本发明的实施例并不局限于附图等所公开的位置、大小、或范围等。 Thus, embodiments of the present invention is not limited to the drawings disclosed in the like position, size, range, or the like.

[0056] 在本说明书等中,使用诸如"第一"、"第二"、"第三"等序数词以避免部件的混同, 并且这些术语并不表示对部件号的限制。 [0056] In the present specification and the like, the use of ordinal numbers such as "first", "second", "third" and the like in order to avoid confusion member, and these terms do not denote a limitation of part numbers.

[0057] 实施例1 [0057] Example 1

[0058] 在本实施例中,参照图1至图15A和15B说明根据所公开的发明的一个方式的半导体装置的结构及其制造方法。 [0058] In the present embodiment, the configuration and the manufacturing method of the semiconductor device of FIG. 1 to FIG. 15A and 15B illustrate one embodiment according to the invention is disclosed.

[0059]〈半导体装置的电路结构〉 [0059] <circuit configuration of a semiconductor device>

[0060] 图1示出半导体装置的电路结构的一个例子。 [0060] FIG. 1 shows an example of a circuit configuration of a semiconductor device. 该半导体装置包括使用氧化物半导体以外的材料的晶体管160和使用氧化物半导体的晶体管162。 Transistor 160 and the transistor using an oxide semiconductor, the semiconductor device includes a semiconductor material other than an oxide 162. 注意,在图1中,对晶体管162增加了0S的符号,以示出晶体管162使用氧化物半导体(0S)。 Note that, in FIG. 1, symbol 0S transistor 162 increases, the transistor 162 is shown to use an oxide semiconductor (0S). 这对于以下的实施例的其他电路图中也是如此。 This is also true for the other embodiments of the circuit diagram of the embodiment below.

[0061] 这里,晶体管160的栅电极与晶体管162的源电极和漏电极中的一方电连接。 [0061] Here, one of a source electrode and a drain electrode of the transistor 160 and the gate electrode of the transistor 162 is connected. 另夕卜,第一布线(其被表示为"第一线",也称为源极线SL)和晶体管160的源电极电连接,第二布线(其被表示为"第二线",也称为位线BL)和晶体管160的漏电极电连接。 Another Bu Xi, a first wiring (which is denoted as a "first line", also referred to as a source line SL) and the source electrode of transistor 160 is connected to a second wiring (which is denoted as a "second line", also known as the bit line BL) and the drain electrode of the transistor 160 is connected. 并且,第三布线(其被表示为"第三线",也称为第一信号线S1)与晶体管162的源电极和漏电极中的另一方电连接,第四布线(其被表示为"第四线",也称为第二信号线S2)和晶体管162的栅电极电连接。 And, a third wiring (which is denoted as a "third line", also referred to as a first signal line S1) is electrically connected to the other of the source electrode and the drain electrode of the transistor 162, the fourth wiring (which is denoted as "on four-wire ", also referred to as a second signal line S2) and the gate electrode of the transistor 162 is connected.

[0062] 与使用氧化物半导体的晶体管相比,使用氧化物半导体以外的材料的晶体管160 可以进行更高速度的操作,因此可以实现存储数据的高速读出。 [0062] Compared with a transistor using an oxide semiconductor, a transistor 160 of a material other than an oxide semiconductor can operate higher speed, it is possible to realize a high speed read out stored data. 另外,使用氧化物半导体的晶体管162具有极小的截止电流。 Further, an oxide semiconductor transistor 162 has an extremely small off current. 因此,在晶体管162处于截止状态时,可以在极长时间内保持晶体管160的栅电极的电压。 Thus, when the transistor 162 in an off state, the voltage of the gate electrode can maintain transistor 160 in a very long time. 另外,在使用氧化物半导体的晶体管162中,不容易导致短沟道效应,这是有利的。 Further, the oxide semiconductor transistor 162, it is not easy to cause a short channel effect, which is advantageous.

[0063] 可以在极长时间内保持栅电极的电压的有点使得能够如下所述地进行信息写入、 保持和读出。 [0063] The voltage of the gate electrode can be kept within a very long period of time such that little can be performed following the information writing, and holding the readout.

[0064] 首先,说明信息的写入及保持。 [0064] First, writing and maintaining information. 首先,将第四布线的电位设定为使晶体管162处于导通状态的电位,从而使晶体管162处于导通状态。 First, the potential of the fourth wiring is set so that the potential in the conductive state of transistor 162 such that transistor 162 in a conducting state. 由此,将第三布线的电位施加到晶体管160的栅电极(信息写入)。 Accordingly, the potential of the third wiring is applied to the gate electrode (information writing) of the transistor 160. 然后,将第四布线的电位设定为使晶体管162处于截止状态的电位,使晶体管162处于截止状态,从而保持晶体管160的栅电极的电位(信息保持)。 Then, the potential of the fourth wiring is set so that the potential in the off state of the transistor 162, the transistor 162 in an off state, thereby maintaining the potential of the gate electrode of the transistor 160 (information holding).

[0065] 因为晶体管162的截止电流极小,因此在长时间内保持晶体管160的栅电极的电位。 [0065] Since the off-current of the transistor 162 is extremely small, thus holding the potential of the gate electrode of the transistor 160 for a long time. 例如,在晶体管160的栅电极的电位为使晶体管160处于导通状态的电位的情况下,在长时间内保持晶体管160的导通状态。 For example, the potential of the gate electrode of the transistor 160 is at the potential in the on state of the transistor 160, the transistor 160 remains in a conducting state for a long time. 另外,在晶体管160的栅电极的电位为使晶体管160 处于截止状态的电位的情况下,在长时间内保持晶体管160的截止状态。 Further, the potential of the gate electrode of the transistor 160 at the potential of the off state of the transistor 160, the transistor 160 remains off for a long time.

[0066] 下面,说明信息的读出。 [0066] Next, the read information. 如上所述,当在如上所述地保持晶体管160的导通状态或截止状态并将预定的电位(低电位)施加到第一布线时,第二布线的电位值根据晶体管160 的导通状态或截止状态而变化。 As described above, when in the ON state or OFF state of the transistor 160 is held as described above and a predetermined potential (low potential) is applied to the first wiring, the second wiring potential value in accordance with the conduction state of the transistor 160 or off state changes. 例如,在晶体管160处于导通状态的情况下,第二布线的电位受第一布线的电位地影响而降低。 For example, in a case where in the on state of the transistor 160, the potential of the second wiring is reduced by the potential influence of the first wiring. 另一方面,在晶体管160处于截止状态的情况下,第二布线的电位不变化。 On the other hand, in the case where the transistor 160 in an off state, the potential of the second line does not change.

[0067] 如上所述,通过在保持信息的状态下将第二布线的电位和预定的电位进行比较, 可以读出信息。 [0067] As described above, by maintaining the state information and the potential of the second predetermined potential wiring comparing the information can be read out.

[0068] 下面,说明信息的重写。 [0068] Next, rewriting of information. 以与上述地信息的写入及保持类似的方式,进行信息的重写。 Writing information to the above-described manner and the holding in a similar manner, overwriting of information. 就是说,将第四布线的电位设定为使晶体管162处于导通状态的电位,从而使晶体管162处于导通状态。 That is, the potential of the fourth wiring is set so that the potential in the conductive state of transistor 162 such that transistor 162 in a conducting state. 由此,将第三布线的电位(与新的信息有关的电位)施加到晶体管160 的栅电极。 Accordingly, the potential of the third wiring (with the new information about the potential) applied to the gate electrode of the transistor 160. 然后,将第四布线的电位设定为使晶体管162处于截止状态的电位,从而使晶体管162处于截止状态,因而新的信息被保持。 Then, the potential of the fourth wiring is set so that the potential of the transistor 162 in an off state, so that the transistor 162 in an off state, and thus new information is maintained.

[0069] 如上所述,在根据所公开的发明的实施例的半导体装置中,可以通过再次写入信息而直接重写信息。 [0069] As described above, in the semiconductor device according to the embodiment of the disclosed invention, by writing information again in accordance with the direct overwrite information. 由此,不需要快闪存储器等所需要的擦除操作;因而可以抑制由于擦除操作导致的操作速度的降低。 This eliminates the need of a flash memory erase operation required; decrease can be suppressed due to the erase operation results in the operation speed. 换而言之,可以实现半导体装置的高速操作。 In other words, it is possible to achieve high speed operation of the semiconductor device.

[0070] 注意,在上述说明中,使用以电子为载流子的n型晶体管(n沟道晶体管)的情况, 但是,不用说也可以使用以空穴为载流子的P型晶体管代替n型晶体管。 [0070] Note that, in the above description, the use of an n-type transistor (n-channel transistor) for the electronic carrier, but, needless to say that P-type transistor may be used as a hole in the carrier instead of n type transistor.

[0071] 另外,当然,也可以对晶体管160的栅电极附加电容器等,以使得容易保持晶体管160的栅电极的电位。 [0071] Further, of course, also be attached to the gate electrode of transistor 160 such as a capacitor, so that the potential of the transistor easier to keep the gate electrode 160.

[0072]〈半导体装置的平面结构及截面结构〉 [0072] <planar structure and a sectional structure of a semiconductor device>

[0073] 图2A和图2B示出上述半导体装置的结构的一个例子。 [0073] FIGS. 2A and 2B illustrates an example of a structure of the semiconductor device. 图2A和图2B分别是半导体装置的截面图和半导体装置的平面图。 2A and 2B are a plan view and a cross-sectional view of a semiconductor device of a semiconductor device. 这里,图2A相当于沿图2B的线A1-A2及线B1-B2 的截面。 Here, FIG. 2A corresponds to FIG. 2B is a cross-sectional along line A1-A2 and B1-B2 of the line. 图2A和图2B所示的半导体装置包括在下部的使用氧化物半导体以外的材料的晶体管160以及在上部的使用氧化物半导体的晶体管162。 2A and 2B comprises a semiconductor device shown in the lower portion of the outside of an oxide semiconductor material using an oxide semiconductor transistor 160 and the transistor 162 in the upper portion. 注意,尽管在晶体管160及晶体管162都是n型晶体管的情况下进行说明,但是也可以采用p型晶体管。 Note that, although explained in the case of the transistor 160 and the transistor 162 are n-type transistor, the p-type transistor may be employed. 尤其是,使用p型晶体管作为晶体管160是容易的。 In particular, the transistor 160 is as easy to use p-type transistor.

[0074] 晶体管160具有:对于包含半导体材料的衬底100设置的沟道形成区域116 ;以其间夹着沟道形成区域116的方式设置的杂质区域114以及其间夹着沟道形成区域116的高浓度杂质区域120 (也将这些区域总称为杂质区域);设置在沟道形成区域116上的栅极绝缘层108 ;设置在栅极绝缘层108上的栅电极110 ;以及电连接到杂质区域114的源电极或漏电极130a以及源电极或漏电极130b。 [0074] The transistor 160 has: a channel 100 is provided for a substrate containing a semiconductor material region 116 is formed; interposed therebetween to form a channel impurity region 114 provided in a region 116 interposed therebetween, and a channel forming region 116 of the high concentration impurity region 120 (also referred to as the total area of ​​these impurity region); a gate insulating layer 108 is formed on the channel region 116; a gate electrode disposed on the gate insulating layer 108, 110; and 114 electrically connected to the impurity region a source or drain electrode 130a and the source or drain electrode 130b.

[0075] 这里,在栅电极110的侧面设置侧壁绝缘层118。 [0075] Here, the gate electrode 110 on the side of the sidewall insulating layer 118 is provided. 另外,在衬底100的在平面图中不重叠于侧壁绝缘层118的区域中设置高浓度杂质区域120。 Further, high-concentration impurity region 120 is provided in the region of the substrate 100 is not overlapped with the side wall insulating layer 118 in a plan view. 在高浓度杂质区域120上设置金属化合物区域124。 A metal compound on the region 124 of high concentration impurity region 120. 在衬底100上,围绕晶体管160地设置有元件隔离绝缘层106,并且设置层间绝缘层126及层间绝缘层128以覆盖晶体管160。 On the substrate 100, 160 is provided to surround the transistor element isolation insulating layer 106, and disposed between the interlayer insulating layer 126 and the interlayer insulating layer 128 to cover the transistor 160. 源电极或漏电极130a和源电极或漏电极130b通过形成在层间绝缘层126及层间绝缘层128中的开口电连接到金属化合物区域124。 The source or drain electrode 130a and the source or drain electrode 130b in the interlayer insulating layer 126 and the interlayer insulating layer 128 in the openings is electrically connected to the metal compound region 124 is formed. 换而言之,源电极或漏电极130a和源电极或漏电极130b经由金属化合物区域124电连接到高浓度杂质区域120及杂质区域114。 In other words, the source or drain electrode and the source electrode 130a or drain electrode 130b connected to the high concentration impurity region 120 and the impurity region 114 through a region 124 is electrically metal compound. 另外,栅电极110电连接到以与源电极或漏电极130a和源电极或漏电极130b类似的方式设置的电极130c。 Further, the gate electrode 130c connected to the electrode 110 with the source or drain electrode 130a or drain electrode and the source electrode 130b in a similar manner.

[0076] 晶体管162具有:设置在层间绝缘层128上的栅电极136d、设置在栅电极136d 上的栅极绝缘层138、设置在栅极绝缘层138上的氧化物半导体层140、设置在氧化物半导体层140上且电连接到氧化物半导体层140的源电极或漏电极142a以及源电极或漏电极142b。 [0076] Transistor 162 has: a gate insulating layer disposed on the interlayer insulating layer 128 of the gate electrode 136d, 136d is provided over the gate electrode 138, an oxide semiconductor layer disposed on the gate insulating layer 138 is 140, provided and the oxide semiconductor layer 140 is electrically connected to the oxide semiconductor layer, a source electrode 140 and the source or drain electrode 142a or drain electrode 142b.

[0077] 这里,栅电极136d被设置为嵌入在形成在层间绝缘层128上的绝缘层132中。 [0077] Here, the gate electrode 136d is provided to be embedded in the insulating layer 132 is formed on the interlayer insulating layer 128.. 另夕卜,与栅电极136d类似的,电极136a、电极136b电极136c被形成为分别与源电极或漏电极130a、源电极或漏电极130b以及电极130c接触。 Another Bu Xi, similar to the gate electrode 136d, the electrode 136a, the electrode 136b is formed to the electrode 136c and the source or drain electrode 130a, the source or drain electrode 130b, and 130c contact electrode.

[0078] 在晶体管162上,与氧化物半导体层140的一部分接触地设置保护绝缘层144。 [0078] In the transistor 162, a portion in contact with the oxide semiconductor layer 140 provided the protective insulating layer 144. 在保护绝缘层144上设置有层间绝缘层146。 An insulating layer 146 is provided over the protective interlayer insulating layer 144. 这里,在保护绝缘层144和层间绝缘层146中,形成有到达源电极或漏电极142a和源电极或漏电极142b的开口。 Here, in the inter-layer insulating layer 144 and the protective insulating layer 146 is formed reaching the source or drain electrode 142a and the source or drain electrode 142b of the opening. 在所述开口中,电极150d 及电极150e被形成为分别接触于源电极或漏电极142a和源电极或漏电极142b。 In the opening, the electrode 150d and the electrode 150e are formed to contact the source or drain electrode 142a and the source or drain electrode 142b. 与电极150d及电极150e类似地,电极150a、电极150b以及电极150c被形成为在设置在栅极绝缘层138、保护绝缘层144和层间绝缘层146中的开口中,分别接触于电极136a、电极136b以及电极136c。 Electrode 150d and 150e and the electrode Similarly, the electrodes 150a, 150b and the electrode 150c is formed as an electrode disposed on the gate insulating layer 138, the protective insulating layer 144 and the interlayer insulating layer 146 in the openings, are in contact with the electrodes 136a, electrode 136b and the electrode 136c.

[0079] 这里,氧化物半导体层140优选为充分去除诸如氢等杂质而被高度纯度化的氧化物半导体层。 [0079] Here, the oxide semiconductor layer 140 is preferably sufficiently remove impurities such as hydrogen and the like is highly purified oxide semiconductor layer. 具体地说,氧化物半导体层140中的氢浓度为小于或者等于5 X 1019原子/cm3, 优选为小于或者等于5 X 1018原子/cm3,更优选为小于或者等于5 X 1017原子/cm3。 Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is less than or equal to 5 X 1019 atoms / cm3, preferably less than or equal to 5 X 1018 atoms / cm3, more preferably less than or equal to 5 X 1017 atoms / cm3. 氧化物半导体层140优选是通过含有充分的氧而使由于氧缺乏导致的缺陷得到减少的氧化物半导体层。 The oxide semiconductor layer 140 preferably contains sufficient oxygen defects are due to the oxygen deficiency due to the resulting reduction of the oxide semiconductor layer. 在其中氢浓度充分降低且由于氧缺乏导致的缺陷得到减少的高度纯化的氧化物半导体层140中,载流子浓度为小于为1 X 1012/cm3,优选为小于或者等于1 X 10n/cm3。 In which the hydrogen concentration is sufficiently reduced due to the oxygen deficiency and deficiency leads to reduction of the obtained highly purified oxide semiconductor layer 140 is smaller than the carrier concentration of 1 X 1012 / cm3, preferably less than or equal to 1 X 10n / cm3. 以这样的方式,通过使用使其成为i型(本征)氧化物半导体或基本上i型的氧化物半导体,可以得到截止电流特性极为优良的晶体管162。 In this manner, by making use of an i-type (intrinsic) or substantially i-type oxide semiconductor is an oxide semiconductor can be obtained an extremely excellent in off-current characteristics of the transistor 162. 例如,在漏极电压Vd为+1V或+10V且栅极电压Vg为-5V至-20V的情况下,截止电流为小于或者等于1 X 10-13A。 For example, the drain voltage Vd or + 10V to + 1V and the gate voltage Vg is -5V to -20V case, the cut-off current is less than or equal to 1 X 10-13A. 当使用其中氢浓度得到充分降低并且由于氧缺乏导致的缺陷得到减少的高度纯化的氧化物半导体层140,并且降低了晶体管162的截止电流时,可以实现具有新的结构的半导体装置。 Wherein when a hydrogen concentration is sufficiently reduced due to oxygen deficiency and lead to defect reduction obtained highly purified oxide semiconductor layer 140, and reduces the current of the transistor 162 can be achieved a semiconductor device having a new structure. 另外,使用二次离子质谱(SIMS)测量上述氧化物半导体层140中的氢浓度。 Further, the use of secondary ion mass spectrometry (SIMS) measurement of the hydrogen concentration in the oxide semiconductor layer 140.

[0080] 另外,在层间绝缘层146上设置有绝缘层152。 [0080] Further, an insulating layer 152 on the interlayer insulating layer 146. 电极154a、电极154b、电极154c以及电极154d设置为嵌入该绝缘层152中。 Electrode 154a, an electrode 154b, an electrode 154c and the electrode 154d is provided to be embedded in the insulating layer 152. 这里,电极154a接触于电极150a,电极154b接触于电极150b,电极154c接触于电极150c及电极150d,并且电极154d接触于电极150e。 Here, the electrode 154a in contact with the electrode 150a, the electrode 154b in contact with the electrode 150b, an electrode 154c in contact with the electrode 150c and the electrode 150 d, 154d and the electrode in contact with the electrode 150e.

[0081] 就是说,在图2A和2B所示的半导体装置中,晶体管160的栅电极110经由电极130c、电极136c、电极150c、电极154c以及电极150d电连接到晶体管162的源电极或漏电极142a。 [0081] That is, in the semiconductor device shown in FIG. 2A and 2B, the gate electrode 110 of the transistor 160 is connected to the source electrode or the drain of the transistor 162 via the electrodes 130c, 136c electrode, an electrode 150c, 154c and the electrode pole electrodes 150d 142a.

[0082]〈半导体装置的制造方法〉 [0082] <Method for Manufacturing Semiconductor Device>

[0083] 下面说明上述半导体装置的制造方法的一个例子。 [0083] Examples of a method of manufacturing the semiconductor device will be described below. 首先,参考图3A至3H说明下部的晶体管160的制造方法,然后,参考图4A至4G和图5A至®说明上部的晶体管162的制造方法。 First, with reference to FIGS. 3A to 3H illustrate a method for manufacturing a lower transistor 160, and then, with reference to FIGS. 4A to 4G and 5A ® manufacturing method of the transistor 162 of the upper portion.

[0084]〈下部的晶体管的制造方法〉 [0084] <Method for producing a transistor of the lower portion>

[0085] 首先,制备包含半导体材料的衬底100 (见图3A)。 [0085] First, a substrate 100 comprising a semiconductor material (see FIG. 3A). 作为包含半导体材料的衬底100,可以使用含硅或碳化硅等的单晶半导体衬底或多晶半导体衬底、含硅锗等的化合物半导体衬底、或SOI衬底等。 The single crystal semiconductor substrate 100, a silicon or silicon carbide and the like may be used as the substrate comprises a semiconductor material or a polycrystalline semiconductor substrate, a silicon germanium, a compound semiconductor substrate, an SOI substrate, or the like. 这里,示出使用单晶硅衬底作为包含半导体材料的衬底100的一个例子。 Here, a substrate comprising a semiconductor material as an example of the single crystal silicon substrate 100 is used.

[0086] 在衬底100上形成作为用于形成元件隔离绝缘层的掩模的保护层102 (见图3A)。 [0086] is formed as a mask for forming the element isolation insulating layer, a protective layer 102 (see FIG. 3A) on the substrate 100. 作为保护层102,例如可以使用以氧化硅、氮化硅、或氮氧化硅等形成的绝缘层。 As the protective layer 102, for example, an insulating layer of silicon oxide, silicon nitride, silicon oxynitride, or the like. 注意,在上述步骤之前或之后,可以将赋予n型导电性的杂质元素和赋予p型导电性的杂质元素添加至附底100,以控制晶体管的阈值电压。 Note that before or after the above step, may be n-type conductivity imparting impurity element and the impurity element imparting p-type conductivity is added to the end attachment 100, in order to control the threshold voltage of the transistor. 在衬底100中所含的半导体材料为硅时,可以使用磷或砷等作为赋予n型导电性的杂质。 The semiconductor material contained in the substrate 100 is silicon, phosphorus or arsenic and the like may be used as the n-type conductivity imparting impurity. 另外,例如可以使用硼、铝、或镓等作为赋予p型导电性的杂质。 Further, for example, using a boron, aluminum, gallium, or imparting p-type conductivity as an impurity.

[0087] 接着,利用上述保护层102作为掩模,通过蚀刻来去除未覆盖有保护层102的区域(露出的区域)中的衬底100的部分。 [0087] Next, the protective layer 102 as a mask to remove a portion of the (exposed region) region of the protective layer 102 uncovered substrate 100 by etching. 由此,形成隔离的半导体区域104 (见图3B)。 Thus, a semiconductor isolation region 104 (see FIG. 3B). 该蚀刻优选使用干蚀刻,但是也可以使用湿蚀刻。 The etching is preferably dry etching, wet etching may be used. 可以根据待蚀刻的对象的材料适当地选择蚀刻气体和蚀刻剂。 Can be suitably selected according to the etching gas and an etchant material to be etched objects.

[0088] 接着,形成绝缘层以覆盖半导体区域104,并且选择性地去除与半导体区域104重叠的区域中的该绝缘层,从而形成元件隔离绝缘层1〇6(见图3B)。 [0088] Next, the insulating layer is formed to cover the semiconductor region 104, and selectively removing the insulating layer region 104 overlapping with the semiconductor region, thereby forming the element isolation insulating layer 1〇6 (see FIG. 3B). 该绝缘层使用氧化硅、氮化硅、或氮氧化硅等而形成。 The insulating layer using silicon oxide, silicon nitride, silicon oxynitride, or the like is formed. 作为该绝缘层的去除方法,有CMP等抛光处理或蚀刻处理等, 可以使用任意这些方法。 As a method of removing the insulating layer, with a polishing treatment such as CMP or etching treatment or the like, any of these methods may be used. 注意,在形成半导体区域104之后,或者,在形成元件隔离绝缘层106之后,去除上述保护层102。 Note that, after forming the semiconductor region 104, or, after forming the element isolation insulating layer 106, the protective layer 102 is removed.

[0089] 接着,在半导体区域104上形成绝缘层,并在该绝缘层上形成包含导电材料的层。 [0089] Next, the insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material on the insulating layer. [0090] 该绝缘层之后将作为栅极绝缘层,并且该绝缘层优选具有采用通过CVD法或溅射法等得到的包含氧化硅、氮氧化硅、氮化硅、氧化铪、氧化铝、或氧化钽等的膜的单层结构或多层结构。 [0090] After the insulating layer as the gate insulating layer, and the insulating layer preferably has adopted by CVD or sputtering method or the like comprising silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or a single layer structure or a multilayer structure of a tantalum oxide film or the like. 替代地,可以通过高密度等离子体处理或热氧化处理来使半导体区域104的表面氧化或氮化,来形成上述绝缘层。 Alternatively, plasma treatment or thermal oxidation treatment to the surface of the oxidizing or nitriding the semiconductor region 104, the insulating layer is formed by high-density. 例如,可以使用诸如He、Ar、Kr、或Xe等稀有气体和诸如氧、氧化氮、氨、氮、或氢等的混合气体来进行高密度等离子体处理。 For example, a high-density plasma treatment to be a mixed gas of He, Ar, Kr, Xe, or the like and a rare gas such as oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, or the like, such as. 另外,对该绝缘层的厚度没有特别的限制,但是其厚度可以为大于或等于lnm且小于或者等于100nm。 Further, there is no particular restriction on the thickness of the insulating layer, the thickness thereof may be equal to or greater than lnm and less than or equal to 100nm.

[0091] 包含导电材料的层可以使用诸如铝、铜、钛、钽、或钨等的金属材料形成。 [0091] The layer may comprise a conductive material such as aluminum, copper, titanium, tantalum, tungsten, or a metal material. 替代地, 可以使用诸如包含导电材料的多晶硅等的半导体材料形成所述包含导电材料的层。 Alternatively, the polysilicon may be used as a conductive material comprising a semiconductor material forming said layer containing a conductive material. 对形成包含导电材料的层方法也没有特别的限制,可以使用诸如蒸镀法、CVD法、溅射法、旋涂法等的各种成膜方法。 There is no particular limitation on the method of forming a layer containing a conductive material, such as various deposition methods may be used a vapor deposition method, CVD method, a sputtering method, a spin coating method or the like. 此外,在本实施例中,说明了使用金属材料形成包含导电材料的层的情况的例子。 Further, in the present embodiment, an example case of using a metal material comprising a layer of conductive material.

[0092] 然后,通过选择性地蚀刻该绝缘层和包含导电材料的层,形成栅极绝缘层108和栅电极110。 [0092] Then, a layer of conductive material by selectively etching the insulating layer containing the gate insulating layer 108 and the gate electrode 110 is formed. (见图3C)。 (See Fig. 3C).

[0093] 接着,形成覆盖栅电极110的绝缘层112 (见图3C)。 [0093] Next, an insulating layer 112 covering the gate electrode 110 is formed (see FIG. 3C). 然后,将磷(P)或砷(As)等添加到半导体区域104,在衬底100中形成浅结深的杂质区域114(见图3C)。 Then, phosphorus (P) or arsenic (As) and the like added to the semiconductor region 104 to form a shallow junction depth of the impurity region 114 (see FIG. 3C) in the substrate 100. 注意,虽然这里添加磷或砷以形成n沟道晶体管,然而在形成p沟道晶体管时可以添加硼(B)或铝(A1) 等的杂质元素。 Note that, although the addition of phosphorus or arsenic to form an n-channel transistor, however, may be added boron (B) or aluminum (A1) or the like when an impurity element is formed in the p-channel transistor. 另外,通过形成杂质区域114,在栅极绝缘层108下的半导体区域104中形成沟道形成区域116 (见图3C)。 Further, 114, a channel formation region 116 (see FIG. 3C) is formed by an impurity region in the semiconductor region 104 under the gate insulating layer 108. 在此,可以适当地设定所添加的杂质的浓度,在半导体元件被高微细化的情况下优选将浓度设置得高。 Here, the concentration may be suitably set the added impurity concentration is preferably set to be high in a case where the semiconductor element is miniaturized high. 此外,虽然这里采用在形成杂质区域114之后形成绝缘层112的工艺,但是也可以采用在形成绝缘层112之后形成杂质区域114的工艺。 Furthermore, although the process using the insulating layer 112 is formed after forming impurity regions 114, the process may be employed in the impurity region 114 is formed after the insulating layer 112 is formed.

[0094] 接着,形成侧壁绝缘层118 (见图3D)。 [0094] Subsequently, a sidewall insulating layer 118 (see FIG. 3D) is formed. 覆盖绝缘层112地形成绝缘层,之后通过对该绝缘层进行高各向异性的蚀刻处理,来以自对准的方式形成侧壁绝缘层118。 An insulating layer is formed to cover the insulating layer 112, followed by highly anisotropic etching process through the insulating layer, a self-aligned manner to form a side wall insulating layer 118. 此时,优选对绝缘层112进行部分蚀刻,从而暴露栅电极110的顶表面和杂质区域114的顶表面。 In this case, it is preferable for the insulating layer 112 is partially etched to expose the top surfaces of the gate and the impurity region 114 of the electrode 110. [0095] 接着,形成绝缘层以覆盖栅电极110、杂质区域114和侧壁绝缘层118等。 [0095] Next, the insulating layer is formed to cover the gate electrode 110, the impurity region 114 and the side wall insulating layer 118 and the like. 然后, 将磷(P)或砷(As)等添加到该绝缘层与杂质区域114接触的区域,从而形成高浓度杂质区域120 (见图3E)。 Then, phosphorus (P) or arsenic (As) and the like is added to the region of the insulating layer in contact with the impurity region 114, so that high-concentration impurity region 120 (see FIG. 3E) is formed. 然后,通过去除上述绝缘层,形成金属层122以覆盖栅电极110、侧壁绝缘层118和高浓度杂质区域120等(见图3E)。 Then, by removing the insulating layer, the metal layer 122 is formed to cover the gate electrode 110, sidewall 118, and the high concentration impurity region of the insulating layer 120 and the like (see FIG. 3E). 该金属层122可以使用诸如真空蒸镀法、溅射法或旋涂法等的任意的各种方法形成。 The metal layer 122 may be formed using any of various methods such as a vacuum deposition method, a sputtering method or a spin coating method or the like. 优选使用与半导体区域104中所含的半导体材料起反应来形成低电阻的金属化合物的金属材料形成金属层122。 The metal layer 122 is preferable to use a metal material and a semiconductor material contained in the semiconductor region 104 react to form a low resistance metal compound is formed. 作为上述金属材料的示例, 有钦、组、鹤、镇、钻、销等。 As examples of the metal material, there Chin, group, crane, town, drills, pins and the like.

[0096] 接着,进行热处理,从而使金属层122与半导体材料起反应。 [0096] Next, heat treatment is performed, so that the metal layer 122 reacts with the semiconductor material. 由此,形成与高浓度杂质区域120接触的金属化合物区域124(见图3F)。 Thereby, a metal compound in contact with the region of high concentration impurity regions 120 124 (see FIG. 3F). 另外,在使用多晶硅等作为栅电极110 的情况下,栅电极110的与金属层122接触的部分也具有金属化合物区域。 Further, the use of polycrystalline silicon as the gate electrode 110, the portion of the metal layer 122 in contact with the gate electrode 110 also has a metal compound region.

[0097]作为上述热处理,可以使用利用闪光灯进行照射的热处理。 [0097] Examples of the heat treatment, the heat treatment may be used with a flash irradiation. 当然,也可以使用其他热处理方法,但是优选使用可以实现极短时间热处理的方法,以提高在金属化合物形成过程中的化学反应的可控性。 Of course, also other heat treatment method is preferably used an extremely short time heat treatment method can be implemented to improve the controllability of the process of chemical reaction to form the metal compound. 另外,上述金属化合物区域通过金属材料与半导体材料之间的反应而形成,并且具有充分提高的电导率。 Further, the metal compound region is formed by a reaction between a metal material and a semiconductor material, and having a sufficiently increased electrical conductivity. 通过形成该金属化合物区域,可以充分降低电阻,并可以提高元件特性。 By forming the metal compound region can be sufficiently reduced resistance, and can improve device characteristics. 在形成金属化合物区域124之后,去除金属层122。 After the formation of the metal compound region 124, metal layer 122 is removed.

[0098]接着,形成层间绝缘层126和层间绝缘层128以覆盖上述步骤中形成的各部件(见图3G)。 [0098] Next, each component interlayer insulating layer 126 and the interlayer insulating layer 128 is formed so as to cover the above steps (see FIG. 3G) is formed. 层间绝缘层126和层间绝缘层128可以使用包含诸如氧化硅、氮氧化硅、氮化硅、 氧化铪、氧化铝、或氧化钽等无机绝缘材料形成。 The interlayer insulating layer 126 and the interlayer insulating layer 128 may be formed using a silicon containing oxide such as, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or inorganic insulating material. 替代地,可以使用诸如聚酰亚胺或丙烯酸树脂等有机绝缘材料。 Alternatively, an organic insulating material such as polyimide or acrylic resin. 注意,虽然这里层间绝缘层126和层间绝缘层128形成两层结构,但是这些层间绝缘层的结构不限于此。 Note that, here, although the inter-layer insulating layer 126 and the interlayer insulating layer 128 is formed two-layer structure, but the structure of the insulating layer between these layers is not limited thereto. 注意,在形成层间绝缘层128之后,优选对层间绝缘层128的表面进行CMP或蚀刻处理等而使其平坦化。 Note that, after forming the interlayer insulating layer 128, preferably the surface of the interlayer insulating layer 128 is etched by CMP or the like planarized process.

[0099]然后,在上述层间绝缘层中形成到达金属化合物区域124的开口,并在该开口中形成源电极或漏电极130a和源电极或漏电极130b (见图3H)。 [0099] Then, an opening formed region 124 reaches the metal compound in the interlayer insulating layer, and forming a source or drain electrode 130a and the source or drain electrode 130b (see Fig. 3H) in the opening. 例如,可以如下形成源电极或漏电极130a和源电极或漏电极130b :使用PVD法或CVD法等在包括所述开口的区域中形成导电层;然后使用蚀刻或CMP等去除上述导电层的一部分。 For example, can be formed by a source or drain electrode 130a and the source or drain electrode 130b: using a PVD method or a CVD method, a conductive layer is formed in a region including the opening; then using a part of the conductive layer is removed by etching or the like CMP .

[0100] 注意,在通过去除上述导电层的一部分而形成源电极或漏电极130a和源电极或漏电极130b的情况下,优选对其表面进行处理以使其平坦。 [0100] Note that, the source electrode is formed by removing a portion of the conductive layer 130a or drain electrode and the source electrode or the drain electrode 130b, it is preferable to process its surface planarized. 例如,在包含所述开口的区域中形成厚度薄的钛膜或氮化钛膜等,然后形成钨膜以嵌入所述开口中的情况下,通过在此之后进行CMP,可以在去除钨膜、钛膜或氮化钛膜等的不需要的部分,并且可以改善表面的平坦度。 For example, an opening is formed in a region including the thickness of the titanium film or a titanium nitride film, a tungsten film is formed and then fitted to the opening of the case, by performing CMP Thereafter, the tungsten film can be removed, unnecessary portions of the titanium film or a titanium nitride film, and can improve the surface flatness. 通过对包含源电极或漏电极130a和源电极或漏电极130b的表面的表面进行平坦化,可以在之后的步骤中形成优良的电极、布线、绝缘层或半导体层等。 By planarized electrode 130a and the source or drain electrode 130b of the surface comprises a surface of the source electrode or drain, excellent electrode, a wiring, a semiconductor layer, insulating layer, or the like may be formed in a subsequent step.

[0101] 注意,虽然仅描述了与金属化合物区域124接触的源电极或漏电极130a和源电极或漏电极130b,但是也可以在同一步骤中形成接触栅电极110的电极(例如,图2A中的电极130c)等。 [0101] Note that, while only the source electrode or drain electrode in contact with the metal compound region 124 electrode 130a and the source or drain electrode 130b, but may be in contact with the gate electrode 110 is formed in the same step (e.g., FIG. 2A electrodes 130c) and the like. 对可以用作源电极或漏电极130a和源电极或漏电极130b的材料没有特别的限制,并且可以使用任意的各种导电材料。 There is no particular limitation on may be used as the source or drain electrode and the source electrode 130a or drain electrode 130b material, and may be any of various conductive materials. 例如,可以使用诸如钥、钛、铬、钽、钨、铝、铜、钕或钪等导电材料。 For example, a conductive material such as a key, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium.

[0102] 通过上述工艺,形成使用包含半导体材料的衬底100的晶体管160。 [0102] Through the above process, the transistor 160 is formed using a substrate 100 including a semiconductor material. 另外,也可以在进行上述工艺之后,形成电极、布线或绝缘层等。 Further, the above process may be performed after forming an electrode, a wiring or the insulating layer and the like. 在使用其中层叠层间绝缘层和导电层的多层布线结构作为布线的结构时,可以提供高度集成的半导体装置。 When used in which inter-layer insulating layer and the laminated structure of the conductive layer of the multilayer wiring structure of a wiring, a semiconductor device can be highly integrated.

[0103]〈上部的晶体管的制造方法〉 [0103] <Method for producing a transistor of the upper portion>

[0104] 接着,参考图4A至4G及图5A至®说明在层间绝缘层128上制造晶体管162的工艺。 [0104] Next, with reference to FIGS. 4A to 4G and 5A to illustrate the process of manufacturing ® transistor 162 in the interlayer insulating layer 128. 注意,图4A至4G及图5A至®示出了在层间绝缘层128上的各种电极和晶体管162 等的制造工艺,而省略了在晶体管162下的晶体管160等。 Note that, FIGS. 4A to 4G and 5A to illustrate various electrode ® transistor 162 and the like on the interlayer insulating layer 128 of the fabrication process, the transistor 160 is omitted in the transistor 162, and the like.

[0105] 首先,在层间绝缘层128、源电极或漏电极130a、源电极或漏电极130b、以及电极130c上形成绝缘层132 (见图4A)。 [0105] First, the interlayer insulating layer 128, a source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 (see FIG. 4A) is formed on the electrode 130c. 可以使用PVD法或CVD法等形成绝缘层132。 Insulating layer 132 may be formed using a PVD method or a CVD method. 可以使用包含诸如氧化硅、氮氧化硅、氮化硅、氧化铪、氧化铝、或氧化钽等无机绝缘材料的材料形成绝缘层132。 Containing materials may be used such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or an inorganic insulating material forming the insulating layer 132.

[0106] 接着,在绝缘层132中形成到达源电极或漏电极130a、源电极或漏电极130b、以及电极130c的开口。 [0106] Next, reach the source or drain electrode 130a in the insulating layer 132, the source or drain electrode 130b, an electrode 130c, and an opening. 此时,在要形成栅电极136d的区域中形成另一开口。 At this point, another opening is formed in a region to be formed in the gate electrode 136d. 然后,将导电层134形成为嵌入上述开口中(见图4B)。 Then, the conductive layer 134 is formed to be embedded in the opening (see FIG. 4B). 例如,上述开口可以使用掩模通过蚀刻等方法形成。 For example, the opening may be formed by etching or the like using a mask. 该掩模通过例如使用光掩模的曝光等方法形成。 The mask is formed by, for example, exposure using a photomask or the like. 对于所述蚀刻,可以使用湿蚀刻或干蚀刻, 但是从微细处理的观点来看,优选使用干蚀刻。 For the etching, wet etching or dry etching, but from the viewpoint of fine processing, it is preferable to use dry etching. 导电层134可以通过诸如PVD法或CVD法等的沉积方法形成。 Conductive layer 134 may be formed by a deposition method such as PVD or CVD and the like. 作为可以用于导电层134的材料的例子,可以举出诸如钥、钛、铬、钽、 钨、铝、铜、钕或钪等导电材料、任意这些材料的合金、以及含任意这些材料的化合物(例如, 任意这些材料的氮化物)等。 As examples of the material for the conductive layer 134 may include a conductive material such as a key, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, alloys of any of these materials, and a compound containing any of these materials (e.g., a nitride of any of these materials) and the like.

[0107] 更具体地说,例如,可以如下形成导电层134 :在包括所述开口的区域中使用PVD 法形成厚度薄的钛膜,并且使用CVD法形成厚度薄的氮化钛膜,然后形成钨膜以嵌入在所述开口中。 [0107] More specifically, for example, conductive layer 134 can be formed by: a thin titanium film using a PVD method including the opening region is formed, a thin titanium nitride film is formed using a CVD method, and then formed a tungsten film is embedded in the opening. 这里,通过PVD法形成的钛膜具有如下功能:将与下面的电极(这里,源电极或漏电极130a、源电极或漏电极130b、或电极130c等)的界面处的氧化膜还原而降低与下面的电极的接触电阻。 Here, the titanium film formed by a PVD method has a function of: an oxide film reduction at the underlying electrode (here, a source or drain electrode 130a, the source or drain electrode 130b, or the electrode 130c and the like) of the interface decreases with the contact resistance of the electrode below. 另外,之后形成的氮化钛膜具有抑制导电材料的扩散的阻挡功能。 Further, after forming a titanium nitride film having a conductive material suppressing diffusion barrier function. 另外, 也可以在由钛或氮化钛等形成阻挡膜之后,使用镀法形成铜膜。 Further, after the barrier film may be formed of titanium or titanium nitride, a copper film is formed using the plating method.

[0108] 在形成导电层134之后,通过蚀刻处理或CMP等去除导电层134的一部分,从而暴露绝缘层132,并形成电极136a、电极136b、电极136c以及栅电极136d (见图4C)。 [0108] After the conductive layer 134 is formed by etching or the like part of the conductive layer 134 is removed by CMP, thereby exposing the insulating layer 132, and forming an electrode 136a, an electrode 136b, an electrode 136c and the gate electrode 136d (see FIG. 4C). 注意, 在去除上述导电层134的一部分以形成电极136a、电极136b、电极136c以及栅电极136d 时,优选进行处理以获得平坦表面。 Note that, a part of the conductive layer 134 is removed to form an electrode 136a, an electrode 136b, an electrode 136c and the gate electrode 136d, the process is preferably performed to obtain a flat surface. 通过将绝缘层132、电极136a、电极136b、电极136c以及栅电极136d的表面处理为平坦,可以在之后的步骤中形成优良的电极、布线、绝缘层、或半导体层等。 A flat, fine electrode, a wiring, an insulating layer, a semiconductor layer, or the like may be formed by the subsequent step 132, the electrode 136a, the electrode 136b, an electrode 136c and the electrode surface of the gate insulating layer 136d process.

[0109] 接着,形成栅极绝缘层138以覆盖绝缘层132、电极136a、电极136b、电极136c以及栅电极136d(见图4D)。 [0109] Next, a gate insulating layer 138 is formed to cover the insulating layer 132, the electrode 136a, the electrode 136b, an electrode 136c and the gate electrode 136d (see FIG. 4D). 栅极绝缘层138可以通过CVD法或溅射法等形成。 The gate insulating layer 138 may be formed by a CVD method or a sputtering method. 另外,栅极绝缘层138优选包含氧化硅、氮化硅、氧氮化硅、氮氧化硅、氧化铝、氧化铪或氧化钽等。 Further, the gate insulating layer 138 preferably comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. 另外, 栅极绝缘层138可以具有单层结构或者叠层结构。 Further, the gate insulating layer 138 may have a single layer structure or a laminated structure. 例如,可以通过使用硅烷(SiH 4)、氧和氮作为原料气体的等离子体CVD法,形成氧氮化硅的栅极绝缘层138。 For example, by using silane (SiH 4), oxygen, and nitrogen source gas as a plasma CVD method, the gate insulating layer 138 of silicon oxynitride. 对栅极绝缘层138的厚度没有特别的限制,但是例如其厚度可以为大于或等于l〇nm且小于或者等于500nm。 There is no particular limitation on the thickness of the gate insulating layer 138, but for example, may have a thickness of greater than or equal to and less than or equal to l〇nm 500nm. 在使用叠层结构时,优选通过层叠厚度为大于或等于50nm且小于或者等于200nm的第一栅极绝缘层和在第一栅极绝缘层上的厚度为大于或等于5nm且小于或者等于300nm的第二栅极绝缘层来形成栅极绝缘层138。 When using the laminated structure, preferably by lamination of a thickness equal to or greater than 50nm and less than or equal to the thickness of the first gate insulating layer and 200nm on the first gate insulating layer is greater than or equal to 5nm and 300nm of less than or equal a second gate insulating layer 138 to form a gate insulating layer.

[0110] 注意,通过去除杂质而成为i型氧化物半导体或者基本上i型的氧化物半导体(高度纯化的氧化物半导体)对界面态或界面电荷极为敏感,因此在使用该氧化物半导体作为氧化物半导体层的情况下,氧化物半导体层与栅极绝缘层之间的界面是重要的。 [0110] Note that, by removing impurities becomes i-type oxide semiconductor or a substantially i-type oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to surface charge or an interface state, and therefore the use of an oxide semiconductor as an oxide the case where the compound semiconductor layer, the interface between the oxide semiconductor layer and the gate insulating layer is important. 就是说,要与高度纯化的氧化物半导体层接触的栅极绝缘层138需要具有高的质量。 That is, a gate insulating layer to be in contact with the highly purified oxide semiconductor layer 138 is required to have high quality.

[0111] 例如,使用微波(2. 45GHz )的高密度等离子体CVD法是理想的,因为可以形成致密且耐压高的高质量的栅极绝缘层138。 [0111] For example, using a microwave (2. 45GHz) high-density plasma CVD method is desirable, because a dense and high withstand voltage can be formed of a high-quality gate insulating layer 138. 以这样的方式,高度纯化的氧化物半导体层与高质量栅极绝缘层彼此接触时,界面态可以得到降低并且可以得到优良的界面特性。 In this manner, highly purified oxide semiconductor layer and a high-quality gate insulating layer in contact with each other, the interface state can be reduced and favorable interface properties can be obtained.

[0112] 当然,即使在使用如此的高度纯化的氧化物半导体层的情况下,也可以使用诸如溅射法或等离子体CVD法等的其他方法,只要能够形成优质的绝缘层作为栅极绝缘层即可。 [0112] Of course, even in the case of using such a highly purified oxide semiconductor layer, may be used other method such as a sputtering method or a plasma CVD method, the gate insulating layer can be formed as long as the quality of the insulating layer It can be. 替代地,也可以使用在形成之后通过热处理而使膜质量以及与氧化物半导体层之间的界面特性得到改善的绝缘层。 Alternatively, the insulating layer may be improved by forming after the heat treatment the interface characteristics between the film quality and the oxide semiconductor layer. 总之,只要形成作为栅极绝缘层138的膜质量优良且可以降低与氧化物半导体层的界面态密度而形成优良的界面的层都是可以接受的。 In short, as long as the layer is formed as a gate insulating film excellent in quality and 138 may reduce the interface state density of the oxide semiconductor layer to form a fine layer interface is acceptable.

[0113] 此外,在温度为85° C,电场强度为2X106V/cm且时间为12小时的偏压-温度测试(BT测试)中,如果在氧化物半导体中含有杂质,则杂质和氧化物半导体的主要成分之间的结合(combination)被强电场(B :偏压)和高的温度(T :温度)切断,并且所生成的悬挂键导致阈值电压(Vth)的偏移。 [0113] Further, at a temperature of 85 ° C, the electric field intensity of 2X106V / cm for 12 hours and bias - temperature test (BT test) and, if the impurities contained in the oxide semiconductor, the oxide semiconductor and the impurity binding between the main component (Combination) is a strong electric field (B: bias) and high temperature (T: temperature) off, and the resulting suspension keys for the threshold voltage (Vth) shift.

[0114] 另一方面,根据所公开的本发明的一个实施例,通过去除氧化物半导体的杂质,尤其是氢或水等,并在栅极绝缘层和氧化物半导体层之间实现优良的界面特性,可以得到即使在BT测试中也稳定的晶体管。 [0114] On the other hand, the present invention according to one embodiment of the disclosed embodiments, and other impurities by removing the oxide semiconductor, in particular hydrogen or water, and to achieve an excellent interface between the gate insulating layer and the oxide semiconductor layer characteristic can be obtained even when the transistor BT test is also stable.

[0115] 接着,在栅极绝缘层138上形成氧化物半导体层,并通过使用掩模的蚀刻等方法处理该氧化物半导体层,以形成岛状的氧化物半导体层140 (见图4E)。 [0115] Next, an oxide semiconductor layer on the gate insulating layer 138, by etching or the like using a mask treating the oxide semiconductor layer to form the island-shaped oxide semiconductor layer 140 (see FIG. 4E).

[0116] 作为氧化物半导体层,可以应用使用任意下述材料的氧化物半导体层:四元金属氧化物,诸如In-Sn-Ga-Zn-0;二兀金属氧化物,诸如In-Ga-Zn-0、In-Sn-Zn-0、 In-Al-Zn-0> Sn-Ga-Zn-0> Al-Ga-Zn-0> Sn-Al-Zn-0;_兀金属氧化物,诸如In_Zn_0、 Sn-Zn-O、Al-Zn-O、Zn-Mg-〇、Sn-Mg-〇、In-Mg-〇;In_0 ;Sn_0 ;以及Zn_0等。 [0116] As the oxide semiconductor layer, the oxide semiconductor layer can be applied using any of the following materials: quaternary metal oxides, such as In-Sn-Ga-Zn-0; Wu two metal oxides, such as In-Ga- Zn-0, In-Sn-Zn-0, In-Al-Zn-0> Sn-Ga-Zn-0> Al-Ga-Zn-0> Sn-Al-Zn-0; _ Wu metal oxides, such In_Zn_0, Sn-Zn-O, Al-Zn-O, Zn-Mg-square, Sn-Mg-square, In-Mg-square; in_0; Sn_0; Zn_0 and the like. 另外,上述氧化物半导体材料也可以包含Si02。 Further, the oxide semiconductor material may also comprise Si02.

[0117] 作为氧化物半导体层,可以使用以InM03 (Zn0)m (m>0)表示的薄膜。 [0117] As the oxide semiconductor layer, a thin film InM03 (Zn0) m (m> 0) expressed. 这里,M表示选自Ga、Al、Mn及Co中的一种或多种金属元素。 Here, M represents one or more metal elements selected from Ga, Al, Mn and Co in. 例如,M可以是Ga、Ga和Al、Ga和Mn、或Ga和Co等。 Example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like. 在以InM0 3 (Zn0)m (m>0)表示的、包含Ga作为M的氧化物半导体膜被称为基于In-Ga-Zn-0的氧化物半导体,并且将基于In-Ga-Zn-0的氧化物半导体的薄膜称为基于In-Ga-Zn-0的氧化物半导体膜(基于In-Ga-Zn-0的非晶膜)。 In, an oxide semiconductor containing Ga is called based on In-Ga-Zn0 M as the oxide semiconductor film, and the In-Ga-Zn- based in InM0 3 (Zn0) m (m> 0) expressed an oxide semiconductor film is referred to as a 0-based oxide semiconductor film of in-Ga-Zn-0 (the amorphous film based on in-Ga-Zn-0's).

[0118] 在本实施例中,作为氧化物半导体层,使用基于In-Ga-Zn-0的氧化物半导体靶材以用于膜形成,通过溅射法形成非晶氧化物半导体层。 [0118] In the present embodiment, as the oxide semiconductor layer, based oxide semiconductor target In-Ga-Zn-0 for the film formation, an amorphous oxide semiconductor layer is formed by sputtering. 注意,通过将硅添加到该非晶氧化物半导体层,可以抑制其晶化,因此,可以使用包含大于或等于2wt.%且小于或者等于10wt.%的Si02的祀材来形成氧化物半导体层。 Note that, by adding Si to the amorphous oxide semiconductor layer, the crystallinity can be suppressed, and therefore, can comprise greater than or equal to 2wt.% And less than or equal to 10wt.% Of Si02 of sacrificial material to form the oxide semiconductor layer .

[0119] 作为用于使用溅射法形成氧化物半导体层的靶材,例如,可以使用含氧化锌为主要成分的氧化物半导体成膜用靶材。 [0119] As a target for forming the oxide semiconductor layer is formed using a sputtering method, for example, using an oxide semiconductor containing zinc oxide as a main component forming the target material. 另外,例如,可以使用用于沉积包含In、Ga和Zn的氧化物半导体的祀材(组成比为ln 203 :Ga203 :Zn0=l: 1:1 [摩尔比])等。 Further, for example, may be used for depositing containing In, Ga, and Zn in the sacrificial material is an oxide semiconductor (a composition ratio of ln 203: Ga203: Zn0 = l: 1: 1 [molar ratio]) and the like. 另外,可以使用其组成比为ln203 :Ga203 :Zn0=l: 1:2 [摩尔比]或ln203 :Ga203 :Zn0=l: 1:4 [摩尔比]的用于沉积包含In、Ga和Zn的氧化物半导体的靶材。 Further, the composition ratio may be used as ln203: Ga203: Zn0 = l: 1: 2 [molar ratio] or ln203: Ga203: Zn0 = l: 1: 4 [molar ratio] for depositing containing In, Ga, and Zn an oxide semiconductor target. 用于沉积氧化物半导体的靶材的填充率为大于或等于90%且小于或者等于100%,优选为大于或等于95% (例如,99. 9%)。 Filling rate target for depositing an oxide semiconductor is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% (e.g., 99.9%). 通过使用填充率高的用于沉积氧化物半导体的靶材,形成致密的氧化物半导体层。 By using a high filling rate target for the deposition of an oxide semiconductor, forming a dense oxide semiconductor layer.

[0120] 氧化物半导体层的形成气氛优选为稀有气体(典型为氦)气氛、氧气氛、或稀有气体(典型为氩)和氧的混合气氛。 [0120] the oxide semiconductor layer is formed in the atmosphere is preferably a rare gas (typically helium) atmosphere, an oxygen atmosphere or a rare gas (typically, argon) and oxygen mixed atmosphere. 特别是,优选使用其中诸如氢、水、氢氧根或氢化物等的杂质的浓度降低到大约几ppm (优选为几ppb)的高纯度气体。 In particular, it is preferable to use the concentration of impurities such as hydrogen, water, hydroxyl, or the like, wherein the hydride is reduced to about several ppm (preferably several ppb) of high-purity gas.

[0121] 在形成氧化物半导体层时,将衬底固定在保持为降低的压力状态下的处理室内, 并且衬底温度为高于或等于100° C且小于或者等于600° C,优选为大于或等于200° C且小于或者等于400° C。 [0121] When the oxide semiconductor layer is formed, the substrate is fixed to the holding process chamber under reduced pressure conditions, and the substrate temperature is higher than or equal to 100 ° C and less than or equal to 600 ° C, preferably greater than or equal to 200 ° C and less than or equal to 400 ° C. 当在加热衬底的同时形成氧化物半导体层时,可以降低氧化物半导体层所包含的杂质的浓度。 When the oxide semiconductor layer is formed while heating the substrate, it can reduce the concentration of the oxide semiconductor layer contains impurities. 另外,可以减轻由溅射导致的损伤。 In addition, it reduces the damage caused by the sputtering. 在去除处理室内的残留水分的同时引入从其去除了氢和水的溅射气体,并使用金属氧化物作为靶材来形成氧化物半导体层。 In addition to hydrogen and water sputtering gas, a metal oxide and the oxide semiconductor layer is formed as a target while removing residual moisture from the treatment chamber is introduced. 优选使用俘获型真空泵,以去除处理室内的残留水分。 Preferably using a capture-type vacuum pump to remove residual moisture in the treatment chamber. 例如,可以使用低温泵、离子泵或钛升华泵。 For example, a cryopump, an ion pump, or a titanium sublimation pump. 抽空单元可以是配有冷阱的涡轮泵。 Evacuation unit may be equipped with a cold trap turbo pump. 从使用低温泵进行抽空的沉积室中去除原子、包含氢原子的化合物(诸如,水(H 2o)等)(优选地,还去除包含碳原子的化合物) 等,因此可以降低在该沉积室中形成的氧化物半导体层所包含的杂质的浓度。 From the cryopump compound removal atom evacuated deposition chamber, comprising a hydrogen atom (such as water (H 2o), etc.) (preferably, also removes a compound containing a carbon atom) and the like, can be reduced in the deposition chamber concentration in the oxide semiconductor layer containing an impurity is formed.

[0122] 作为形成条件,例如,可以采用如下条件:衬底和靶材之间的距离为100mm,压力为0. 6Pa,直流(DC)功率为0. 5kW,并且气氛为氧气氛(氧流量比例为100%)。 [0122] As the forming conditions, e.g., the following conditions may be adopted: the distance between the substrate and the target is 100mm, a pressure of 0. 6Pa, direct current (DC) power is 0. 5kW, and the atmosphere is an oxygen atmosphere (oxygen flow ratio of 100%). 优选使用脉冲直流(DC)电源,因为可以减少粉状物质(也称为微粒或尘埃),并且膜厚度的变化可以较小。 Preferably pulsed direct-current (DC) power, it can be reduced because the powder substances (also referred to as particles or dust), and the variation of the film thickness can be small. 将氧化物半导体层的厚度设定为大于或等于2nm且小于或者等于200nm、优选为大于或等于5nm且小于或者等于30nm。 The thickness of the oxide semiconductor layer is set to be greater than or equal to 2nm and less than or equal to 200nm, preferably greater than or equal to 5nm and less than or equal to 30nm. 另外,氧化物半导体层的适当的厚度根据使用的氧化物半导体材料而不同,因此可以根据使用的材料适当地选择氧化物半导体层的厚度。 Further, an appropriate thickness of the oxide semiconductor layer is an oxide semiconductor material in accordance with different use, the thickness can be appropriately selected depending on the material of the oxide semiconductor layer is used.

[0123] 另外,优选在通过溅射法形成氧化物半导体层之前,通过其中引入氩气体并产生等离子体的反溅射,来去除附着在栅极绝缘层138的表面的尘埃。 [0123] Further, before the oxide semiconductor layer is formed by sputtering by which argon gas is introduced and plasma is generated in the reverse sputtering to remove the dust attached to the surface of the gate insulating layer 138. 这里,通常的溅射是通过离子碰撞溅射靶材实现的,而反溅射是指通过离子碰撞待处理物体的表面以改变表面的质量的方法。 Here, generally by sputtering a sputtering target to achieve ion collision, and reverse sputtering is a method by an ion collision to be treated to alter the surface of the object surface quality. 作为使离子碰撞待处理物体的表面的方法,有其中在氩气氛中将高频电压施加到所述表面并在衬底附近生成等离子体的方法。 As the ions impact the surface of an object to be treated methods, wherein argon atmosphere with a high-frequency voltage is applied to said surface, and generating a plasma in the vicinity of the substrate. 另外,也可以使用氮气氛、氦气氛或氧气氛等代替氩气氛。 It is also possible to use a nitrogen atmosphere, an oxygen atmosphere, a helium atmosphere, or the like instead of the argon atmosphere.

[0124] 对于上述氧化物半导体层的蚀刻,可以使用干蚀刻或湿蚀刻。 [0124] For the etching of the oxide semiconductor layer may be dry etching or wet etching. 当然,也可以使用干蚀刻和湿蚀刻的组合。 Of course, also possible to use a combination of dry etching and wet etching. 根据材料适当地设定蚀刻条件(蚀刻气体、蚀刻液、蚀刻时间、或温度等),以可以将氧化物半导体层蚀刻成所希望的形状。 The material is appropriately set etching conditions (etching gas, etchant, etching time, temperature, or the like), the oxide semiconductor layer to be etched into a desired shape.

[0125] 作为干蚀刻所使用的蚀刻气体的例子,有含有氯的气体(基于氯的气体,例如氯(Cl2)、三氯化硼(BC13)、四氯化硅(SiCl 4)、或四氯化碳(CC14)等)等。 [0125] Examples of the etching gas used for dry etching, a gas (chlorine-based gas such as chlorine (of Cl2), boron trichloride (BC13), silicon tetrachloride (SiCl 4), or tetra-chlorine containing carbon chloride (CC14), etc.) and the like. 替代地,可以使用:含有氟的气体(基于氟的气体,例如四氟化碳(CF4)、六氟化硫(SF6)、三氟化氮(NF 3)、三氟甲烷(CHF3)等);溴化氢(HBr);氧(02);或对其添加了氦(He)或氩(Ar)等的稀有气体的任意上述气体等。 Alternatively, may be used: a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (of CF4), sulfur hexafluoride (of SF6), nitrogen trifluoride (NF 3), trifluoromethane (CHF3), etc.) ; hydrogen bromide (of HBr); any of the above gases or the like is added thereto as helium (He) or argon (Ar) such as a rare gas; oxygen (02).

[0126] 作为干蚀刻法,可以使用平行板型反应性离子蚀刻(RIE)法或感应耦合等离子体(ICP)蚀刻法。 [0126] As the dry etching method, a parallel plate type reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method. 适当地设定蚀刻条件(施加到线圈形电极的电功率、施加到衬底一侧的电极的电功率、衬底一侧的电极的温度等),以将该层蚀刻成所希望的形状。 Appropriately setting etching conditions (the electric power applied to the coil-shaped electrode, is applied to the electric power, the electrode temperature on the substrate side electrode on the substrate side) to the layer is etched into a desired shape.

[0127] 作为用于湿蚀刻的蚀刻剂,可以使用磷酸、醋酸以及硝酸的混合溶液等。 [0127] As an etchant used for wet etching, a phosphoric acid, acetic acid, and a mixed solution of nitric acid and the like. 替代地, 可以使用IT007N (由Kanto Chemical Co.,Inc 制造)等。 Alternatively, use IT007N (, Inc manufactured by Kanto Chemical Co.) and the like.

[0128] 接着,优选对氧化物半导体层进行第一热处理。 [0128] Next, the oxide semiconductor layer is preferably first heat treatment. 通过进行该第一热处理,可以使氧化物半导体层脱水化或脱氢化。 By performing the first heat treatment, the oxide semiconductor layer can be dehydrated or dehydrogenated. 第一热处理在如下温度进行:大于或等于300° C且小于或者等于750° C,优选大于或等于400° C且低于衬底的应变点。 The first heat treatment is carried out at the following temperature: greater than or equal to 300 ° C and less than or equal to 750 ° C, preferably greater than or equal to 400 ° C and lower than the strain point of the substrate. 例如,将衬底引入到使用电阻加热元件等的电炉中,在氮气氛中在450° C的温度对氧化物半导体层140进行热处理1小时。 For example, the substrate is introduced into an electric furnace using resistive heating element or the like, heat-treated for 1 hour at a temperature of the oxide semiconductor layer 140 is 450 ° C in a nitrogen atmosphere. 此时,防止氧化物半导体层140接触大气,从而避免水或氢的混入。 In this case, to prevent the oxide semiconductor layer 140 in contact with the atmosphere, so as to avoid mixing of water or hydrogen.

[0129] 另外,热处理装置不限于电炉,也可以包括利用诸如被加热的气体等介质发出的热传导或热辐射对待处理的物体进行加热的装置。 [0129] The heat treatment apparatus is not limited to an electric furnace, and may include the use of heat conduction or heat radiation, such as a medium such as heated gas emanating treated object processing apparatus for heating. 例如,可以使用快速热退火(RTA)装置, 诸如气体快速热退火(GRTA)装置或灯快速热退火(LRTA)装置等。 For example, a rapid thermal annealing (RTA) apparatus, such as a gas rapid thermal annealing (a GRTA) device or a lamp rapid thermal anneal (an LRTA) device or the like. LRTA装置是利用从灯(如卤素灯、金卤灯、氙弧灯、碳弧灯、高压钠灯、或高压汞灯等)发出的光(电磁波)的辐射加热待处理物体的装置。 LRTA apparatus is an apparatus with light (an electromagnetic wave) emitted from the lamp (e.g., halogen lamp, metal halide lamp, a xenon arc lamp, a carbon arc lamp, high pressure sodium, high pressure mercury lamp, or the like) of radiation heating of the object to be treated. GRTA装置是利用高温气体进行热处理的装置。 GRTA apparatus is an apparatus for heat treatment using a high temperature gas. 作为所述气体,使用不会因加热处理而与待处理物体起反应的惰性气体,诸如氩等稀有气体或氮等。 As the gas, an inert gas heat treatment will not react with the object to be processed, a rare gas such as argon or nitrogen.

[0130] 例如,作为第一热处理,也可以进行如下GRTA处理。 [0130] For example, as the first heat treatment may be performed as follows GRTA process. 将衬底置于到被加热到650° C至700° C的高温的惰性气体中,行加热几分钟,然后从该惰性气体中取出衬底。 Placing the substrate is heated to a high temperature to 650 ° C to 700 ° C in an inert gas, heated a few rows, the substrate is then removed from the inert gas. GRTA处理使得可以在短时间内进行高温热处理。 GRTA process such that high temperature heat treatment may be performed in a short time. 另外,该热处理仅是在短时间内进行,因此即使在超过衬底的应变点的温度条件下也可以使用该热处理。 Further, this heat treatment only in a short time, and therefore can be used even when the heat treatment at a temperature exceeding the strain point of the substrate.

[0131] 另外,优选在含有氮或稀有气体(氦、氖或氩等)为主要成分且不包含水或氢等的气氛中进行第一热处理。 [0131] Further, the first heat treatment is preferably carried out in an atmosphere containing nitrogen or a rare gas (helium, neon, or argon) as its main component and does not contain water or hydrogen. 例如,优选将引入加热处理装置中的氮或诸如氦、氖、氩等的稀有气体的纯度设定为大于或等于6N (99. 9999 % ),优选设定为大于或等于7N (99. 99999%) (即,杂质浓度为小于或者等于lppm,优选为小于或者等于0. lppm)。 For example, nitrogen is preferably introduced into a heat treatment apparatus or the purity of a rare gas such as helium, neon, argon and the like is set to be equal to or greater than 6N (99. 9999%), preferably greater than or equal to 7N (99. 99999 %) (i.e., the impurity concentration is less than or equal lppm, preferably less than or equal to 0. lppm).

[0132] 根据第一加热处理的条件或氧化物半导体层的材料,有时可能将氧化物半导体层晶化成为微晶层或多晶层。 [0132] The heat treatment conditions or the material of the first oxide semiconductor layer, the oxide semiconductor layer may sometimes become crystallized microcrystalline layer or a polycrystalline layer. 例如,氧化物半导体层可以被晶化为晶化程度大于或等于90% 或大于或等于80%的微晶氧化物半导体层。 For example, the oxide semiconductor layer may be crystallized into the crystallization degree is greater than or equal to 90%, or greater than or equal to 80% microcrystalline oxide semiconductor layer. 另外,根据第一热处理的条件或氧化物半导体层的材料,氧化物半导体层可以变为不含晶体成分的非晶氧化物半导体层。 Further, according to the conditions of heat treatment or the material of the first oxide semiconductor layer, the oxide semiconductor layer may become amorphous oxide semiconductor layer containing no crystalline component.

[0133] 氧化物半导体层可以成为这样的氧化物半导体层,其中晶体(粒径(gain diameter)为大于或等于lnm且小于或者等于20nm,典型为大于或等于2nm且小于或者等于4nm)混合在非晶氧化物半导体(例如,氧化物半导体层的表面)中。 [0133] Such an oxide semiconductor layer may be an oxide semiconductor layer, wherein the crystal (grain size (gain diameter) equal to or greater than or equal to 20 nm and less than lnm, typically greater than or equal to and less than or equal to 2nm of 4 nm) were mixed in an amorphous oxide semiconductor (e.g., the surface of the oxide semiconductor layer) in.

[0134] 另外,可以通过在氧化物半导体层的非晶表面上设置晶体层,改变氧化物半导体层的电特性。 [0134] Further, by providing a crystal layer on the surface of the amorphous oxide semiconductor layer, change in electrical characteristics of the oxide semiconductor layer. 例如,在使用基于In-Ga-Zn-0的氧化物半导体的成膜靶材来形成氧化物半导体层的情况下,可以通过形成其中电各向异性的In 2Ga2Zn07W晶粒被对准的晶体部,改变氧化物半导体层的电特性。 For example, in the case where the oxide semiconductor layer is formed on the deposition of an oxide semiconductor target In-Ga-Zn-0 is, by forming an anisotropic crystal portion where the crystal grains are aligned In 2Ga2Zn07W , changing the electrical characteristics of the oxide semiconductor layer.

[0135] 更具体地,例如,通过将In2Ga2Zn0 7的c轴在垂直于氧化物半导体层的表面的方向的方式来使晶粒对准,可以提高在平行于氧化物半导体层表面的方向上的导电性,从而可以提高在垂直于氧化物半导体层表面的方向上的绝缘性。 [0135] More specifically, for example, by the c-axis In2Ga2Zn0 7 in a direction perpendicularly to the surface of the oxide semiconductor layer to align crystal grains can be increased in a direction parallel to the surface of the oxide semiconductor layer conductive, insulating property can be improved in the direction perpendicular to the surface of the oxide semiconductor layer. 另外,上述晶体部具有抑制诸如水或氢等杂质侵入到氧化物半导体层中的功能。 Further, the inhibition of crystal portion having impurities such as water or hydrogen from entering the oxide semiconductor layer functions.

[0136] 注意,具有上述晶体部的氧化物半导体层可以通过GRTA来对氧化物半导体层表面进行加热而形成。 [0136] Note that an oxide semiconductor layer of the crystalline portion may be heated by GRTA surface of the oxide semiconductor layer to be formed. 通过使用Zn含量小于In或Ga含量的溅射靶材,可以实现更理想的氧化物半导体层的形成。 By using the sputtering target is less than the content of In or Ga Zn content can be achieved more preferably an oxide semiconductor layer is formed.

[0137] 对氧化物半导体层140的第一热处理也可以对还未被处理为岛状的氧化物半导体层140来进行。 [0137] The first heat treatment on the oxide semiconductor layer 140 may also be processed as yet island-shaped oxide semiconductor layer 140 is performed. 在此情况下,在进行第一热处理之后,从加热装置取出衬底,并进行光刻步骤。 In this case, after performing the first heat treatment, the substrate is taken from the heating apparatus and a photolithography step.

[0138] 另外,上述第一热处理可以对氧化物半导体层140进行脱水化或脱氢化,因此也可以被称为脱水化处理或脱氢化处理等。 [0138] Further, the first thermal treatment on the oxide semiconductor layer 140 can be subjected to dehydration or dehydrogenation, it can also be referred to as dehydration or dehydrogenation treatment. 可以在任何时机进行上述脱水化处理或脱氢化处理,例如,在形成氧化物半导体层之后,在将源电极或漏电极层叠在氧化物半导体层140上之后,或者,在将保护绝缘层形成在源电极或漏电极上之后等。 May be the dehydration or dehydrogenation treatment process at any time, e.g., after formation of the oxide semiconductor layer, after the laminated the source or drain electrode over the oxide semiconductor layer 140, or, in the protective insulating layer is formed after the source electrode or drain electrode on the other. 可以进行该脱水化处理或脱氢化处理一次以上。 The dehydration process may be performed or dehydrogenation process more than once.

[0139] 接着,形成源电极或漏电极142a和源电极或漏电极142b与氧化物半导体层140 接触(见图4F)。 [0139] Next, the source or drain electrode 142a and the source or drain electrode 142b in contact with the oxide semiconductor layer 140 (see FIG. 4F). 可以通过形成导电层以覆盖氧化物半导体层140之后对该导电层选择性地进行蚀刻的方式,形成源电极或漏电极142a和源电极或漏电极142b。 Can be formed so as to cover the conductive layer 140 after etching the conductive layer is selectively an oxide semiconductor layer, a source electrode or drain electrode 142a and the source or drain electrode 142b.

[0140]该导电层可以使用诸如溅射法的PVD法或诸如等离子体CVD法等的CVD法形成。 [0140] The conductive layer may be formed using a PVD method such as a sputtering method or a plasma CVD method such as a CVD method. 另外,作为导电层的材料,可以使用选自铝、铬、铜、钽、钛、钥和钨的元素或含任意上述元素作为其成分的合金等。 Further, as the material of the conductive layer may be used an element selected from aluminum, chromium, copper, tantalum, titanium, tungsten, and the key or any of the above-containing alloy elements as its component. 也可以使用选自锰、镁、锆、铍和钍的任何一种或多种材料。 You may be used any one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium. 另外,对于该导电层的材料,也可以适用其中组合了铝与选自钛、钽、钨、钥、铬、钕和钪的一种元素或多种元素材料。 Further, the material of the conductive layer, which may be applied in combination with aluminum is selected from titanium, tantalum, tungsten, key elements, chromium, neodymium, and scandium or more elements of the material.

[0141] 替代地,该导电层也可以使用导电金属氧化物形成。 [0141] Alternatively, the conductive layer may be formed using a conductive metal oxide. 作为导电金属氧化物,可以使用氧化铟(ln 203)、氧化锡(Sn02)、氧化锌(ZnO)、氧化铟氧化锡合金(In 203-Sn02,有时缩写为IT0)、氧化铟氧化锌合金(In 203-Zn0)、或者其中含有硅或氧化硅的任意上述金属氧化物材料。 As the conductive metal oxide, indium oxide (ln 203), tin oxide (Sn02), zinc oxide (ZnO), indium oxide-tin oxide alloy (In 203-Sn02, sometimes abbreviated as IT0), indium oxide-zinc oxide alloy ( in 203-Zn0), or wherein any of the above metal oxide materials containing silicon or silicon oxide.

[0142] 该导电层既可为单层结构,又可为两层或更多层的叠层结构。 [0142] The conductive layer may have a single structure, but also for two or more layers of the laminate structure. 例如,可以举出包含硅的铝膜的单层结构、在铝膜上层叠有钛膜的两层结构、以及顺序层叠有钛膜、铝膜和钛膜的三层结构等。 For example, a single-layer structure may include an aluminum film containing silicon, a two-layer structure of a titanium film is stacked over an aluminum film, and a titanium film are stacked sequentially, an aluminum film and a titanium film of three-layer structure and the like.

[0143] 这里,对于用于形成蚀刻掩模的曝光,优选使用紫外线、KrF激光束、或ArF激光束。 [0143] Here, an etching mask used for the exposure, it is preferable to use ultraviolet rays, KrF laser beam or ArF laser beam.

[0144] 晶体管的沟道长度(L)由源电极或漏电极142a的下边缘部和源电极或漏电极142b的下边缘部的间隔决定。 [0144] transistor channel length (L) of the source or drain electrode and the lower edge portion of the source electrode or drain electrode 142a of the lower edge portion of the interval determination electrode 142b. 另外,当在沟道长度(L)短于25nm的条件下,使用波长极短的几nm至几十nm的极紫外线(Extreme Ultraviolet)进行用于形成掩模的曝光。 In addition, when the channel length (L) shorter than 25nm under conditions of extremely short wavelength EUV several nm to several tens of nm (Extreme Ultraviolet) exposure for forming a mask. 在利用超紫外线的曝光中,分辨率高,并且焦深(focus d印th)大。 Using extreme ultraviolet light exposure, a high resolution and depth of focus (focus d printing th) large. 因此,可以之后将形成的晶体管的沟道长度(L)可以为大于或等于10nm且小于或者等于lOOOnm,从而可以提高电路的操作速度。 Thus, the transistor channel length (L) may then be formed may be greater than or equal to 10nm and less than or equal to lOOOnm, which can increase the operating speed of the circuit. 此外,该晶体管的截止电流极小,因此可以抑制功耗的增大。 Further, off-state current of the transistor is extremely small, thus increasing the power consumption can be suppressed.

[0145] 可以适当地调节层的材料和蚀刻条件,以使得在对该导电层进行蚀刻时不会把氧化物半导体层140去除。 [0145] layer material and etching conditions may be suitably adjusted, so as not to remove the oxide semiconductor layer 140 is etched while the conductive layer. 另外,根据材料和蚀刻条件,有时在该蚀刻步骤中氧化物半导体层140被部分蚀刻而具有凹槽部(凹部)。 Further, depending on the materials and the etching conditions, this etching step is sometimes the oxide semiconductor layer 140 is partially etched and has a groove portion (recessed portion).

[0146] 可以在氧化物半导体层140和源电极或漏电极142a之间或者在氧化物半导体层140和源电极或漏电极142b之间形成氧化物导电层。 [0146] In the oxide conductive layer may be an oxide semiconductor layer and the source or drain electrode or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b between the electrodes 142a 140. 可以连续形成(连续沉积)氧化物导电层和用于形成源电极或漏电极142a和源电极或漏电极142b的金属层。 It may be formed continuously (continuous deposition) and the oxide conductive layer for forming the source or drain electrode 142a and the source or drain electrode layer 142b of metal. 氧化物导电层可以用作源区或漏区。 Oxide conductive layer may function as a source region or a drain region. 通过设置该氧化物导电层,可以降低源区或漏区的电阻,并可以实现晶体管的高速操作。 By providing the oxide conductive layer can reduce the resistance of the source region or the drain region of the transistor and high speed operation can be realized.

[0147] 可以使用多色调掩模(其是一种将光透射为具有多种强度的曝光掩模)形成的抗蚀剂掩模来进行蚀刻,以减少掩模和步骤的数量。 [0147] using the multi-tone mask can be etched (which is a light exposure mask having a plurality of transmission to the intensity) of the resist mask formed in order to reduce the number of masks and steps. 使用多色调掩模形成的抗蚀剂掩模具有多种厚度的形状(阶梯状),并且可以通过灰化来进一步改变形状,因此该抗蚀剂掩模可以用于处理为不同的图案的多个蚀刻工艺中。 Multi-tone mask using a resist mask formed in a shape having a plurality of thicknesses (stepped), and may be further changed in shape by ashing, so that the resist mask may be used for processing a plurality of different patterns an etching process. 就是说,利用一个多色调掩模,可以形成对应于至少两种或两种以上的不同图案的抗蚀剂掩模。 That is, using one multi-tone mask, a resist mask may be formed corresponding to at least two or more different patterns. 因此,可以削减曝光掩模数,并且可以削减所对应的光刻步骤数,因此可以简化工艺。 Thus, light-exposure masks can be reduced, and can reduce the number of corresponding photolithography step, it is possible to simplify the process.

[0148] 另外,优选在上述步骤之后,进行使用诸如队0、队或Ar等的气体的等离子体处理。 [0148] Further, preferably after the above step, such as using 0 teams, team, or Ar gas plasma treatment. 通过该等离子体处理,去除附着于露出的氧化物半导体层表面的水等。 By the plasma treatment to remove water and the like adhering to the exposed surface of the oxide semiconductor layer. 替代地,可以使用诸如氧和氩的混合气体等的包含氧的气体进行等离子体处理。 Alternatively, a gas containing oxygen such as oxygen and argon mixed gas plasma treatment or the like. 以这样的方式,可以将氧供给给氧化物半导体层而减少由于氧缺乏导致的缺陷。 In this manner, the oxygen may be supplied to the oxide semiconductor layer is reduced due to defects due to oxygen deficiency.

[0149] 接着,不接触空气地形成与部分氧化物半导体层140接触的保护绝缘层144(见图4G)。 [0149] Subsequently, without exposure to air to form a protective insulating layer in contact with the oxide semiconductor layer 140 portions 144 (see FIG. 4G).

[0150] 保护绝缘层144可以通过适当地使用溅射法等的防止水或氢等的杂质混入到保护绝缘层144的方法而形成。 [0150] The protective insulating layer 144 may be formed by suitably used to prevent impurities such as water or hydrogen is mixed into the sputtering method of the protective insulating layer 144. 保护绝缘层144的厚度为大于或等于lnm。 The thickness of the protective insulating layer 144 is equal to or greater than lnm. 作为可以用于保护绝缘层144的材料,有氧化硅、氮化硅、氧氮化硅、氮氧化硅等。 It may be used as the protective insulating layer material 144, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide or the like. 保护绝缘层144可以具有单层结构或者叠层结构。 The protective insulating layer 144 may have a single layer structure or a laminated structure. 优选将形成保护绝缘层144时的衬底温度设定为大于或等于室温且小于或等于300° C。 Preferably the temperature of the substrate forming a protective insulating layer 144 is set to be greater than or equal to room temperature and less than or equal to 300 ° C. 用于形成保护绝缘层144的气氛优选采用稀有气体(典型为氩)气氛、氧气氛、或稀有气体(典型为氩)和氧的混合气氛。 For forming the protective insulating layer 144 is preferably an atmosphere of rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a rare gas (typically, argon) and oxygen mixed atmosphere.

[0151] 在保护绝缘层144包含氢的情况下,导致氢侵入到氧化物半导体层或者由氢从氧化物半导体层中抽取氧等,并且使得氧化物半导体层的背沟道一侧的电阻低,这可能形成寄生沟道。 [0151] In the case where the protective insulating layer 144 containing hydrogen, resulting in hydrogen from entering the oxide semiconductor layer or extraction of oxygen from the oxide semiconductor layer by hydrogen or the like, and so that the low-resistance oxide semiconductor layer, a back channel side this may form a parasitic channel. 因此,重要的是在保护绝缘层144的形成过程中不使用氢,以使得氧化物绝缘层144含尽可能少的氢。 Thus, it is important not to use hydrogen in the protective insulating layer 144 is formed in the process, so that the oxide insulating layer 144 containing as little hydrogen.

[0152]另外,优选在去除处理室内的残留水分的同时形成保护绝缘层144。 [0152] Further, preferably at the same time remove the remaining moisture of the treatment chamber forming the protective insulating layer 144. 这是为了防止氧化物半导体层140和保护绝缘层144中包含氢、羟基或水。 This is to prevent the oxide semiconductor layer, an insulating layer 144 containing hydrogen, hydroxy or 140 and water protection.

[0153] 优选使用俘获型真空泵,以去除处理室内的残留水分。 [0153] preferable to use a capture-type vacuum pump to remove residual moisture in the treatment chamber. 例如,优选使用低温泵、离子泵或钛升华泵。 For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. 另外,作为抽空单元,可以使用配有冷阱的涡轮泵。 Further, as the evacuation means, a cold trap can be used with a turbo pump. 从使用低温泵进行抽空的沉积室中,去除了氢原子或包含氢原子的化合物(诸如水(H 20)等)等,因此可以降低在该沉积室中形成的保护绝缘层144所包含的杂质的浓度。 From the cryopump for evacuating the deposition chamber, in addition to a hydrogen atom or a compound (such as water (H 20), etc.) and the like comprising a hydrogen atom, can be reduced impurity protective insulating layer 144 formed in the deposition chamber contained concentration.

[0154] 作为形成保护绝缘层144时的溅射气体,优选使用其中将诸如氢、水、羟基或氢化物等的杂质的浓度降低到大约几ppm (优选为几ppb)的高纯度气体。 [0154] As a sputtering gas forming the protective insulating layer 144, preferably wherein the concentration of impurities such as hydrogen, water, a hydroxyl group, or hydride is reduced to about several ppm (preferably several ppb) using high-purity gas.

[0155] 接着,优选在惰性气体气氛中或在氧气氛中进行第二热处理(优选为在大于或等于200° C且小于或者等于400° C,例如大于或等于250° C且小于或者等于350° C的温度)。 [0155] Next, in an oxygen atmosphere or preferably in an inert gas atmosphere a second heat treatment (preferably at higher than or equal to 200 ° C and less than or equal to 400 ° C, for example greater than or equal to 250 ° C and less than or equal to 350 temperature ° C.). 例如,在氮气氛下在250° C的温度进行第二热处理一小时。 For example, the second heat treatment temperature for one hour to 250 ° C under a nitrogen atmosphere. 第二热处理可以降低晶体管的电特性的变化。 The second heat treatment can reduce variation in electric characteristics of the transistor. 另外,通过第二热处理,可以将氧供给给氧化物半导体层。 Further, the second heat treatment, oxygen may be supplied to the oxide semiconductor layer.

[0156]另外,可以在空气中在大于或等于100° C且小于或者等于200° C的温度进行热处理大于或等于1小时且小于或者等于30小时。 [0156] Further, greater than or equal to 100 ° C in air and a temperature of less than or equal to 200 ° C heat treatment is greater than or equal to 1 hour and less than or equal to 30 hours. 该热处理可在固定的加热温度进行。 The heat treatment may be performed at a fixed heating temperature. 替代地,可以反复多次应用如下的温度循环:温度从室温增加到大于或等于100° C且小于或者等于200° C的温度,并然后降低到室温。 Alternatively, the application can be repeated temperature cycling as follows: the temperature increased to greater than or equal to 100 ° C and less than or equal to a temperature of from room temperature to 200 ° C, and then lowered to room temperature. 另外,可以在形成保护绝缘层之前在降低的压力下进行该热处理。 Further, this heat treatment may be performed under reduced prior to formation of the protective insulating layer pressure. 通过降低的压力使得可以缩短热处理时间。 By reducing the pressure such that the heat treatment time can be shortened. 另外,可以进行该热处理代替上述第二热处理;替代地,可以在第二热处理以外,在第二热处理之前和/或之后,进行该热处理。 Further, this heat treatment may be performed instead of the second heat treatment; alternatively, may be other than the second heat treatment, the second heat treatment before and / or after the heat treatment is performed.

[0157] 然后,在保护绝缘层144上形成层间绝缘层146 (见图5A)。 [0157] Then, an interlayer insulating layer 146 (see FIG. 5A) is formed on the protective insulating layer 144. 层间绝缘层146可以使用PVD法或CVD法等形成。 The interlayer insulating layer 146 may be formed using a PVD method or a CVD method. 另外,可以使用包含诸如氧化硅、氮氧化硅、氮化硅、氧化铪、 氧化铝、或氧化钽等的无机绝缘材料的材料形成层间绝缘层146。 Further, the interlayer insulating layer 146 is formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like. 另外,优选在形成层间绝缘层146之后,对层间绝缘层146的表面进行CMP或蚀刻处理等,以使其平坦化。 Further, preferably after the interlayer insulating layer 146 is formed on the surface of the interlayer insulating layer 146 by CMP or etching treatment or the like so as to be planarized.

[0158] 接着,在层间绝缘层146、保护绝缘层144以及栅极绝缘层138中形成到达电极136a、电极136b、电极136c、源电极或漏电极142a、以及源电极或漏电极142b的开口;然后,形成导电层148以嵌入这些开口中(见图5B)。 [0158] Next, the interlayer insulating layer 146, the protective insulating layer 144 and the gate insulating layer 138 is formed to reach the electrode 136a, the electrode 136b, an electrode 136c, the source or drain electrode 142a, and the source or drain electrode 142b of the opening ; then, a conductive layer 148 embedded in the openings (see FIG. 5B). 例如,上述开口可以使用掩模通过蚀刻形成。 For example, the opening may be formed by etching using a mask. 例如,上述掩模可以通过使用光掩模的曝光形成。 For example, the mask may be formed by exposure using a photomask. 作为蚀刻,可以使用湿蚀刻或干蚀亥IJ,但是从微细处理的观点来看,优选使用干蚀刻。 As the etching, wet etching or dry etching Hai IJ, but from the viewpoint of fine processing, it is preferable to use dry etching. 导电层148可以使用诸如PVD法或CVD 法等的沉积法形成。 Conductive layer 148 may be formed using a PVD method such as a CVD method or a deposition method. 作为可以用于形成导电层148的材料,可以举出诸如以下的导电材料: 钥、钛、铬、钽、钨、铝、铜、钕和钪,任意这些元素的合金,或含任意这些元素的化合物(例如, 任意这些元素的氮化物)等。 As the material for the conductive layer 148 can be formed include conductive materials such as the following: keys, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, alloys of any of these elements, or containing any of these elements compound (e.g., nitride of any of these elements) and the like.

[0159] 具体地说,例如,可以如下形成导电层148 :在包括所述开口的区域中使用PVD法形成厚度薄的钛膜,然后使用CVD法形成厚度薄的氮化钛膜;然后,形成钨膜以嵌入开口中。 [0159] Specifically, for example, conductive layer 148 may be formed as follows: a thin titanium film is formed using a PVD method including the opening region, a thin titanium nitride film is then formed by a CVD method; then formed a tungsten film is embedded in the openings. 这里,通过PVD法形成的钛膜具有使与下面的电极(这里,电极136a、电极136b、电极136c、源电极或漏电极142a、或源电极或漏电极142b等)的界面处的氧化膜还原从而降低与下面的电极的接触电阻的功能。 Here, the titanium film formed by a PVD method has a underlying electrode (here, the electrode 136a, the electrode 136b, an electrode 136c, the source or drain electrode 142a, or the source or drain electrode 142b, etc.) of an oxide film reduction at the interface thereby reducing the function of the electrode with the underlying contact resistance. 另外,随后形成的氮化钛膜具有抑制导电材料的扩散的阻挡功能。 Further, the titanium nitride film is then formed having a conductive material suppressing diffusion barrier function. 另外,可以在利用钛或氮化钛等形成阻挡膜之后,使用镀的方法来形成铜膜。 Further, after forming a barrier film of titanium nitride or titanium, the plated copper film forming method.

[0160] 在形成导电层148之后,通过使用蚀刻或CMP等去除导电层148的一部分,从而暴露层间绝缘层146,并形成电极150a、电极150b、电极150c、电极150d以及电极150e (见图5C)。 [0160] After the formation of the conductive layer 148, by etching, CMP, or the like is removed using a portion of the conductive layer 148, to expose the interlayer insulating layer 146, and forming an electrode 150a, an electrode 150b, an electrode 150c, 150d and the electrode electrode 150e (see FIG. 5C). 另外,在通过去除上述导电层148的一部分来形成电极150a、电极150b、电极150c、 电极150d以及电极150e时,优选进行处理以获得平坦表面。 Further, when the formed 150a, an electrode 150b, an electrode 150c, 150d and the electrode 150e electrode by removing a portion of the conductive electrode layer 148, preferably treated to obtain a flat surface. 通过将层间绝缘层146、电极150a、电极150b、电极150c、电极150d以及电极150e的表面处理为平坦,可以在之后的步骤中形成优良的电极、布线、绝缘层、或半导体层等。 A flat, fine electrode, a wiring, an insulating layer, a semiconductor layer, or the like may be formed by the subsequent step 146, the electrode 150a, the electrode 150b, the surface electrode 150c, 150d and the electrode 150e electrode processing interlayer insulating layer.

[0161] 此外,形成绝缘层152,并在绝缘层152中形成到达电极150a、电极150b、电极150c、电极150d以及电极150e的开口;然后,形成导电层以嵌入在所述开口中。 [0161] Further, the insulating layer 152 is formed, and forming 150a, an electrode 150b, an electrode 150c, 150d and the electrode opening 150e of the electrodes in the electrode reaches the insulating layer 152; Then, a conductive layer is embedded in the opening. 然后,使用蚀刻或CMP等去除该导电层的一部分,从而暴露绝缘层152,并形成电极154a、电极154b、电极154c以及电极154d (见图OT)。 Then, etching or the like using a portion of the conductive layer is removed by CMP, thereby exposing the insulating layer 152, and forming an electrode 154a, an electrode 154b, an electrode 154c and the electrode 154d (see FIG. OT). 该步骤与形成电极150a等的步骤相同,因而省略其详细说明。 The step of forming an electrode 150a and the like of the same, and thus the detailed description thereof will be omitted.

[0162] 在以上述方式制造晶体管162的情况下,氧化物半导体层140的氢浓度为小于或者等于5X10 19原子/cm3,并且晶体管162的截止电流为小于或者等于lXl(T13A,g卩,检测极限。晶体管162的截止电流(这里,每微米沟道宽度的电流)为小于或者等于lOOzA/ym。 如此,通过使用其中氢浓度被充分降低并且由于氧缺乏导致的缺陷得到降低的高度纯化的氧化物半导体层140,可以得到特性优良的晶体管162。另外,可以制造包括在下部的使用氧化物半导体以外的材料的晶体管160以及在上部的使用氧化物半导体的晶体管162的特性优良的半导体装置。 [0162] In the case of manufacturing a transistor 162 in the above manner, the hydrogen concentration in the oxide semiconductor layer 140 is less than or equal to 5X10 19 atoms / cm3, and the off current of the transistor 162 is less than or equal lXl (T13A, g Jie, detection limit. off-state current (here, current per micrometer of channel width) of the transistor 162 is less than or equal lOOzA / ym. thus, since the oxide is sufficiently reduced and the oxygen defect caused by the lack of highly purified obtained by reduction of the hydrogen concentration used in which semiconductor layer 140 can be obtained excellent characteristics of the transistor 162. Furthermore, excellent characteristics can be manufactured comprising a material other than an oxide semiconductor in a lower portion of the transistor using an oxide semiconductor and a transistor 160 in the upper portion 162 of the semiconductor device.

[0163] 另外,虽然对氧化物半导体的物理性质已在进行各种各样的研究,但是这些研究并未启示充分降低能隙中的局部态(localized states)的思想。 [0163] Further, although the physical properties of the oxide semiconductor various studies have been performed, but these studies have not thought energy gap is sufficiently reduced Implications local state (localized states) of. 在所公开的发明的一个实施例方式中,从氧化物半导体中去除可以引入局部态的水或氢,从而制造了高度纯化的氧化物半导体。 In one embodiment of the disclosed embodiment of the invention, it can be removed from the oxide semiconductor introduction of local state of water or hydrogen, thereby producing a highly purified oxide semiconductor. 这是基于充分降低能隙中的局部态的思想的。 This is based on the idea of ​​sufficiently reducing localized states in the energy gap. 由此,可以制造极为优良的工业产品。 As a result, it can be manufactured very excellent industrial products.

[0164] 另外,在去除氢或水等时,氧有时也被去除。 [0164] Further, when the removal of water or other hydrogen, oxygen sometimes removed. 由此,优选地是,通过将氧供给给由氧缺乏而产生的金属的悬挂键以减少由氧缺乏而导致的局部态,进一步使氧化物半导体纯化(使其成为i型氧化物半导体)。 Thus, preferably, the oxygen supplied to the oxygen deficiency resulting from dangling bonds of the metal to reduce the oxygen deficiency caused by the local state, further purified oxide semiconductor (i-type oxide semiconductor to become). 例如,可以以如下方式减少由氧缺乏而导致的局部态:与沟道形成区域紧密接触地形成氧过剩的氧化膜;并进行在200° C至400° C (典型为大约250° C)的温度的热处理,从而将氧从该氧化膜供给给氧化物半导体。 For example, the following manner may be reduced partially by oxygen deficiency states caused: oxygen-excess oxide film is formed in close contact with the channel forming region; and at 200 ° C to 400 ° C (typically about 250 ° C) of the heat treatment temperature, whereby oxygen from the oxide to the oxide semiconductor film is supplied. 在第二热处理期间, 可以将惰性气体切换为含氧的气体,或者将含氧的气体切换为惰性气体。 During the second heat treatment, an inert gas may be switched to a gas containing oxygen, or an oxygen-containing gas is switched to an inert gas. 此外,可以在第二热处理之后,在氧气氛中或者在其中充分降低了氢或水的气氛中,通过降温过程,将氧供给给氧化物半导体。 Further, after the second heat treatment in an oxygen atmosphere or an atmosphere in which substantially reduce the hydrogen or water, through the cooling process, the oxygen supplied to the oxide semiconductor.

[0165] 可以认为,氧化物半导体特性恶化的一个因素是由氢过剩导致的导带下的0. leV 至〇. 2eV处的较浅能级或由氧缺乏导致的较深能级等。 [0165] It is believed that one factor deteriorating the characteristics of the oxide semiconductor is caused by the excess hydrogen of the conduction band to 0. leV billion. 2eV shallower level at a deeper level, or as a result of lack of oxygen. 尽量去除氢并且充分供给氧以消除上述缺陷的技术思想应当是有效的。 Try to remove the hydrogen and oxygen is supplied sufficiently to eliminate the aforementioned drawbacks of the technical idea should be effective.

[0166] 在所公开的发明中,因为氧化物半导体被高度纯化,因此氧化物半导体中的载流子密度充分低。 [0166] In the disclosed invention, since the oxide semiconductor is highly purified, thus the carrier density of the oxide semiconductor is sufficiently low.

[0167] 此外,利用常温下的费米-狄拉克分布函数,能隙处于3. 05至3. 15eV的氧化物半导体的本征载流子密度为IX KTVcm3,这比硅的本征载流子密度1. 45X lO^Vcm3低得多。 [0167] Further, at room temperature using a Fermi - Dirac distribution function of the energy gap in the intrinsic carrier density of the oxide semiconductor is 3.05 to 3. 15eV to IX KTVcm3, which carriers than silicon intrinsic density 1. 45X lO ^ Vcm3 much lower.

[0168] 因此,作为少数载流子的空穴的数目极少。 [0168] Thus, as a minimal number of minority carrier of holes. 绝缘栅型场效应管(Insulated Gate Field Effect Transistor,IGFET)在截止状态下的泄漏电流被预期为在常温下为小于或者等于100aA/ ii m,优选为小于或者等于10aA/ ii m,或者更优选为小于或者等于laA/ ii m。 Leakage current insulation gate type field effect transistor (Insulated Gate Field Effect Transistor, IGFET) in the OFF state at normal temperature is expected to be less than or equal 100aA / ii m, preferably less than or equal 10aA / ii m, or more preferably less than or equal laA / ii m. 这里,"laA/iim"表示晶体管的每微米沟道宽度流过laA (1X1(T18A)的电流。 Here, "laA / iim" denotes a channel width of each transistor is flowing through the LAA microns (current 1X1 (T18A) a.

[0169] 实际上,作为能隙为大于或等于3eV的宽带隙半导体,已知4H_SiC (3. 26eV)和GaN (3. 42eV)等。 [0169] In fact, as the energy gap is greater than or equal to 3eV wide band gap semiconductor, known 4H_SiC (3. 26eV) and GaN (3. 42eV) and the like. 预期利用这些半导体材料能够得到与上述特性类似的晶体管特性。 These semiconductor materials is expected to use the characteristics described above can be obtained with similar transistor characteristics. 但是,因为这些半导体材料大于或等于1500° C的工艺温度,因此在基本上是不可能形成这些半导体材料的薄膜的。 However, semiconductor materials such as a process temperature greater than or equal to 1500 ° C, so it is impossible to form a thin film substantially of these semiconductor materials. 另外,工艺温度过高使得不能在硅集成电路上进行三维层叠这些材料。 Further, the process temperature is too high so that these materials can not be three-dimensional stacked on a silicon integrated circuit. 另一方面,因为氧化物半导体可以通过在室温至400C的加热溅射而沉积成薄膜,并且可以在450° C至700° C进行脱水化或脱氢化(去除氢或水)及供给氧;因此,可以在硅集成电路上三维地层叠氧化物半导体。 On the other hand, since the oxide semiconductor can be obtained by heating from room temperature to 400C in the sputtering is deposited as a thin film, and may be 450 ° C to 700 ° C for dehydration or dehydrogenation (hydrogen or water removal) and oxygen is supplied; thus , the oxide semiconductor may be stacked three-dimensionally on a silicon integrated circuit.

[0170] 另外,尽管通常氧化物半导体为n型,但是在所公开的发明的一个实施方式中,通过去除杂质(诸如水或氢等)并供给作为氧化物半导体的构成元素的氧,使得氧化物半导体成为i型氧化物半导体。 [0170] Further, although typically n-type oxide semiconductor, in one embodiment of the disclosed embodiment of the invention, by removing impurities (such as water or hydrogen) and oxygen is supplied as a constituent element of an oxide semiconductor, such oxide an i-type semiconductor becomes an oxide semiconductor. 在这一点上,与通过添加杂质而使硅成为i型硅的情况不同,因此可以说,所公开的发明的一个实施例包含了新的技术思想。 In this regard, in the case of silicon impurity is added to the i-type silicon becomes different, it can be said, one embodiment of the disclosed invention comprises a new technical idea.

[0171] 〈使用氧化物半导体的晶体管的电导通机理〉 [0171] <conduction mechanism of a transistor using an oxide semiconductor>

[0172] 这里,将参考图6至图9说明使用氧化物半导体的晶体管的电导通机理。 [0172] Here, referring to FIGS. 6 to 9 illustrate the electrical conduction mechanism of a transistor using an oxide semiconductor. 注意,为便于理解,以下的说明是基于理想情况的假设的,并不必然反映实际情况。 Note that, for ease of understanding, the following description is based on the assumption of the ideal case, does not necessarily reflect the actual situation. 另外,以下说明只是一个考虑,而并不影响发明的有效性。 In addition, the following description is just a consideration, but does not affect the validity of the invention.

[0173] 图6是包含氧化物半导体的晶体管(薄膜晶体管)的截面图。 [0173] FIG. 6 is a sectional view of a transistor (thin film transistor) including an oxide semiconductor. 在栅电极(GE1)上设置有氧化物半导体层(0S )而栅极绝缘层(GI)插入在二者之间,并且其上设置有源电极(S ) 和漏电极(D)。 An oxide semiconductor layer is provided (0S) on the gate electrode (GE1) and the gate insulating layer (GI) interposed therebetween, and disposed on the active electrode (S) and drain electrode (D). 提供绝缘层以覆盖源电极(S)和漏电极(D)。 Providing an insulating layer to cover the source electrode (S) and drain electrode (D).

[0174] 图7示出沿图6的A-A'截面的能带图(示意图)。 [0174] FIG. 7 shows in FIG. 6 along the A-A 'cross section of an energy band diagram (schematic diagram). 在图7中,黑色圆点(•)表示电子,而白色圆点(〇)表示空穴,它们分别具有电荷(_q,+q)。 In FIG. 7, a black circle (•) represents an electron, and the white dots (square) denotes a hole, each having a charge (_q, + q). 在将正电压施加到漏电极(V D>0)的情况下,虚线表示不将电压施加到栅电极的情况(V#),而实线表示将正电压施加到栅电极的情况(\>0)。 In the case of a positive voltage is applied to the drain electrode (VD> 0), the broken line represents no voltage is applied to the gate electrode (V #), and the solid line shows a positive voltage is applied to the gate electrode (\> 0 ). 在不将电压施加到栅电极的情况下,因为势垒高,因此载流子(电子)不从电极注入到氧化物半导体一侧,从而没有电流流过,这意味着截止状态。 In the case where no voltage is applied to the gate electrode, because of the high potential barrier, so the carriers (electrons) is not injected from the electrode into the oxide semiconductor layer side, so that no current flows, which means an off state. 另一方面, 在将正电压施加到栅极的情况下,势垒降低,因而电流流过,这意味着导通状态。 On the other hand, in the case where a positive voltage is applied to the gate, the potential barrier decreases, so that current flows, which means the conduction state.

[0175] 图8A和8B示出沿图6的B-B'的截面的能带图(示意图)。 [0175] FIGS. 8A and 8B show along B-B 6 'of a cross section of an energy band diagram (schematic diagram). 图8A示出将正电压(V e>0)施加到栅电极(GE1),并且在源电极和漏电极之间流过载流子(电子)的导通状态。 8A shows a positive voltage (V e> 0) is applied to the gate electrode (GE1), and flows through the conducting state the carriers (electrons) between the source and drain electrodes. 图8B示出将负电压(\〈0)施加到栅电极(GE1)并且不流过少数载流子的截止状态。 8B shows a negative voltage (\ <0) is applied to the gate electrode (GE1) and the off-state does not flow through the minority carriers.

[0176] 图9示出真空能级和金属的功函数((^)之间以及真空能级和氧化物半导体的电子亲和势(X)之间的关系。 [0176] FIG. 9 shows a vacuum level and the work function of the relationship between the metal and the oxide semiconductor vacuum level of electron affinity (X) (between the (^) and.

[0177] 在常温下,金属中的电子劣化,并且费米能级位于导带内。 [0177] at room temperature, deterioration of the electrons in the metal, the Fermi level and the conduction band is located. 另一方面,常规的氧化物半导体为n型半导体,其中费米能级(EF)远离位于带隙中央的本征费米能级(EP,并且位置更接近导带。另外,已知在氧化物半导体中部分的氢成为施主,并这是导致氧化物半导体成为n型半导体的因素之一。 On the other hand, a conventional oxide semiconductor is an n-type semiconductor, wherein the Fermi level (EF) is located away from the center of the bandgap of the intrinsic Fermi level (EP, and a position closer to the conduction band. Further, it is known oxidation the hydrogen partial semiconductor serves as a donor, and this is one of the factors leading to an oxide semiconductor is an n-type semiconductor.

[0178] 另一方面,根据所公开的发明的一个实施例的氧化物半导体是通过如下获得的本征(i型)的或者基本本征的氧化物半导体:从氧化物半导体去除作为半导体n型化的因素的氢,并对氧化物半导体进行纯化,以使得尽可能使得其中不含氧化物半导体的主要成分以外的元素(杂质元素)。 [0178] On the other hand, an oxide semiconductor according to one embodiment of the disclosed invention is an oxide semiconductor is obtained by intrinsic (i-type) or substantially intrinsic: removing from a semiconductor n-type oxide semiconductor factors of hydrogen, and the oxide semiconductor is purified, such as that wherein the elements (impurity elements) other than the main component of the oxide-free semiconductor. 就是说,其特征在于:通过尽可能多地去除诸如氢或水等的杂质, 得到纯化的i型(本征)半导体或接近本征的半导体,而不是通过添加杂质元素。 That is, characterized in that: by removing impurities as much as possible, such as hydrogen or the like water, purified i-type (intrinsic) semiconductor or near intrinsic semiconductor, not by adding an impurity element. 由此,可以使费米能级(EF)与本征费米能级(EP相当。 Thereby, it is possible that the Fermi level (EF) and the intrinsic Fermi level (EP considerably.

[0179] 据称,氧化物半导体的带隙(Eg)是3. 15eV,并且电子亲和势(x )是4.3V。 [0179] Allegedly, the oxide semiconductor band gap (Eg) is 3. 15eV, electron affinity, and (x) is 4.3V. 源电极及漏电极中所含的钛(Ti)的功函数与氧化物半导体的电子亲和势(x )基本相等。 Titanium (Ti) source and drain electrodes included in the work function and electron affinity of the oxide semiconductor and the potential (x) is substantially equal. 在此情况下,在金属和氧化物半导体地界面处不形成对电子的肖特基势垒。 In this case, without forming a Schottky barrier to electrons in the metal and the oxide semiconductor interface.

[0180] 就是说,在金属的功函数(和氧化物半导体的电子亲和势(x )相当的情况下, 在金属和氧化物半导体彼此接触时获得如图7所示的能带图(示意图)。 [0180] That is, in the case of considerable electron affinity (x) work function of metal (and the oxide semiconductor, is obtained as shown when the metal-oxide-semiconductor contact with each other and an energy band diagram (schematic diagram in FIG. 7 ).

[0181] 在图7中,黑色圆点(•)表示电子。 [0181] In FIG 7, black circles (•) represents an electron. 在将正电位施加到漏极时,电子超过势垒而注入到氧化物半导体,并流向漏极。 When a positive potential is applied to the drain, electrons over the potential barrier are injected into the oxide semiconductor, and to the drain. 势垒的高度取决于栅极电压和漏极电压。 Height of the barrier depends on the gate voltage and the drain voltage. 在施加正的漏极电压时,势垒的高度低于未施加电压情况下的图7中的势垒的高度,即带隙(E g)的1/2。 When applying a positive drain voltage is lower than the height of the barrier height of the barrier of FIG. 7 is not applied in the voltage, i.e., the band gap (E g) of 1/2.

[0182] 此时,如图8A所示,电子在栅极绝缘层和被纯化的氧化物半导体的界面附近(氧化物半导体的能量稳定的最低部)移动。 [0182] In this case, as shown, the electrons move (the lowest portion of the oxide semiconductor energetically stable) FIG. 8A and the gate insulating layer in the vicinity of the purified oxide semiconductor interface. 另外,如图8B所示,在将负电位施加到栅电极(GE1)时,因为作为少数载流子的空穴基本为0,因此电流地值极为接近于0。 Further, as shown in FIG negative potential is applied to the gate electrode (GE1) 8B, since the minority carrier holes substantially zero, so the current value is extremely close to zero.

[0183] 以这样的方式,通过进行纯化以使得尽可能少地包含氧化物半导体的主要元素以外的元素(杂质元素),来得到本征(i型)的或基本上本征的氧化物半导体。 [0183] In this manner, purified by such elements (impurity elements) other than the main element including an oxide semiconductor as little as possible to obtain an intrinsic (i-type) or substantially intrinsic oxide semiconductor . 由此,氧化物半导体与栅极绝缘层之间的界面的特性变得明显。 Thereby, characteristics of the interface between the oxide semiconductor and the gate insulating layer becomes apparent. 因此,栅极绝缘层需要能够与氧化物半导体形成优良界面。 Therefore, the gate insulating layer needs to be able to form a good interface between the oxide semiconductor. 具体地说,优选使用例如,通过使用利用VHF频带至微波频带的范围中电源频率而产生的高密度等离子体的CVD法而形成的绝缘层,或通过溅射法形成的绝缘层等。 Specifically, it is preferable to use, for example, by using high-density plasma is formed by using the VHF band to microwave band frequency range, the power generated by a CVD method of the insulating layer, the insulating layer or the like formed by sputtering.

[0184] 在对氧化物半导体进行纯化并使得氧化物半导体和栅极绝缘层的界面理想时,例如,在晶体管的沟道宽度(W)为1 X 104 i! m且沟道长度(L)为3 i! m的情况下,可以实现1(T13A 或更低的截止电流和〇. lV/dec.的亚阈值摆幅值(S值)(栅极绝缘层的厚度:100nm)。 [0184] When the oxide semiconductor is purified such that the interface and over the oxide semiconductor and the gate insulating layer, e.g., the channel width of the transistor (W) of 1 X 104 i! M and the channel length (L) .!. the case where m is 3 i can be realized 1 (t13A or lower the off current and square lV / dec subthreshold swing value (S value) (the gate insulating layer thickness: 100nm).

[0185] 如上所述地对氧化物半导体进行纯化以尽可能少地包含氧化物半导体的主要成分以外的元素(杂质元素),从而使得晶体管可以以理想的方式操作。 [0185] The oxide semiconductor is purified as described above to elements (impurity elements) other than a main component including an oxide semiconductor as little as possible, so that the transistor may be operated in a desired manner.

[0186] 〈载流子浓度〉 [0186] <carrier concentration>

[0187] 在根据所公开的发明的技术思想中,通过充分减小氧化物半导体层的载流子浓度,使其尽可能接近本征(i型)氧化物半导体层。 [0187] In the technical idea according to the disclosed invention, the carrier concentration of the oxide semiconductor layer is sufficiently reduced, as close as possible an intrinsic (i-type) oxide semiconductor layer. 以下,将参考图10及图11说明计算载流子浓度的方法和实际测量的载流子浓度。 Hereinafter, with reference to FIG. 10 and FIG. 11 illustrates a method of calculating the carrier concentration and the carrier concentration actually measured.

[0188] 首先,简单说明计算载流子浓度的方法。 [0188] First, a brief description of the method of the carrier concentration is calculated. 可以通过制造M0S电容器并估算M0S电容器的CV测量的结果(cv特性),来计算载流子浓度。 And the capacitor can be estimated by making M0S M0S the CV measurement result of the capacitor (cv characteristic), the carrier concentration is calculated.

[0189] 更具体地,以如下方式计算载流子浓度Nd :通过绘制M0S电容器的栅极电压Ve与电容C的关系而获得CV特性;利用该CV特性得到栅极电压\与(1/C) 2的关系的图;找到在该图的弱反型区中(1/C)2的微分值;并且将该微分值代入公式1。 [0189] More specifically, in the following manner calculated carrier concentration Nd: CV characteristics are obtained by plotting the relationship between the gate voltage and the Ve M0S capacitance C of the capacitor; CV characteristic obtained by using the gate voltage \ and (1 / C ) 2 of FIG relationship; found (1 / C) in the differential value of the weak inversion region in FIG. 2; and the differential value is substituted into equation 1. 注意,在公式1中, e表示元电荷,表示真空介电常数,并且e表示氧化物半导体的相对介电常数。 Note that, in the formula 1, e represents elementary electric charge, it represents a dielectric constant of vacuum, and e represents the relative permittivity of an oxide semiconductor.

[0190] 公式1 [0190] Equation 1

[0191] [0191]

Figure CN102598266BD00251

[0192] 接着,说明使用上述方法实际测量的载流子浓度。 [0192] Next, the carrier concentration actually measured using the above method. 在进行测量时使用如下形成的样品(M0S电容器):在玻璃衬底上形成有300nm厚的钛膜,在钛膜上形成有100nm厚的氮化钛膜,在氮化钛膜上形成有2pm厚的使用基于In-Ga-Zn-0的氧化物半导体的氧化物半导体层;并在氧化物半导体层上形成有300nm厚的银膜。 Formed during use as a measurement sample (capacitor M0S): forming a titanium film with a thickness of 300nm on a glass substrate, is formed with a 100nm thick titanium nitride film on the titanium film, formed on the titanium nitride film 2pm a thick oxide semiconductor layer on the oxide semiconductor in-Ga-Zn-0's; and formed with a 300nm thick silver film on the oxide semiconductor layer. 注意,通过使用包含In、Ga和Zn的用于沉积氧化物半导体的祀材(ln 203 :Ga203 :ZnO=l : 1 :1 [摩尔比]),通过溉射法,形成氧化物半导体层。 Note that, by containing In, Ga, and Zn sacrificial material for depositing an oxide semiconductor (ln 203: Ga203: ZnO = l: 1: 1 [molar ratio]), by irrigation sputtering method, an oxide semiconductor layer. 另外,氧化物半导体层的形成气氛为氩和氧的混合气氛(流量比为Ar :02=30 (seem) : 15 (sccm))〇 Further, the oxide semiconductor layer is formed in the atmosphere is a mixed atmosphere of argon and oxygen (flow ratio of Ar: 02 = 30 (seem): 15 (sccm)) square

[0193] 图10和图11分别示出CV特性和V。 [0193] FIGS. 10 and 11 show CV characteristics and V. 与(1/C)2的关系。 Relation (1 / C) 2 a. 使用公式1从图11的弱反型区中的(1/C) 2的微分值计算得到的载流子浓度为6. 0 X lCT/cm3。 Using Equation 1 from the weak inversion region in FIG. 11 (1 / C) the carrier concentration of the calculated differential value is 2 6. 0 X lCT / cm3.

[0194] 如上所述,通过使用使其成为i型或者基本上i型的氧化物半导体(例如,载流子浓度低于1 X 1012/cm3,优选为小于或者等于1 X 10n/cm3),可以得到截止电流特性极为优良的晶体管。 [0194] As described above, by making use of i-type or a substantially i-type oxide semiconductor (e.g., the carrier concentration is less than 1 X 1012 / cm3, preferably less than or equal to 1 X 10n / cm3), It can get extremely excellent in off-current characteristics of the transistor.

[0195] 〈修改例〉 [0195] <Modified Example>

[0196] 将参考图12至图15A和15B说明半导体装置的结构的修改例。 [0196] with reference to FIGS. 12 to 15A and 15B illustrate modified examples of the structure of a semiconductor device. 另外,在下面的修改例中,晶体管162的结构与上述的不同。 Further, in the modification below, a transistor structure 162 of the above-described different. 换而言之,晶体管160的结构与上述的类同。 In other words, the above-described structure similar to transistor 160.

[0197] 在图12所示的例子中,晶体管162具有:在氧化物半导体层140下的栅电极136d ; 以及源电极或漏电极142a和源电极或漏电极142b,其在氧化物半导体层140的底表面处接触氧化物半导体层140。 [0197] In the example shown in FIG. 12, the transistor 162 has: a gate electrode 136d in the oxide semiconductor layer 140; and a source or drain electrode 142a and the source or drain electrode 142b, in which the oxide semiconductor layer 140 the bottom surface 140 in contact with the oxide semiconductor layer. 另外,平面的结构可以根据截面而适当地改变,因此,这里只示出截面结构。 Further, the planar structure can be appropriately changed according to the cross-section, and therefore, here, only the cross-sectional structure is shown.

[0198] 图12所示的结构和图2A和2B所示的结构的一大不同之处在于:存在源电极或漏电极142a和源电极或漏电极142b与氧化物半导体层140连接的连接位置。 And the structure shown in FIG. [0198] FIG. 12 2A differs from a large structure and 2B in that: the drain or source electrode connected to the presence and location of a source or drain electrode 142b connected to the electrode 140 with the oxide semiconductor layer 142a . 就是说,在图2A和2B所示的结构中,源电极或漏电极142a和源电极或漏电极142b在氧化物半导体层140的顶表面接触氧化物半导体层140 ;另一方面,在图12所示的结构中,源电极或漏电极142a和源电极或漏电极142b在氧化物半导体层140的底表面处接触氧化物半导体层140。 That is, in the configuration shown in FIGS. 2A and 2B, the source or drain electrode 142a and the source or drain electrode 142b in the oxide semiconductor layer in contact with a top surface of the oxide semiconductor layer 140, 140; on the other hand, in FIG. 12 in the configuration shown, the source or drain electrode 142a and the source or drain electrode 142b of the oxide semiconductor layer in contact with the bottom surface of the oxide semiconductor layer 140 is 140. 另外,由于接触的不同,其他电极或其他绝缘层等的位置也发生变化。 Further, due to the different contact positions of the other electrodes or other insulating layer or the like is also changed. 各部件的详细与图2A 和2B等中那些部件相同。 Like those of the same components and detailed view of components 2A and 2B.

[0199] 具体地,晶体管162包括:设置在层间绝缘层128上的栅电极136d ;设置在栅电极136d上的栅极绝缘层138 ;设置在栅极绝缘层138上的源电极或漏电极142a和源电极或漏电极142b ;以及接触源电极或漏电极142a和源电极或漏电极142b的顶表面的氧化物半导体层140。 [0199] Specifically, transistor 162 comprises: disposed on the interlayer insulating layer 128 of the gate electrode 136d; a gate insulating layer disposed over the gate electrode 136d, 138; source electrode or drain insulating layer over the gate electrode 138 and the source electrode 142a or drain electrode 142b; and contacting the source or drain electrode 142a and the source or drain electrode 142b of the top surface of the oxide semiconductor layer 140.

[0200] 这里,栅电极136d设置为嵌入在形成在层间绝缘层128上的绝缘层132中。 [0200] Here, the gate electrode 136d is provided to be embedded in the insulating layer 132 is formed on the interlayer insulating layer 128.. 另夕卜,与栅电极136d类同的,分别形成接触于源电极或漏电极130a的电极136a、接触于源电极或漏电极130b的电极136b以及接触于电极130c的电极136c。 Another Bu Xi, similar to the gate electrode 136d are formed in contact with the source electrode 130a or drain electrode 136a, in contact with the source or drain electrode 130b of the electrode 136b to the electrode and the contact electrode 130c, 136c.

[0201] 另外,在晶体管162上,设置有保护绝缘层144,其与氧化物半导体层140的一部分接触。 [0201] Further, in the transistor 162, a protective insulating layer 144 in contact with the oxide semiconductor layer 140 is a part. 在保护绝缘层144上设置有层间绝缘层146。 An insulating layer 146 is provided over the protective interlayer insulating layer 144. 这里,在保护绝缘层144和层间绝缘层146中,形成有到达源电极或漏电极142a和源电极或漏电极142b的开口。 Here, in the inter-layer insulating layer 144 and the protective insulating layer 146 is formed reaching the source or drain electrode 142a and the source or drain electrode 142b of the opening. 在这些开口中, 电极150d及电极150e被形成为分别与源电极或漏电极142a和源电极或漏电极142b接触。 In these openings, the electrode 150d and the electrode 150e is formed in contact with the source or drain electrode 142a and the source or drain electrode 142b. 与电极150d及电极150e类似地,电极150a、电极150b以及电极150c被形成为在设置在栅极绝缘层138、保护绝缘层144和层间绝缘层146中的开口中与电极136a、电极136b以及电极136c接触。 Electrode 150d and 150e and the electrode Similarly, the electrode 150a, the electrode 150b and the electrode 150c is formed 136a, the electrode 136b is provided on the gate insulating layer 138, the protective layer 144 and the interlayer insulating layer, the insulating layer 146 and the electrode opening a contact electrode 136c.

[0202] 另外,在层间绝缘层146上设置有绝缘层152。 [0202] Further, an insulating layer 152 on the interlayer insulating layer 146. 将电极154a、电极154b、电极154c 以及电极154d设置为嵌入该绝缘层152中。 The electrode 154a, an electrode 154b, an electrode 154c and the electrode 154d is provided to be embedded in the insulating layer 152. 这里,电极154a接触于电极150a,电极154b接触于电极150b,电极154c接触于电极150c及电极150d,并且电极154d接触于电极150e。 Here, the electrode 154a in contact with the electrode 150a, the electrode 154b in contact with the electrode 150b, an electrode 154c in contact with the electrode 150c and the electrode 150 d, 154d and the electrode in contact with the electrode 150e.

[0203] 图13A和13B示出在氧化物半导体层140上具有栅电极136d的例子。 [0203] FIGS. 13A and 13B show an example of a gate electrode 136d on the oxide semiconductor layer 140. 这里,图13A 示出源电极或漏电极142a和源电极或漏电极142b在氧化物半导体层140的底表面处接触氧化物半导体层140的例子,而图13B示出源电极或漏电极142a和源电极或漏电极142b 在氧化物半导体层140的顶表面处接触氧化物半导体层140的例子。 Here, FIG 13A shows the source or drain electrode 142a and the source or drain electrode 142b in the example of the oxide semiconductor layer in contact with the bottom surface 140 of the oxide semiconductor layer 140, and FIG 13B shows the source or drain electrode 142a and the source electrode or drain electrode 142b in the example of the oxide semiconductor layer at the top surface 140 in contact with the oxide semiconductor layer 140.

[0204] 图13A和13B所示的结构和图2A和2B及图12所示的结构的较大不同之处在于: 在氧化物半导体层140上具有栅电极136d。 [0204] larger and differs from the configuration of FIGS. 13A and 2B and the structure shown in FIG. 12 and shown in FIG. 13B 2A in that: a gate electrode 136d over the oxide semiconductor layer 140. 另外,图13A所示的结构和图13B所示的结构的较大不同之处在于:源电极或漏电极142a和源电极或漏电极142b与氧化物半导体层140 的底表面接触还是与氧化物半导体层140的顶表面接触。 Further, the structure greatly different from the configuration shown in FIGS. 13A 13B and shown that: the source or drain electrode 142a and a bottom surface in contact with the source electrode or the drain electrode 142b and the oxide semiconductor layer 140 and the oxide or the top surface of the semiconductor layer 140 in contact. 另外,由于这些的不同,其他电极或绝缘层等的位置可以改变。 Further, since the position of these various other electrodes or the like of the insulating layer may be changed. 各部件的细节与图2A和2B等的相同。 Details are the same for each member of FIG. 2A and 2B and the like.

[0205] 具体地,在图13A中,晶体管162包括:设置在层间绝缘层128上的源电极或漏电极142a和源电极或漏电极142b ;接触源电极或漏电极142a和源电极或漏电极142b的顶表面的氧化物半导体层140 ;设置在氧化物半导体层140上的栅极绝缘层138 ;以及与氧化物半导体层140重叠的区域中设置在栅极绝缘层138上的栅电极136d。 [0205] Specifically, in FIG. 13A, the transistor 162 includes: a source electrode or a drain electrode on the interlayer insulating layer 128 of the electrode 142a and the source or drain electrode 142b; contacting the source or drain electrode 142a and the source electrode or drain electrode 142b is the top surface of the oxide semiconductor layer 140; the gate insulating layer 138 is disposed on the oxide semiconductor layer 140; 136d and a gate electrode disposed on the gate insulating layer 138 and the region 140 overlapping with the oxide semiconductor layer .

[0206] 在图13B中,晶体管162包括:设置在层间绝缘层128上的氧化物半导体层140 ;设置为与氧化物半导体层140的顶表面接触的源电极或漏电极142a和源电极或漏电极142b ; 设置在氧化物半导体层140、源电极或漏电极142a和源电极或漏电极142b上的栅极绝缘层138 ;以及在重叠于氧化物半导体层140的区域中设置在栅极绝缘层138上的栅电极136d。 [0206] In FIG 13B, the transistor 162 includes: an oxide semiconductor layer 140 is disposed on the interlayer insulating layer 128; source electrode or drain is provided in contact with the top surface of the oxide semiconductor layer 140 and the source electrode or electrode 142a drain electrode 142b; 140 is provided, the source electrode or drain electrode 142a and the oxide semiconductor layer, a gate insulating layer on the source electrode or the drain electrode 142b 138; and is provided in the gate insulating region 140 overlaps with the oxide semiconductor layer the gate electrode 136d on the layer 138.

[0207] 另外,在图13A和13B所示的结构中,有时可以将图2A和2B等中示出了的部件省略(例如,电极150a或电极154a等)。 [0207] Further, in the structure shown in FIGS. 13A and 13B, can be sometimes FIGS. 2A and 2B illustrate other components will be omitted (e.g., the electrode 150a or the electrode 154a and the like). 在此情况下,可以得到制造工艺的简化的效果。 In this case, it is possible to obtain the effect of simplifying the manufacturing process. 当然, 在图2A和2B等所示的结构中也可以省略不必要的部件。 Of course, in the configuration shown in Figures 2A and 2B may be omitted, and the like unnecessary parts.

[0208] 图14A和14B示出在元件的尺寸比较大并且在氧化物半导体层140下设置栅电极136d的结构的例子。 [0208] FIGS. 14A and 14B show the structure and the gate electrode 136d is disposed in the oxide semiconductor layer 140 is an example of the size of elements is relatively large. 在此情况下,因为对表面的平坦度或覆盖度的要求不太高,因此不需要将布线或电极等形成为嵌入绝缘层中。 In this case, since the requirements for the flatness or coverage of the surface is not too high, it is not necessary to other wiring or an electrode formed to be embedded in the insulating layer. 例如,可以通过在形成导电层之后进行构图,来形成栅电极136d等。 For example, by performing patterning after forming the conductive layer to form the gate electrode 136d and the like. 另外,虽然这里未图示,但是也可以类同地制造晶体管160。 Further, although not illustrated herein, but may be manufactured similar transistor 160.

[0209] 另外,图14A所示的结构和图14B所示的结构的较大不同之处在于:源电极或漏电极142a和源电极或漏电极142b与氧化物半导体层140的底表面接触还是与氧化物半导体层140的顶表面接触。 [0209] Further, the structure greatly different from the configuration shown in FIGS. 14A 14B and shown that: a bottom surface contacting the source or drain electrode 142a and the source or drain electrode 142b and the oxide semiconductor layer 140 or contact with the top surface of the oxide semiconductor layer 140. 另外,由于这些的不同,其他电极或绝缘层等的位置可以发生改变。 Further, since the position of these various other electrodes or the like of the insulating layer may change. 各部件的详细说明与图2A和2B等的相同。 The same detailed description of each member of FIG 2A and 2B and the like.

[0210] 具体地,在图14A中,晶体管162包括:设置在层间绝缘层128上的栅电极136d ; 设置在栅电极136d上的栅极绝缘层138 ;设置在栅极绝缘层138上的源电极或漏电极142a 和源电极或漏电极142b ;以及接触源电极或漏电极142a和源电极或漏电极142b的顶表面的氧化物半导体层140。 [0210] Specifically, in FIGS. 14A, transistor 162 comprising: an interlayer insulating layer disposed on the gate electrode 128 on 136d; 136d disposed on the gate electrode 138 of the gate insulating layer; disposed over the gate insulating layer 138 the source or drain electrode 142a and the source or drain electrode 142b; and contacting the source or drain electrode 142a and the source or drain electrode 142b of the top surface of the oxide semiconductor layer 140.

[0211] 在图14B中,晶体管162包括:设置在层间绝缘层128上的栅电极136d ;设置在栅电极136d上的栅极绝缘层138 ;在重叠于栅电极136d的区域中设置在栅极绝缘层138上的氧化物半导体层140 ;以及设置为接触氧化物半导体层140的顶表面的源电极或漏电极142a和源电极或漏电极142b。 [0211] In FIG. 14B, the transistor 162 includes: the gate electrode 136d provided on the interlayer insulating layer 128; a gate insulating layer 138 on the gate electrode 136d; a gate disposed in the region of overlap with the gate electrode 136d in an oxide semiconductor layer on the gate insulating layer 138 140; and a source electrode arranged in contact with the top surface of the oxide semiconductor layer 140 and the source or drain electrode 142a or drain electrode 142b.

[0212] 另外,在图14A和14B所示的结构中,有时可以从图2A和2B等所示的结构中省略某些部件。 [0212] Further, in the structure shown in FIG 14A 14B, sometimes 2A and 2B like the structure shown some components omitted from FIG. 在此情况下,也可以得到制造工艺简化的效果。 In this case, the manufacturing process can be simplified to obtain the effect.

[0213] 图15A和15B示出在元件的尺寸比较大并且在氧化物半导体层140上设置栅电极136d的结构的例子。 [0213] FIGS. 15A and 15B show the structure of a relatively large size element and the gate electrode 136d provided on the oxide semiconductor layer 140 is an example. 在此情况下,因为对表面的平坦度或覆盖度的要求不太高,因此不需要将布线或电极等形成为嵌入绝缘层中。 In this case, since the requirements for the flatness or coverage of the surface is not too high, it is not necessary to other wiring or an electrode formed to be embedded in the insulating layer. 例如,可以通过在形成导电层之后进行构图,来形成栅电极136d等。 For example, by performing patterning after forming the conductive layer to form the gate electrode 136d and the like. 另外,虽然这里未图示,但是也可以类同地制造晶体管160。 Further, although not illustrated herein, but may be manufactured similar transistor 160.

[0214] 图15A所示的结构和图15B所示的结构的较大不同之处在于:源电极或漏电极142a和源电极或漏电极142b与氧化物半导体层140的底表面接触还是与氧化物半导体层140的顶表面接触。 Greatly different from the [0214] structure shown in FIG. 15A and FIG. 15B configuration in that: the source or drain electrode 142a and a bottom surface in contact with the source electrode or the drain electrode 142b and the oxide semiconductor layer 140 and the oxide or the top surface of semiconductor layer 140 in contact. 由于这些的不同,其他电极或绝缘层等的为可以发生改变。 Since these are different from the other electrodes or the like of the insulating layer may change. 各部件的详细说明与图2A和2B等的相同。 The same detailed description of each member of FIG 2A and 2B and the like.

[0215] 具体地,在图15A中,晶体管162包括:设置在层间绝缘层128上的源电极或漏电极142a和源电极或漏电极142b ;接触源电极或漏电极142a和源电极或漏电极142b的顶表面的氧化物半导体层140;设置在源电极或漏电极142a、源电极或漏电极142b以及氧化物半导体层140上的栅极绝缘层138;以及在重叠于氧化物半导体层140的区域中设置在栅极绝缘层138上的栅电极136d。 [0215] Specifically, in FIG. 15A, the transistor 162 includes: a source electrode or a drain electrode on the interlayer insulating layer 128 of the electrode 142a and the source or drain electrode 142b; contacting the source or drain electrode 142a and the source electrode or drain electrode 142b is the top surface of the oxide semiconductor layer 140; provided the source or drain electrode 142a, the source or drain electrode 142b and the gate insulating layer 140 on the oxide semiconductor layer 138; and overlaps with the oxide semiconductor layer 140 region is provided on the gate insulating layer 138 of the gate electrode 136d.

[0216] 在图15B中,晶体管162包括:设置在层间绝缘层128上的氧化物半导体层140; 设置为接触氧化物半导体层140的顶表面的源电极或漏电极142a和源电极或漏电极142b; 设置在源电极或漏电极142a、源电极或漏电极142b、以及氧化物半导体层140上的栅极绝缘层138 ;以及在重叠于氧化物半导体层140的区域中设置在栅极绝缘层138上的栅电极136d。 [0216] In FIG 15B, the transistor 162 includes: an oxide semiconductor disposed on the interlayer insulating layer 128 on layer 140; a top surface disposed in contact with the oxide semiconductor layer 140, a source or drain electrode 142a and the source or drain electrode electrode 142b; provided the source or drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 138 on the gate insulating layer 140; and a gate disposed in the region of overlap with the insulating layer 140 of the oxide semiconductor the gate electrode 136d on the layer 138.

[0217] 另外,在图15A和15B所示的结构中,有时可以省略图2A和2B所示的结构中的部件。 [0217] Further, in the structure shown in FIGS. 15A and 15B, sometimes the structure member and 2B is omitted in FIG. 2A. 在此情况下,也可以得到制造工艺的简化的效果。 In this case, the effect can be obtained in the manufacturing process simplified.

[0218] 如上所述,根据所公开的发明的一个实施例,实现了具有新的结构的半导体装置。 [0218] As described above, according to one embodiment of the disclosed embodiment of the invention, to achieve a semiconductor device having a new structure. 虽然在本实施例中,晶体管160和晶体管162层叠,但是半导体装置的结构不限于此。 Although this embodiment, transistor 160 and transistor 162 are stacked in the present embodiment, but the structure of the semiconductor device is not limited thereto. 另外, 虽然说明了晶体管160和晶体管162的沟道长度方向相互垂直的例子,但是晶体管160和晶体管162的位置不限于此。 Further, although described in the channel length direction of the transistor 162 and the transistor 160 are perpendicular to each example, the position of the transistor 160 and the transistor 162 is not limited thereto. 此外,也可以将晶体管160和晶体管162设置为彼此重叠。 Furthermore, transistor 160 may be set and the transistor 162 overlap each other.

[0219] 另外,尽管在本实施例中,为了便于理解而说明了最小存储单位(1位)的半导体装置,但是半导体装置的结构不限于此。 [0219] Further, although in the present embodiment, for ease of understanding the description smallest unit of storage (1) of the semiconductor device, the structure of the semiconductor device is not limited thereto. 也可以通过适当地连接多个半导体装置而构成更高级的半导体装置。 It may be constituted of a semiconductor device higher by appropriately connecting a plurality of semiconductor devices. 例如,可以使用多个上述半导体装置构成NAND型或N0R型的半导体装置。 For example, the semiconductor device may be configured using a plurality of NAND type or N0R type semiconductor device. 布线的结构也不局限于图1所示,并且可以适当地改变布线的结构。 The wiring structure shown in Figure 1 is not limited, and may be changed as appropriate cabling.

[0220] 在根据本实施例的半导体装置中,晶体管162的低截止电流使得能够在极长时间内保持信息。 [0220] In the semiconductor device of the present embodiment, a low off-state current of the transistor 162 so that information can be held in a very long time. 也就是说,不需要进行DRAM等所需要的刷新操作,因而可以抑制功耗。 That is, the refresh operation of the DRAM does not require the like required, power consumption can be suppressed. 另外, 可以将该半导体装置基本上用作非易失性存储装置。 Further, the semiconductor device can be substantially as a non-volatile memory device.

[0221] 另外,因为通过晶体管162的开关操作而进行信息写入,因此在该半导体装置中不需要高电位,也没有元件劣化的问题。 [0221] Further, since the switching operation is performed by the transistor 162 for writing information, without high potential in this semiconductor device, there is no problem of deterioration of elements. 此外,根据晶体管的导通或截止而进行信息写入或擦除,从而也可以容易实现高速操作。 Further, according to the transistor turned on or off while the information is written or erased, and thus high-speed operation can be easily realized. 另外,通过控制输入到晶体管的电位,可以直接重写信息。 Further, by controlling the input to the potential of the transistor can be directly overwrite information. 由此,不需要快闪存储器等所需要的擦除操作,并可以抑制由于擦除操作导致的操作速度的降低。 This eliminates the need of a flash memory erase operation required, and can suppress a decrease in operation speed due to the operation of erasure.

[0222] 另外,与使用氧化物半导体的晶体管相比,使用氧化物半导体以外的材料的晶体管可以进行更高速度的操作,因此,可以进行高速的存储信息的读出。 [0222] Further, as compared with a transistor using an oxide semiconductor, a material other than an oxide semiconductor transistor may operate in a higher speed, and therefore, a high speed can be read out of the stored information.

[0223] 本实施例所示的结构、方法等可以与其他实施例所示的结构、方法等适当地组合。 [0223] The structure shown in this embodiment, a method may be implemented with other embodiments shown in structures, methods, and other appropriate combination.

[0224] 实施例2 [0224] Example 2

[0225] 在本实施例中,将说明根据本发明的一个实施例的半导体装置的电路结构及其操作方法。 [0225] In the present embodiment, the circuit configuration and operation method of a semiconductor device in accordance with one embodiment of the present invention.

[0226]〈存储单元的结构〉 [0226] <of the memory cells>

[0227] 图16示出半导体装置所具有的存储单元电路图的一个例子。 [0227] FIG. 16 shows an example of a circuit diagram of a memory cell having a semiconductor device. 图16所示的存储单元200包括第一信号线S1、字线WL、晶体管201 (第一晶体管)、晶体管202 (第二晶体管)、 以及电容器203。 Memory cell shown in FIG. 16, 200 includes a first signal lines S1, the word line WL, transistors 201 (a first transistor), a transistor 202 (a second transistor), and a capacitor 203. 晶体管201使用氧化物半导体以外的材料而形成,晶体管202使用氧化物半导体而形成。 Material other than an oxide semiconductor transistor 201 is formed using an oxide semiconductor transistor 202 is formed. 这里,晶体管201优选具有与实施例1所示的晶体管160类同的结构。 Here, the transistor 201 preferably has a structure shown in Example 1 of the embodiment is similar to transistor 160. 另夕卜,晶体管202优选具有与实施例1所示的晶体管162类同的结构。 Another Bu Xi, transistor 202 preferably has a structure of the transistor shown in Embodiment 1162 is similar. 另外,存储单元200电连接到源极线SL及位线BL,也可以经由晶体管(包括其他存储单元中的晶体管)电连接到源极线SL及位线BL。 Further, the storage unit 200 is electrically connected to the source line SL and bit line BL, it can be electrically connected to the source line SL and bit line BL via a transistor (including other memory cell transistors).

[0228] 这里,晶体管201的栅电极、晶体管202的源电极和漏电极中的一方、以及电容器203的电极中的一方相互电连接。 [0228] Here, the gate electrode of the transistor 201, one of a source electrode of the transistor 202 and the drain electrode, and one electrode of the capacitor 203 is electrically connected to each other. 另外,源极线SL与晶体管201的源电极相互电连接。 Further, the source line SL and a source electrode of the transistor 201 are electrically connected. 位线BL与晶体管201的漏电极相互电连接。 Bit line BL and the drain of the transistor 201 are electrically connected to the electrode. 第一信号线S1与晶体管202的栅电极相互电连接。 A first signal line S1 are electrically connected to the gate electrode of the transistor 202. 字线WL、晶体管202的源电极和漏电极中的另一方、以及电容器203的电极中的另一方相互电连接。 A word line WL, the source electrode of the transistor 202 and the drain of the other, and the electrode of the capacitor 203 are electrically connected to the other one. 另外,源极线SL和晶体管201的源电极可以经由晶体管(包括其他存储单元中的晶体管)相互连接。 Further, the source line SL and a source electrode of the transistor 201 may be connected to each other via a transistor (including other memory cell transistors). 另外,位线BL和晶体管201的漏电极可以经由晶体管(包括其他存储单元中的晶体管)相互连接。 Further, bit line BL and the drain electrode of the transistor 201 can be connected to each other via a transistor (including other memory cell transistors).

[0229]〈半导体装置的结构〉 [0229] <Structure of Semiconductor Device>

[0230] 图17示出具有mXn位的存储容量的半导体装置的模块电路图。 [0230] FIG. 17 shows a block circuit diagram of a semiconductor memory device having a mXn bits capacity. 这里,作为一个例子,示出其中存储单元200相互串联连接的NAND型半导体装置。 Here, as an example, illustrating the NAND type semiconductor device in which memory cells 200 are connected in series to each other.

[0231] 根据本发明的一个实施例的半导体装置包括:m个字线WL ;n个位线BL ;n个第一信号线S1;两个选择线SEL (1)及SEL (2);存储单元阵列210,其中多个存储单元200 (1、 1)至200 (m、n)配置为m行(横向)Xn列(纵向)(m、n为自然数)的矩阵形式;晶体管215 (1、1)至215 (l、n),沿选择线SEL (1)配置在位线BL (1)至BL (n)与存储单元200 (1、 1)至200 (l、n)之间;晶体管215 (2、1)至215 (2、n),沿选择线SEL (2)配置在源极线SL (1)至SL (n)与存储单元200 (m、l)至200 (m、n)之间;以及外围电路,诸如位线及第一信号线的驱动电路211、字线的驱动电路213、以及读出电路212。 [0231] In accordance with one embodiment of the present invention, a semiconductor device of the embodiment comprises: m word lines WL; n bit lines BL; n of first signal lines Sl; two select lines SEL (1) and SEL (2); memory cell array 210, wherein the plurality of memory cells 200 (1, 1) to 200 (m, n-) m rows (horizontal) Xn column (longitudinal) (m, n-a natural number) in a matrix form; transistor 215 (1, 1) to 215 (l, n), the SEL along the selection line (1) arranged in the bit line BL (1) to between BL (n) and the storage unit 200 (1, 1) to 200 (l, n); transistor 215 (2, 1) to 215 (2, n), along a selection line SEL (2) disposed on the source line SL (1) to SL (n) and the storage unit 200 (m, l) to 200 (m, n between); and a drive circuit 211 peripheral circuits such as a bit line and the first signal line, a word line drive circuit 213, and a readout circuit 212. 作为其他外围电路,也可以设置有刷新电路等。 Examples of the other peripheral circuits, may be provided with a refresh circuit.

[0232] 存储单元200 (i、j)(这里,i为大于或等于1且小于或者等于m的整数,j为大于或等于1且小于或者等于n的整数)连接到第一信号线SI (j)及字线WL (i)。 [0232] The storage unit 200 (i, j) (where, i is greater than or equal to 1 and less than or equal to an integer m, j is greater than or equal to 1 and less than or equal to the integer n) is connected to a first signal line SI ( j) and the word line WL (i). 另外,存储单元200 (ip j) (L为2至m的整数)所具有的晶体管201的漏电极连接到存储单元200 (ii_l、j)所具有的晶体管201的源电极。 Further, the storage unit 200 (ip j) (L is an integer of 2 to m) of the transistor 201 has a drain connected to the source electrode of the storage unit 200 (ii_l, j) has a transistor 201. 另外,存储单元200 (l、j)所具有的晶体管201 的漏电极连接到晶体管215 (l、j)的源电极,并且存储单元200 (m、j)所具有的晶体管201 的源电极连接到晶体管215 (2、j)的漏电极。 A source electrode Further, a drain 200 (l, j) has a transistor memory cell 201 is connected to the transistor 215 (l, j) of the source electrode, and the storage unit 200 (m, j) has a transistor 201 connected to the transistor 215 (2, j) is the drain electrode. 晶体管215 (l、j)的漏电极连接到位线BL (j),而晶体管215 (2、j)的源电极连接到源极线SL (j)。 Transistor 215 (l, j) is a drain electrode connected to bit line BL (j), and the transistor 215 (2, j) a source electrode connected to the source line SL (j). 另外,晶体管215 (l、j)的栅电极连接到选择线SEL (1),晶体管215 (2、j)栅电极连接到选择线SEL (2)。 Further, the transistor 215 (l, j) the gate electrode is connected to the select line SEL (1), the transistor 215 (2, j) a gate electrode connected to the selection line SEL (2).

[0233] 另外,位线BL (1)至BL (n)及第一信号线SI (1)至SI (n)连接到位线及第一信号线的驱动电路211。 [0233] Further, the bit line BL (1) to BL (n) and the first signal line SI (1) to SI (n) and the bit line connected to the first signal line driver circuit 211. 字线WL (1)至WL (m)和选择线SEL (1)及SEL (2)连接到字线的驱动电路213。 Word lines WL (1) to WL (m) and a selection line SEL (1) and SEL (2) is connected to the word line driving circuit 213. 另外,位线BL (1)至BL (n)也连接到读出电路212。 Further, the bit line BL (1) to BL (n) is also connected to the readout circuit 212. 电位Vs施加到源极线SL (1)至SL (n)。 Potential Vs is applied to the source line SL (1) to SL (n). 另外,源极线SL (1)至SL (n)并不必须分开而,也可以互相电连接。 Further, the source lines SL (1) to SL (n) are not necessarily separate and may be electrically connected to each other.

[0234]〈半导体装置的操作〉 [0234] <Operation of Semiconductor Device>

[0235] 接着,将说明图17所示的半导体装置的操作。 [0235] Next, operation of the semiconductor device shown in FIG. 17 will be explained. 在本结构中,按列进行写入,并按行进行读出。 In this configuration, by writing a column, read out row by row.

[0236] 在对第j列中的存储单元200 (l,j)至200 (m,j)写入时,将第一信号线SI (j) 的电位设定为VI(任意电位,例如2V),以使目标存储单元的晶体管202处于导通状态。 [0236] When writing to the j-th column in the memory cell 200 (l, j) to 200 (m, j), the first line of the SI signal (j) is set to the potential VI (an arbitrary potential, e.g. 2V ) to make the transistors target memory cell 202 in the oN state. 另一方面,将除第一信号行SI (j)以外的第一信号线S1的电位设定为V0 (任意电位,例如0V), 以使非目标存储单元的晶体管202处于截止状态。 On the other hand, the potential of signal line other than the first row of the first signal SI (j) is set to S1 of V0 (arbitrary potential, for example 0V), so that the transistor 202 non-target memory cell in an off state. 至于其他布线,将位线BL (1)至BL (n) 的电位、选择线SEL (1)及SEL (2)的电位、以及源极线SL (1)至SL (n)的电位Vs设定为V0。 As another wiring, the bit line BL (1) to BL (n) the potential, the select line SEL (1) and SEL (2) the potential, and the source lines SL (1) to SL (n) of the potential Vs provided as V0. 这里,电位VI被设定为通过将其施加到栅电极使晶体管201、晶体管202以及晶体管215处于导通状态的电位。 Here, the potential VI is set by applying it to the gate electrode of the transistor 201, the transistor 202 in a conducting state and a potential of the transistor 215. 电位V0被设定为通过将其施加到栅电极而使晶体管201、晶体管202以及晶体管215处于截止状态的电位。 It is set to a potential V0 by the transistor 201 which is applied to the gate electrode of transistor 202 and transistor 215 at the potential of the OFF state.

[0237] 当在这个状态下,将字线WL的电位VWL设定为预定的电位时,数据被写入。 [0237] When in this state, the potential VWL of the word line WL is set to a predetermined potential, data is written. 例如, 在写入数据" 1"时,将连接到目标存储单元的字线WL的电位设定为Vw_l,而在写入数据"0" 时,将连接到目标存储单元的字线WL的电位设定为Vw_0。 For example, the data "1" is connected to the word line WL of the target memory cell potential is set Vw_l, and when writing data "0", the memory cell connected to the target potential of the word line WL set Vw_0. 另外,在写入结束时,在字线WL 的电位变化之前,将第一信号线Sl(j)的电位设定为V0,从而使目标存储单元的晶体管202 处于截止状态。 Further, at the end of writing, before the potential change of the word line WL, the first signal line Sl (j) is set to a potential V0, so that the target memory cell transistor 202 is turned off.

[0238] 这里,对应于写入时的字线WL的电位VWL的电荷QA被累积在连接到晶体管201 的栅电极的节点(以下称为节点A)中,由此存储数据。 [0238] Here, the corresponding word line WL is a write potential VWL QA charges are accumulated in the node connected to the gate electrode of the transistor 201 (hereinafter, referred to as Node A), thereby storing data. 这里,晶体管202的截止电流极小或者基本为0,因此在长时间内保持所写入的数据。 Here, the current of the transistor 202 is extremely small or substantially zero, thus holding the written data for a long time. 在其他列中的存储单元中,存储到节点A 中累积的电荷QA不变。 In the other columns the storage unit stores the charge accumulated in the node A QA unchanged.

[0239] 另外,虽然在写入时位线BL (1)至BL (n)的电位被设定为V0,但是这些电位也可以处于浮置状态,或者可以充电到任意电位,只要晶体管215 (1,1)至215 (l,n)处于截止状态即可。 [0239] Further, although the write bit line BL (1) to a potential BL (n) is set to V0, the potential of these may be in a floating state, or may be charged to an arbitrary potential, as long as transistor 215 ( 1, 1) to 215 (l, n) to an off state.

[0240] 另外,在进行写入时,在半导体装置没有衬底电位的情况下,诸如在晶体管形成在SOI衬底上的情况下,例如,如下将数据写入到存储单元:首先,将选择线SEL (1)的电位设定为V0,并且将选择线SEL (2)的电位设定为VI,从而使晶体管215 (1,j)处于截止状态并且使晶体管215 (2, j)处于导通状态。 In the case [0240] Further, when writing is performed, the semiconductor device in the case without a substrate potential, such as a transistor formed on the SOI substrate, for example, the following writing data to the memory cell: first, the selection line SEL (1) is set to the potential V0, and the selection line SEL (2) is set to the potential VI, so that the transistor 215 (1, j) in an off state and the transistor 215 (2, j) in the ON state. 第一信号线SI (j)的电位设定为VI,以使第j列中的存储单元200 (l,j)至200 (m,j)的晶体管202处于导通状态。 The first line of the SI signal (j) is set to the potential VI, such that the j-th column in the memory cell 200 (l, j) to 200 (m, j) of the transistor 202 in the ON state. 另外,字线WL (1)至WL (m)的电位设定为VI,以使第j列中的存储单元200 (l,j)至200 (m,j)的晶体管201 处于导通状态。 Further, the word lines WL (1) to WL (m) is set to the potential Vl, j-th column so that the memory cell 200 (l, j) to 200 (m, j) of the transistor 201 in the ON state. 然后,从第一行中的存储单元200 (l,j)开始,将字线WL的电位VWL设定为预定的电位,以进行上述数据的写入。 Then, from the first row of the storage unit 200 (l, j) begins, the potential VWL of the word line WL is set to a predetermined potential, for writing said data. 在到第m行中的存储单元200 (m,j)的数据写入完时,将选择线SEL (2)的电位设定为V0,从而使晶体管215 (2, j)处于截止状态。 In the m-th row data to the memory cell 200 (m, j) is finished writing, the selection line SEL (2) is set to a potential V0, so that the transistor 215 (2, j) in an off state. 由此, 可以在将第j列中的存储单元的晶体管201的源电极的电位设定为大约V0的同时进行写入数据。 Thereby, the potential of the source electrode of the transistor in the j-th column of the memory cell 201 is set to write data simultaneously V0 is about. 另外,可以以与上述的数据写入类同的方式进行到其他布线的数据写入。 Further, the data can be written to another wiring in a manner similar to the above written data. 另外,虽然已经说明了从第一行到第m行进行数据写入的方法,但是本发明不限于此。 Further, although the method has been described for writing data from the first row to the m-th row, but the present invention is not limited thereto. 也可以将位线BL (1)至BL (n)的电位设定为V0,并且将选择线SEL (1)的电位设定为VI以使晶体管215 (1,j)处于导通状态,从而可以从第m行到第一行进行数据写入。 It may be the bit line BL (1) to a potential BL (n) is set to V0, and the selection line SEL (1) is set to the potential of the transistor VI to 215 (1, j) in the conduction state, whereby data can be written to the m-th row from the first row.

[0241] 另一方面,在半导体装置具有衬底电位的情况下,诸如在将晶体管形成在单晶半导体衬底上的情况下,可以利用0V的衬底电位设进行上述数据写入。 In the case [0241] On the other hand, in the case where a semiconductor device having a substrate potential, such as a transistor formed on a single crystal semiconductor substrate, may be provided by using the above-described data writing substrate potential of 0V.

[0242] 通过将字线WL的电位VWL设定为预定的电位,对第i行中的存储单元200 (i,1) 至200 (i,n)进行读出。 [0242] VWL of the word line WL is set by the potential of a predetermined potential, the i-th row of the memory cell 200 (i, 1) to 200 (i, n) is read out. 在对第i行中的存储单元200 (i,l)至200 (i,n)进行读出时, 将选择线SEL (1)及SEL (2)的电位设定为VI,将第一信号线SI (1)至SI (n)的电位设定为V0,将源极线SL (1)至SL (n)的电位Vs设定为V0,并且使连接到位线BL (1)至BL (n)的读出电路212处于操作状态。 When the potential of the i-th row memory cell 200 (i, l) to 200 (i, n) is read out, the selection line SEL (1) and SEL (2) is set to Vl, the first signal line SI (1) to SI (n) is set to a potential V0, the source line SL (1) to SL (n) the potential Vs is set to V0, and the connected bit line BL (. 1) to BL ( n) the readout circuit 212 in an operating state. 由此,使晶体管215 (1,1)至215 (2, n)处于导通状态,并且使所有存储单元的晶体管202处于截止状态。 Accordingly, the transistors 215 (1, 1) to 215 (2, n) in the ON state, and the transistors of all the memory cells 202 in an off state.

[0243] 然后,将字线WL (i)的电位设定为Vr_l,并将第i行以外的行的字线WL的电位设定为Vr_0。 [0243] Then, the word line WL (i) is set to the potential Vr_l, the word lines other than the row line WL and the potential of the i-th set Vr_0. 此时,第i行以外的存储单元的晶体管201处于导通状态。 In this case, the memory cell transistors other than the i-th row 201 in the ON state. 结果,根据第i行中的存储单元的晶体管201的装置是处于导通状态还是处于截止状态而决定存储单元列的电阻状态。 As a result, the transistor means i-th row of the memory cell 201 is in the ON state according to an off state is determined or the resistance state of the memory cell column. 在第i行中的具有数据"〇"的存储单元中,晶体管201处于截止状态,因此该存储单元列处于高电阻状态。 In the i-th row of data having the "square" of the memory cell, the transistor 201 is in an off state, so that the column of memory cells in a high resistance state. 另一方面,在第i行中的具有数据"1"的存储单元中,晶体管201处于导通状态,因此,该存储单元列处于低电阻状态。 On the other hand, the i-th row of data having "1" in the memory cell, the transistor 201 in the ON state, and therefore, the memory cell column in a low resistance state. 结果,读出电路212可以根据存储单元列的电阻状态的不同而读出数据"〇"或" 1"。 As a result, the readout circuit 212 can read the data "square" or "1" depending on the resistance state of the memory cell column.

[0244] 以下,说明写入时字线WL的电位Vw_0及Vw_l、读出时字线WL的电位Vr_0及Vr_l 的确定方法。 [0244] Hereinafter, the potential Vw_0 Vw_l writing and the word line WL, read out the method for determining the potential of the word line WL and Vr_l of Vr_0.

[0245] 确定晶体管201的状态的节点A的电位VA取决于晶体管201的栅极和晶体管201 的源极(漏极)间的电容C1和电容器203的电容C2。 Potential VA [0245] state of the transistor 201 to determine the node A depends on the gate of transistor 201 and the source of the transistor 201 and the capacitor C1 is the capacitance between electrode (drain) of the capacitor C2 203. 利用写入时的字线WL的电位VWL(写) 以及读出时的字线WL的电位VWL (读),VA可以表示为如下: Using the writing word line WL of the VWL voltage (write) and read word line WL of the VWL voltage (read), VA may be expressed as follows:

[0246] VA= (C1 • VWL (写)+C2 • VWL (读))/ (C1+C2) [0246] VA = (C1 • VWL (write) + C2 • VWL (read)) / (C1 + C2)

[0247] 在其中读出被选择的存储单元200中,VWL (读)=Vr_l,而在其中读出未被选择的存储单元200中,VWL (读)=Vr_0。 [0247] in which the selected memory cell is read out in 200, VWL (read) = Vr_l, wherein the memory cell is read out in the unselected 200, VWL (read) = Vr_0. 另外,在写入数据"1"时,VWL (写)=Vw_l,而在写入数据"0"时,VWL (写)=Vw_0。 Further, in the data "1", the VWL (write) = Vw_l, and when writing data "0", VWL (write) = Vw_0. 就是说,各状态下的节点A的电位可以以下式表示: That is, the potential of the node A in each state can be represented by the following formula:

[0248] 在读出被选择并且写入有数据"1"的情况下,节点A的电位被表示如下: In the case [0248] is selected in the read and write data "1", the potential of the node A is expressed as follows:

[0249] VA ^ (C1 • Vw_l+C2 • Vr_l) / (C1+C2) [0249] VA ^ (C1 • Vw_l + C2 • Vr_l) / (C1 + C2)

[0250] 在读出被选择状态并且写入有数据"0"的情况下,节点A的电位被表示如下: In the case [0250] is selected in the read state and the write data "0", the potential of the node A is expressed as follows:

[0251] VA ^ (C1 • Vw_0+C2 • Vr_l) / (C1+C2) [0251] VA ^ (C1 • Vw_0 + C2 • Vr_l) / (C1 + C2)

[0252] 在读出未被选择并且写入有数据"1"的情况下,节点A的电位被表示如下: In the case [0252] is not selected in the read and write data "1", the potential of the node A is expressed as follows:

[0253] VA ^ (C1 • Vw_l+C2 • Vr_0) / (C1+C2) [0253] VA ^ (C1 • Vw_l + C2 • Vr_0) / (C1 + C2)

[0254] 在读出未被选择并且写入有数据"0"的情况下,节点A的电位被表示如下: In the case [0254] is not selected in the read and write data "0", the potential of the node A is expressed as follows:

[0255] VA ^ (C1 • Vw_0+C2 • Vr_0) / (C1+C2) [0255] VA ^ (C1 • Vw_0 + C2 • Vr_0) / (C1 + C2)

[0256] 在读出被选择且写入有数据"1"时,优选晶体管201处于导通状态,并且节点A的电位VA优选超过晶体管201的阈值电压V th。 [0256] is selected in the read and the write data "1", the transistor 201 is preferably in a conductive state, and the potential VA of the node A preferably exceeds the threshold voltage of the transistor is V th 201. 就是说,优选满足如下公式: That is, it is preferable to satisfy the following formula:

[0257] (C1 • Vw_l+C2 • Vr_l) / (C1+C2) >Vth [0257] (C1 • Vw_l + C2 • Vr_l) / (C1 + C2)> Vth

[0258] 在读出被选择且写入有数据"0"时,优选晶体管201处于截止状态,并且节点A的电位VA优选低于晶体管201的阈值电压V th。 [0258] a is selected, and when the read data is "0" is written, the transistor 201 is preferably in an off state, and the potential VA of the node A is preferably lower than the threshold voltage V th of the transistor 201. 就是说,优选满足如下公式: That is, it is preferable to satisfy the following formula:

[0259] (C1 • Vw_0+C2 • Vr_l) / (C1+C2) <Vth [0259] (C1 • Vw_0 + C2 • Vr_l) / (C1 + C2) <Vth

[0260] 在读出未被选择时,即使写入有数据"1"或数据"0",晶体管201也需要处于导通状态。 [0260] When the readout is not selected, even if the write data "1" or data "0", the transistor 201 need to be in a conducting state. 因此节点A的电位VA需要高于晶体管201的阈值电位V th。 Thus the potential VA of the node A needs to be above the threshold potential of transistor 201 is V th. 就是说,优选满足如下公式: That is, it is preferable to satisfy the following formula:

[0261] (C1 • Vw_l+C2 • Vr_0) / (C1+C2) >Vth [0261] (C1 • Vw_l + C2 • Vr_0) / (C1 + C2)> Vth

[0262] (Cl • Vw_0+C2 • Vr_0) / (C1+C2) >Vth [0262] (Cl • Vw_0 + C2 • Vr_0) / (C1 + C2)> Vth

[0263] 通过以满足上述关系的方式确定Vw_0、Vw_l、Vr_0、Vr_l等,可以使半导体装置操作。 [0263] By way of satisfying the above relationship is determined Vw_0, Vw_l, Vr_0, Vr_l the like, the semiconductor device can operate. 例如,在晶体管201的阈值电压V th=0. 3 (V)且C1/C2为1的情况下,可以将电位设置为:V0=0 (V),V1=2 (V),Vw_0=0 (V),Vw_l=2 (V),Vr_0=2 (V),Vr_l=0 (V)。 For example, the transistor 201 threshold voltage V th = 0 3 (V), and C1 / C2 is 1, and the potential of the set: V0 = 0 (V), V1 = 2 (V), Vw_0 = 0 (V), Vw_l = 2 (V), Vr_0 = 2 (V), Vr_l = 0 (V). 另外,这些电位只是一个例子,可以在满足上述条件的范围内适当地改变。 Further, these potentials is merely an example, can be suitably changed within a range satisfying the above conditions.

[0264] 这里,在Cl/C2〈〈l的条件下,节点A和字线WL紧密结合,因此不管晶体管202是处于导通状态还是处于截止状态,字线WL的电位与节点A的电位基本相同。 [0264] Here, under the condition of Cl / C2 << l, the node A and the word line WL closely, so whether the transistor 202 is in the ON state or in OFF state, the potential of the word line WL and the potential of the node A is substantially the same. 因此,即使在晶体管202处于导通的状态下写入数据时,节点A能够存储的电荷也是极少的,数据"0"和"1"之间的差异变小。 Accordingly, even when the data is written in the ON state of the transistor 202, the charge stored in the node A can also little difference between the "1" data "0" and smaller.

[0265] 具体地,在将所选择的字线WL的电位设定为Vr_l的同时进行上述读出的情况下, 不管是写入有数据"〇"还是写入有数据" 1",存储单元的节点A的电位都下降,从而使晶体管201处于截止状态。 In the case [0265] Specifically, in the selected word line WL is set to a potential Vr_l performed while the read, whether the data is written is "square" or write data "1", the memory cell a potential of the node are decreased, so that the transistor 201 is turned off. 结果,难以读出数据。 As a result, it is difficult to read data.

[0266] 另一方面,在C1/C2>>1的条件下,因为节点A和字线WL的结合较弱,因此即使字线WL的电位改变,节点A的电位也几乎不变。 [0266] On the other hand, under the condition of C1 / C2 >> 1, the node A because the binding is weak and the word line WL, even if the change in the potential of the word line WL, the potential of the node A hardly changes. 因此,能够控制晶体管201的导通状态和截止状态的节点A的电位非常有限,而难以控制晶体管201的导通状态和截止状态。 Accordingly, it is possible to control the potential of the node A transistor off state and the state 201 is limited, it is difficult to control the ON state and OFF state of the transistor 201.

[0267] 特别是,在将非选择的字线WL的电位设定为Vr_0并进行上述读出的情况下,存储单元的节点A的电位几乎不增加,并具有数据"0"的晶体管201处于截止状态。 In the case [0267] In particular, in the non-selected word line WL is set to the potential of the read Vr_0 and the potential of the node A of the memory cell hardly increases, and having a data "0" of the transistor 201 is the off-state. 结果,难以读出数据。 As a result, it is difficult to read data.

[0268] 因为存在随C1和C2的大小而难以进行操作的情况,因此在确定C1和C2时须加以关注。 [0268] Since the presence and size with the C1 and C2 is difficult to operate, thus determining the C1 and C2 shall be concerned. 另夕卜,在Vw_0为0 (V),Vw_l为Vdd,Vr_0为0 (V),Vr_l为Vdd的情况下,当C1/ C2在Vth/ (Vdd-Vth)至(Vdd-Vth) /Vth的范围内时,半导体装置可以充分进行操作。 Another Xi Bu, in Vw_0 is 0 (V), Vw_l to Vdd, Vr_0 to 0 (V), Vr_l case of Vdd, when C1 / C2 in Vth / (Vdd-Vth) to (Vdd-Vth) / Vth within the range, the semiconductor device can be sufficiently operated.

[0269] 另外,数据" 1"和数据"0"只是为了方便起见而区分的,因此数据" 1"和数据"0" 可以彼此互换。 [0269] Further, data "1" and data "0" is only for convenience of distinction, the data "1" and data "0" can be interchanged with each other. 另外,也可以使用接地电位GND等作为V0,使用电源电位Vdd等作为VI。 Further, the ground potential GND can be used like as V0, and the like used as a power supply potential Vdd VI.

[0270] 使用氧化物半导体的晶体管的截止电流极小,因此通过使用该晶体管可以相当长时间地保持存储的数据。 [0270] current of the transistor using an oxide semiconductor is extremely small, quite a long time can be maintained by use of the data storage transistors. 就是说,因为不需要进行刷新操作,或者,可以显著地降低刷新操作的频率,因此可以充分降低功耗。 That is, since no refresh operation, or may significantly reduce the frequency of the refresh operation, power consumption can be sufficiently reduced. 另外,即使没有电力供给,也可以长期保持存储的数据。 Further, even if power is not supplied, it can be long-term data storage.

[0271] 另外,信息的写入不需要高电压,而且也没有元件劣化的问题。 [0271] Further, writing of information do not require high voltage, and there is no problem of deterioration of elements. 此外,根据晶体管的导通状态或截止状态而进行信息写入,从而可以容易地实现高速操作。 Further, according to the conductive state or the OFF state of the transistor and writing information, whereby high-speed operation can be easily realized. 另外,还有不需要快闪存储器等所需的用于擦除信息的操作的优点。 Further, there is not need for a flash memory or the like needed to erase advantage of operating information.

[0272]由于与使用氧化物半导体的晶体管相比,使用氧化物半导体以外的材料的晶体管可以以更高速度进行操作,因此,通过使用该晶体管可以高速读出存储的数据。 [0272] as compared with a transistor using an oxide semiconductor, a transistor using a material other than an oxide semiconductor can operate at a higher speed, and therefore, high-speed read data stored by using the transistor.

[0273] 本实施例所示的结构或方法等可以与其他实施例所示的结构或方法等适当地组合。 Other structures or methods [0273] embodiment of the present embodiment shown in the structures or methods shown in the other embodiments may be appropriately combined.

[0274] 实施例3 [0274] Example 3

[0275] 以下,将参照图18说明根据本发明一个实施例的半导体装置中所具有的读出电路212的例子。 [0275] Hereinafter, an example of a circuit 212 of a semiconductor device according to an embodiment of the present invention is read with reference to the FIG. 18.

[0276] 图18所示的读出电路212具有晶体管204和读出放大器205。 The readout circuit shown in [0276] 18 212 has a transistor 204 and a sense amplifier 205. 将偏置电压V bias施加到晶体管204的栅电极,并且预定的电流流过晶体管204。 The bias voltage V bias is applied to the gate electrode of the transistor 204, and the predetermined current flows through the transistor 204. 将参考电位V,ef输入到读出放大器205的一个输入端子。 The reference potential V, ef inputted to the sense amplifier 205 to one input terminal.

[0277] 在读出数据时,将读出放大器205的另一个输入端子和连接到从其读出数据的存储单元的位线BL相互电连接。 [0277] In reading data, sense amplifier 205 is connected to the other input terminal and BL are electrically connected to the bit lines from the memory cells for reading data.

[0278] 存储单元根据所存储的数据" 1"或"0"而具有不同的电阻。 [0278] The storage unit according to the stored data "1" or "0" has a different resistance. 具体地,在所选择的存储单元中的晶体管201处于导通状态时,存储单元处于低电阻状态,而在所选择的存储单元的晶体管201处于截止状态时,存储单元处于高电阻状态。 Specifically, the transistor in the selected memory cell 201 is in the conductive state, the memory cell in a low resistance state, the transistor in the memory cell 201 is selected in the off state, the memory cell in a high resistance state.

[0279] 在存储单元处于高电阻状态时,读出放大器205的所述另一输入端子的电位高于参考电位Vref,而从读出放大器205的输出端子输出数据" 1"。 [0279] When the memory cell is in a high resistance state, the sense amplifier 205 to the other input terminal is higher than the potential of the reference potential Vref, the sense amplifier from the output terminal 205 of the data "1." 另一方面,在存储单元处于低电阻状态时,读出放大器205的两个输入端子中的另一方的电位低于参考电位Vref,而从读出放大器205的输出端子输出数据"0"。 On the other hand, when the memory cell is in the low resistance state, read the potential of the other two input terminals of the amplifier 205 is lower than the reference voltage Vref, the sense amplifier from the output terminal 205 of the data "0."

[0280] 如上所述,通过使用读出电路212,可以读出存储在存储单元中的数据。 [0280] As described above, by using the read circuit 212 may read out the data stored in the storage unit. 另外,读出电路212只是一个例子,也可以使用具有其他结构的读出电路。 Further, the readout circuit 212 is merely an example, the read circuit may be used with other structures. 例如,读出电路212也可以具有预充电电路。 For example, readout circuitry 212 may include a precharge circuit.

[0281] 本实施例所示的结构和方法等可以与其他实施例所示的结构和方法等适当地组合。 Structures and methods [0281] Examples of the present embodiment shown in the structure and method may be implemented with other embodiments shown in appropriate combination.

[0282] 实施例4 [0282] Example 4

[0283] 在本实施例中,将说明与任意上述实施例所示的存储单元不同的存储单元的电路结构及其操作。 [0283] In the present embodiment, the circuit configuration of the memory cell shown in any of the above embodiments of different embodiments of storage unit and its operation.

[0284]〈存储单元的结构〉 [0284] <of the memory cells>

[0285] 图19示出根据本实施例的存储单元的电路图的一个例子。 [0285] FIG. 19 shows an example of a circuit diagram of the memory cell of the embodiment of the present embodiment. 图19所示的存储单元220包括第一信号线S1、字线WL、晶体管221 (第一晶体管)、晶体管222 (第二晶体管)以及电容器223。 The storage unit 19 shown in FIG. 220 includes a first signal lines S1, the word line WL, transistors 221 (a first transistor), a transistor 222 (a second transistor) and a capacitor 223. 晶体管221使用氧化物半导体以外的材料而形成,晶体管222使用氧化物半导体而形成。 Material other than an oxide semiconductor transistor 221 is formed using an oxide semiconductor transistor 222 is formed. 这里,晶体管221优选被形成为具有与实施例1所示的晶体管160类同的结构。 Here, the transistor 221 is preferably formed as a structure 160 similar to the embodiment shown having a transistor. 另外,晶体管222优选被形成为具有与实施例1所示的晶体管162类同的结构。 Further, the transistor 222 is preferably formed as a transistor having the structure shown in Example 1 and 162 similar to the embodiment. 另外, 存储单元220电连接到源极线SL及位线BL,也可以经由晶体管(包括其他存储单元中的晶体管)电连接到源极线SL及位线BL。 Further, the storage unit 220 is electrically connected to the source line SL and bit line BL, it can be electrically connected to the source line SL and bit line BL via a transistor (including other memory cell transistors).

[0286] 这里,晶体管221的栅电极、晶体管222的源电极和漏电极中的一方、以及电容器223的电极中的一个相互电连接。 [0286] Here, one of the gate electrode of the transistor 221, the source electrode of the transistor 222 and the drain electrode, and the electrode of the capacitor 223 is electrically connected to one another. 另外,源极线SL和晶体管221的源电极相互电连接。 Further, the source line SL and a source electrode of transistor 221 is connected electrically to each other. 位线BL与晶体管221的漏电极相互电连接。 Bit line BL and the drain of the transistor 221 are electrically connected to the electrode. 第一信号线S1与晶体管222的源电极和漏电极中的另一方相互电连接。 A source electrode and a drain electrode of the first transistor S1 and the signal line 222 are electrically connected to the other one. 字线WL和晶体管222的栅电极与电容器223的电极中的另一方相互电连接。 Word lines WL and the gate electrode of the transistor 222 and the capacitor electrode 223 are electrically connected to the other one. 另外,源极线SL和晶体管221的源电极也可以经由晶体管(包括其他存储单元中的晶体管)相互连接。 Further, the source line SL and a source electrode of transistor 221 may be connected to each other via a transistor (including other memory cell transistors). 另外,位线BL和晶体管221的漏电极也可以经由晶体管(包括其他存储单元中的晶体管)连接。 Further, the drain bit line BL and the source of the transistor 221 may be connected via a transistor (including other memory cell transistors).

[0287]〈存储单元的操作〉 [0287] <operation of the memory cells>

[0288] 以下,将具体说明存储单元的操作。 [0288] Hereinafter, the operation will be specifically described memory cell.

[0289] 在对存储单元220进行写入时,将晶体管221的源电极或漏电极的电位设定为V0 (任意电位,例如0V),并将字线WL的电位设定为VI(任意电位,例如2V)。 [0289] When writing to memory cell 220, the source electrode of the transistor or the potential of the drain electrode 221 is set to V0 (arbitrary potential, for example 0V), and the potential of the word line WL is set to VI (an arbitrary potential , for example, 2V). 此时,晶体管222 处于导通状态。 At this time, the transistor 222 in the ON state.

[0290] 当在这个状态下,将第一信号线S1的电位VS1设定为预定的电位时,写入数据。 [0290] When in this state, the potential of the first signal line S1 is set to a predetermined electric potential VS1, the write data. 例如,在写入数据" 1"时,将第一信号线S1的电位设定为Vw_l,而在写入数据"0"时,将第一信号线S1的电位设定为Vw_0。 For example, the data "1", the potential of the first signal line S1 is set to Vw_l, and when writing data "0", the potential of the first signal line S1 is set to Vw_0. 另外,在写入结束时,在第一信号线S1的电位变化之前,将字线WL的电位设定为V0,从而使晶体管222处于截止状态。 Further, at the end of writing, before the potential change of the first signal line S1, the potential of the word line WL is set to V0, so that the transistor 222 is turned off.

[0291] 对应于写入时的第一信号线S1的电位的电荷QA累积在连接到晶体管221的栅电极的节点(以下称为节点A),由此存储数据。 [0291] corresponds to the first write signal line S1 charges accumulated in the potential of the node QA is connected to the gate electrode of transistor 221 (hereinafter, referred to as Node A), thereby storing data. 这里,晶体管222的截止电流极小或者基本上为0,因此长时间地保持所写入的数据。 Here, the current of the transistor 222 is extremely small or substantially 0, and therefore time to maintain written data.

[0292] 通过将字线WL的电位VWL设定为预定的电位,从存储单元220进行读出。 [0292] VWL of the word line WL is set by the potential of a predetermined potential, read out from the storage unit 220. 例如, 在从其读出数据的存储单元220中,字线WL的电位设定为Vr_l,而在未从其读出数据的存储单元220中,字线WL的电位设定为Vr_0。 For example, in reading data from the storage unit 220, the potential of the word line WL is set to Vr_l, and if not, reading data from the storage unit 220, the potential of the word line WL is set to Vr_0. 在任一情况下,将第一信号线S1的电位设定为VI。 In either case, the potential of the first signal line S1 is set to VI.

[0293] 以如下方式设定写入时的第一信号线S1的电位Vw_l及Vw_0、读出时的字线WL 的电位Vr_l及Vr_0 :在将字线WL的电位为Vr_l时,存储有数据"1"的存储单元的晶体管221处于导通状态,而存储有数据"0"的存储单元的晶体管221处于截止状态。 [0293] and the potential Vw_l Vw_0 first signal line S1 is written in setting such a manner, the read word line WL and the potential Vr_l Vr_0: when the potential of the word line WL Vr_l, stores data transistor "1" in the memory cell 221 in the oN state, the transistor stores data "0" of the memory cell 221 is in an off state. 此外,电位Vw_l及Vw_0和电位Vr_l及Vr_0被设置为使得晶体管222处于截止状态。 Further, the potential and potential Vr_l Vw_l and Vw_0 Vr_0 and is set such that the transistor 222 is turned off. 另外,在将字线WL的电位设定为Vr_0时,不管是存储有数据"1"还是存储有数据"0",在存储单元中,晶体管221都处于导通状态并且晶体管222处于截止状态。 Further, when the potential of the word line WL is set to Vr_0, whether stored data "1" or the stored data "0" in the memory cell, transistor 221 are in the ON state and the transistor 222 is turned off.

[0294] 在使用存储单元220形成NAND型非易失性存储器的情况下,就是说,被选择用于读出的存储单元可以根据所存储的数据而具有不同的电阻,并且在存储单元列中的其他存储单元可以具有低的电阻而不管所存储的数据如何。 [0294] In the case where the storage unit 220 form a NAND type nonvolatile memory, that is, the memory cell is selected for readout can have different resistances according to data stored in the storage unit and the column other memory cells may have a low resistance regardless of how the data is stored. 结果,通过使用检测位线BL的电阻状态之间的不同的读出电路,可以读出存储单元中的数据。 As a result, by using different readout circuit detecting the resistance state between the bit line BL, the data can be read out of the memory cell.

[0295] 另外,数据"1"和数据"0"只是为了方便起见而被区别的,因此数据"1"和数据"0" 可以彼此互换。 [0295] Further, data "1" and data "0" is only for convenience of distinction, the data "1" and data "0" can be interchanged with each other. 另外,也可以使用接地电位GND等作为V0,使用电源电位Vdd等作为VI。 Further, the ground potential GND can be used like as V0, and the like used as a power supply potential Vdd VI.

[0296] 另外,在使用本实施例所示的存储单元220的情况下,也可以实现具有矩阵结构的半导体装置。 [0296] Further, in the case of the present embodiment shown in the embodiment of the storage unit 220, the semiconductor device can be realized with a matrix structure. 可以通过使用其结构与任意上述实施例中结构类同的电路并且通过根据信号线的结构适当地形成驱动电路、读出电路和写入电路,来实现所述具有矩阵结构的半导体装置。 By using the structure of any of the above embodiments and configuration similar to a circuit formed by appropriately driving circuit structure according to a signal line, the read circuit and a write circuit, having achieved a semiconductor device a matrix structure. 另外,在使用存储单元220的情况下,按行进行读出和写入。 Further, in the case where the storage unit 220, by reading and writing rows.

[0297] 本实施例所示的结构和方法等可以与其他实施例所示的结构和方法等适当地组合。 Structures and methods [0297] Examples of the present embodiment shown in the structure and method may be implemented with other embodiments shown in appropriate combination.

[0298] 实施例5 [0298] Example 5

[0299] 在本实施例中,将参考图20A至20F说明安装有根据任意上述实施例得到的半导体装置的电子设备的例子。 [0299] In the present embodiment, with reference to FIGS. 20A to 20F illustrate an example of an electronic apparatus mounted with the semiconductor device obtained in accordance with any of the above embodiments. 根据任意上述实施例得到的半导体装置即使没有电力供给也可以保持信息。 The semiconductor device of any of the above embodiments according to the embodiment obtained even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,利用该半导体装置,可以提供具有新的结构的电子设备。 Thus, by using the semiconductor device can be provided an electronic device having a new structure. 另外,根据任意上述实施例的半导体装置被集成安装到电路板等上,以将其安装到电子设备。 Further, the semiconductor device according to any of the above embodiments is mounted on the integrated circuit board or the like, to be mounted to the electronic device.

[0300] 图20A示出包括根据任意上述实施例的半导体装置的膝上型个人计算机,其包括主体301、壳体302、显示部303和键盘304等。 [0300] FIG. 20A shows a laptop personal computer comprising a semiconductor device according to any of the above embodiments which includes a main body 301, a housing 302, a keyboard 304 and a display unit 303 and the like. 通过将根据本发明的一个实施例的半导体装置应用于膝上型个人计算机,即使没有电力供给也可以保持信息。 The semiconductor device according to one embodiment of the present invention is applied to a laptop personal computer, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明的实施例的半导体装置应用于膝上型个人计算机。 Thus, preferably the laptop personal computer is applied to a semiconductor device of an embodiment of the present invention.

[0301] 图20B示出包括根据任意上述实施例的半导体装置的便携式信息终端(PDA),并且其设有主体311,包括显示部313、外部接口315和操作按钮314等。 [0301] FIG 20B illustrates a portable information terminal comprising a semiconductor device according to any of the above embodiments (PDA), and which is provided with a body 311, includes a display unit 313, external interface 315 and the operation button 314 and the like. 另外,作为操作用附属部件,有触笔312。 Further, as an accessory for operation with the stylus 312. 通过将根据本发明的一个实施例的半导体装置应用于PDA,即使没有电力供给也可以保持信息。 PDA semiconductor device by applying an embodiment of the present invention, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明的实施例的半导体装置应用于PDA。 Accordingly, the preferred embodiment of the semiconductor device used in PDA embodiment of the present invention.

[0302] 图20C示出作为包括根据任意上述实施例的半导体装置的电子纸的一个例子的电子书阅读器320。 [0302] FIG 20C illustrates an example of as comprising an electronic paper of a semiconductor device of any of the above embodiments of the e-book reader 320. 电子书阅读器320包括两个壳体,即壳体321及壳体323。 E-book reader 320 includes two housings, a housing 321 and housing 323. 壳体321及壳体323由绞接单元337组合,且可以以该绞接单元337为轴进行开闭操作。 Housing 321 and the housing 323 by the hinge unit 337 in combination, and may be opened and closed to the hinge unit 337 as an axis. 通过这种结构,电子书阅读器320可以像纸质图书一样使用。 With this structure, the e-book reader 320 can be used like a paper book the same. 通过将根据本发明的一个实施例的半导体装置应用于电子纸,即使没有电力供给也可以保持信息。 The semiconductor device is applied to an electronic paper in accordance with one embodiment of the embodiment of the present invention, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明实施例的半导体装置应用于电子纸。 Accordingly, the electronic paper is preferably applied to the semiconductor device according to an embodiment of the present invention.

[0303] 壳体321中安装有显示部325,而壳体323中安装有显示部327。 [0303] In the housing 321 is attached to the display unit 325, the housing 323 is mounted in a display unit 327. 显示部325和显示部327可显示一个图像或不同图像。 A display unit 325 and the display unit 327 may display one image or different images. 在显示部325和显示部327显示不同图像时,例如可以在右侧的显示部(图20C中的显示部325)显示文本,而在左侧的显示部(图20C中的显示部327)显示图像。 When the display unit 325 and the display unit 327 display different images, for example, text can be displayed on the right display portion (the display portion 325 in FIG. 20C), while the display portion (the display portion 327 in FIG. 20C) on the left side of the display image.

[0304] 图20C中示出壳体321中备有操作部等的例子。 [0304] FIG 20C shows an example of a housing 321 provided with the operation portion and the like. 例如,壳体321具备电源331、操作键333以及扬声器335等。 For example, the housing 321 includes a power supply 331, operation keys 333 and a speaker 335 and the like. 利用操作键333可以翻页。 333 pages can be turned with the operation key. 注意,键盘、指示装置等可以设置在与壳体的其上设有显示部的表面上。 Note that a keyboard, a pointing device and the like may be provided on the surface of the display portion is provided thereon with the housing. 另外,也可以采用在壳体的背面及侧面设置外部连接用端子(耳机端子、USB端子、或可与AC适配器及USB电缆等的各种线缆连接的端子等)、 记录介质插入部等。 Further, the back surface may be employed and the side surface of the housing is provided with an external connection terminal (an earphone terminal, a USB terminal, or the terminal may be connected to an AC adapter and various cables such as a USB cable or the like), a recording medium insertion portion and the like. 此外,电子书阅读器320可以具有电子词典的功能。 In addition, e-book reader 320 may have an electronic dictionary function.

[0305] 电子书阅读器320可以采用以无线的方式收发信息的结构。 [0305] e-book reader 320 may have a configuration of the radio transmitting and receiving data. 通过无线通信,可以从电子书籍服务器购买并下载所希望的书籍数据等。 Through wireless communication, can be purchased and downloaded from an electronic book server desired book data.

[0306] 注意,电子纸可以用于任意可以显示信息的领域中的电子设备。 [0306] Note that the electronic paper can be used to display any information in the field of electronic devices. 例如,除了电子书阅读器以外,还可以将电子纸应用于招贴、诸如列车等交通工具中的广告、诸如信用卡等各种卡片中的显不等。 For example, in addition to the e-book reader, may also be applied to an electronic paper posters, advertisements in vehicles such as trains, a variety of cards such as credit cards ranging substantially like.

[0307] 图20D示出包括根据任意上述实施例的半导体装置的移动电话。 [0307] FIG 20D illustrates a mobile telephone comprising a semiconductor device according to any of the above embodiment. 该移动电话包括两个壳体,壳体340及壳体341。 The mobile phone includes two housings, a housing 340 and housing 341. 壳体341包括显示面板342、扬声器343、麦克风344、指示装置346、相机镜头347、外部连接端子348等。 Housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348 and the like. 另外,壳体340包括用于对该移动电话充电的太阳能电池349和外部存储器插槽350等。 Further, the housing 340 includes a solar cell 349 and the external memory slot 350 for charging the mobile telephone and the like. 此外,天线被设置在壳体341中。 In addition, the antenna 341 is provided in the housing. 通过将根据本发明的一个实施例的半导体装置应用于移动电话,即使没有电力供给也可以保持信息。 The semiconductor device according to one embodiment of the present invention is applied to a mobile phone, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明实施例的半导体装置应用于移动电话。 Thereby, the mobile telephone is preferably applied to a semiconductor device in accordance with an embodiment of the present invention.

[0308] 显示面板342具有触摸屏功能。 [0308] The display panel 342 has a touch panel function. 图20D中以虚线示出显示的多个操作键345。 FIG 20D shown in dashed lines in the plurality of operation keys 345 is displayed. 另夕卜,该移动电话包括用于将太阳能电池349所输出的电位升压到各电路所需要的电位的升压电路。 Another Bu Xi, the mobile phone includes the potential for solar cell 349 to the output of the booster circuit boosting the potential required for each circuit. 另外,除了上述结构以外,还可以采用安装有非接触1C芯片、或小型记录装置等的结构。 Further, in addition to the above-described structure, the structure may also be a non-contact 1C chip is mounted, the recording apparatus or the like using compact.

[0309] 显示面板342的显示方向根据使用模式适当地改变。 [0309] direction of the display panel 342 is changed appropriately according to the use mode. 另外,在与显示面板342同一表面上设有相机镜头347,因此其可以用作视频电话。 Further, in the display panel 342 is provided with the same upper surface of the camera lens 347, so it can be used as a video phone. 扬声器343及麦克风344可以用于视频电话、录音、回放等,而不限于语音通信。 A speaker 343 and a microphone 344 can be used for videophone, recording, playback, without being limited to voice communication. 此外,在如图20D所示处于展开状态的壳体340和壳体341可以滑动从而使得一个重叠在另一个上,这使得移动电话适于携带。 Further, as shown in FIG. 20D in the expanded state of the housing 340 and the housing 341 can be slid so that one overlaps the other, which makes the mobile phone suitable for being carried.

[0310] 外部连接端子348可以连接到各种线缆,比如AC适配器或USB线缆,这使得可以进行充电或者通信。 [0310] The external connection terminal 348 may be connected to various cables such as an AC adapter or USB cable, which makes it possible to charge or communication. 另外,通过将记录媒体插入到外部存储器插槽350中,移动电话可以应对更大容量的信息储存及移动。 Further, by inserting a recording medium into the external memory slot 350, the mobile phone may respond to the mobile information storage and larger capacity. 另外,移动电话除了上述功能以外还可以具有红外线通讯功能、电视接收功能等。 Further, in addition to the functions of the mobile phone may also have an infrared communication function, a television reception function.

[0311] 图20E示出包括根据任意上述实施例的半导体装置的数码相机。 [0311] FIG 20E shows a digital camera comprising a semiconductor device according to any of the above embodiment. 该数码相机包括主体361、显示部(A) 367、取景器363、操作开关364、显示部(B) 365、以及电池366等。 The digital camera includes a main body 361, a display unit (A) 367, a viewfinder 363, an operation switch 364, a display unit (B) 365, the battery 366 and the like. 通过将根据本发明的一个实施例的半导体装置应用于数码相机,即使没有电力供给也可以保持信息。 By applying the semiconductor device of one embodiment of a digital camera embodiment of the present invention, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明实施例的半导体装置应用于数码相机。 Accordingly, the preferred embodiment applied to a digital camera embodiment of the semiconductor device according to the present invention.

[0312] 图20F示出包括根据任意上述实施例的半导体装置的电视装置。 [0312] FIG 20F illustrates a television device comprising a semiconductor device according to any of the above embodiment. 在电视装置370 中,壳体371中安装有显示部373。 In the television 370, the housing 371 is attached to the display unit 373. 显示部373可以显示图像。 The display unit 373 may display an image. 此外,在利用支架375支撑壳体371。 Further, the housing 371 is supported by a stand 375.

[0313] 可以通过利用壳体371的操作开关或另行提供的遥控器380进行电视装置370的操作。 [0313] The television device 370 can be operated by using the operation switch of the housing 371 or a separate remote controller 380. 可利用遥控器380的操作键379控制频道和音量,从而可以控制显示部373上显示的图像。 379 can control the operation keys and remote volume control channel 380, which can control the image displayed on the display unit 373. 此外,遥控器380可以设有显示从该遥控器380输出的信息的显示部377。 In addition, remote unit 380 may be provided with a display information output from the remote controller 380 is 377. 通过将根据本发明的一个实施例的半导体装置应用于电视装置,即使没有电力供给也可以保持信息。 The semiconductor device according to one embodiment of the present invention applied to the television apparatus, even if power is not supplied information can be held. 另外,不发生由写入和擦除导致的劣化。 Further, the deterioration caused by the writing and erasing does not occur. 此外,其操作速度快。 Further, the operation speed thereof. 由此,优选将根据本发明实施例的半导体装置应用于电视装置。 Thus, a semiconductor device is preferably applied to a television device according to an embodiment of the present invention.

[0314] 另外,电视装置370优选设置有接收器、调制解调器等。 [0314] Further, the television device 370 is preferably provided with a receiver, a modem, and the like. 通过接收器,可接收一般的电视广播。 Via the receiver, general television broadcasting can be received. 此外,当电视装置370通过有线或无线连接经由调制解调器连接到通信网络时,可执行单向(从发送器到接收器)或双向(在发送器与接收器之间或者在接收器之间) 的信息通信。 Further, when the television apparatus 370 via a modem connected to a communication network by wired or wireless connection, perform a one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) of Information and Communication.

[0315] 本实施例所示的结构和方法等可以与其他实施例所示的结构和方法等适当地组合。 Structures and methods [0315] Examples of the present embodiment shown in the structure and method may be implemented with other embodiments shown in appropriate combination.

[0316]本申请基于2009年11月20日在日本专利局提交的日本专利申请第2009-264615 号,通过引用将其全部内容包括在此。 [0316] This application is based on Japanese patent application filed in Japan Patent Office on November 20, 2009 No. 2009-264615, incorporated by reference in its entirety, including this.

Claims (32)

1. 一种半导体装置,包括: 源极线; 位线; 多个存储单元,串联地电连接在所述源极线和所述位线之间, 信号线;以及字线, 其中,所述多个存储单元之一包括第一晶体管、第二晶体管、以及电容器,所述第一晶体管包含第一栅电极、第一源电极以及第一漏电极,所述第二晶体管包含第二栅电极、第二源电极以及第二漏电极, 所述第一晶体管设置在包含半导体材料的衬底中, 所述第二晶体管包含氧化物半导体层, 所述第一栅电极、所述第二源电极和所述第二漏电极中的一方、以及所述电容器的一个电极相互电连接, 所述源极线与所述第一源电极相互电连接, 所述位线与所述第一漏电极相互电连接, 其中,所述信号线与所述第二栅电极相互电连接,并且所述字线、所述第二源电极和所述第二漏电极中的另一方、以及所述电容器的另一个电极 1. A semiconductor device, comprising: a source line; bit lines; a plurality of memory cells, electrically connected in series between the source line and said bit line, a signal line; and a word line, wherein said one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, said first transistor comprising a first gate electrode, a first source electrode and first drain electrode, the second transistor includes a second gate electrode, a second source electrode and second drain electrode of the first transistor disposed in a substrate comprising semiconductor material, the second transistor including an oxide semiconductor layer, the first gate electrode, the source electrode and the second the one of the second drain electrode, and one electrode of the capacitor are electrically connected to the first source line and the source electrodes are electrically connected to the first bit line and the drain electrode are electrically connecting the signal line and the second gate electrodes are electrically connected to the word line and the other of the second source electrode and the drain electrode of the other of the second, and the capacitor electrode 互电连接。 Mutual electrical connection.
2. 根据权利要求1所述的半导体装置,其中所述第二晶体管包括在所述包含半导体材料的衬底上的所述第二栅电极、在所述第二栅电极上的第二栅极绝缘层、在所述第二栅极绝缘层上的所述氧化物半导体层、以及电连接到所述氧化物半导体层的所述第二源电极及所述第二漏电极。 The semiconductor device according to claim 1, wherein said second transistor comprises the substrate on said second semiconductor material comprising a gate electrode, a second gate on the second gate electrode the insulating layer, the oxide semiconductor layer on the second gate insulating layer, and electrically connected to the oxide semiconductor layer, a second source electrode and the second drain electrode.
3. 根据权利要求1所述的半导体装置,其中所述包含半导体材料的衬底为单晶半导体衬底或SOI衬底。 The semiconductor device according to claim 1, wherein said substrate comprises a semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
4. 根据权利要求1所述的半导体装置,其中所述半导体材料为硅。 4. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.
5. 根据权利要求1所述的半导体装置,其中所述氧化物半导体层包括基于In-Ga-Zn-0 的氧化物半导体材料。 The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an oxide-based semiconductor material, In-Ga-Zn-0's.
6. 根据权利要求1所述的半导体装置,其中所述氧化物半导体层包括In2Ga2Zn07的晶体。 6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal of In2Ga2Zn07.
7. 根据权利要求1所述的半导体装置,其中所述氧化物半导体层的氢浓度为小于或者等于5X1019原子/cm3。 The semiconductor device according to claim 1, wherein the hydrogen concentration in the oxide semiconductor layer is less than or equal to 5X1019 atoms / cm3.
8. 根据权利要求1所述的半导体装置,其中所述第二晶体管的截止电流为小于或者等于lXIO'A。 The semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal lXIO'A.
9. 一种半导体装置,包括: 源极线; 位线; 多个存储单元,串联地电连接在所述源极线和所述位线之间,所述多个存储单元之一包括: 第一晶体管,所述第一晶体管包含第一栅电极、第一源电极以及第一漏电极, 第二晶体管,所述第二晶体管包含第二栅电极、第二源电极以及第二漏电极,以及电容器; 信号线; 字线; 第一选择线; 第二选择线; 第三晶体管,所述第三晶体管包含第三栅电极、第三源电极以及第三漏电极,所述第三栅电极电连接到所述第一选择线;以及第四晶体管,所述第四晶体管包含第四栅电极、第四源电极以及第四漏电极,所述第四栅电极电连接到所述第二选择线, 其中,所述第一晶体管设置在包含半导体材料的衬底中, 所述第二晶体管包含氧化物半导体层, 所述第一栅电极、所述第二源电极和所述第二漏电极中的一方 A semiconductor device, comprising: a source line; bit lines; a plurality of memory cells, electrically connected in series between the source line and said bit line, one of said plurality of memory cells comprises: a first a transistor, the first transistor comprising a first gate electrode, a first source electrode and first drain electrode, a second transistor, the second transistor comprises a second gate electrode, a second source electrode and second drain electrode, and a capacitor; a signal line; a word line; a first select line; second select line; the third transistor, the third transistor includes a third gate electrode, a third source and a third drain electrode, the third gate electrode connected to the first selection line; and a fourth transistor, the fourth transistor comprising a fourth gate electrode, a fourth source and a fourth drain electrode, the fourth gate electrode electrically connected to the second select line wherein the first transistor disposed in a substrate comprising semiconductor material, the second transistor including an oxide semiconductor layer, the first gate electrode, the second source electrode and the drain electrode of the second party 、以及所述电容器的一个电极相互电连接, 所述源极线通过所述第四晶体管与所述第一源电极和所述第一漏电极中的一方电连接, 所述位线通过所述第三晶体管与所述第一源电极和所述第一漏电极中的另一方电连接, 其中,所述信号线与所述第二栅电极相互电连接,并且所述字线、所述第二源电极和所述第二漏电极中的另一方、以及所述电容器的另一个电极相互电连接。 , And one electrode of the capacitor are electrically connected to the source line via the fourth transistor connected to the first source electrode and the drain electrode of the first one of electrically, the bit line through the a third transistor connected to the first electrode and the source electrode in the other of said first drain, wherein the signal line and the second gate electrode are electrically connected, and said word line, said first two second source electrode and the drain electrode in the other, and the other electrode of the capacitor are electrically connected.
10. 根据权利要求9所述的半导体装置,其中所述第二晶体管包括在所述包含半导体材料的衬底上的所述第二栅电极、在所述第二栅电极上的第二栅极绝缘层、在所述第二栅极绝缘层上的所述氧化物半导体层、以及电连接到所述氧化物半导体层的所述第二源电极及所述第二漏电极。 The semiconductor device according to claim 9, wherein said second transistor comprises the substrate on said second semiconductor material comprising a gate electrode, a second gate on the second gate electrode the insulating layer, the oxide semiconductor layer on the second gate insulating layer, and electrically connected to the oxide semiconductor layer, a second source electrode and the second drain electrode.
11. 根据权利要求9所述的半导体装置,其中所述包含半导体材料的衬底为单晶半导体衬底或SOI衬底。 The semiconductor device according to claim 9, wherein said substrate comprises a semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
12. 根据权利要求9所述的半导体装置,其中所述半导体材料为硅。 12. The semiconductor device according to claim 9, wherein the semiconductor material is silicon.
13. 根据权利要求9所述的半导体装置,其中所述氧化物半导体层包括基于In-Ga-Zn-0的氧化物半导体材料。 The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises an oxide-based semiconductor material, In-Ga-Zn-0's.
14. 根据权利要求9所述的半导体装置,其中所述氧化物半导体层包括In2Ga2Zn07的晶体。 14. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises In2Ga2Zn07 crystals.
15. 根据权利要求9所述的半导体装置,其中所述氧化物半导体层的氢浓度为小于或者等于5X1019原子/cm3。 The semiconductor device according to claim 9, wherein the hydrogen concentration in the oxide semiconductor layer is less than or equal to 5X1019 atoms / cm3.
16. 根据权利要求9所述的半导体装置,其中所述第二晶体管的截止电流为小于或者等于1X1(T13A。 The semiconductor device according to claim 9, wherein off-state current of the second transistor is less than or equal 1X1 (T13A.
17. -种半导体装置,包括: 源极线; 位线; 多个存储单元,串联地电连接在所述源极线和所述位线之间; 信号线;以及字线, 其中,所述多个存储单元之一包括第一晶体管、第二晶体管以及电容器,所述第一晶体管包含第一栅电极、第一源电极以及第一漏电极,所述第二晶体管包含第二栅电极、第二源电极以及第二漏电极, 所述第一晶体管设置在包含半导体材料的衬底中, 所述第二晶体管包含氧化物半导体层, 所述第一栅电极、所述第二源电极和所述第二漏电极中的一方、以及所述电容器的一个电极相互电连接, 所述源极线与所述第一源电极相互电连接, 所述位线与所述第一漏电极相互电连接, 并且,所述第一晶体管包括设置在所述包含半导体材料的衬底中的沟道形成区域、以夹着所述沟道形成区域的方式设置的杂质区域、在所述沟道形成 17. - semiconductor device, comprising: a source line; bit lines; a plurality of memory cells, electrically connected in series between the source line and said bit line; signal line; and a word line, wherein said one of the plurality of memory cells includes a first transistor, a second transistor and a capacitor, said first transistor comprising a first gate electrode, a first source electrode and first drain electrode, the second transistor includes a second gate electrode, the first second source electrode and second drain electrode of the first transistor disposed in a substrate comprising semiconductor material, the second transistor including an oxide semiconductor layer, the first gate electrode, the source electrode and the second a second one of said drain electrode, and one electrode of the capacitor are electrically connected to the first source line and the source electrodes are electrically connected to the first bit line and the drain electrode is electrically connected to each other and, said first transistor comprises a channel disposed in a substrate comprising said semiconductor material region is formed to sandwich the channel forming impurity region a region provided, are formed in the channel 区域上的第一栅极绝缘层、在所述第一栅极绝缘层上的所述第一栅电极、以及电连接到所述杂质区域的所述第一源电极及所述第一漏电极, 其中,所述信号线与所述第二栅电极相互电连接,并且所述字线、所述第二源电极和所述第二漏电极中的另一方、以及所述电容器的另一个电极相互电连接。 A first insulating layer on the gate region, the gate on the first insulating layer, a first gate electrode, and electrically connected to the impurity region of the first source electrode and a drain electrode of the first wherein the signal line and the second gate electrode are electrically connected, and the word line, the second source electrode and the drain electrode of the other of the second, and the other electrode of the capacitor They are electrically connected.
18. 根据权利要求17所述的半导体装置,其中所述第二晶体管包括在所述包含半导体材料的衬底上的所述第二栅电极、在所述第二栅电极上的第二栅极绝缘层、在所述第二栅极绝缘层上的所述氧化物半导体层、以及电连接到所述氧化物半导体层的所述第二源电极及所述第二漏电极。 18. The semiconductor device according to claim 17, wherein said second transistor comprises the substrate on said second semiconductor material comprising a gate electrode, a second gate on the second gate electrode the insulating layer, the oxide semiconductor layer on the second gate insulating layer, and electrically connected to the oxide semiconductor layer, a second source electrode and the second drain electrode.
19. 根据权利要求17所述的半导体装置,其中所述包含半导体材料的衬底为单晶半导体衬底或SOI衬底。 19. The semiconductor device according to claim 17, wherein said substrate comprises a semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
20. 根据权利要求17所述的半导体装置,其中所述半导体材料为硅。 20. The semiconductor device according to claim 17, wherein the semiconductor material is silicon.
21. 根据权利要求17所述的半导体装置,其中所述氧化物半导体层包括基于In-Ga-Zn-0的氧化物半导体材料。 21. The semiconductor device according to claim 17, wherein the oxide semiconductor layer comprises an oxide-based semiconductor material, In-Ga-Zn-0's.
22. 根据权利要求17所述的半导体装置,其中所述氧化物半导体层包括In2Ga2Zn07的晶体。 22. The semiconductor device according to claim 17, wherein the oxide semiconductor layer includes a crystal of In2Ga2Zn07.
23. 根据权利要求17所述的半导体装置,其中所述氧化物半导体层的氢浓度为小于或者等于5X1019原子/cm3。 23. The semiconductor device according to claim 17, wherein the hydrogen concentration in the oxide semiconductor layer is less than or equal to 5X1019 atoms / cm3.
24. 根据权利要求17所述的半导体装置,其中所述第二晶体管的截止电流为小于或者等于1X1(T13A。 24. The semiconductor device according to claim 17, wherein off-state current of the second transistor is less than or equal 1X1 (T13A.
25. -种半导体装置,包括: 源极线; 位线; 多个存储单元,串联地电连接在所述源极线和所述位线之间,所述多个存储单元之一包括: 第一晶体管,所述第一晶体管包含第一栅电极、第一源电极以及第一漏电极, 第二晶体管,所述第二晶体管包含第二栅电极、第二源电极以及第二漏电极,以及电容器; 信号线; 字线; 第一选择线; 第二选择线; 第三晶体管,所述第三晶体管包含第三栅电极、第三源电极以及第三漏电极,所述第三栅电极电连接到所述第一选择线;以及第四晶体管,所述第四晶体管包含第四栅电极、第四源电极以及第四漏电极,所述第四栅电极电连接到所述第二选择线, 其中所述第一晶体管设置在包含半导体材料的衬底中, 所述第二晶体管包含氧化物半导体层, 所述第一栅电极、所述第二源电极和所述第二漏电极中的一方、 25. - semiconductor device, comprising: a source line; bit lines; a plurality of memory cells, electrically connected in series between the source line and said bit line, one of said plurality of memory cells comprises: a first a transistor, the first transistor comprising a first gate electrode, a first source electrode and first drain electrode, a second transistor, the second transistor comprises a second gate electrode, a second source electrode and second drain electrode, and a capacitor; a signal line; a word line; a first select line; second select line; the third transistor, the third transistor includes a third gate electrode, a third source and a third drain electrode, the third gate electrode connected to the first selection line; and a fourth transistor, the fourth transistor comprising a fourth gate electrode, a fourth source and a fourth drain electrode, the fourth gate electrode electrically connected to the second select line wherein the first transistor disposed in a substrate comprising semiconductor material, the second transistor including an oxide semiconductor layer, the first gate electrode, the second source electrode and the drain electrode of the second party, 及所述电容器的一个电极相互电连接, 所述源极线通过所述第四晶体管与所述第一源电极和所述第一漏电极中的一方电连接, 所述位线通过所述第三晶体管与所述第一源电极和所述第一漏电极中的另一方电连接, 所述第一晶体管包括设置在所述包含半导体材料的衬底中的沟道形成区域、以夹着所述沟道形成区域的方式设置的杂质区域、在所述沟道形成区域上的第一栅极绝缘层、在所述第一栅极绝缘层上的所述第一栅电极、以及电连接到所述杂质区域的所述第一源电极及所述第一漏电极, 其中,所述信号线与所述第二栅电极相互电连接,并且所述字线、所述第二源电极和所述第二漏电极中的另一方、以及所述电容器的另一个电极相互电连接。 And one electrode of the capacitor are electrically connected to the source line via the fourth transistor connected to the first source electrode and the drain electrode of the first one of electrically, the first bit line through the the other of the first and the third transistor is electrically source electrode and the first drain electrode is connected to the first transistor comprises a channel disposed in a substrate comprising said semiconductor material region is formed to sandwich the a channel region formed in said impurity region provided embodiment, the first gate insulating layer is formed on the channel region, the gate on the first insulating layer, a first gate electrode, and is electrically connected to the a first impurity region of the source electrode and the first drain electrode, wherein the signal line and the second gate electrode are electrically connected, and the word line, the source electrode and the second He said the other of the second drain electrode, and the other electrode of the capacitor are electrically connected.
26. 根据权利要求25所述的半导体装置,其中所述第二晶体管包括在所述包含半导体材料的衬底上的所述第二栅电极、在所述第二栅电极上的第二栅极绝缘层、在所述第二栅极绝缘层上的所述氧化物半导体层、以及电连接到所述氧化物半导体层的所述第二源电极及所述第二漏电极。 26. The semiconductor device according to claim 25, wherein said second transistor comprises the substrate on said second semiconductor material comprising a gate electrode, a second gate on the second gate electrode the insulating layer, the oxide semiconductor layer on the second gate insulating layer, and electrically connected to the oxide semiconductor layer, a second source electrode and the second drain electrode.
27. 根据权利要求25所述的半导体装置,其中所述包含半导体材料的衬底为单晶半导体衬底或SOI衬底。 27. The semiconductor device according to claim 25, wherein said substrate comprises a semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
28. 根据权利要求25所述的半导体装置,其中所述半导体材料为硅。 28. The semiconductor device according to claim 25, wherein the semiconductor material is silicon.
29. 根据权利要求25所述的半导体装置,其中所述氧化物半导体层包括基于In-Ga-Zn-0的氧化物半导体材料。 29. The semiconductor device according to claim 25, wherein the oxide semiconductor layer comprises an oxide-based semiconductor material, In-Ga-Zn-0's.
30. 根据权利要求25所述的半导体装置,其中所述氧化物半导体层包括In2Ga2Zn07的晶体。 30. The semiconductor device according to claim 25, wherein the oxide semiconductor layer includes a crystal of In2Ga2Zn07.
31. 根据权利要求25所述的半导体装置,其中所述氧化物半导体层的氢浓度为小于或者等于5X1019原子/cm3。 31. The semiconductor device according to claim 25, wherein the hydrogen concentration in the oxide semiconductor layer is less than or equal to 5X1019 atoms / cm3.
32.根据权利要求25所述的半导体装置,其中所述第二晶体管的截止电流为小于或者等于1X1(T13A。 32. The semiconductor device according to claim 25, wherein off-state current of the second transistor is less than or equal 1X1 (T13A.
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180133548A (en) 2009-11-20 2018-12-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
KR101790365B1 (en) 2009-11-20 2017-10-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
EP2513966A4 (en) 2009-12-18 2016-08-10 Semiconductor Energy Lab Semiconductor device
EP2517245B1 (en) 2009-12-25 2019-07-24 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device
CN103985760B (en) 2009-12-25 2017-07-18 株式会社半导体能源研究所 The semiconductor device
CN106847816A (en) * 2010-02-05 2017-06-13 株式会社半导体能源研究所 Semiconductor device
US8664658B2 (en) 2010-05-14 2014-03-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2012014790A1 (en) * 2010-07-27 2012-02-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8467232B2 (en) * 2010-08-06 2013-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012256821A (en) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd Memory device
US8421071B2 (en) 2011-01-13 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Memory device
US9117916B2 (en) 2011-10-13 2015-08-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor film
US9076505B2 (en) 2011-12-09 2015-07-07 Semiconductor Energy Laboratory Co., Ltd. Memory device
US9208849B2 (en) 2012-04-12 2015-12-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving semiconductor device, and electronic device
US20130341180A1 (en) * 2012-06-22 2013-12-26 Semiconductor Energy Laboratory Co., Ltd. Sputtering target and method for using the same
JP2014011173A (en) * 2012-06-27 2014-01-20 Toshiba Corp Semiconductor device and method of manufacturing the same
JP5960000B2 (en) * 2012-09-05 2016-08-02 ルネサスエレクトロニクス株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US10211397B1 (en) 2014-07-07 2019-02-19 Crossbar, Inc. Threshold voltage tuning for a volatile selection device
US9460788B2 (en) 2014-07-09 2016-10-04 Crossbar, Inc. Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
JP2016149177A (en) 2015-02-09 2016-08-18 株式会社半導体エネルギー研究所 Semiconductor device and electronic apparatus including the same
US20180174647A1 (en) * 2016-12-19 2018-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device, Display Panel, and Electronic Device
WO2019008483A1 (en) * 2017-07-06 2019-01-10 株式会社半導体エネルギー研究所 Semiconductor device and semiconductor device actuating method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920391A (en) * 1988-04-05 1990-04-24 Oki Electric Industry Co., Ltd. Semiconductor memory device
CN1389927A (en) * 2001-05-31 2003-01-08 株式会社半导体能源研究所 Semiconductor device and electronic device
CN1641882A (en) * 2004-01-12 2005-07-20 三星电子株式会社 Node contact structures in semiconductor devices and methods of fabricating the same
CN101258607A (en) * 2005-09-06 2008-09-03 佳能株式会社 Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous
CN101328409A (en) * 2007-06-22 2008-12-24 三星电子株式会社 Oxide-based thin film transistor, zinc oxide etchant, and a method of forming the same
CN101339954A (en) * 2007-07-04 2009-01-07 三星电子株式会社 Oxide semiconductor, thin film transistor including the same and method of manufacturing a thin film transistor

Family Cites Families (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0053878B1 (en) * 1980-12-08 1985-08-14 Kabushiki Kaisha Toshiba Semiconductor memory device
JPH0254572A (en) * 1988-08-18 1990-02-23 Matsushita Electric Ind Co Ltd Semiconductor memory
JP2791613B2 (en) * 1990-10-12 1998-08-27 三菱電機株式会社 Semiconductor device and manufacturing method thereof
DE69635107D1 (en) * 1995-08-03 2005-09-29 Koninkl Philips Electronics Nv A semiconductor device with a transparent switching element
JP3625598B2 (en) * 1995-12-30 2005-03-02 三星電子株式会社 A method of manufacturing a liquid crystal display device
JP3766181B2 (en) * 1996-06-10 2006-04-12 株式会社東芝 The semiconductor memory device and system with it
US5796650A (en) * 1997-05-19 1998-08-18 Lsi Logic Corporation Memory circuit including write control unit wherein subthreshold leakage may be reduced
JPH11126491A (en) * 1997-08-20 1999-05-11 Fujitsu Ltd Semiconductor memory
US6198652B1 (en) * 1998-04-13 2001-03-06 Kabushiki Kaisha Toshiba Non-volatile semiconductor integrated memory device
JP4299913B2 (en) * 1998-04-13 2009-07-22 株式会社東芝 A semiconductor memory device
JP4170454B2 (en) 1998-07-24 2008-10-22 Hoya株式会社 Article and manufacturing method thereof having a transparent conductive oxide thin film
US6628551B2 (en) 2000-07-14 2003-09-30 Infineon Technologies Aktiengesellschaft Reducing leakage current in memory cells
JP2000150861A (en) * 1998-11-16 2000-05-30 Hiroshi Kawazoe Oxide thin film
JP3276930B2 (en) * 1998-11-17 2002-04-22 科学技術振興事業団 Transistor and semiconductor device
JP3936830B2 (en) * 1999-05-13 2007-06-27 株式会社日立製作所 Semiconductor device
WO2000070683A1 (en) * 1999-05-13 2000-11-23 Hitachi, Ltd. Semiconductor memory
US6266272B1 (en) * 1999-07-30 2001-07-24 International Business Machines Corporation Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells
JP2001053167A (en) 1999-08-04 2001-02-23 Sony Corp Semiconductor storage device
TW460731B (en) * 1999-09-03 2001-10-21 Ind Tech Res Inst Electrode structure and production method of wide viewing angle LCD
WO2001073846A1 (en) * 2000-03-29 2001-10-04 Hitachi, Ltd. Semiconductor device
US6266269B1 (en) 2000-06-07 2001-07-24 Xilinx, Inc. Three terminal non-volatile memory element
JP4089858B2 (en) 2000-09-01 2008-05-28 国立大学法人東北大学 Semiconductor device
KR20020038482A (en) * 2000-11-15 2002-05-23 모리시타 요이찌 Thin film transistor array, method for producing the same, and display panel using the same
JP3997731B2 (en) * 2001-03-19 2007-10-24 富士ゼロックス株式会社 A method of forming a crystalline semiconductor thin film on a substrate
JP2002289859A (en) 2001-03-23 2002-10-04 Minolta Co Ltd Thin-film transistor
JP2003037249A (en) 2001-07-23 2003-02-07 Hitachi Ltd Semiconductor integrated circuit device
JP3925839B2 (en) 2001-09-10 2007-06-06 シャープ株式会社 The semiconductor memory device and its testing method
JP4090716B2 (en) 2001-09-10 2008-05-28 シャープ株式会社 Thin film transistor and a matrix display device
WO2003040441A1 (en) * 2001-11-05 2003-05-15 Japan Science And Technology Agency Natural superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
JP4083486B2 (en) * 2002-02-21 2008-04-30 裕道 太田 LnCuO (S, Se, Te) The method of producing single crystal thin film
US7049190B2 (en) * 2002-03-15 2006-05-23 Sanyo Electric Co., Ltd. Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
JP3933591B2 (en) 2002-03-26 2007-06-20 三菱重工業株式会社 The organic electroluminescent element
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
JP2004022625A (en) * 2002-06-13 2004-01-22 Murata Mfg Co Ltd Manufacturing method of semiconductor device and its manufacturing method
US7105868B2 (en) * 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
JP4164562B2 (en) 2002-09-11 2008-10-15 Hoya株式会社 Transparent thin film field effect transistor using homologous film as an active layer
US6882010B2 (en) 2002-10-03 2005-04-19 Micron Technology, Inc. High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
US7067843B2 (en) * 2002-10-11 2006-06-27 E. I. Du Pont De Nemours And Company Transparent oxide semiconductor thin film transistors
JP4166105B2 (en) 2003-03-06 2008-10-15 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP2004273732A (en) 2003-03-07 2004-09-30 Masashi Kawasaki Active matrix substrate and its producing process
JP4108633B2 (en) * 2003-06-20 2008-06-25 シャープ株式会社 Thin film transistor and its manufacturing method, and electronic device
US7262463B2 (en) * 2003-07-25 2007-08-28 Hewlett-Packard Development Company, L.P. Transistor including a deposited channel region having a doped portion
US7145174B2 (en) * 2004-03-12 2006-12-05 Hewlett-Packard Development Company, Lp. Semiconductor device
US7297977B2 (en) 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
KR20070116888A (en) * 2004-03-12 2007-12-11 도꾸리쯔교세이호징 가가꾸 기쥬쯔 신꼬 기꼬 Amorphous oxide and thin film transistor
US7282782B2 (en) * 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
US7211825B2 (en) * 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
JP2006100760A (en) * 2004-09-02 2006-04-13 Casio Comput Co Ltd Thin-film transistor and its manufacturing method
US7285501B2 (en) * 2004-09-17 2007-10-23 Hewlett-Packard Development Company, L.P. Method of forming a solution processed device
US7298084B2 (en) * 2004-11-02 2007-11-20 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
US7829444B2 (en) * 2004-11-10 2010-11-09 Canon Kabushiki Kaisha Field effect transistor manufacturing method
US7863611B2 (en) * 2004-11-10 2011-01-04 Canon Kabushiki Kaisha Integrated circuits utilizing amorphous oxides
BRPI0517560B8 (en) * 2004-11-10 2018-12-11 Canon Kk field-effect transistor
US7791072B2 (en) 2004-11-10 2010-09-07 Canon Kabushiki Kaisha Display
KR100953596B1 (en) * 2004-11-10 2010-04-21 고쿠리츠다이가쿠호진 토쿄고교 다이가꾸 Light-emitting device
CA2708337A1 (en) * 2004-11-10 2006-05-18 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
US7453065B2 (en) * 2004-11-10 2008-11-18 Canon Kabushiki Kaisha Sensor and image pickup device
US7579224B2 (en) * 2005-01-21 2009-08-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film semiconductor device
TWI472037B (en) * 2005-01-28 2015-02-01 Semiconductor Energy Lab Semiconductor device, electronic device, and method of manufacturing semiconductor device
TWI569441B (en) * 2005-01-28 2017-02-01 半導體能源研究所股份有限公司 Semiconductor device, electronic device, and method of manufacturing semiconductor device
US7858451B2 (en) * 2005-02-03 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
US7948171B2 (en) * 2005-02-18 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20060197092A1 (en) * 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
US8681077B2 (en) * 2005-03-18 2014-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device, driving method and electronic apparatus thereof
JP5008323B2 (en) * 2005-03-28 2012-08-22 株式会社半導体エネルギー研究所 Memory device
US7544967B2 (en) * 2005-03-28 2009-06-09 Massachusetts Institute Of Technology Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications
US7645478B2 (en) * 2005-03-31 2010-01-12 3M Innovative Properties Company Methods of making displays
JP4849817B2 (en) 2005-04-08 2012-01-11 ルネサスエレクトロニクス株式会社 A semiconductor memory device
US8300031B2 (en) * 2005-04-20 2012-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element
JP2006344849A (en) * 2005-06-10 2006-12-21 Casio Comput Co Ltd Thin film transistor
US7691666B2 (en) * 2005-06-16 2010-04-06 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7402506B2 (en) * 2005-06-16 2008-07-22 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7507618B2 (en) * 2005-06-27 2009-03-24 3M Innovative Properties Company Method for making electronic devices using metal oxide nanoparticles
KR100711890B1 (en) * 2005-07-28 2007-04-25 삼성에스디아이 주식회사 Organic Light Emitting Display and Fabrication Method for the same
JP2007059128A (en) * 2005-08-23 2007-03-08 Canon Inc Organic electroluminescent display device and manufacturing method thereof
JP2007073705A (en) * 2005-09-06 2007-03-22 Canon Inc Oxide-semiconductor channel film transistor and its method of manufacturing same
JP4850457B2 (en) * 2005-09-06 2012-01-11 キヤノン株式会社 Thin film transistors and thin film diodes
JP5116225B2 (en) * 2005-09-06 2013-01-09 キヤノン株式会社 Method of manufacturing an oxide semiconductor device
JP4280736B2 (en) * 2005-09-06 2009-06-17 キヤノン株式会社 Semiconductor element
JP4560502B2 (en) * 2005-09-06 2010-10-13 キヤノン株式会社 Field-effect transistor
EP1998375A3 (en) * 2005-09-29 2012-01-18 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device having oxide semiconductor layer and manufacturing method
JP5037808B2 (en) * 2005-10-20 2012-10-03 キヤノン株式会社 Field effect transistor using an amorphous oxide, and a display device including the transistor
CN101577281B (en) * 2005-11-15 2012-01-11 株式会社半导体能源研究所 Active matrix display and TV comprising the display
TWI292281B (en) * 2005-12-29 2008-01-01 Ind Tech Res Inst Pixel structure of active organic light emitting diode and method of fabricating the same
US7867636B2 (en) * 2006-01-11 2011-01-11 Murata Manufacturing Co., Ltd. Transparent conductive film and method for manufacturing the same
JP4977478B2 (en) * 2006-01-21 2012-07-18 三星電子株式会社Samsung Electronics Co.,Ltd. Method for producing a ZnO film and the TFT using the same
US7576394B2 (en) * 2006-02-02 2009-08-18 Kochi Industrial Promotion Center Thin film transistor including low resistance conductive thin films and manufacturing method thereof
US7977169B2 (en) * 2006-02-15 2011-07-12 Kochi Industrial Promotion Center Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof
KR20070101595A (en) * 2006-04-11 2007-10-17 삼성전자주식회사 Zno thin film transistor
US20070252928A1 (en) * 2006-04-28 2007-11-01 Toppan Printing Co., Ltd. Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof
JP5028033B2 (en) * 2006-06-13 2012-09-19 キヤノン株式会社 Dry etching method for an oxide semiconductor film
JP4999400B2 (en) * 2006-08-09 2012-08-15 キヤノン株式会社 Dry etching method for an oxide semiconductor film
JP4609797B2 (en) * 2006-08-09 2011-01-12 Nec液晶テクノロジー株式会社 Thin film device and manufacturing method thereof
JP4332545B2 (en) * 2006-09-15 2009-09-16 キヤノン株式会社 Field effect transistor and manufacturing method thereof
JP4274219B2 (en) * 2006-09-27 2009-06-03 セイコーエプソン株式会社 Electronic devices, organic electroluminescent devices, organic thin-film semiconductor device
JP5164357B2 (en) * 2006-09-27 2013-03-21 キヤノン株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US7622371B2 (en) * 2006-10-10 2009-11-24 Hewlett-Packard Development Company, L.P. Fused nanocrystal thin film semiconductor and method
KR100829570B1 (en) * 2006-10-20 2008-05-14 삼성전자주식회사 Thin film transistor for cross-point memory and manufacturing method for the same
US7772021B2 (en) * 2006-11-29 2010-08-10 Samsung Electronics Co., Ltd. Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
JP2008140684A (en) 2006-12-04 2008-06-19 Toppan Printing Co Ltd Color el display, and its manufacturing method
KR101303578B1 (en) 2007-01-05 2013-09-09 삼성전자주식회사 Etching method of thin film
US8207063B2 (en) 2007-01-26 2012-06-26 Eastman Kodak Company Process for atomic layer deposition
US7994000B2 (en) * 2007-02-27 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
KR100851215B1 (en) 2007-03-14 2008-08-07 삼성에스디아이 주식회사 Thin film transistor and organic light-emitting dislplay device having the thin film transistor
US7795613B2 (en) * 2007-04-17 2010-09-14 Toppan Printing Co., Ltd. Structure with transistor
JP2008270313A (en) * 2007-04-17 2008-11-06 Matsushita Electric Ind Co Ltd Semiconductor memory element
KR101325053B1 (en) * 2007-04-18 2013-11-05 삼성디스플레이 주식회사 Thin film transistor substrate and manufacturing method thereof
KR20080094300A (en) * 2007-04-19 2008-10-23 삼성전자주식회사 Thin film transistor and method of manufacturing the same and flat panel display comprising the same
KR101334181B1 (en) * 2007-04-20 2013-11-28 삼성전자주식회사 Thin Film Transistor having selectively crystallized channel layer and method of manufacturing the same
CN101663762B (en) * 2007-04-25 2011-09-21 佳能株式会社 Oxynitride semiconductor
WO2008136505A1 (en) * 2007-05-08 2008-11-13 Idemitsu Kosan Co., Ltd. Semiconductor device, thin film transistor and methods for manufacturing the semiconductor device and the thin film transistor
KR101345376B1 (en) * 2007-05-29 2013-12-24 삼성전자주식회사 Fabrication method of ZnO family Thin film transistor
CN101681925B (en) * 2007-06-19 2011-11-30 三星电子株式会社 And the oxide semiconductor thin film transistor comprises the oxide semiconductor
US8202365B2 (en) * 2007-12-17 2012-06-19 Fujifilm Corporation Process for producing oriented inorganic crystalline film, and semiconductor device using the oriented inorganic crystalline film
JP5213458B2 (en) * 2008-01-08 2013-06-19 キヤノン株式会社 Amorphous oxide and field effect transistor
JP5121478B2 (en) * 2008-01-31 2013-01-16 株式会社ジャパンディスプレイウェスト Optical sensing element, the image pickup apparatus, an electronic apparatus, and a memory device
KR101490112B1 (en) * 2008-03-28 2015-02-05 삼성전자주식회사 Inverter and logic circuit comprising the same
US8455371B2 (en) * 2008-05-22 2013-06-04 Idemitsu Kosan Co., Ltd. Sputtering target, method for forming amorphous oxide thin film using the same, and method for manufacturing thin film transistor
JP4623179B2 (en) * 2008-09-18 2011-02-02 ソニー株式会社 Thin film transistor and a manufacturing method thereof
JP5451280B2 (en) * 2008-10-09 2014-03-26 キヤノン株式会社 Substrate for growing a wurtzite type crystal and its manufacturing method and a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920391A (en) * 1988-04-05 1990-04-24 Oki Electric Industry Co., Ltd. Semiconductor memory device
CN1389927A (en) * 2001-05-31 2003-01-08 株式会社半导体能源研究所 Semiconductor device and electronic device
CN1641882A (en) * 2004-01-12 2005-07-20 三星电子株式会社 Node contact structures in semiconductor devices and methods of fabricating the same
CN101258607A (en) * 2005-09-06 2008-09-03 佳能株式会社 Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous
CN101328409A (en) * 2007-06-22 2008-12-24 三星电子株式会社 Oxide-based thin film transistor, zinc oxide etchant, and a method of forming the same
CN101339954A (en) * 2007-07-04 2009-01-07 三星电子株式会社 Oxide semiconductor, thin film transistor including the same and method of manufacturing a thin film transistor

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