JP3189094B2 - Ferroelectric memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device, and more particularly to a ferroelectric memory device in which a memory cell is composed of a field effect transistor and a ferroelectric capacitor.

[0002]

2. Description of the Related Art The mainstream of a conventional semiconductor memory device is a dynamic random access memory (DRAM). D
The RAM is a volatile memory, and when the power supply is stopped, the stored contents are lost. A non-volatile memory that does not lose its stored contents even when the supply of power is stopped has been developed.

In recent years, a ferroelectric memory using a ferroelectric material has attracted attention as one of nonvolatile memories. There are roughly two types of ferroelectric memories. One is a method for detecting a change in the storage capacitance of a ferroelectric capacitor, and the other is a method for detecting a resistance change of a semiconductor due to the influence of remanent polarization of a ferroelectric film.

A ferroelectric memory using the former method includes:
2Tr-2C type that stores 1-bit information with two transistors and two capacitors, and 1 that stores 1-bit information with one transistor and one capacitor
There is a Tr-1C type. A ferroelectric memory using the latter method has a 1T in which a gate insulating film is formed of a ferroelectric.
An r-type is known.

[0005]

A 2Tr-2C type ferroelectric memory having a storage capacity of 64 kbits has been put to practical use. However, since two transistors and two capacitors are required to store one-bit information, it is difficult to increase the degree of integration. 1Tr-
It is relatively easy to increase the degree of integration of the 1C type ferroelectric memory. However, a reference cell (reference cell) is easily degraded with driving, and it is difficult to improve reliability and extend the life.

[0006] In the case of a 1Tr type ferroelectric memory, operation at the element single level has only been confirmed, and a driving method of the cell array has not been established. Further, since a source line is required in addition to a word line and a bit line, and a back gate is also required, it is difficult to reduce the cell area.

An object of the present invention is to provide a ferroelectric memory device suitable for high integration.

[0008]

According to one aspect of the present invention, a field effect transistor including a source region, a drain region, and a gate electrode is provided, and a field effect transistor for connecting the source region and the gate electrode is provided. There is provided a ferroelectric memory device having one ferroelectric capacitor and a second ferroelectric capacitor connecting the drain region and the gate electrode.

[0009] By applying a predetermined voltage between the source region and the drain region, remnant polarization can be generated in the dielectric film of the ferroelectric capacitor. The information can be stored by associating the direction of the remanent polarization with the information “0” and “1”.

According to another aspect of the present invention, a plurality of first wirings extending in a first direction on the surface of the substrate and a second wiring intersecting the first direction on the surface of the substrate. A plurality of second wirings extending in the direction of the arrow, an interlayer insulating film for mutually insulating the first wiring and the second wiring at intersections between the first wiring and the second wiring, A memory cell arranged corresponding to an intersection with a wiring, wherein each of the memory cells includes a field-effect transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor. Each of the field effect transistors includes a source region, a drain region, and a gate electrode; the first ferroelectric capacitor connects a source region and a gate electrode of the field effect transistor of the memory cell; Of the ferroelectric capacitor The plurality of memories, wherein a drain region and a gate electrode of a field effect transistor of a memory cell are connected, the source region is connected to a corresponding first wiring, and the drain region is connected to a corresponding second wiring. A ferroelectric memory device having a cell is provided.

A memory cell is selected by applying a write signal to predetermined wirings of the first wiring and the second wiring to cause remanent polarization in a ferroelectric capacitor of the memory cell. Can be. The information can be stored by associating the directions of the remanent polarization with the information “0” and “1”. The remanent polarization changes the current-voltage characteristics of the field effect transistor. By reading this change, information stored in the memory cell can be identified.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the circuit configuration and operation principle of a ferroelectric memory device according to an embodiment of the present invention will be described.

FIG. 1A shows a configuration of a cell array of a ferroelectric memory device according to an embodiment. A plurality of word lines WL arranged in parallel with each other and a plurality of bit lines BL arranged in parallel with each other intersect. A memory cell 3 is arranged at each intersection between the word line WL and the bit line BL. Each memory cell 3 is connected to a corresponding word line WL and bit line BL. All word lines W
L is connected to the word line control circuit 1, and all bit lines BL are connected to the bit line control circuit 2.

FIG. 1B shows an equivalent circuit diagram of one memory cell. Each memory cell 3 is an n-channel MISFE
T5, the first capacitor 6, and the second capacitor 7 are included. The source region 5S and the drain region 5D of the MISFET 5 are connected to the corresponding word lines WL.
And the bit line BL. The ground potential is applied to the channel region of the MISFET 5. Note that M
The channel region of ISFET 5 may be connected to source region 5S.

The first and second capacitors 6 and 7 are ferroelectric capacitors. The first capacitor 6 is
The gate electrode 5G of the SFET 5 is connected to the source region 5S, and the second capacitor 7 connects the gate electrode 5G and the drain region 5D.

In this specification, of the source region and the drain region of the MISFET 5, the one connected to the word line WL is called the source region 5S, and the bit line BL
Is called the drain region 5D, but it is not necessary to clearly distinguish the source region and the drain region. A region connected to the word line WL may be called a drain region, and a region connected to the bit line BL may be called a source region.

Next, a method of writing information "1" or information "0" to each memory cell will be described with reference to FIG. In each drawing of FIG. 2, the MISFET 5 of FIG.
Is represented as a MIS capacitor 5C formed by the channel and the gate electrode 5G.

FIG. 2A shows a state where information "1" is written. A ground potential of 0 V is applied to the word line WL, and a voltage V _CC is applied to the bit line BL. The first capacitor 6 has M
Since the IS capacitors 5C are connected in parallel, charges corresponding to the sum of charges stored in the first capacitor 6 and the MIS capacitor 5C are stored in the second capacitor 7. The ferroelectric films of the first and second capacitors 6 and 7 are polarized according to the stored charges.

The word lines WL and WL not selected at the time of writing
For example, the voltage V _CC/ 2 is applied.
Voltage V_CC/ 2 is the value of the first and second capacitors 6 and 7
Voltage that does not reverse the direction of the remanent polarization of the ferroelectric film
It is. Thereby, the word line WL and the bit line BL
Only, selectively write information "1" to one memory cell
Can be taken.

FIG. 2B shows a state where information "1" is stored. A ground potential of 0 V is applied to the bit line BL and the word line WL. Remanent polarization remains in the ferroelectric films of the first and second capacitors 6 and 7. The magnitude of the remanent polarization differs between the first capacitor 6 and the second capacitor 7. Charges corresponding to the remanent polarization remain in the first and second capacitors 6 and 7. First and second capacitors 6
And 7 remain in the MIS capacitor 5C. That is, a positive charge remains on the gate electrode 5G. In the channel region, holes move to a deep region of the substrate, and the substrate surface is depleted. Therefore, if a slight positive voltage is applied to the gate electrode 5G,
Electrons are accumulated in the channel region and are turned on.

FIGS. 2C and 2D show a state where information "0" is written and a state where information "0" is stored, respectively. When writing information "0", a negative voltage is applied (-V _CC) to the bit line BL. Each capacitor is charged in a direction opposite to the state of charge shown in FIG. When the bit line BL is set to the ground potential, the gate electrode 5
A state in which negative charges remain in G and holes are accumulated in the channel region. Therefore, to make the channel conductive,
A large voltage must be applied to the gate electrode 5G.

[0022] The non-selected word line WL and bit line BL at the time of writing for example, is applied voltage (-V _CC / 2). Thus, information “0” can be selectively written into one memory cell only by the word line WL and the bit line BL.

FIG. 3 shows the current-voltage characteristics of the MISFET 5 of FIG. The horizontal axis represents the gate voltage appearing on the gate electrode 5G, and the vertical axis represents the current flowing through the MISFET5. The curves L1 and L0 in FIG.
2B, that is, the current-voltage characteristic when the information “1” is stored, and FIG. 2D, that is, the current-voltage characteristic when the information “0” is stored. Is shown.

When information "1" is stored, a drain current Iread flows when the gate voltage is set to Vr. On the other hand, when the information “0” is stored, almost no drain current flows even if the gate voltage is set to Vr. Due to this difference in current, stored information can be read. For example, this current is applied to the word line WL
Every time, it can be detected by the word line control circuit 1 of FIG. In order to apply the voltage Vr to the gate electrode, a ground potential is applied to the word line WL.
A voltage of about 2 Vr may be applied to the bit line BL.

Next, a first embodiment of the present invention will be described with reference to FIGS.

The steps up to FIG. 4A will be described.
By selectively oxidizing the surface of the p-type silicon substrate 11, a field oxide film 12 is formed. An active region is defined by field oxide film 12. A 10 nm thick SiO ₂ film is formed on the surface of the active region by thermal oxidation. On this SiO ₂ film, a Ti film having a thickness of 30 nm and a Pt film having a thickness of 200 nm are laminated by sputtering. The Ti film functions as an adhesive layer. The thickness of the Ti film is 5 to 50 nm, and the thickness of the Pt film is 100 to 30 nm.
It may be 0 nm.

Patterning is performed from the Pt film to the SiO ₂ film, and the gate insulating film 13 and the gate electrode 14 are left. This patterning is performed by reactive ion etching (RIE) using CF ₄ and Ar.

After depositing a SiO ₂ film on the entire surface, anisotropic etching is performed to leave the sidewall insulating film 15 on the side surfaces of the gate insulating film 13 and the gate electrode 14. The n-type source region 16 and the drain region 17 are formed by introducing an n-type impurity such as P by a diffusion method or the like. In the present embodiment, M
Although the ISFET is configured to share the drain region 17, it is not always necessary to adopt the shared configuration.

Steps up to FIG. 4B will be described.
First, a mixed alkoxide solution in which powders of Sr, Bi, and Ta are mixed is applied on the substrate surface. After application, temperature 2
Dry in an atmosphere of 50 ° C. After repeating the steps of coating and drying a total of four times, the coating and drying are performed in an oxygen atmosphere at a temperature of 800 ° C.
A heat treatment for 0 minutes is performed. By this heat treatment, a thickness of 200
nm SrBi ₂ Ta ₂ O ₉ (SBT) film is obtained. Note that the thickness of the SBT film may be 50 to 500 nm.

By patterning the SBT film, a ferroelectric film 18 covering the gate electrode 14 is left. SB
The patterning of the T film can be performed by RIE using a mixed gas of CF ₄ and Ar.

Steps up to FIG. 4C will be described.
An IrO ₂ film having a thickness of 50 nm and a Pt film having a thickness of 100 nm are formed on the entire surface of the substrate by sputtering. In addition, the thickness of the IrO ₂ film is set to 10 to 100 nm,
The Pt film may have a thickness of 50 to 500 nm. IrO
_{The two} films act as diffusion barrier layers. The lamination of the IrO ₂ film and the Pt film is patterned to leave the word lines 19. The word line 19 covers approximately half of the surface of the ferroelectric film 18 from the surface of the source region 16 on the drain region side.
This word line 19 extends in a direction perpendicular to the paper surface of FIG.

Steps up to FIG. 4D will be described.
On the whole surface of the substrate, SiO is formed by chemical vapor deposition (CVD)
Deposit _two films. This SiO ₂ film is patterned so that a region of the surface of the ferroelectric film 18 that is not covered with the word line 19 and a surface of the drain region 17 are exposed. The interlayer insulating film 20 covering the word line 19 remains.

On the entire surface of the substrate, a 50 nm-thick IrO ₂
A film and a Pt film having a thickness of 100 nm are formed. The lamination structure of the IrO ₂ film and the Pt film is patterned, and the bit line 21 is formed.
Leave. The bit line 21 covers approximately half of the surface of the drain region 17 and the surface of the ferroelectric film 18 on the drain region 17 side, and extends in a direction crossing the word line 19.

The first capacitor 6 shown in FIG. 1B is formed by the gate electrode 14, the ferroelectric film 18 and the word line 19, and is formed by the gate electrode 14, the ferroelectric film 18 and the bit line 21. , A second capacitor 7 is formed.

FIG. 5 is a plan view of the ferroelectric memory device according to the first embodiment. By the field oxide film 12,
Active regions distributed in a matrix are defined. Two word lines 19 are arranged corresponding to each column of the active region, and one bit line 21 is arranged corresponding to each row. The gate electrode 14 is arranged at each intersection between the word line 19 and the bit line 21. In FIG. 5, the source region 16 is shown to extend beyond the word line 19 in order to clearly indicate the position of the source region 16.

In the ferroelectric memory device according to the first embodiment, as shown in FIG.
The ferroelectric film 18 is used to form a ferroelectric capacitor. That is, one memory cell is formed by substantially only one transistor. Therefore, the area occupied by one memory cell can be reduced as compared with the conventional 2Tr-2C type FeRAM, and high integration can be achieved.

The word line 19 and the bit line 21
Arbitrary memory cells can be randomly accessed only by the types of bus lines. For this reason, the memory driving method can be simplified. Furthermore, conventional 1T
Since the source line required for the r-1C type FeRAM becomes unnecessary, it is advantageous for high integration.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 6 is a sectional view of a ferroelectric memory device according to the second embodiment. The surface of the p-type silicon substrate 31 is selectively oxidized to form a field oxide film (not shown).
The surface of the active region defined by the field oxide film is thermally oxidized to form a 10 nm thick SiO ₂ film. This S
On the iO ₂ film, a polycrystalline silicon film having a thickness of 180 nm is deposited by CVD. Note that the thickness of the polycrystalline silicon film may be 100 to 500 nm.

The laminated structure of the SiO ₂ film and the polycrystalline silicon film is patterned to leave the gate insulating film 32 and the polycrystalline silicon gate electrode 33. At this time, the gate electrode of the MISFET is also formed in the peripheral circuit section.

After depositing a SiO ₂ film on the entire surface of the substrate,
By performing anisotropic etching, the sidewall insulating film 34 is left on the side surface of the gate electrode 33. Then P
The n-type drain region 35 and the source region 36 are formed by introducing an n-type impurity such as by a diffusion method. Incidentally, as in the first embodiment shown in FIG.
The drain region 35 is formed by two adjacent MISFEs.
It is good also as composition which T shares.

On the entire surface of the substrate, a 50 nm-thick TiN
A film and a Pt film having a thickness of 100 nm are stacked by sputtering. Note that the thickness of the TiN film is set to 20 to 100 n.
m, and the thickness of the Pt film may be 50 to 500 nm. By patterning the laminated structure of the TiN film and the Pt film, a gate electrode composed of the TiN film 37 and the Pt film 38 is left on the polycrystalline silicon gate electrode 33. The TiN film 37 functions as a diffusion prevention layer. Etching of the TiN film and the Pt film can be performed by RIE using a mixed gas of CF ₄ and Ar. A ferroelectric film 39 covering the gate electrodes 37 and 38 is formed by a method similar to that of the first embodiment described with reference to FIG.

On the entire surface of the substrate, a 50 nm-thick IrO ₂
A film and a Pt film having a thickness of 100 nm are deposited. This IrO
_{The two} films and the Pt film are patterned to leave the word lines 41 and the bit line connection electrodes 40. The word line 41 is shown in FIG.
Has the same shape as the word line 19 in the first embodiment shown in FIG.

The bit line connection electrode 40 is connected to the drain region 3
5 and about half of the surface of the ferroelectric film 39 on the drain region 35 side. Bit line connection electrode 40
Are connected to bit lines formed in an upper wiring layer not shown. Note that the word line 19, the interlayer insulating film 20, and the bit line 21 of the first embodiment shown in FIG.

In the second embodiment, since the lower part of the gate electrode is made of polycrystalline silicon, the steps of forming the source and drain regions are performed by the MISFE of the peripheral circuit.
Can be shared with T.

The TiN film 37 shown in FIG. 6 is for preventing an alloy reaction between the polycrystalline silicon gate electrode 33 and the Pt film 38. By preventing the alloy reaction, it is possible to prevent the formation of irregularities on the surface of the Pt film. However, the TiN film 37 is not essential, and in some cases, the polysilicon gate electrode 33 may be used.
The Pt film 38 may be formed directly on the substrate.

Next, a third embodiment will be described with reference to FIG.

FIG. 7 is an equivalent circuit diagram of a memory cell of the ferroelectric memory device according to the third embodiment. In the ferroelectric memory device shown in FIG.
The drain region 5D of the ISFET 5 is directly connected to the corresponding bit line BL. On the other hand, in the third embodiment, as shown in FIG. 7, the drain region 51D of the MISFET 51 is
It is connected to the corresponding bit line 55. Source area 5
1S is connected to the corresponding word line 56.

The gate electrode of the switching transistor 54 is connected to a switching control line 57 running in parallel with the word line 56.
It is connected to the. The conduction state of the switching transistor 54 is controlled by a signal applied to the switching control line 57. By providing the switching transistor 54, disturb at the time of writing to an unselected memory cell can be prevented.

The gate electrode of the switching transistor 54 is preferably formed of polycrystalline silicon as in the second embodiment shown in FIG.

In the first and second embodiments, the sidewall insulating film 15 or 34 is formed on the side surface of the gate electrode. However, the sidewall insulating film is not essential. The ferroelectric film 18 or 39 may be configured to directly contact the side surface of the gate electrode.

In the first embodiment, as shown in FIG. 4B, the ferroelectric film 18 is formed of the source region 16 and the drain region 1.
7 is not covered. Also in the second embodiment, as shown in FIG. 6, the ferroelectric film 39 includes the source region 36 and the drain region 3.
5 is not covered. As another configuration example, these ferroelectric films may cover the source region and the drain region. In this case, a contact hole is formed in the ferroelectric film on the source region and the drain region, and the source region and the word line are connected via the contact hole.
Connect the drain region and the bit line.

In the first and second embodiments, the MISF
Although the source and drain regions of the ET have a simple structure,
A low concentration drain (LDD) structure may be used.

In the above embodiment, the word lines and the bit lines have a two-layer structure of a Pt layer and an IrO ₂ layer. IrO ₂
The layer is in direct contact with the ferroelectric layer and acts as a diffusion barrier and an adhesion layer. Instead of the IrO ₂ layer, another noble metal oxide layer, for example, a RuO ₂ layer, a RhO ₂ layer, or the like may be used.
Further, the Pt layer may be formed of pure Pt.
It may be formed of a Pt alloy containing r, Rh, Ru, or the like.

In the above embodiment, the ferroelectric layer is formed of SB
Although formed of T, it may be formed of another ferroelectric material.
As an example of a ferroelectric material, a general formula

[0056]

^{Embedded image} A Bi-based layered perovskite-based oxide represented by (Bi ₂ O ₂ ) ²⁺ (A _n-1 B _n O _{3n + 1} ) ^2- is exemplified. Here, A is Bi, Pb, Ba, Sr, Ca,
Na or K, B is Ti, Ta, Nb, W,
Mo, Fe, Co, or Cr, and n is an integer of 1 to 5. In particular, A may be Sr and B may be a mixed crystal of Ta and Nb. The SBT is obtained by converting A in the above general formula to S
This corresponds to the case where r is set, B is set to Ta, and n is set to 2.

Still other ferroelectric materials include strontium titanate (ST), strontium barium titanate (BST), lead zirconate titanate (PZT), and lanthanum lead zirconate titanate (PLZT). When a Bi-based layered perovskite oxide such as SBT is used, the switching charge amount Q _SW of the ferroelectric capacitor is reduced, but the S / N ratio can be increased. On the other hand, when PZT or the like is used, the switching charge amount Q _SW can be increased.

In the first and second embodiments, FIG.
First capacitor 6 and second capacitor 7 shown in FIG.
It is preferable to make the capacitances equal to each other. If the two are made equal, even when the ferroelectric film is deteriorated, the two ferroelectric capacitors are equally deteriorated. Therefore, a stable memory operation can be maintained.

Next, a third embodiment will be described with reference to FIGS.

FIG. 8 is an equivalent circuit diagram of a main part of the ferroelectric memory device according to the third embodiment. The memory cell 3, the word line WL, and the bit line BL are the same as the circuit of the embodiment shown in FIG. In the third embodiment, a dummy cell 4 is provided outside the memory cell 3. Dummy cell 4
Is the same as the circuit configuration of the memory cell 3. However, in the dummy cell 4, the gate width of the MISFET is smaller than the gate width of the MISFET of the memory cell 3. For example, the MISFE of the dummy cell 4
The gate width of T is set to の of the gate width of the MISFET of the memory cell 3. MISFET of dummy cell 4
Are connected to a dummy word line DWL, and the drain region is connected to a reference line RL.

The bit line BL is connected to one current detection terminal 9A of the sense amplifier 9, and the reference line RL is
It is connected to the other current detection terminal 9B of the sense amplifier 9. The sense amplifier 9 applies a voltage at the current detection terminals 9A and 9B, and detects a difference between currents flowing through the current detection terminals 9A and 9B at that time.

FIG. 9 shows current-voltage characteristics of the memory cell 3 and the dummy cell 4 of FIG. The horizontal axis represents the voltage between the bit line BL and the word line WL, and the voltage between the dummy word line DWL and the reference line RL. The vertical axis represents the current flowing through the memory cell 3 and the dummy cell 4.

A curve N _m1 in FIG. 9 shows a characteristic in a state where information “1” is stored in the memory cell 3, and a curve N _m1 .
_m0 indicates a characteristic in a state where the information “0” is stored in the memory cell 3, and a curve N _d1 indicates the information “1” in the dummy cell 4.
Indicates the characteristic in the state where is stored. M of dummy cell 4
The gate width of the ISFET is equal to the MISFET of the memory cell 3.
, The current flowing through the dummy cell 4 when the information “1” is stored (corresponding to the curve N _d1 )
Is about 1 of the current flowing through the memory cell 3 (corresponding to the curve N _m1 ).
/ 2.

Next, referring to FIG. 8 and FIG.
A method for reading information stored in cell 3 will be described.
I will tell. Ground to word line WL and dummy word line DWL
A potential is applied, and two current detection terminals 9 of the sense amplifier 9 are applied.
A voltage Vr is applied to A and 9B. Applicable voltage Vr
Curve N when hit_m1, N_d1, And N_m0Current indicated by
Is I_nm1, I_nd1, And I_nm0It is. Voltage V
r is the conditional expression I_nm1> I_{nd 1}> I_nm0Such that
Pressure.

The sense amplifier 9 supplies a current to the current detection terminal 9A.
Current that flows through the current detection terminal 9B.
You. When information “1” is stored in the memory cell 3
Is the current I at the current detection terminal 9A._nm1Flows and the current detection end
Current I to child 9B_nd1Flows. That is, the current detection terminal
More current flows through 9A than at current detection terminal 9B. Me
If information “0” is stored in the memory cell 3,
The current I is supplied to the current detection terminal 9A._{nm 0}Flows, and the current detection terminal 9B
Current I_nd1Flows. That is, the current detection terminal 9A
A smaller current flows than the current detection terminal 9B.

Therefore, the information stored in the memory cell 3 can be identified by detecting the magnitude relationship between the currents flowing through the two current detection terminals 9A and 9B. Therefore, it is possible to read information stably.

In the third embodiment, the M of the dummy cell 4
Set the gate width of the ISFET to the MISFET of the memory cell 3.
The case where the gate width is made smaller than the gate width described above has been described. Instead of making the gate width different, the gate length of the MISFET of the dummy cell 4 may be longer than the gate length of the MISFET of the memory cell 3. For example, the MISFET of the dummy cell 4
May be twice the gate length of the MISFET of the memory cell 3. Thus, the MI of the dummy cell 4
When the resistance value of the SFET in the conductive state is
The current-voltage characteristics as shown in FIG. 9 can be obtained by making the MISFET larger than that of the MISFET.

FIG. 10 is an equivalent circuit diagram of a main part of a ferroelectric memory device according to a fifth embodiment of the present invention. In the fourth embodiment shown in FIG. 8, the MISFETs in the memory cell 3 and the dummy cell 4 are of n-channel type. On the other hand, in the fifth embodiment, the MISFETs in the memory cell 3P and the dummy cell 4P are configured by p-channel MISFETs. The gate width of the p-channel MISFET in the dummy cell 4P is the same as that of the fourth embodiment.
Is about 1/2 of the gate width of the MISFET. Other configurations are the same as those of the fourth embodiment shown in FIG.

To store information "1" in memory cell 3P, a ground potential is applied to word line WL and bit line B
A write voltage _Vcc is applied to L. When storing information "0" in the memory cell 3P, a ground potential is applied to the bit line BL, and a write voltage _Vcc is applied to the word line WL. Information “0” is stored in the dummy cell 4P.

FIG. 11 shows the memory cell 3P and the dummy cell 4
4 shows the current-voltage characteristics of P. The graph of FIG. 11 is equivalent to the graph of FIG. 9 with the signs of the voltage and current inverted. That is, between the bit line BL and a word line WL, and when applying a voltage -Vr between the reference line RL and the dummy word-line DWL, the the memory cell 3-Way, current -I _pm1 or -I _pm0 The current -I _pd0 flows through the dummy cell 4P. These currents include (−I _pm1 )>
(−I _pm0 )> (− I _pd0 ). Therefore, the fourth
As in the case of the embodiment, the information stored in the memory cell 3P can be read stably.

Next, a method of manufacturing a ferroelectric memory device according to a sixth embodiment of the present invention will be described with reference to FIG.

The steps up to the state shown in FIG. An element isolation structure 61 is formed on a surface of a p-type silicon substrate 60. The element isolation structure 61 may be, for example, a field oxide film formed by using a local oxidation of silicon (LOCOS) technique or a shallow trench type. A 10 nm-thick gate insulating film 5 is formed on the surface of the active region defined by the element isolation structure 61 by thermal oxidation.
Form I.

On the gate insulating film 5I, a 30-nm thick Ti film 5G1 and a 200-nm thick Pt film 5G2 are laminated in this order. The Ti film 5G1 and the Pt film 5G2 can be deposited by sputtering. Ti film 5G
1 has a function of improving the adhesion between the gate insulating film 5I and the Pt film 5G2.

The Pt film 5G2, the Ti film 5G1, and the gate insulating film 5I are patterned to form a gate electrode 5G. The etching of the Pt film 5G2 and the Ti film 5G1 is performed by etching C
It can be performed by reactive ion etching (RIE) using a mixed gas of F ₄ and Ar. At the beginning of RIE, the incident angle of ions is set to about 10 °
0 °. By controlling the angle of incidence of ions in this way, it is possible to prevent generation of a fence-shaped resist residue remaining along the edge of the upper surface of the gate electrode 5G. Further, the side surface of the gate electrode 5G can be inclined.

A sidewall insulating film 65 made of SiO ₂ is formed on the side surface of the gate electrode 5G. The sidewall insulating film 65 is formed by depositing a SiO ₂ film on the entire surface of the substrate and then performing anisotropic etching by RIE. Using the gate electrode 5G and the sidewall insulating film 65 as a mask, phosphorus (P) is ion-implanted to form a source region 5S and a drain region 5D.

As shown in FIG. 12B, a 200 nm thick ferroelectric film 70 made of SBT is formed on the entire surface of the substrate.
Is formed by a sol-gel method. Hereinafter, the ferroelectric film 70
The method for forming the film will be described. First, Sr, Bi, Ta
An alkoxide solution obtained by mixing the above powders is spin-coated on the substrate surface and dried at a temperature of 250 ° C. This spin coating and drying process are repeated four times. Preliminary firing is performed for 30 minutes in an oxygen atmosphere at a temperature of 600 ° C. At this stage, the ferroelectric film 70 is not crystallized. Since the surface of the thin film formed by the sol-gel method tends to be flat, the thickness of the source / drain region 5
It becomes thinner than the film thickness above S and 5D.

As shown in FIG. 12C, the ferroelectric film 7
0, contact holes 71S and 71 exposing a part of the surface of each of source region 5S and drain region 5G.
Form D. The etching of the ferroelectric film 70 can be performed by, for example, RIE using a mixed gas of CF ₄ and Ar.

As shown in FIG. 12D, an IrO ₂ film 73 having a thickness of 50 nm and a thickness of 100 nm were formed on the entire surface of the substrate.
m Pt films 74 are stacked in this order. IrO ₂ film 7
The deposition of No. 3 is performed by reactive sputtering using an Ir target and using Ar and O ₂ as a sputtering gas. The sputtering conditions were as follows: substrate temperature 300 ° C., atmospheric pressure 5 mTorr, DC power 500 W, Ar flow rate 40
sccm, O ₂ flow rate 80 sccm. Note that, as an assist gas for heating the substrate, Ar gas is flowed at a flow rate of 30 sccm between the substrate holder and the substrate.

When the IrO ₂ film formed under the above conditions was evaluated by X-ray diffraction, a peak corresponding to IrO ₂ was detected. Further, when the cross section of the IrO ₂ film was observed with a scanning electron microscope (SEM), it was confirmed that columnar IrO ₂ crystal grains were formed. IrO ₂
The film 23 functions as a diffusion prevention layer.

The Pt film 74 can be deposited by sputtering using a Pt target and using Ar as a sputtering gas.

The IrO ₂ film 73 and the Pt film 74 are patterned and separated into a word line WL connected to the drain region 5D and a drain electrode 75 connected to the source region 5S. The Pt film 74 and the IrO ₂ film 73 are etched by C
This is performed by RIE using a mixed gas of F ₄ and Ar.

The drain electrode 75 faces a part of the upper surface of the gate electrode 5G via the ferroelectric film 70. Drain electrode 75, ferroelectric film 70, and gate electrode 5G
Is formed. Word line W
L faces a partial region of the upper surface of the gate electrode 5G via the ferroelectric film 70. Word line WL, ferroelectric film 7
0 and a first capacitor 6 composed of the gate electrode 5G. The word line WL extends in a direction perpendicular to the plane of FIG. 12D, and the other memory cells 3 shown in FIG.
Connected to the source region of

After patterning the IrO ₂ film 73 and the Pt film 74, a heat treatment is performed to crystallize the ferroelectric film 70. This heat treatment is performed in an oxygen atmosphere at a temperature of 750 to 800 ° C. for about 30 minutes.

An interlayer insulating film 76 covering the word line WL and the drain electrode 75 is formed. The interlayer insulating film 76 is made of, for example, C using tetraethylorthosilicate (TEOS).
It is formed by VD. A contact hole exposing a part of the surface of the drain electrode 75 is formed in the interlayer insulating film 76. On the interlayer insulating film 76, a bit line BL extending in a direction crossing the word line WL is formed. Bit line BL
Is formed, for example, of Al.

In the ferroelectric memory device shown in FIG. 12D, the MISFET 1 is almost the same as in the first embodiment.
One memory cell is arranged in each of the regions. Also,
A desired memory cell can be accessed only by the word line WL and the bit line BL.

In the ferroelectric memory device shown in FIG. 12D, a side wall insulating film 65 is formed on the side surface of the gate electrode 5G. Therefore, the gate electrode 5G
And the source region 5S, and between the gate electrode 5G and the drain region 5D.

FIG. 13A shows current-voltage characteristics of the memory cell shown in FIG. The horizontal axis represents the voltage of the bit line BL with respect to the word line WL in the unit “V”, and the vertical axis represents the current flowing between the bit line BL and the word line WL in the unit “A”. Note that the MI of the memory cell to be measured is
The gate width of the SFET is 10 μm and the gate length is 1 μm. When the voltage is gradually increased, the current gradually increases as shown by the curve FL.

When the voltage applied to the bit line BL becomes 5 V, the voltage change starts to decrease. When the voltage is gradually reduced, the current gradually decreases as shown by the curve BL. When the voltage increases and decreases, the current change does not follow the same path and shows hysteresis. This is because the polarization of the ferroelectric film 70 forming the first and second capacitors 6 and 7 shown in FIG. 12D has a hysteresis characteristic with respect to the applied voltage.

FIG. 13B shows current-voltage characteristics of a memory cell storing information "1" and a memory cell storing information "0". The horizontal axis represents the bit line B with respect to the word line WL.
The voltage of L is represented by the unit “V”, and the vertical axis represents the current flowing between the bit line BL and the word line WL by the unit “μA”. A curve LD1 in FIG. 13B indicates that the bit line BL
A current change of a memory cell storing information "1" by applying 5 V is shown, and a curve LD0 shows a current change of a memory cell storing information "0" by applying -5 V to the bit line BL. .

It can be seen that the current flowing through the memory cell storing the information “1” is larger than the current flowing through the memory cell storing the information “0”. For example, when a voltage of 1.5 V is applied, about 1
While a current of μA flows, only a current of about 0.3 μA flows in a memory cell storing information “0”. By detecting this current difference, information stored in the memory cell can be read.

FIG. 14 is a sectional view of one memory cell part of the ferroelectric memory device according to the seventh embodiment. FIG.
In the sixth embodiment shown in (D), the source / drain regions 5S and 5D are in direct contact with the ferroelectric film 70.
In the case of the seventh embodiment, the word line WL and the drain electrode 7 on the surfaces of the source / drain regions 5S and 5D are formed.
The region not in contact with 5 is covered with a protective insulating film 80 made of SiO ₂ . Note that the sidewall insulating film 65 illustrated in FIG. 12D is not formed. Other configurations are the same as those of the sixth embodiment shown in FIG.

Hereinafter, a method for forming the protective insulating film 80 will be described. After ion implantation for forming the source / drain regions 5S and 5D shown in FIG. 12A, the natural oxide film on the surfaces of the source / drain regions 5S and 5D is removed. Then, the surface of the source / drain regions 5S and 5D can be covered with the protective insulating film 80 by thermally oxidizing the substrate surface. As shown in FIG. 12A, before the ion implantation, the side wall insulating film 65 is formed.
May be formed.

Alternatively, the Ti film 5G1 shown in FIG.
May be performed under conditions that increase the etching selectivity to SiO ₂ , and the gate insulating film 5I may be left on the surfaces of the source / drain regions 5S and 5D. For example, the Ti film is etched by RIE using a mixed gas of Cl ₄ and BCl ₃ . Under these conditions, the etching selectivity of Ti to SiO ₂ is about 10. Note that Ti
The Pt film 5G2 on the film 5G1 is etched by RIE using a mixed gas of CF ₄ and Ar.

In the seventh embodiment, the surfaces of the source / drain regions 5S and 5D are covered with a protective insulating film 80. Therefore, the source / drain regions 5S or 5D
Leakage current between the semiconductor device and the ferroelectric film 70 can be reduced.

FIG. 15 is a sectional view showing one memory cell portion of the ferroelectric memory device according to the eighth embodiment. FIG.
In the sixth embodiment shown in (D), the ferroelectric film 70 forming the first capacitor 6 and the ferroelectric film 70 forming the second capacitor 7 are formed of one continuous thin film. It had been. In the eighth embodiment, the ferroelectric films 70 constituting the first and second capacitors 6 and 7 are separated from each other. The other configuration is the same as the sixth configuration shown in FIG.
This is the same as the embodiment.

The ferroelectric film 70 is separated by patterning the Pt film 74 and the Ti film 73 shown in FIG. 12D of the sixth embodiment and then using the same resist pattern. Can be performed by etching. Groove 70a formed by separation of ferroelectric film 70
The inside is buried with an interlayer insulating film 76.

The dielectric constant of the interlayer insulating film 76 depends on the ferroelectric film 7
It is smaller than the dielectric constant of 0. Therefore, lines of electric force between the IrO ₂ film 73 and the gate electrode 5G can be preferentially generated in the thickness direction of the ferroelectric film 70. This makes it possible to improve the performance of the first and second capacitors 6 and 7.

FIG. 16 is a sectional view of one memory cell portion for explaining a method of manufacturing a ferroelectric memory device according to the ninth embodiment. 16A through substantially the same steps as the steps up to the state of FIG. 12B of the sixth embodiment.
State. However, in the ninth embodiment, FIG.
The (B) side wall insulating film 65 is not formed.

As shown in FIG. 16B, the ferroelectric film 7
The surface of No. 0 is flattened by chemical mechanical polishing (CMP). P
The CMP is stopped when the upper surface of the t film 5G is exposed. A 200 nm thick SiO ₂ film 85 is coated on the entire surface of the
It is formed by VD.

As shown in FIG. 16C, contact holes 86S and 86D exposing a part of the surface of the source / drain regions 5S and 5D are formed. SiO ₂ film 8
5 and the ferroelectric film 70 are etched by RIE using a mixed gas of CF ₄ and Ar. Gate electrode 5G
Ferroelectric film 70b remains between the side surface of the contact hole 86S and the side surface of the contact hole 86D.
0a remains.

As shown in FIG. 16D, a drain electrode 75 connected to the drain region 5D is formed by filling the contact hole 86D. Contact hole 86
S is buried to form a word line WL connected to the source region 5S. The formation of the drain electrode 75 and the word line WL is performed in the same manner as the formation of the drain electrode 75 and the word line WL illustrated in FIG.

In the ninth embodiment shown in FIG. 16D, no ferroelectric film is disposed on the upper surface of the gate electrode 5G, and the ferroelectric films 70a and 70b are disposed only on the side surfaces. Have been. The first capacitor 6 includes the ferroelectric film 70b on the side surface, and the second capacitor 7 includes the ferroelectric film 70a. Since the upper surface of the gate electrode 5G is not used as a capacitor, the gate length can be reduced. By shortening the gate length,
High integration can be achieved.

FIG. 17 is a cross-sectional view of one memory cell portion for explaining a method of manufacturing a ferroelectric memory device according to a modification of the ninth embodiment. Through the same steps as in the ninth embodiment, the state shown in FIG. Ferroelectric film 70
Is anisotropically etched to leave a ferroelectric film only on the side surface of the gate electrode 5G. This anisotropic etching is performed by, for example, RIE using a mixed gas of CF ₄ and Ar.

FIG. 17A shows a state after anisotropic etching. A ferroelectric film 70c is formed on the side surface of the gate electrode 5G.
And 70d remain. The surfaces of the source region 5S and the drain region 5D are exposed.

As shown in FIG. 17B, a drain electrode 75 in contact with the drain region 5D and a word line WL in contact with the source region 5S are formed. The formation of the drain electrode 75 and the word line WL is performed in the same manner as the formation of the drain electrode 75 and the word line WL illustrated in FIG.

In the modification of the ninth embodiment, as in the ninth embodiment, the first capacitor 6 includes the ferroelectric film 70d on the side surface of the gate electrode 5G. The second capacitor 7 includes the ferroelectric film 70c. Since the upper surface of the gate electrode 5G is not used as a capacitor, the gate length can be reduced, and high integration can be achieved.

Each of the drawings for describing the seventh to ninth embodiments shows a case where one memory cell is arranged in one active region. For example, the first embodiment shown in FIG. As described above, two memory cells may be arranged in one active region.

FIG. 18 is a sectional view of a ferroelectric memory device in which two memory cells according to the sixth embodiment are arranged in one active region. The configuration of one memory cell is shown in FIG.
It is the same as that shown in (D). The drain region 5D arranged in the center of FIG. 18 is shared by two memory cells.

The drain region 5D is in contact with a bit line connection portion 77 made of a stack of an IrO ₂ film 73 and a Pt film 74. The bit line connection part 77 is provided on both sides of the MISF
The second capacitor 7 is provided between each of the gate electrodes 5G of the ET.
To form The bit line BL is formed on the interlayer insulating film 76. The bit line BL is electrically connected to a bit line connection portion 77 via a contact hole provided in the interlayer insulating film 76.

Next, referring to FIG. 19 to FIG.
An example will be described.

The steps up to the state shown in FIG. 19A are the same as the steps of forming a general MISFET. On the surface of p-type silicon substrate 90, a memory cell region and a peripheral circuit region are defined. In the surface layer in the memory cell area, p
A mold well 91 is formed, and n is formed on the surface layer in the peripheral circuit region.
A mold well 92 and a p-type well 93 are formed. Field oxide film 9 formed on the surface of silicon substrate 90
4, an active area is defined on the surface of each well.

In the p-type well 91, an n-channel MISF
ET 96 is formed, and p-channel M
An ISFET 97 is formed, and an n-channel MISFET 98 is formed in a p-type well 93. Each MISFE
The gate insulating films 96I, 97I, and 98I of T have a thickness of 7 nm.
Is the formation of SiO ₂ film, a gate electrode 96G, 97G,
98G is formed of a 180 nm-thick n ⁺ -type polycrystalline silicon film. Sidewall insulating films are formed on the side surfaces of each of the gate electrodes 96G, 97G, 98G.

As shown in FIG. 19B, a 200 nm thick SiO ₂ film 100 is formed on the entire surface of the silicon substrate 90.
To form The SiO ₂ film 100 is made of, for example, SiH ₄ and O ₂
And can be formed by CVD using

As shown in FIG. 19C, the SiO ₂ film 1
The surface of No. 00 is flattened by chemical mechanical polishing (CMP).
Gate electrodes 96G, 97G, 9 made of polycrystalline silicon
When the surface of 8G is exposed, the CMP is stopped. Ir having a thickness of 50 nm is formed on the surface of the planarized SiO ₂ film 100.
An O ₂ film and a Pt film having a thickness of 175 nm are stacked. This 2
The layer is patterned leaving the capacitor lower electrode 102. The capacitor lower electrode 102 covers the upper surface of the gate electrode 96G.

The shape of the capacitor lower electrode 102 when viewed from the normal direction of the substrate may be the same as the shape of the gate electrode 96G, or a shape including the gate electrode 96G as described later with reference to FIG. It may be.

As shown in FIG. 20D, the SiO ₂ film 1
An SBT film having a thickness of 200 nm is formed on the S00. S
The BT film is formed by the same method as the formation of the ferroelectric film 70 according to the sixth embodiment described with reference to FIG. The SBT film on the peripheral circuit region is removed, and the ferroelectric film 103 made of SBT is left on the memory cell region. The ferroelectric film 103
The capacitor lower electrode 102 is covered. When the SBT film is formed by the sol-gel method, the surface of the film tends to be flat. For this reason, the film thickness of the ferroelectric film 103 on the capacitor lower electrode 102 is smaller than the film thickness of other regions.

As shown in FIG. 20E, the ferroelectric film 1
03 and the SiO ₂ film 100, to form a contact hole exposing a surface of the source region and the drain region of MISFET96. The etching of the ferroelectric film 103
Performed by RIE using a mixed gas of CF ₄ and Ar,
The etching of the SiO ₂ film 100 can be performed by RIE using a mixed gas of CF ₄ and H ₂ .

On the outermost surface of the substrate, a 50 nm thick IrO
_Two films and a Pt film having a thickness of 100 nm are laminated. The two layers are patterned to form a word line WL and a bit line connection 10.
Leave 7. The word line WL is connected to the source region 96S of the MISFET 96 via the inside of the contact hole 105, and the bit line connection portion 107 is connected to the contact hole 10
5, the drain region 96D of the MISFET 96
Connected to.

Word line WL and capacitor lower electrode 102
Thus, a first ferroelectric capacitor is formed, and the bit line connecting portion 107 and the capacitor lower electrode 102 form a second ferroelectric capacitor.

In the tenth embodiment, the MI of the memory cell portion is
The gate electrode of the SFET 96 is the MISFE of the peripheral circuit section.
Like the gate electrodes of T97 and T98, they are formed of polycrystalline silicon. Therefore, the MISFET in the memory cell section can be formed simultaneously with the formation of the MISFET in the peripheral circuit section.

FIG. 21 is a plan view of a memory cell portion of a ferroelectric memory device according to the tenth embodiment. FIG. 20E is a cross-sectional view taken along a dashed-dotted line A21-A21 in FIG.
Of the MISFET 96 of FIG.

The gate electrode 96G covers a region of the active region 110 excluding the left and right ends in the figure. Capacitor lower electrode 1
02 includes a gate electrode 96G and covers a wider area. Almost the left half area of the capacitor lower electrode 102 in the drawing is covered with the bit line connection part 107, and the right half area is covered with the word line WL. The bit line connection unit 107
The word line WL is connected to the drain region 96D via the contact hole 105, and is connected to the other contact hole 10D.
5, and is connected to the source region 96S.

In the tenth embodiment, the patterning of the gate electrode 96G and the patterning of the capacitor lower electrode 102 are performed in different steps. For this reason, both shapes can be determined independently of each other. As shown in FIG. 21, by making the capacitor lower electrode 102 larger than the gate electrode 96G, it is possible to increase the capacitance of the ferroelectric capacitor.

In the tenth embodiment, the capacitor lower electrode 102 is formed of two layers of the IrO ₂ film and the Pt film, but may have another structure. For example, a TiN layer may be used instead of the IrO ₂ layer, or a stacked structure in which a Ti layer and a TiN layer are stacked in this order may be used. Ti
The layer acts as an adhesion layer, and the TiN layer acts as a diffusion barrier. Note that an Ir layer may be used instead of the Pt layer.

In the tenth embodiment, as in the modification of the sixth embodiment shown in FIG.
One memory cell is formed in one active region, and each M
The ISFET may share the drain region. Further, as shown in FIG. 4D, a structure in which the bit line is directly in contact with the drain region may be employed.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0127]

As described above, according to the present invention,
One memory cell can be arranged in a region for one field effect transistor. Further, a desired memory cell can be accessed only by a word line and a bit line. Therefore, high integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a ferroelectric memory device according to an embodiment of the present invention, and an equivalent circuit diagram of one memory cell.

FIG. 2 is an equivalent circuit diagram of one memory cell for describing a method of writing and holding information in a ferroelectric memory device according to an embodiment of the present invention.

FIG. 3 is a graph showing current-voltage characteristics of one memory cell for explaining a method of reading information in a ferroelectric memory device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a substrate for explaining a method of manufacturing the ferroelectric memory device according to the first embodiment of the present invention.

FIG. 5 is a plan view of the ferroelectric memory device according to the first embodiment.

FIG. 6 is a cross-sectional view of one memory cell of the ferroelectric memory device according to the second embodiment.

FIG. 7 is an equivalent circuit diagram of one memory cell of the ferroelectric memory device according to the third embodiment.

FIG. 8 is an equivalent circuit diagram of one memory cell and a dummy cell of a ferroelectric memory device according to a fourth embodiment.

FIG. 9 is a graph showing current-voltage characteristics of one memory cell and a dummy cell for explaining a method of reading information in a ferroelectric memory device according to a fourth embodiment.

FIG. 10 illustrates a ferroelectric memory device according to a fifth embodiment.
FIG. 3 is an equivalent circuit diagram of a memory cell and a dummy cell.

FIG. 11 is a graph showing current-voltage characteristics of one memory cell and a dummy cell for explaining a method of reading information in a ferroelectric memory device according to a fifth embodiment.

FIG. 12 is a sectional view of a substrate for describing a method of manufacturing a ferroelectric memory device according to a sixth embodiment.

FIG. 13A is a graph showing measured values of current-voltage characteristics of a memory cell according to a sixth embodiment, and FIG.
FIG. 3B is a graph showing measured values of the current-voltage characteristics of the memory cell in a state where the information “1” is stored in the memory cell and a state where the information “0” is stored in the memory cell.

FIG. 14 illustrates a ferroelectric memory device according to a seventh embodiment.
FIG. 3 is a cross-sectional view of a memory cell portion.

FIG. 15 shows a ferroelectric memory device according to an eighth embodiment.
FIG. 3 is a cross-sectional view of a memory cell portion.

FIG. 16 is a sectional view of one memory cell portion for illustrating a method of manufacturing a ferroelectric memory device according to a ninth embodiment.

FIG. 17 is a sectional view of one memory cell portion for illustrating a method of manufacturing a ferroelectric memory device according to a modification of the ninth embodiment.

FIG. 18 is a sectional view of a ferroelectric memory device according to a modification of the sixth embodiment.

FIG. 19 is a sectional view (part 1) of a substrate for explaining a method of manufacturing a ferroelectric memory device according to a tenth embodiment.

FIG. 20 is a sectional view (part 2) of the substrate for describing the method for manufacturing the ferroelectric memory device according to the tenth embodiment.

FIG. 21 is a plan view of one memory cell part of a ferroelectric memory device according to a tenth embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 word line control circuit 2 bit line control circuit 3 memory cell 5, 51, 96, 97, 98 MISFET 6 first capacitor 7 second capacitor 9 sense amplifier 11, 31, 60, 90 p-type silicon substrate 12, 61 , 94 Field oxide film 13, 32 Gate insulating film 14, 33, 38 Gate electrode 15, 34, 65 Side wall insulating film 16, 36 Source region 17, 35 Drain region 18, 39, 70, 103 Ferroelectric film 19, 41, 56 Word line 20, 76 Interlayer insulating film 21, 55 Bit line 37 TiN film 40 Bit line connection electrode 54 Switching transistor 57 Switching control line 73 IrO ₂ film 74 Pt film 75 Drain electrode 77, 107 Bit line connection part 80 Protection insulating film 85,100 SiO ₂ film 86D, 86S, 1 5 contact holes 91 and 93 p-type well 92 n-type well 102 capacitor lower electrode 110 active region

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Wataru Nakamura 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takashi Eshita 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (56) References JP-A-7-221207 (JP, A) JP-A 9-45088 (JP, A) JP-A 11-204747 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 27/105 G11C 11/22 G11C 14/00 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (21)

(57) [Claims] A field effect transistor including a source region, a drain region, and a gate electrode; a first ferroelectric capacitor connecting the source region and the gate electrode; A ferroelectric memory device having a second ferroelectric capacitor connected to the gate electrode. 2. The semiconductor device according to claim 1, wherein said gate electrode is formed of polycrystalline silicon, and is further disposed on said gate electrode, wherein Pt or I
2. The ferroelectric memory device according to claim 1, further comprising a capacitor lower electrode formed by r, wherein the capacitor lower electrode forms one electrode of each of the first and second ferroelectric capacitors. 3. The ferroelectric film of the first and second ferroelectric capacitors covers the gate electrode, the first ferroelectric capacitor having an electrode connected to the source region, and Of the second ferroelectric capacitor,
3. The ferroelectric memory device according to claim 1, wherein an electrode connected to the drain electrode is arranged so as to overlap the gate electrode when viewed from a normal direction of the substrate. 4. The ferroelectric film of the first ferroelectric capacitor and the ferroelectric film of the second ferroelectric capacitor are formed of one continuous thin film. The ferroelectric memory device according to claim 1. 5. The ferroelectric film of the first ferroelectric capacitor and the ferroelectric film of the second ferroelectric capacitor are spaced from each other on the surface of the gate electrode in an in-plane direction. And burying a space between the ferroelectric film of the first ferroelectric capacitor and the ferroelectric film of the second ferroelectric capacitor on the gate electrode; 4. The ferroelectric memory device according to claim 3, further comprising an embedded member formed of an insulating material having a smaller dielectric constant than the ferroelectric films of the first and second ferroelectric capacitors. 6. The ferroelectric memory device according to claim 1, wherein a capacitance of said first ferroelectric capacitor is substantially equal to a capacitance of said second ferroelectric capacitor. . 7. The first ferroelectric capacitor, wherein an electrode connected to the source region extends in a first direction in a substrate surface to form a first wiring. 7. The ferroelectric memory device according to any one of items 1 to 6. 8. The second wiring of the second ferroelectric capacitor, wherein an electrode connected to the drain region extends in a second direction intersecting the first direction in a substrate surface. 8. The ferroelectric memory device according to claim 7, further comprising an interlayer insulating film that electrically insulates the first wiring and the second wiring at intersections between the first wiring and the second wiring. 9. A first protective insulating film covering a region of the surface of the source region other than a region in contact with the first ferroelectric capacitor, and a surface of the drain region. 9. The ferroelectric memory device according to claim 1, further comprising: a second protective insulating film covering a region excluding a region in contact with said second ferroelectric capacitor. 10. The ferroelectric memory device according to claim 1, further comprising a sidewall insulating film made of an insulating material disposed so as to cover a side surface of said gate electrode. 11. The electrode of the first ferroelectric capacitor connected to the source region, and the second ferroelectric capacitor,
The electrode of the ferroelectric capacitor connected to the drain region faces the side surface of the gate electrode via a ferroelectric film and is not disposed on the upper surface of the gate electrode. Item 2. The ferroelectric memory device according to item 1. 12. A plurality of first wirings extending in a first direction on a surface of the substrate, and a plurality of wirings extending in a second direction on the surface of the substrate, the second direction intersecting the first direction. A second wiring, at an intersection of the first wiring and the second wiring, an interlayer insulating film that insulates the first wiring and the second wiring from each other, and corresponds to an intersection of the first wiring and the second wiring. Memory cells, each of the memory cells being:
A first ferroelectric capacitor including a field effect transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor, wherein each field effect transistor includes a source region, a drain region, and a gate electrode; Body capacitor
The source region and the gate electrode of the field effect transistor of the memory cell are connected, the second ferroelectric capacitor connects the drain region and the gate electrode of the field effect transistor of the memory cell, and the source region is , A plurality of memory cells connected to a corresponding first wiring, and the drain region is connected to the corresponding second wiring. 13. A first control circuit connected to the first wiring, the first control circuit selectively applying a first write signal to a part of the plurality of first wirings, and 2 lines, and selectively applies a second write signal to some of the plurality of second lines.
Of the first and second ferroelectric capacitors of the memory cell corresponding to the intersection of the first wiring to which the first write signal is applied and the second wiring to which the second write signal is applied. The second write signal which causes remanent polarization in a specific direction in the dielectric film and does not change the polarization directions of the ferroelectric films of the first and second ferroelectric capacitors of the other memory cells. 13. The ferroelectric memory device according to claim 12, further comprising a second control circuit to be applied. 14. The semiconductor device according to claim 1, further comprising: connecting each source region of said memory cell to a corresponding first wiring or a corresponding drain region and a corresponding second wiring; 14. The ferroelectric memory device according to claim 12, further comprising a switching element for selecting a non-conductive state. 15. The drain region of a memory cell adjacent in the second direction is shared with each other.
15. The ferroelectric memory device according to any one of items 14 to 14. 16. The electrode of the first ferroelectric capacitor connected to the source region and the first wiring are formed of the same wiring layer.
16. The ferroelectric memory device according to any one of 15. 17. An electrode connected to the drain region of the second ferroelectric capacitor, the second ferroelectric capacitor being connected to the second ferroelectric capacitor.
17. The wiring of claim 16 is formed in the same wiring layer.
3. The ferroelectric memory device according to 1. 18. An electrode of the second capacitor connected to the drain region is formed in the same wiring layer as the first wiring, and the second wiring is formed in the interlayer insulating film. 17. The ferroelectric memory device according to claim 16, wherein the ferroelectric memory device is connected to an electrode connected to the drain region of the second capacitor of the corresponding memory cell via the inside of the formed contact hole. 19. The method according to claim 19, further comprising: forming a third substrate on the substrate.
And a fourth wiring; a dummy cell having one terminal connected to the third wiring and the other terminal connected to the fourth wiring; a current flowing through the second wiring; 13. The ferroelectric memory device according to claim 12, further comprising: a comparison circuit for comparing a current flowing through said wiring. 20. The dummy cell, comprising: a dummy field effect transistor having a source region connected to the third wiring and a drain region connected to the fourth wiring; a gate electrode of the dummy field effect transistor and a source region. 20. The ferroelectric memory device according to claim 19, further comprising: a third ferroelectric capacitor connecting the first ferroelectric capacitor to the first ferroelectric capacitor, and a fourth ferroelectric capacitor connecting the gate electrode and the drain region of the dummy field effect transistor. 21. The ferroelectric memory device according to claim 20, wherein the resistance of the dummy field-effect transistor in a conductive state is larger than the resistance of the field-effect transistor of the memory cell in a conductive state.