JPH1027856A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory of an MFMIS(metal/ ferroelectric/metal insulator/semiconductor) structure, wherein even if a power- supply voltage is a voltage of 5V or lower, the operation of a nonvolatile memory is made possible. SOLUTION: A ferroelectric capacitor, which consists of an upper electrode 109, a ferroelectric film 108 and a lower electrode 107, is patterned and thereafter, after protective films 110 are respectively formed on the sidewalls of the capacitor, a floating gate electrode 106 is processed. By adjusting the thickness of the films 110 on the sidewalls of the capacitor, the area of the film 108 which comes into contact with the electrodes 109 and 107 is formed smaller than that of the electrode 106. The capacity of the ferroelectric capacitor becomes smaller than that of a gate insulating film capacitor, which consists of the electrode 106, a gate insulating film 102 and an Si substrate 101. Therefore, even if a power-supply voltage is a low voltage of 5V or lower, a full reversing voltage can be applied to the film 108 and the operation of a nonvolatile memory becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (El
ectrical Erasable and Programmable Read OnlyMemor
The present invention relates to a nonvolatile semiconductor memory device such as y) and a method of manufacturing the same, and in particular, MFMIS utilizing spontaneous polarization of a ferroelectric film.
(Metal / Ferroelectric / Metal / Insulator / Semi
The present invention relates to a nonvolatile semiconductor memory device having a (conductor) structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile memory using a ferroelectric film, a one-transistor-one capacitor (1Tr) for detecting the direction of polarization of a ferroelectric capacitor connected in series with a source or a drain of a MOS transistor is known. -1
Type C) and a ferroelectric capacitor connected in series to the gate of the MOS transistor to operate also as a gate as shown in the equivalent circuit diagram of FIG. 3 to detect a change in resistance of the semiconductor due to spontaneous polarization of the ferroelectric. There is a transistor (1Tr) type.

In the former 1Tr-1C type non-volatile memory, the direction of polarization of a ferroelectric capacitor is detected to determine "1" and "0" of data. When rewriting data, the direction of polarization is inverted. When reading data, a voltage is applied to the ferroelectric capacitor to check whether the polarization is inverted. When the polarization is inverted, the capacitor releases electric charge. Therefore, the rise in the potential of the connected bit line at this time is latched at a high level by the sense amplifier, and data "1" is read. Therefore, since data is destroyed at the time of reading, it is necessary to perform rewriting after reading to return the polarization state to the original state.

On the other hand, the latter 1Tr type non-volatile memory only detects a change in the resistance of the semiconductor due to spontaneous polarization of the ferroelectric substance, so that the data is not destroyed when data is read. For this reason, the number of times of rewriting can be improved. Therefore, as a nonvolatile memory using a ferroelectric, the latter single transistor type is expected to be promising in the future. The present invention relates to an improvement of this single-transistor nonvolatile memory. The former is described, for example, on page 17 of Nikkei Electronics in the May 24, 1993 issue (No. 581). Regarding the latter, see, for example, "Integrated Ferroelectrics", Vol. 6, pp. 23-34, 1995 (Integrated Ferroelectrics, 1995, Vol. 6, pp. 23-3).
It is described in 4).

Here, FIG. 2 shows the element structure of a conventional single-transistor nonvolatile memory. FIG. 3 is an equivalent circuit thereof. In FIG. 2, reference numeral 101 denotes silicon (S
i) shows a substrate, and has a thickness of 25 nm on the Si substrate 101
Gate oxide film 102 is formed. 200 nm of platinum (Pt) is deposited on the gate oxide film 102 for the floating gate electrode 114, and the platinum is patterned on the element isolation oxide film 105. Furthermore, PZT having a thickness of 240 nm is formed on platinum for the floating gate electrode 114.
Ferroelectric film 108 using (lead zirconate titanate)
And a thickness of 200 nm for the control gate electrode 115
Is sequentially deposited and then patterned. In an element having such a structure, a memory operation at ± 6 V has been confirmed. In FIG. 2, reference numeral 103 denotes a drain diffusion layer, 104 denotes a source diffusion layer, 111 denotes an interlayer insulating film, and 112 denotes a metal wiring.

A Pt / Pt / IrO ₂ layer is used as a barrier layer for the floating gate electrode 114.
IrO ₂ / poly-Si or Ir / IrO ₂ / poly-
By using a stacked film of Si, the adhesion between the floating gate electrode 114 and the gate oxide film 102 can be improved,
The fact that the diffusion of lead (Pb) into the gate oxide film can be suppressed and the device performance can be improved has been reported in, for example, 199 of the magazine "Electronic Materials".
It is described on pages 30 to 32 of the August 2004 issue.

[0007]

According to the conventional single-transistor nonvolatile memory described above, the gate structure on the channel region is composed of the control gate electrode 115, the ferroelectric film 108, and the floating gate electrode 114. A multi-layer capacitor structure of a ferroelectric capacitor and a gate oxide film capacitor composed of a floating gate electrode 114, a gate oxide film 102, and a substrate 101, that is, an MFMIS structure. In order for this device to operate as a non-volatile memory, it is necessary to apply a voltage sufficient for the ferroelectric film 108 to invert the polarization. The voltage applied to the ferroelectric film 108 depends on the coupling ratio (C _ox / (C _f + C _ox )) between the capacitance C _f of the ferroelectric capacitor and the capacitance C _ox of the gate oxide film capacitor.

FIG. 4 shows the ratio C _f / C _ox between the capacitance C _f of the ferroelectric capacitor and the capacitance C _ox of the gate oxide film, and the ratio V _f / C of the voltage V _f applied to the ferroelectric capacitor and the circuit voltage V _cc. The relationship between _Vcc is shown. It can be seen that as the C _f / C _ox ratio increases, the voltage applied to the ferroelectric capacitor rapidly decreases. Generally, the capacitance C _f of the ferroelectric capacitor is much larger than the capacitance C _ox of the gate oxide film capacitor, and in order to apply a sufficient voltage to the ferroelectric film 108, the circuit voltage V _cc must be increased. . Alternatively, the coupling ratio can be improved by lowering the relative permittivity of the ferroelectric, but the ferroelectric material has a property that the polarization decreases when the relative permittivity is lowered, which makes the nonvolatile memory operation of the semiconductor device difficult. become.

At present, the reversal voltage of the polarization of the ferroelectric material is P
About 2.5 V is required for ZT, and about 1.7 V is required for a layered ferroelectric film called so-called Y1 (Y1). _Assuming that the circuit voltage _Vcc is 5 V from FIG. 4, the C _f / C _ox ratio is suppressed to 2 or less, that is, 2 or more, in order to obtain at least 1.7 V or more necessary for spontaneous polarization of Y1. There is a need. Further, considering the low power consumption of the device, it is desirable to further reduce the C _f / C _ox ratio. Even while the structure shown in FIG. 2, the strength is the capacity C _f of the ferroelectric capacitor by increasing the thickness of the dielectric film 108 may be reduced, the strength of the dielectric film thickness film with an increase of the fine Processing becomes difficult, and the step of the element becomes large, so that processing of the interlayer insulating film 111 and the wiring 112 becomes difficult.

It is an object of the present invention to provide a single-transistor nonvolatile semiconductor memory device using a ferroelectric capacitor, which can perform nonvolatile memory operation even when the circuit voltage, that is, the power supply voltage is as low as 5 V or less. It is to provide a manufacturing method.

[0011]

A nonvolatile semiconductor memory device according to the present invention includes a ferroelectric capacitor connected to a gate electrode of a field effect transistor, and a spontaneous ferroelectric film forming the ferroelectric capacitor is spontaneously formed. In a nonvolatile semiconductor memory device that stores information using polarization, it is preferable that the capacity of the ferroelectric capacitor does not exceed twice the capacity of a gate insulating film capacitor formed of a gate insulating film of the field effect transistor. It is a feature. here,
The capacitance of the capacitor will be described. In general, the capacitance C of a flat plate capacitor sandwiching an insulator is represented by C = ε × S / d using the electrode area S, the electrode interval d, and the dielectric constant ε of the insulator. To reduce the capacitance C, the dielectric constant ε or the electrode area S may be reduced, or the electrode interval d may be increased. Among the insulators, the dielectric constant ε _f of the ferroelectric is the dielectric constant ε of the oxide film.
It is about 100 times _ox , and it is an empirical practical level that the thickness d _{f of the} ferroelectric is suppressed to about 15 times the thickness d _ox of the gate oxide film. In consideration of these, the capacitance C _f of the ferroelectric capacitor is _calculated as 2 _times the capacitance C _ox of the gate oxide film capacitor.
So as not to exceed twice, i.e., doubling or less, it may be the effective area S _f of the ferroelectric capacitor 30% or less of the area S _ox area or channel area of the gate oxide film capacitor. Therefore, the above problem can be solved by setting the area of the lower electrode or the upper electrode of the ferroelectric capacitor to 30% or less of the area of the channel region of the field effect transistor. However, in order to determine the polarization value of the ferroelectric substance, that is, the amount of charge stored in the ferroelectric capacitor part as a threshold fluctuation amount of the MIS transistor with a margin, the electrode area S of the ferroelectric capacitor is required.
It is desirable that _{F be} 1/20 or more of the plane area of the channel region, that is, 5% or more. Furthermore, when a tantalum pentoxide film having a higher dielectric constant than a silicon oxide film is used for the gate insulating film, lower voltage operation can be achieved.

In the nonvolatile semiconductor memory device, the gate insulating film capacitor includes a first gate electrode serving as a floating gate electrode, a gate insulating film, and a semiconductor substrate. It is preferable to include a second gate electrode which is in contact with one of the gate electrodes and serves as a lower electrode, a ferroelectric film, and an upper electrode, that is, a third gate electrode which serves as a control gate electrode. In this case, the contact area between the ferroelectric film forming the ferroelectric capacitor and the second gate electrode may be smaller than the area of the channel region of the field effect transistor, that is, 5 to 30%.

Further, a third ferroelectric capacitor may be formed.
The contact area between the gate electrode and the ferroelectric film may be smaller than the area of the channel region of the field effect transistor. In that case, it is preferable that the contact area between the third gate electrode and the ferroelectric film is 5 to 30% of the area of the channel region.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of depositing a gate electrode material after at least growing a gate oxide film and a step of depositing a material to be a lower electrode of a ferroelectric capacitor And a step of depositing a ferroelectric film, and a step of depositing an upper electrode material of the ferroelectric capacitor. Forming a ferroelectric capacitor by patterning the laminated film, forming a sidewall protective film on the sidewall of the ferroelectric capacitor, and forming the gate electrode material in a size larger than the electrode area of the ferroelectric capacitor. Patterning step.

In a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of depositing a gate electrode material after at least growing a gate oxide film and a step of depositing a material to be a lower electrode of a ferroelectric capacitor are performed. And a step of depositing a ferroelectric film, and a step of depositing an upper electrode material of a ferroelectric capacitor, wherein the upper electrode material, the ferroelectric film, and the lower electrode Forming a ferroelectric capacitor by patterning the laminated film made of the material so that the side walls have a forward tapered shape; and patterning the gate electrode material with a size larger than the upper electrode area of the ferroelectric capacitor. May be used.

Alternatively, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of depositing a gate electrode material after at least growing a gate oxide film, and a step of depositing a material to be a lower electrode of a ferroelectric capacitor. Forming a ferroelectric film, a lower electrode material, and a gate electrode material in a method of manufacturing a nonvolatile semiconductor memory device including a step of depositing a ferroelectric film and a step of depositing a ferroelectric film. Depositing an interlayer insulating film on the laminated film and opening the interlayer insulating film on the ferroelectric film, and patterning after depositing a material to be an upper electrode of the ferroelectric capacitor on the interlayer insulating film having the opening; And forming an upper electrode by performing the method.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a nonvolatile semiconductor memory device according to the present invention includes a ferroelectric capacitor connected to a gate electrode of a field effect transistor, and a ferroelectric capacitor constituting the ferroelectric capacitor. In a single-transistor nonvolatile semiconductor memory device that stores information by using spontaneous polarization of a body film, for example, as shown in FIG. 1, a gate oxide film capacitor includes a first gate electrode 106 serving as a floating gate electrode and a first gate electrode 106 serving as a floating gate electrode. A gate oxide film 102, a semiconductor substrate 101, and a ferroelectric capacitor, a second gate electrode 107 contacting the first gate electrode 106 and serving as a lower electrode, and a ferroelectric film 10
8 and a third gate electrode 109 serving as an upper electrode, so that the capacitance of this ferroelectric capacitor does not exceed twice the capacitance of the gate oxide film capacitor, that is, the electrode area of the ferroelectric capacitor is This is a non-volatile semiconductor memory having an MFMIS structure configured to be as small as about 5 to 30% of the electrode area of the oxide film capacitor.

With this configuration, it is possible to apply a voltage sufficient for the ferroelectric film to reverse the polarization of the ferroelectric film even when the power supply voltage is 5 V or less,
Non-volatile memory operation becomes possible.

A preferred embodiment of the method for manufacturing a nonvolatile semiconductor memory according to the present invention having the above structure is as follows.
For example, as shown in FIGS. 5 to 14, at least after a gate oxide film 102 is grown, a step of depositing a gate electrode material 106, a step of depositing a material 107 to be a lower electrode of a ferroelectric capacitor, and In a method for manufacturing a nonvolatile semiconductor memory including a step of depositing a dielectric film and a step of depositing an upper electrode material 109 of a ferroelectric capacitor, an upper electrode material 109, a ferroelectric film 108 and a lower electrode material 107 are provided. Forming a ferroelectric capacitor by patterning a laminated film comprising: a step of forming a sidewall protective film 110 on a side wall of the ferroelectric capacitor; and forming a gate electrode having a size larger than the electrode area of the ferroelectric capacitor. And a step of patterning the material 106.

[0020]

Next, more specific embodiments of the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a sectional view of an element structure showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. A method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1 will be described below in the order of steps with reference to FIGS.
1 and 5 to 14, the same components as those of the conventional example shown in FIG. 2 will be described with the same reference numerals.

First, as shown in FIG. 5, a p-type Si substrate 1 is formed.
After the element isolation oxide film 105 is formed on the substrate 01, a gate oxide film 102 having a thickness of 10 nm is grown. Next, as shown in FIG. 6, tungsten 106 as an electrode material to be a first gate electrode, that is, a floating gate electrode,
Pt 107 serving as a gate electrode, that is, a lower electrode of a ferroelectric capacitor, and PZT 108 serving as a ferroelectric film are respectively deposited to a thickness of 100 nm by sputtering. After a heat treatment at 650 ° C. in an oxygen atmosphere, platinum 109 serving as a third gate electrode (ferroelectric capacitor upper electrode), that is, a control gate electrode is formed to a thickness of 100 nm by sputtering.
The resist is deposited and a mask of a ferroelectric capacitor pattern is formed by a resist 116 through a lithography process.

Thereafter, as shown in FIG. 7, the ferroelectric capacitor upper electrode 109, the ferroelectric film 108, and the lower electrode 107 of the ferroelectric capacitor are processed by dry etching using the pattern of the resist 116 as a mask. As shown in FIG. 8, the sidewall protective film 110 of the ferroelectric capacitor is formed.
Ozone (O ₃ ) by plasma enhanced chemical vapor deposition
TEOS (Tetraethyloxysilane or Tetraethylorthosi
Licate) film is deposited to a thickness of 100 nm and dry-etched to a thickness of 100 nm by an etch-back method to leave a sidewall protection film 110 on the sidewall of the capacitor. Note that the remaining sidewall protective film 110
Can be adjusted to a desired width by changing the deposited film thickness during the growth of the O ₃ -TEOS film.

Subsequently, as shown in FIG. 9, tungsten 106 serving as a floating gate electrode is also processed by dry etching. Then, as shown in FIG. 10, after phosphorus is ion-implanted, the n-type drain diffusion layer 103 and the source diffusion layer 104 are subjected to a heat treatment at 700 ° C.
To form

Thereafter, as shown in FIG.
A titanium oxide film of 100 nm was formed by sputtering as 11
After depositing and covering the surface, through a lithography process, a resist 117 having a pattern for making contact on the drain diffusion layer 103, the source diffusion layer 104 and the upper electrode 109 of the ferroelectric capacitor is formed. Based on the pattern of the resist 117, contact holes are formed by dry etching on the drain diffusion layer 103, the source diffusion layer 104, and the ferroelectric capacitor upper electrode 109 as shown in FIG.

Thereafter, as shown in FIG.
14 is deposited by sputtering to a thickness of 150 nm, and a wiring pattern mask is formed by a resist 118 through a lithography process as shown in FIG. By dry-etching the tungsten of the metal film 112 using the resist 118 as a mask to form wiring, the element structure shown in FIG. 1 is obtained.

As described above, in this embodiment, after the ferroelectric capacitor portion is formed, the side wall protective film 1 described in the step of FIG.
By adjusting the width of 10, strong and effective area S _f of the dielectric capacitor in less than 30% of the area S _ox of the channel region, i.e. Osaere so as not to exceed 30%. Therefore, the size is larger than the second gate electrode 107,
By forming the first gate electrode 106, the capacitance C _f of the ferroelectric capacitor can be reduced. However, the polarization value of the ferroelectric, i.e. strongly accumulated charge amount of the ferroelectric capacitor section to determine with ease as the threshold variation of the MIS transistor, the electrode area S _F of the ferroelectric capacitor of the channel region Rights It is desirable that the area be 1/20 or more, that is, 5% or more. From this, the capacity ratio C
_If the lower limit of _f / C _ox is estimated, about 1/3 is the lower limit.

Here, the method for manufacturing the element structure of the memory cell which is the most important in manufacturing the nonvolatile semiconductor memory device according to the present invention has been described. The non-volatile semiconductor memory device is completed by adding the interlayer insulating film, forming a through hole, and wiring steps after the above manufacturing steps.

In the above-described embodiment, the sidewall protective film 110 of the ferroelectric capacitor is deposited after the processing of the capacitor lower electrode 107. However, as shown in FIG. etched back by depositing a sidewall passivation layer 110 after etching the dielectric film 108, then capacitor C _f and the gate oxide film of the ferroelectric capacitor in the device structure to produce a lower electrode 107 and the gate electrode 106 is dry-etched it is possible to reduce the ratio of the capacitance C _ox.

Although not shown in the figure, after processing the capacitor upper electrode 109, a sidewall protective film 110 is deposited and etched back, and then the ferroelectric film 108, the capacitor lower electrode 107, and the gate electrode 106 are successively formed. A similar effect can be obtained with an element structure manufactured by processing.

In this embodiment, the source diffusion layer 104 and the drain diffusion layer 103 are formed after the gate electrode is patterned. However, after forming the diffusion layers 103 and 104, the material of the gate electrode 106 and the lower part of the capacitor are formed. Electrode 10
7, the material of the ferroelectric film 108 and the material of the upper electrode 109 may be deposited, and a gate electrode may be disposed between the source diffusion layer 104 and the drain diffusion layer 103 and patterned by a combination of lithography steps. In that case, the stability of the element against heat treatment is improved.

Further, in this embodiment, lead zirconate titanate (PZT) is used as the ferroelectric film 108,
A layered ferroelectric film such as 1 may be used. Further, as a gate electrode material, iridium (Ir), ruthenium (Ru), or an oxide thereof and poly-Si may be stacked. Also, the sidewall protection film 110 of the capacitor
Instead of using a titanium oxide film alone, coverage can be improved by using a thin titanium oxide film overlaid with an O ₃ -TEOS film by a chemical vapor deposition method. In this embodiment, the p-type Si substrate 101 is used. However, when an n-type Si substrate is used or an element is formed in an n-type well region, the drain region diffusion layer 103 and the source region diffusion layer 104 are formed. The doping may be performed using a p-type impurity such as boron.

<Embodiment 2> FIG. 16 is a sectional view of an element structure showing another embodiment of the nonvolatile semiconductor memory device according to the present invention. The element structure of the nonvolatile semiconductor memory device according to the present embodiment is manufactured as follows. In FIG. 16, the same components as those of the first embodiment shown in FIG. 1 will be described with the same reference numerals.

An element isolation oxide film 1 is formed on a p-type Si substrate 101.
After the formation of the gate oxide film 10, the gate oxide film 10 having a thickness of 10 nm is formed.
Grow 2. Next, a tungsten 106 serving as a first gate electrode, ie, a floating gate electrode, a platinum 107 serving as a second gate electrode, ie, a lower electrode of a ferroelectric capacitor, and a PZT 108 serving as a ferroelectric film are deposited by 100 nm by sputtering. . After heat treatment at 650 ° C. in an oxygen atmosphere, a third gate electrode, that is, platinum 109 to be an upper electrode of a ferroelectric capacitor is deposited to a thickness of 100 nm by a sputtering method, and tungsten is further deposited thereon by a 250 nm sputtering method.

Subsequently, a mask of a ferroelectric capacitor pattern is formed by a resist through a lithography process, and tungsten on the platinum 109 is etched using the resist pattern as a mask. Thereafter, using the tungsten as a mask, the upper electrode 109 of the ferroelectric capacitor, the ferroelectric film 108, and the lower electrode 107 of the ferroelectric capacitor are used.
Is tapered by a dry etching method using reactive ion etching (RIE) so as to have a wider shape, that is, a forward tapered shape.

Subsequently, the tungsten 106 serving as a floating gate electrode is also processed by dry etching. At this time, the tungsten on the upper electrode 109 of the ferroelectric capacitor is simultaneously etched and disappears. Then, an n-type drain diffusion layer 103 and a source diffusion layer 104 are formed through ion implantation and a heat treatment process.

After that, an O ₃ -TEOS film is deposited as an interlayer insulating film 111 by a plasma enhanced chemical vapor deposition method to a thickness of 100 nm.
3 and a resist mask having a pattern to make contact with each other on the source diffusion layer 104 and on the upper electrode 109 of the ferroelectric capacitor. Based on the resist pattern, the drain diffusion layer 103 and the source diffusion layer 104
Contact holes are formed on the upper electrode and on the ferroelectric capacitor upper electrode 109 by dry etching.

Thereafter, 150 nm of tungsten of the metal film 112 is deposited by a sputtering method, and a wiring pattern mask is formed by a resist through a lithography process.
By dry-etching the tungsten of the metal film 112 using this resist mask to form wiring, the element structure shown in FIG. 16 is obtained.

[0039] The thus cross-sectional shape of the ferroelectric capacitor unit performs dry etching by RIE so that the forward tapered shape, and further by adjusting the taper angle, the ferroelectric capacitor effective area S _f What is necessary is just to suppress the area not _exceeding 30% of the area _Sox of the channel region. The taper angle of the ferroelectric capacitor may be adjusted by adjusting the acceleration energy of ion etching during dry etching by RIE.

In this embodiment shown in FIG. 16, only the ferroelectric capacitor portion (upper electrode 107, ferroelectric film 108, lower electrode 109) is tapered to form the gate electrode 106.
Is vertically processed, but the same effect can be obtained by an element manufactured by tapering including the gate electrode 106.
A similar effect can also be obtained in an element manufactured by tapering the upper electrode 109 and the ferroelectric film 108 of the ferroelectric capacitor and vertically processing the lower electrode 107 and the gate electrode 106.

Further, in this embodiment, lead zirconate titanate (PZT) is used for the ferroelectric film, but a layered ferroelectric such as Y1 may be used. As a gate electrode material, Ir or Ru or an oxide film thereof and poly-S
i may be stacked and used. Further, as the sidewall protective film of the capacitor, a titanium oxide film formed by a sputtering method may be used instead of the O ₃ -TEOS film. Further, in this embodiment, a p-type Si substrate is used. However, when an n-type Si substrate is used or an element is formed in an n-type well region, the drain region diffusion layer 103 and the source region diffusion layer 104 are made of boron or the like. Doping using the p-type impurity.

<Embodiment 3> FIG. 17 is a sectional view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention. The element structure of the nonvolatile semiconductor memory device of this embodiment is as follows.
It is manufactured as follows. In FIG. 17, the same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals and described.

First, after forming an element isolation oxide film 105 on a p-type Si substrate 101, a gate oxide film 102 having a thickness of 10 nm is grown. On this gate oxide film 102,
Tungsten 106 serving as a first gate electrode, that is, a floating gate electrode, and platinum 107 serving as a second gate electrode, that is, a platinum electrode that serves as a lower electrode of a ferroelectric capacitor, are each deposited to a thickness of 100 nm by sputtering. continue,
A pattern of a floating gate electrode is formed by a resist through a lithography process, and the lower electrode 107 and the tungsten 106 of the ferroelectric capacitor are processed by dry etching using the resist pattern as a mask.

Next, through ion implantation and heat treatment, n
A drain diffusion layer 103 and a source diffusion layer 104 are formed. Thereafter, a TiO film is deposited as the interlayer insulating film 111 by 100 nm by a sputtering method, and an opening is formed on the lower electrode 107 of the ferroelectric capacitor through a lithography process and a dry etching process. After that, PZT108 is deposited as a ferroelectric film by a sputtering method at 100 nm, and a heat treatment at 650 ° C. is performed in an oxygen atmosphere, and then a third gate electrode, ie, platinum 109 of a ferroelectric capacitor upper electrode is deposited to a thickness of 50 nm by a sputtering method. .

Again, a resist mask having a pattern also serving as a wiring with the upper electrode 109 of the ferroelectric capacitor is formed through a lithography process, and dry etching is performed using this resist pattern as a mask. Then, a resist mask having a pattern for making contact with each of the drain diffusion layer 103 and the source diffusion layer 104 and on the upper electrode of the ferroelectric capacitor is formed, and using the resist pattern as a mask, the drain diffusion layer 103 and the source diffusion layer 104 are formed. Up,
A contact hole is formed on the upper electrode of the ferroelectric capacitor by dry etching.

Thereafter, tungsten of the metal film 112 is deposited to a thickness of 150 nm by sputtering, and wiring is formed by dry-etching the tungsten of the metal film 112 using the resist of the wiring pattern formed in the lithography process as a mask. The device structure shown is obtained.

[0047] Also in the device structure of this embodiment obtained in this way, to suppress the effective area S _f of the ferroelectric capacitor 30% or less of the area S _ox of the channel region, i.e. so as not to exceed 30% Therefore, even when the power supply voltage is as low as 5 V or less, the nonvolatile memory operation is possible.

In this embodiment, the capacitor lower electrode 107
After processing platinum of platinum and tungsten of the gate electrode 106, an interlayer insulating film 111 is deposited. As shown in FIG. 18, the gate electrode 106 and the capacitor lower electrode 107 are deposited as shown in FIG.
A similar effect can be obtained by forming an upper electrode 109 by depositing an interlayer insulating film 111, opening a contact hole, and then forming a ferroelectric film 108 and processing these laminated films.

In this embodiment, the upper electrode 109 also serves as the wiring, but the upper electrode is processed as a control gate electrode, and it is possible to form a wiring having a lower wiring resistance by separately forming the wiring. it can.

<Embodiment 4> Although the cross section of the element structure which is the basis of the nonvolatile semiconductor memory device according to the present invention and the manufacturing method thereof have been described in Embodiments 1 to 3, in the present embodiment, these semiconductors are used. The arrangement of elements suitable for forming a nonvolatile semiconductor memory device by integrating elements will be described with reference to plan views.

FIG. 19 is a plan view of a main part showing an embodiment of an element arrangement in the case where the basic semiconductor elements of the nonvolatile semiconductor memory device according to the present invention are integrated. Element isolation region 20
Floating gate electrode 206 is arranged so as to straddle the active region sandwiched by 5, and control gate electrode 209 is arranged at the center of floating gate electrode 206. A bit line contact 214 is arranged in a diffusion layer region between a pair of transistors, and a bit line interconnection 213 is arranged so as to cross a word line interconnection 212 in which control gate electrodes 209 are combined. The diffusion layer that does not open the bit line contact 214 is connected to a common ground potential. By arranging in this way and using a diffusion layer for connection between elements, the degree of integration can be increased.

The nonvolatile semiconductor memory device according to the present invention may be arranged as shown in the plan view of FIG. The degree of integration can be increased by forming the element isolation by the planar isolation method and employing the diffusion layer wiring. Bit lines are connected to the diffusion layer bit line 2 with respect to the floating gate electrode 206, the control gate electrode 209, and the word line wiring 212 connecting the control gate electrode.
16. By using the other diffusion layer as the reference potential line 215, the element structure can be simplified and the degree of integration can be improved. In this case, the transistor is connected to the diffusion layer bit line 216.
Is connected in parallel.

Further, the nonvolatile semiconductor memory device according to the present invention may be arranged as shown in the plan view of FIG. This arrangement also uses a diffusion layer as a bit line. Floating gate electrode 206 and control gate electrode 2
09 and the word line wiring 212 connecting the control gate electrode, the transistor is connected to the diffusion layer bit line 2.
Connect at 16. In this case, the transistors are connected in series by the diffusion layer bit line 216. It is sufficient to provide one contact 214 for at least 128 bits for each diffusion layer bit line 216 connected in series.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. Of course.

[0055]

As described above, according to the present invention, the MFM
In a non-volatile semiconductor memory device having an IS structure, after patterning a ferroelectric capacitor, a sidewall protective film is formed and a floating gate electrode is processed in an area including the sidewall protective film, or the cross section of the ferroelectric capacitor is tapered forward. By processing into a shape, the contact area between the ferroelectric film and the upper electrode or the contact area between the ferroelectric film and the lower electrode can be reduced, so that the capacitance of the ferroelectric capacitor is reduced by the gate insulating film capacitance. It can be suppressed to twice or less. Thus, the circuit voltage, that is, the power supply voltage is 5 V
Even if it is lowered below, the nonvolatile memory operation can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a sectional view showing a conventional example of a nonvolatile semiconductor memory device.

FIG. 3 is an equivalent circuit diagram of the nonvolatile semiconductor memory device shown in FIG. 2;

FIG. 4 is a characteristic diagram showing a relationship between a ratio of a capacitance of a ferroelectric capacitor and a gate oxide film capacitance in an MFMIS structure and a ratio of a voltage applied to a ferroelectric capacitor unit.

FIG. 5 is a sectional structural view in the course of manufacturing the nonvolatile semiconductor memory device having the structure shown in FIG. 1;

FIG. 6 is a sectional structural view showing a manufacturing step subsequent to FIG. 5;

FIG. 7 is a sectional structural view showing a manufacturing step subsequent to FIG. 6;

FIG. 8 is a sectional structural view showing a manufacturing step subsequent to FIG. 7;

FIG. 9 is a sectional structural view showing a manufacturing step subsequent to FIG. 8;

FIG. 10 is a sectional structural view showing a manufacturing step subsequent to FIG. 9;

FIG. 11 is a sectional structural view showing the next manufacturing step of FIG. 10;

FIG. 12 is a sectional structural view showing a manufacturing step subsequent to FIG. 11;

FIG. 13 is a sectional structural view showing a manufacturing step subsequent to FIG. 12;

FIG. 14 is a sectional structural view showing a manufacturing step subsequent to FIG. 13;

FIG. 15 is a sectional view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 16 is a sectional view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 17 is a sectional view showing still another embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 18 is a sectional view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 19 is a plan view showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 20 is a plan view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 21 is a plan view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

[Explanation of symbols]

Reference Signs List 101: Si substrate, 102: Gate insulating film, 103: Drain diffusion layer, 104: Source diffusion layer, 105: Element isolation oxide film, 106: First gate electrode (floating gate electrode), 107: Second gate electrode (Lower electrode of ferroelectric capacitor), 108: ferroelectric film, 109: third gate electrode (upper electrode of ferroelectric capacitor), 110: sidewall protective film of ferroelectric capacitor, 111: interlayer insulating film 112, a metal wiring film, 114, a floating gate electrode, 115, a control gate electrode, 116, 117, 118, a resist, 205, an element isolation region, 206, a floating gate electrode, 209, a control gate electrode, 212, a word line wiring , 213: bit line wiring, 214: bit line contact, 215: expansion Layer reference potential line, 216 ... diffusion layer bit lines.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/108 21/8242 (72) Inventor Hiroshi Miki 1-280, Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory (72) Inventor Kenichi Shoji 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory

Claims (9)

[Claims] 1. A nonvolatile semiconductor memory device comprising a ferroelectric capacitor connected to a gate electrode of a field effect transistor and storing information by utilizing spontaneous polarization of a ferroelectric film forming the ferroelectric capacitor. A nonvolatile semiconductor memory device, wherein the capacitance of the ferroelectric capacitor does not exceed twice the capacitance of a gate insulating film capacitor formed of a gate insulating film of the field effect transistor. 2. The gate insulating film capacitor includes a first gate electrode serving as a floating gate electrode, a gate insulating film, and a semiconductor substrate, and the ferroelectric capacitor includes a first gate electrode. 2. The non-volatile semiconductor memory device according to claim 1, comprising a second gate electrode which is in contact with the electrode and serves as a lower electrode, a ferroelectric film, and a third gate electrode which serves as an upper electrode. 3. The nonvolatile semiconductor memory according to claim 2, wherein a contact area between a ferroelectric film constituting said ferroelectric capacitor and a second gate electrode is smaller than an area of a channel region of said field effect transistor. apparatus. 4. The non-volatile semiconductor memory device according to claim 3, wherein a contact area between said ferroelectric film and a second gate electrode is 5 to 30% of an area of said channel region. 5. The nonvolatile semiconductor memory according to claim 2, wherein a contact area between the third gate electrode and the ferroelectric film constituting the ferroelectric capacitor is smaller than an area of a channel region of the field effect transistor. apparatus. 6. The nonvolatile semiconductor memory device according to claim 5, wherein a contact area between said third gate electrode and a ferroelectric film is 5 to 30% of an area of said channel region. 7. After growing at least a gate oxide film,
A step of depositing a gate electrode material, a step of depositing a material to be a lower electrode of the ferroelectric capacitor, a step of depositing a ferroelectric film, and a step of depositing an upper electrode material of the ferroelectric capacitor A method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of: patterning a laminated film including the upper electrode material, the ferroelectric film, and the lower electrode material to form a ferroelectric capacitor; A method for manufacturing a nonvolatile semiconductor memory device, comprising: a step of forming a side wall protective film; and a step of patterning the gate electrode material with a size larger than an electrode area of a ferroelectric capacitor. 8. After growing at least a gate oxide film,
A step of depositing a gate electrode material, a step of depositing a material to be a lower electrode of the ferroelectric capacitor, a step of depositing a ferroelectric film, and a step of depositing an upper electrode material of the ferroelectric capacitor Forming a ferroelectric capacitor by patterning a stacked film made of the upper electrode material, the ferroelectric film, and the lower electrode material so that a side wall has a forward tapered shape; Patterning the gate electrode material with a size larger than the area of the upper electrode of the ferroelectric capacitor. 9. After growing at least a gate oxide film,
A method for manufacturing a nonvolatile semiconductor memory device, comprising: a step of depositing a gate electrode material; a step of depositing a material to be a lower electrode of a ferroelectric capacitor; and a step of depositing a ferroelectric film. Patterning a laminated film made of the lower electrode material and the gate electrode material; depositing an interlayer insulating film on the patterned laminated film and opening the interlayer insulating film on the ferroelectric film; Depositing a material for an upper electrode of a ferroelectric capacitor on an interlayer insulating film having a pattern, and then patterning the material to form an upper electrode, the method comprising the steps of: