JPH09213899A - Non-volatile memory device provided with ferroelectric film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory (FRAM) which is formed from a ferroelectric film that is new in composition, free from Pb and Bi, and enhanced in reliability and degree of integration. SOLUTION: A ferroelectric film 12 is formed on a ferroelectric device of MFM(metal-ferroelectric-metal) structure or a field effect ferroelectric device of MFS(metal-ferroelectric-silicon) structure or MFIS(metal-ferroelectric-insulator- silicon) structure on a semiconductor substrate 1. The ferroelectric film 12 (F) is formed of solid solution of M12 (M2X, Ta1- X)2 O7 structure, wherein M1 is at least one element selected from Sr, Ca, La, and Nd, M2 denotes at least one element out of Nb and Ti, and X is so set as to satisfy a formula, 0.1<=x<=0.5. When X is set smaller than 0.1, the solid solution is not able to have a Curie point higher than a room temperature and large in crystal anisotropy, and when X is set larger than 0.5, the solid solution can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device using a ferroelectric film, and more particularly to a material for the ferroelectric film.

[0002]

2. Description of the Related Art In a ferroelectric film, electric polarization once generated when an electric field is applied remains even when the electric field is not applied, and an electric field having a certain strength or more in a direction opposite to the electric field. Has the characteristic that the direction of polarization is inverted when is applied. Focusing on the polarization characteristics that the direction of polarization of this ferroelectric film is reversed, a technology has been developed to realize a nonvolatile ferroelectric memory cell by using a ferroelectric material for the dielectric film of the information storage capacitor of the memory cell. Has been done. The non-volatile memory that utilizes the ferroelectricity of the ferroelectric film is a general-purpose non-volatile memory with low power consumption, as well as a contactless card (RFID: Radio).
o Frequency Identification) and other applications are expected. This non-volatile memory includes MFM (metal-
A type in which a ferroelectric-metal) structure is formed on a MOS transistor has been put into practical use. Further, as the field-effect element that becomes the ultimate nondestructive memory, an MFS (metal-ferroelectric-silicon) structure, an MFMIS (metal-ferroelectric-metal-insulator-silicon) structure, or an MFIS (metal-metal) structure is used.
A field effect ferroelectric element having a ferroelectric-insulator-silicon structure has been proposed. In these elements, a conductive oxide may be used instead of the metal M.

In these ferroelectric films, PZT (Pb (Zr, Ti) O ₃ ) and PLZT are used as the ferroelectric substance.
((Pb, La) (Zr , Ti) 0 3), PLT ((P
_{b, La) Ti0 3) SrBi} 2 Ta 2 0 layered compound containing a ferroelectric or Bi containing Pb, such as
₉ is known.

[0004]

However, a major problem in manufacturing these ferroelectrics is the diffusion of Pb and Bi into the electrodes and silicon, and the evaporation in the heat step. Since these elements have low melting points and high vapor pressures, it is very difficult to control the composition ratio with other elemental components in the film forming process such as sputtering or CVD. Evaporating element is M
Not only does it contaminate other layers such as the OS structure, but it also becomes a mist and causes particles in the chamber and heat treatment furnace, which significantly reduces the mass productivity of the device. Further, since these elements diffuse into the electrode or other layers during heat treatment, which causes memory malfunction and increase in contact resistance or wiring resistance, isolation with a thick passivation film is necessary, and high integration of elements is required. It is a big obstacle in measuring. Furthermore, not only manufacturing problems but also composition deviation from the stoichiometric ratio causes lattice defects and oxygen vacancies, which results in a large decrease in fatigue characteristics of the ferroelectric film. The present invention has been made under such circumstances, and provides a highly integrated non-volatile memory with high reliability by a ferroelectric film containing no Pb or Bi.

[0005]

The present invention is directed to a ferroelectric element having an MFM structure, an MFS structure, an MFMIS structure, or an M structure.
The FIS structure field effect ferroelectric element is characterized in that the ferroelectric film F has an M1 ₂ (M2 _x , Ta _1-x ) ₂ O ₇ structure. However, M1 is Sr, Ca, L
at least one element of a and Nd, M2 is Nb,
At least one element of Ti, 0.1 ≦ x ≦
0.5. The ferroelectric film of the present invention comprises a solid solution of M1 ₂ M2 ₂ O ₇ and M1 ₂ Ta ₂ O ₇ . These two systems are a ferroelectric substance (Curie point (Tc) = 1342 ° C.) and a paraelectric substance (Curie point (Tc) = − 107 ° C.) at room temperature, and as shown in FIGS. 6 and 7, Each has a structure in which oxygen octahedra are sandwiched between low-density layers. The difference between the two is whether or not the oxygen octahedron between layers has a twisted structure. In the dielectric structure below the Curie point, this twist contributes to the development of ferroelectricity.

Of these, M1 ₂ M2 having ferroelectricity at room temperature
_{The 2} O ₇ structure material has the following two problems as a thin film material for a ferroelectric memory. One is that the Curie point is 1000 ° C or higher, which is much higher than room temperature, and a large voltage is required for polarization at room temperature. This is because a large remanent polarization cannot be obtained because it tends to be oriented on the axis of difficult polarization. In order to solve these two problems, the inventor found that in this solid solution system, a ferroelectric film capable of obtaining a large remanent polarization can be obtained in a practical low voltage region of 5 V or less at room temperature. . This is because the solid solution of the M1 ₂ Ta ₂ O ₇ structure having a low Curie point causes the Curie point to be 90.
0 ℃ can be below, the polarization that can be easily temperature range, also, M1 ₂ M2 crystalline anisotropy as compared to the ₂ O ₇ structure is very small M1 ₂ Ta ₂ O ₇ structure This is because it is possible to form a non-oriented film or a film containing many axes of easy polarization by solid solution. The solid solution forming this ferroelectric film has a composition of M1 ₂ (M2 _x , Ta _1-x ) ₂ O _7, but when x is smaller than 0.1, it is Curie in a temperature range higher than room temperature. It cannot have dots and has large crystal anisotropy. Further, if x is larger than 0.5, no solid solution is formed.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the ferroelectric film, the electric polarization once generated when an electric field is applied remains even when the electric field is no longer applied, and when an electric field of a certain strength or more is applied in the direction opposite to the electric field. It has the property of reversing the direction of polarization. The present invention pays attention to the polarization characteristic in which the direction of polarization of this dielectric is inverted, and realizes a nonvolatile ferroelectric memory cell by using a ferroelectric for an insulating film of a capacitor for storing information of the memory cell. The ferroelectric film is
It is composed of a solid solution of M1 ₂ M2 ₂ O ₇ and M1 ₂ Ta ₂ O _7, and in particular, M1 ₂ M2 ₂ O ₇ contains 10 to 10% of the solid solution.
It is characterized by occupying 50 mol%. M1
Is at least one element of Sr, Ca, La, and Nd, and M2 is at least one element of Nb and Ti. FIG. 5 shows an equivalent circuit of a ferroelectric memory cell having a one-transistor / one-capacitor configuration.
It has the same circuit connection as the equivalent circuit of the AM cell.

Here, C is an information recording capacitor 10 using a ferroelectric material having a perovskite structure as an inter-electrode insulating film, and Q is a MOS transistor 20 for charge transfer, WL connected in series to this capacitor. Is this MOS
The word line connected to the gate of the transistor, BL
Is a bit line connected to one of the source / drain regions of the MOS transistor, PL is a plate line connected to one end (plate) of the capacitor, and VPL is a plate line voltage. The method of using a ferroelectric film for a semiconductor device is (1) M (metal) -F (ferroelectric) -S (semiconductor) structure or MFI using a ferroelectric as an insulating film.
Field effect transistor of S, MFMIS structure (MFS
There are two methods, one is for use as a FET) and the other is (2) when a ferroelectric is used as a storage capacitor (excluding the case where the ferroelectric is used as a paraelectric). The present invention is based on the ferroelectric memory (FRAM; Fe
rroelectric Random Access Memory), that is, a non-volatile memory device using a ferroelectric film. FRA
Several schemes have been proposed for M. In a memory having a relatively small capacity, a 2-transistor 2-capacitor (2T
/ 2C) cell may be used, but in order to bring the chip cost close to that of a DRAM, an operation method using one transistor / one ferroelectric capacitor (1T / lC) cell is advantageous.
FIG. 1 is a sectional structure of a memory cell.

In a non-volatile memory, after forming a capacitor insulating film, it is necessary to perform fine processing as a capacitor of each memory cell. Wet etching, ion milling, ion beam etching, laser etching, plasma etching, ECR
Etching and the like are known. Particularly in plasma etching, the reactive species activated by obtaining high energy by plasma discharge form a reaction product having a high vapor pressure and the etching proceeds, so that fine processing can be performed even using a noble metal electrode. When applied to the silicon process, the characteristics required as the electrode material used for the ferroelectric film are:
(1) It has excellent oxidation resistance or is a conductive oxide. (2) Good compatibility with the ferroelectric film. (3) There is no mutual diffusion with respect to silicon and the ferroelectric film. P
t or Ir is an electrode having excellent oxidation resistance, and has good compatibility with the ferroelectric film. However, there are problems with adhesion.
For this reason, Ti, T is formed at the interface between Pt or Ir and the silicon substrate.
It is desirable to form and use an intervening layer of a, IrO ₂ or the like. Nitride TiN, ZrN, etc. can also be used. For example, in the MFM structure, the capacitor structure is C in order from the bottom.
MOS / BPSG layer / lower electrode (titanium or titanium nitride / platinum) / ferroelectric film / upper electrode (platinum / titanium nitride / aluminum).

The non-volatility of the "data" of the non-volatile memory of the present invention utilizes the polarization characteristic of the ferroelectric film having hysteresis, and corresponds to two remanent polarizations of positive and negative even in the no electric field (E = 0) state. Because it can store value information. DR
It also has a feature that a refresh cycle is not required like AM. The “high speed of data writing / erasing” of the nonvolatile memory of the present invention is 10 nsec even if the polarization reversal speed (switching speed) of the ferroelectric substance by applying an external voltage is low.
Because it is faster than the following. This is due to the high electric field (10 ⁷
This is more advantageous than an EEPROM that performs a write / erase operation (operation time on the order of μsec) by injecting / drawing out hot carriers from the insulating film under V / cm order).
When forming a ferroelectric film, be careful that the composition ratio of the single-phase film does not deviate from the intended composition ratio, that the crystallinity is good and that the characteristics are equal to or better than those of the bulk body, and that the film thickness is easy to control. It is necessary. As a typical film forming method of the ferroelectric film, the sol-gel or MOD method shown in FIG.
There are a sputtering method and a MOCVD method, and their outline will be described. The sol-gel method or the MOD method is a method in which a solution using an organic metal compound or the like as a source material is applied to a substrate by dipping or spin coating, and the solution is thermally decomposed. This enables film formation even in the air, and makes it easy to increase the area of the film.

The sputtering method is a method in which an ionized gas (Ar gas or the like) in a glow discharge is made to collide with a target made of a material to be a thin film, and the knocked-out particles are deposited on the substrate. It is possible to form a film such as a difficult high melting point material. For this film formation method, DC sputtering,
There are radio frequency (RF) sputtering, magnetron sputtering, ion beam sputtering, reactive sputtering, laser ablation, and the like. A sintered body or powder is used as a target, and sputtering is performed in an atmosphere of argon and oxygen. When a magnet is placed in the vicinity of the target, sputtered ions are confined to the magnetic field and sputter can be performed with a low gas pressure ( ^{-10 -4} Torr), which increases the film growth rate several times. The fine structure and characteristics of the ferroelectric film depend on the sputtering conditions (sputtering voltage, gas composition and gas pressure, film forming rate, substrate material, substrate temperature, etc.). The basis of CVD is to introduce a compound of an element to be formed into a thin film into a high-temperature furnace and deposit it on the surface of the substrate to form a film, thereby forming an equilibrium state on the surface of the substrate. Since the film is formed, a more uniform crystal film may be obtained. MOC
The VD has a ferroelectric film formed from an organic metal such as acetylacetonate or alkoxide as a raw material.

Next, for example, a 2-transistor / 2-capacitor type FRAM cell of the present invention and its operating principle will be described.
10 and FIG. 11 show a case where two memory cells of FIG. 4 are used.
In order to explain the principle of the write operation and the read operation of the ferroelectric memory cell having the transistor and the two-capacitor structure, the applied electric field and electric polarization state of the ferroelectric capacitor are shown. This ferroelectric memory cell has a first transistor Q whose gate is connected to a word line WL.
The first and second transistors Q1 and C2 are composed of a first capacitor C1 and a second capacitor C2 whose plate lines PL are connected to the plates, respectively, and the first and second transistors Q1 and C1 are connected in series. , Second
The transistor Q2 and the second capacitor C2 are connected in series. Then, one end of each of the first transistor Q1 and the second transistor Q2 is connected to the first bit line BL.
It is connected to the first and second bit lines BL2. The word line WL and the plate line PL are provided in parallel, the word line WL is supplied with a word line signal from a row decoder (not shown) for the word line, and the plate line PL is supplied from a plate decoder (not shown). The plate line voltage VPL is supplied. In this case, not all the plate lines PL are connected in common, but the plate lines PL like DRAMs.
This is different from the case where a predetermined potential (for example, Vss / 2) is applied to.

A sense amplifier (not shown) for bit line potential sense amplification, a write circuit (not shown) and a precharge circuit (not shown) are connected to the two bit lines BL1 and BL2. ing. When writing or reading data to or from the ferroelectric memory cell, the potential of the plate line PL of the selected memory cell is set to 0, for example.
The direction of dielectric polarization is controlled by changing the voltage from V to 5V to 0V. That is, in the write operation, in the initial state, the plate line PL is set to the ground potential Vss (0V), and the two bit line bit lines BL1 and BL2 are precharged to 0V respectively. First, the two bit lines B
One of L1 and BL2 (for example, the second bit line BL
2) is set to 5 V, for example, and 5 V is applied to the word line WL to turn on the transistors Q1 and Q2, a potential difference is generated between both ends of the second capacitor C2, for example, downward polarization in the figure. Occurs, but the polarization of the first capacitor C1 does not occur (FIG. 10A). Next, when the plate line PL is set to 5V, the first capacitor C1
, A potential difference is generated between both ends of the second capacitor C2 and an upward polarization occurs in the figure, but the polarization of the second capacitor C2 is not inverted. As a result, the two capacitors C1 and C2 are in a state where polarizations in opposite directions are generated as shown in the figure, and this state corresponds to the write state of data "1" or "0" (FIG. 10B). ).

Next, the plate line PL is set to 0V, the word line WL is set to 0V, and the two transistors Q1 and Q2 are set.
Is turned off (FIG. 10 (c)). In the read operation, in the initial state, the plate line PL is set to 0V and the two bit lines BL1 and BL2 are precharged to 0V. In this state, it is assumed that data is written in the two capacitors C1 and C2, for example, as shown in FIG. 11A, data in which polarization directions opposite to each other are generated (FIG. 11A). . Then, first, as shown in FIG. 11B, when the plate line PL is set to 5V and 5V is applied to the word line WL to turn on the two transistors Q1 and Q2, the second capacitor is turned on. A potential difference is generated between both ends of C2 and its polarization direction is inverted, but the polarization direction of the first capacitor C1 is not inverted. The read potentials from the two capacitors C1 and C2 are sense-amplified by a sense amplifier, and the two bit lines BL1 and BL2 are correspondingly set to 0V and 5V by the output of the sense amplifier, based on the output of the sense amplifier. Then, "1" and "0" of the read data are identified (Fig. 1
1 (b)). Next, when the plate line PL is set to 0V, a potential difference is generated between both ends of the second capacitor C2 and its polarization direction is inverted, and the polarization direction of the first capacitor C1 is not inverted, and the initial state is restored. Return (FIG. 11 (c)).

Next, a nonvolatile memory device having a ferroelectric film according to the first embodiment will be described with reference to FIG. The figure shows
FIG. 4 is a cross-sectional view of a semiconductor substrate on which a MOS transistor and a capacitor having an MFM structure are formed. The main surface of the p-type silicon semiconductor substrate 1 is surface-treated to form a field oxide film 2 in the element isolation region. Then, an insulating film 3 made of a silicon oxide film is formed on the semiconductor substrate 1 by heat treatment or the like, and a MOS transistor 20 having the insulating film 3 as a gate oxide film is formed. The MOS transistor 20 includes an n ⁺ source / drain region 4, a gate oxide film 3 formed between the source / drain regions, and a gate 22 such as polysilicon formed on the gate oxide film 3. There is. The gate 22 is an interlayer insulating film 5 such as a silicon oxide film.
Coated with Next, the MOS transistor 20
A process of forming the MFM structure capacitor 10 and the wiring 30 thereof will be described. First, a Ti / Pt film to be the lower electrode 11 is formed on the interlayer insulating film 5 by continuous sputtering. Next, Sr ₂ (Nd _0.4 ,
The ferroelectric film 12 made of Ta _0.6 ) ₂ O ₇ film was formed into Ti / P.
A film is formed on the t film by the sol-gel method and annealed.
After annealing, the Pt film that will become the upper electrode 13 is replaced with the ferroelectric film 1.
Sputter on top of 2.

Next, the laminated Ti / Pt film, the ferroelectric film and the Pt film are patterned by RIE to form an MF including a lower electrode 11, a ferroelectric film 12 and an upper electrode 13.
The M-structure capacitor 10 is formed. This capacitor 1
An insulating film 15 such as a silicon oxide film is deposited on the interlayer insulating film 5 so as to cover 0. The insulating film 15 is etched to form the source / drain regions 4 of the MOS transistor 20.
On the other hand, contact holes are formed in the upper electrode 13 and the lower electrode 11, and then the internal wiring 31 is formed on the insulating film 15. The internal wiring 31 is patterned to form an internal wiring 31 (A) that electrically connects one of the source / drain regions 4 and the upper electrode 13, and an internal wiring 31 (B) that serves as a lead electrode of the lower electrode 11. Have. Internal wiring 3
An insulating film 6 such as a silicon oxide film is formed on the insulating film 15 so as to cover 1. The insulating film 6 is etched to form a contact hole in the internal wiring 31B. Then, an aluminum wiring 33 having a predetermined pattern and serving as an external wiring is formed on the insulating film 6. Aluminum wiring 33
Are electrically connected to the internal wiring 31B through the barrier layer 32 in this contact hole. Finally, a passivation film (not shown) is deposited on these circuits to form a non-volatile memory device.

The circuit configuration of the memory cell of the non-volatile memory device is as shown in FIG. 5, and the MOS transistor Q in this circuit diagram corresponds to the MOS transistor 20 in FIG.
The capacitor C corresponds to the capacitor 10. Word line W
L is connected to the gate 22, and the bit line BL is source /
It is electrically connected to the other of the drain regions 4. Wiring 30
Is used as the plate line PL. The memory cells of the non-volatile memory device of this embodiment can be driven at 2V,
Fatigue resistance was exhibited ¹⁰ times or more. The switching speed was 100 ns or less. The switching charge amount was measured and found to be 15 μC / cm ² . In addition, after completing the non-volatile memory device, wiring and MF
When the M structure was etched, the MOS transistor was taken out, and the component analysis was performed, no diffusion of the ferroelectric component was observed.

Comparative Example 1 The nonvolatile memory device of this comparative example has the same element structure as that of the first embodiment, but the compositions of the ferroelectric film are different from each other. MOS transistor 20
Then, the capacitor 10 is formed. On Ti / Pt film of the lower electrode _{11, Sr 2 (Nb 0. 1} , T
An a _0.9 ) ₂ O ₇ film (film thickness 200 nm) is formed by the sol-gel method, annealed, and then the Pt film of the upper electrode 13 is sputtered (see FIG. 1). Since the other steps are the same as those in the first embodiment, the description thereof will be omitted, but this nonvolatile memory element could not write data. Ti
When the Sr ₂ (Nb _0.1 , Ta _0.9 ) ₂ O ₇ film on the / Pt film was investigated by X-ray diffraction, only an X-ray pattern having a paraelectric structure was obtained.

Next, a second embodiment will be described with reference to FIG. The figure is a cross-sectional view of a semiconductor substrate on which a MOS transistor and a capacitor having an MFM structure are formed. p
The main surface of the type silicon semiconductor substrate 1 is surface-treated to form a field oxide film 2 in the element isolation region. Next, the insulating film 3 made of a silicon oxide film is formed on the semiconductor substrate 1 by heat treatment or the like, and the MOS transistor 20 using the insulating film 3 as a gate oxide film is formed. The MOS transistor 20 includes an n ⁺ source / drain region 4, a gate oxide film 3 formed between the source / drain regions, and a gate 22 such as polysilicon formed on the gate oxide film 3. There is. The gate 22 is covered with an interlayer insulating film such as a silicon oxide film. This interlayer insulating film is etched to form a contact hole on one of the source / drain regions 4 of the MOS transistor 20. Then, the plug 21 is formed by filling the contact hole with polysilicon.
To form The capacitor 10 having the MFM structure is formed on the plug 21. The MFM structure has a laminated film of IrO ₂ / Ir film of the lower electrode 11 connected to the plug 21, a La ₂ (Ti _0.3 , Ta _0.7 ) ₂ O ₇ film (film thickness 200 nm) of the ferroelectric film 12, The upper electrode 13 is composed of an IrO ₂ / Ir film.

An IrO ₂ / Ir film for the lower electrode is laminated by sputtering and annealed. Then, a La ₂ (Ti _0.3 , Ta _0.7 ) ₂ O ₇ film is formed on the lower electrode by sputtering, and further an IrO ₂ / Ir film 13 is laminated to form a nonvolatile memory element. MOS transistor 20
The other of the source / drain regions 4 is connected to an external wiring 34 such as aluminum used for the bit line BL,
The gate 22 is used for the word line WL. Upper electrode 13
Are electrically connected to the wiring 35 used for the plate line PL. The switching charge amount of this memory cell is 1
It was 0 μC / cm ² . The circuit configuration of this memory cell is the same as that of FIG. This nonvolatile memory element has a cell area of 4 while maintaining the same characteristics as those of the first embodiment.
It can be reduced by 0%.

Comparative Example 2 The nonvolatile memory device of this comparative example has the same element structure as that of the second embodiment, but the compositions of the ferroelectric film are different from each other. After forming the MOS transistor 20, the capacitor 10 is formed. Lower electrode 1
No. 1 IrO ₂ / Ir film with a Sr thickness of 200 nm
_{A 2} (Nb _0.5 , Ta _0.5 ) ₂ O ₇ film is formed by sputtering and annealed, and then IrO ₂ /
The Ir film is sputtered (see FIG. 2). Since the other steps are the same as those in the second embodiment, the description thereof is omitted, but this nonvolatile memory element could not write data. Similarly, a La ₂ Ti ₂ O ₇ film is formed as a ferroelectric film by sputtering to form a nonvolatile memory element.
No data could be written to this memory element. Sr ₂ (Nb _0.5 , Ta _0.5 ) ₂ O ₇ film and La ₂
When the Ti ₂ O ₇ film was examined by X-ray diffraction, a strong b-axis orientation, which was difficult to polarize, appeared in each case.

Next, a third embodiment will be described with reference to FIG. The figure is a cross-sectional view of a field effect ferroelectric element having an MFMIS structure. Source / drain regions 4 are formed in the surface region of the p-type silicon semiconductor substrate 1. Ferroelectric film 1 in which metal layers 15 and 16 are formed on both surfaces of the source / drain region 4 with a gate oxide film 3 interposed therebetween.
2 are arranged. In this element, charge is accumulated in the ferroelectric film, and reading is performed in the field effect element portion.
Ca ₂ (Nb _0.2 , which rotates the ArF excimer laser light,
By irradiating the ceramic target surface consisting of Ta _{0.8) 2} O ₇ hammered the particles, it is deposited at a substrate temperature of 600 ° C. on the silicon semiconductor substrate 1 to form a ferroelectric film. As a result of measuring the CV characteristics of the ferroelectric film, FIG.
A hysteresis loop corresponding to the polarization history is obtained as shown in. Ps is the saturation polarizability and Pr is the residual polarizability. The switching charge amount (= 2Pr) is equal to twice the residual polarizability. Ec is a coercive electric field. The dielectric constant of this ferroelectric film was 60. A similar film is formed using Nb ₂ (Ti
_A similar hysteresis loop was obtained even when a ceramic target made of _0.2 , Ta _0.8 ) ₂ O ₇ was used. In addition, a gate oxide film (film thickness 15 nm) 3, Pt electrode 15, Ca ₂ (Nb _0.2 Ta) is formed on the silicon semiconductor substrate.
_0.8 ) ₂ O ₇ film (film thickness 200 nm) 12, Pt electrode 16
Are sequentially deposited to form the ferroelectric element having the MFMIS structure shown in FIG. This non-volatile memory device was able to switch at 3 V or less.

(Comparative Example 3) Ca ₂ (N in the third embodiment)
b _0.2 Ta _0.8 ) ₂ O ₇ film was replaced with a PZT film, and a gate oxide film (film thickness 15 nm), Pt was formed on a silicon semiconductor substrate.
An electrode, a PZT film (film thickness 200 nm), and a Pt electrode are sequentially deposited to form a film having an MFMIS structure having the same structure as in FIG. In this nonvolatile memory, since the ferroelectric PZT has a large dielectric constant, the capacitance ratio with the gate oxide film, which is a laminated capacitor, becomes large. Therefore, the substantial voltage applied to the ferroelectric film becomes small, and switching cannot be performed at 3V.

Next, a fourth embodiment will be described with reference to FIG. The figure is a cross-sectional view of a semiconductor substrate on which a MOS transistor and a capacitor having an MFM structure are formed. This embodiment is basically formed by using the same process as the second embodiment, and uses a ferroelectric film having the same composition as that of the above-mentioned embodiment. In the second embodiment, the capacitors are formed on the source / drain regions, but in this embodiment they are formed on the gates. Therefore, the cell area can be further reduced as compared with the above embodiment. The main surface of the p-type silicon semiconductor substrate 1 is surface-treated to form a field oxide film 2 in the element isolation region. Next, the insulating film 3 made of a silicon oxide film is formed on the semiconductor substrate 1 by heat treatment or the like, and the MOS transistor 20 using the insulating film 3 as a gate oxide film is formed. The MOS transistor 20 includes an n ⁺ source / drain region 4, a gate oxide film 3 formed between the source / drain regions, and a gate 22 such as polysilicon formed on the gate oxide film 3. The gate 22 is covered with an insulating film 15 such as a silicon oxide film. The capacitor 10 having the MFM structure is formed on the insulating film 15. The MFM structure is based on Ir of the lower electrode 11.
A laminated film of O ₂ / Ir film and La ₂ (T
i _0.3 , Ta _0.7 ) ₂ O ₇ film (film thickness 200 nm) and the IrO ₂ / Ir film of the upper electrode 13.

An IrO ₂ / Ir film for the lower electrode is laminated by sputtering and annealed. After etching and patterning, a La ₂ (Ti _0.3 , Ta _0.7 ) ₂ O ₇ film is formed by sputtering, and further an IrO ₂ / Ir film 13 is laminated to form a nonvolatile memory element. Capacitor 10
Are covered and protected by the insulating film 6. One of the source / drain regions 4 of the MOS transistor 20 is connected to the wiring 36 such as aluminum used for the bit line BL, and the gate 22 is used for the word line WL. The upper electrode 13 is electrically connected to the metal wiring 37 such as aluminum connected to the other of the source / drain regions 4 through the contact holes of the insulating films 6 and 15. The circuit configuration of this memory cell is the same as that of FIG. This non-volatile memory device can have a cell area smaller than that of the first embodiment like the second embodiment while maintaining the same characteristics as those of the second embodiment. The lower electrode 11 is connected to the plate line PL.

[0026]

The non-volatile memory element using the ferroelectric thin film of the present invention does not contain Pd or Bi that easily diffuses, and therefore compositional deviation is unlikely to occur in the dielectric film, resulting in oxygen vacancies. Excellent fatigue characteristics because it does not occur. Further, since the diffusion element does not affect other layers, high integration can be achieved. Also, since there is no component that easily evaporates, the problem of particles caused by the evaporative component does not occur,
Excellent mass productivity. Furthermore, since the dielectric film in the memory device of the present invention has a small dielectric constant of less than 100 and a small capacitive load, it is possible to reduce power consumption and improve the inversion speed.

[Brief description of drawings]

FIG. 1 is a sectional view of a memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a memory device according to an embodiment of the present invention.

FIG. 3 is a sectional view of a memory device according to an embodiment of the present invention.

FIG. 4 is a sectional view of a memory device according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of the memory device shown in FIGS.

FIG. 6 is a crystal configuration diagram showing a ferroelectric structure in a ferroelectric film of a conventional memory device.

FIG. 7 is a crystal configuration diagram showing a ferroelectric structure in the ferroelectric film of the memory device of the present invention.

FIG. 8 is a Ps-Ec characteristic diagram showing polarization characteristics of a ferroelectric film.

FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a ferroelectric film of the present invention.

FIG. 10 is a circuit diagram illustrating a write / read operation of the memory element of the present invention.

FIG. 11 is a circuit diagram illustrating a write / read operation of the memory element of the present invention.

[Explanation of symbols]

1 ... semiconductor substrate 2 ... field oxide film
3 ... Gate oxide film, 4 ... Source / drain regions, 5, 6, 7, 8, 15 ... Insulating film, 10 ...
-MFM structure capacitor, 11 ... capacitor lower electrode, 12 ... ferroelectric film, 13 ... capacitor upper electrode, 15, 16 ... metal layer (Pt electrode), 20 ... MOS transistor, 21 ... Plug, 22 ... Gate, 30, 33, 34, 3
5, 36, 37 ... Wiring, 31 ... Internal wiring and electrodes, 32 ... Metal wiring.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (3)

[Claims] 1. A memory cell array in which a plurality of memory cells, each of which is formed by serially connecting an information storage capacitor using a ferroelectric film as a dielectric between electrodes and a charge transfer MOS transistor, are arranged in a matrix. A plurality of word lines that are commonly connected to the gates of the MOS transistors of the memory cells in the same row, and a plurality of plate lines that are commonly connected to the plates of the capacitors of the memory cells in the same row. And a plurality of bit lines commonly connected to any one of the source / drain regions of the MOS transistors of the memory cells in the same column, the ferroelectric film is M1 ₂ M2 ₂ O ₇ and M1 ₂ Ta ₂
A solid solution of O ₇ (where M1 is at least one element selected from Sr, Ca, La and Nd, and M2 is at least one element selected from Nb and Ti). Non-volatile memory device. 2. The solid solution constituting the ferroelectric film is represented by M1 ₂ (M2 _x , Ta _1-x ) ₂ O ₇ ,
The non-volatile memory device according to claim 1, wherein 1 ≦ x ≦ 0.5. 3. A semiconductor substrate, a source / drain region formed in a surface region of the semiconductor substrate, a gate insulating film formed between the source / drain regions, and formed on the gate insulating film. A first metal film formed on the first metal film, a ferroelectric film formed on the first metal film, and a second metal film formed on the ferroelectric film. Is M1 ₂ M2 ₂ O ₇ and M1 ₂ Ta ₂
O ₇ (provided that M 1 is at least one element selected from Sr, Ca, La, and Nd, M 2 is at least one element selected from Nb and Ti), and spontaneously. A non-volatile memory device characterized by storing information by utilizing polarization characteristics.