KR20050038297A - Non-volatile for 1t1c type of using ferroelectric a semiconductor - Google Patents

Abstract

The present invention is connected to the plate line via a ferroelectric semiconductor capacitor of the group 2-6 compound to the source of the cell selection transistor, so that the voltage sensing for reading and writing to the cell is smooth and stable for a long time 1T1C using a ferroelectric semiconductor It relates to a nonvolatile memory.

In a 1T1C nonvolatile memory cell array arranged in a matrix form,

The gate of the cell selection transistor TR of the cell is connected to the word line WL, and the drain thereof is connected to the bit line BL through the capacitor C _B.

The ferroelectric semiconductor capacitor FES connected to the plate line PL is connected to the source of the cell selection transistor TR.

Description

Non-volatile for 1T1C type of using ferroelectric a semiconductor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 1T1C nonvolatile memory using a ferroelectric semiconductor. In particular, a ferroelectric semiconductor capacitor of a group 2-6 compound connected to a plate line is formed at a source of a cell selection transistor, so that voltage sensing for read / write in a cell is smooth. The present invention relates to a 1T1C nonvolatile memory using ferroelectric semiconductors, which can be stably performed for a long time.

In general, ferroelectrics are materials in which spontaneous polarization exists at a certain temperature and such spontaneous polarization is inverted by an external magnetic field, and information stored by spontaneous polarization characteristics is not erased even when the power supply is cut off. It is well known that research is being actively conducted to replace nonvolatile memory using excellent information integrity.

Since there is a limit to high integration and large capacity of existing semiconductor memory devices, researches on ferroelectric memory having high dielectric constant and non-volatility have been actively conducted.

The ferroelectric memory is based on the deposition of a perovskites oxide ferroelectric on a Si substrate, which is a metal-ferroelectric-semiconductor (MFS), two transistors and two capacitors (2T2C) or one It is made using a transistor and one capacitor (1T1C) structure.

Ferroelectrics act like gate dielectrics in MFS cells.

The polarization of the ferroelectric controls the surface potential, and as a result, current flows from source to drain.

Other currents due to polarization are used for logic sensing.

Since the use of perovskite oxidized ferroelectrics inevitably does not conform structurally well at the interface when ferroelectrics and silicon are bonded, this is a major factor in device deterioration such as fatigue, preservation, and stamping.

That is, in the conventional ferroelectric random access memory (FRAM), when an electric field is applied to a FRAM cell, polarization of charge occurs, and the relationship between the applied voltage and the amount of polarization is represented by so-called hysteresis characteristics.

Fig. 1 shows an equivalent circuit of a one transistor / 1 capacitor (1T / 1C) type configuration as one embodiment of a conventional FRAM cell.

In a memory cell array in which a plurality of FRAM cells are arranged in a matrix, the drain of the cell selection MOS transistor Tst of each cell is connected to the bit line BL, and the gate of the cell selection MOS transistor Tst is It is connected to the word line WL, and one end of the ferroelectric capacitor Cm is connected to the plate line PL.

Fig. 2 is a characteristic diagram showing a relationship (hysteresis curve) between an applied electric field (applied voltage V) and a polarization amount P of a ferroelectric film used in a FRAM cell.

As can be seen from this hysteresis characteristic, the residual polarization Pr of the ferroelectric film is positive when the electric field is not applied to the ferroelectric film of the ferroelectric capacitor of the FRAM cell, that is, the applied voltage V = 0 between the capacitor electrodes. Alternatively, the secondary data determined depending on whether it is negative is stored in the FRAM cell.

Here, the positive (+) and the negative (-) of the residual polarization Pr indicate which direction the polarization direction is facing between the plate electrode of the ferroelectric capacitor and the bit line BL side electrode, and the polarization appears in one direction. The state in which the polarization is present is defined as data '1', and the state in which polarization appears in the other direction is defined as data '0'.

However, in order to improve the reliability of the FRAM as described above, the number of times that the FRAM cell can be written must be increased, the data must be retained for a long time, the environmental resistance is improved, and the imprint must be suppressed.

In addition, the ferroelectric has a spontaneous polarization, and the polarization can be reversed by an electric field. Spontaneous polarization and polarization reversal are essential elements for ferroelectrics.

It can be seen that the polarization induced by the electric field maintains a certain amount of residual polarization (+ Pr, -Pr state) without being destroyed due to the presence of spontaneous polarization even when the electric field is removed. The residual polarization + Pr and -Pr states Is used as a memory element by mapping 0 and 1, respectively, and in each of these states, data is retained even when the electric field is removed.

When the FRAM is operated, that is, to read and write data, it must be changed into two states of + Pr and -Pr from time to time, and moving from + Pr to -Pr or vice versa is called polarization inversion.

That is, the P (Polarization) -V (Voltage) characteristic when the bipolar electric field is continuously applied so that polarization reversal occurs in the ferroelectric thin film such as PZT, + Pr,-as the applied electric field cycle increases. The residual polarization of Pr becomes smaller and smaller, and thus cannot finally serve as a memory device.

That is, there is a problem in that the fatigue phenomenon of the ferroelectric thin film is suddenly frozen.

In addition, the fatigue phenomenon of the ferroelectric thin film forms a large amount of point bonds (for example, hydrogen vacancies) and dislocations at the interface between the ferroelectric insulating film and the dielectric substrate, which are dependent upon growth or including a metallization process. It can be seen that this is a result of attenuation including fatigue, preservation, and stamping caused by the phenomenon of internal penetration of atoms during phosphorus process.

In order to solve the above problems, a structure in which an appropriate dielectric is inserted between the ferroelectric insulating film and the silicon substrate, that is, a metal-ferroelectric-insulator-semiconductor structure (MFIS) must be formed, or another metal layer is deposited on the insulator. A structure, that is, a metal-insulator-metal-insulator-semiconductor structure had to be formed.

However, there is a disadvantage that not only affects the thickness of the semiconductor that needs to be thinned, but also the manufacturing process becomes complicated.

Accordingly, the present invention has been made to solve the above problems, by forming a ferroelectric semiconductor capacitor of a group 2-6 compound connected to the plate line to the source of the cell selection transistor, thereby making the cell read / write. It is an object of the present invention to provide a 1T1C non-volatile memory using ferroelectric semiconductors that allow voltage sensing to be smooth and stable for a long time.

In the 1T1C nonvolatile memory cell array using a ferroelectric semiconductor according to the present invention for achieving the above object is arranged in a matrix shape,

The gate of the cell selection transistor TR of the cell is connected to the word line WL, and the drain thereof is connected to the bit line BL through the capacitor C _B.

The ferroelectric semiconductor capacitor FES connected to the plate line PL is connected to the source of the cell selection transistor TR.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

3 is a block diagram of the present invention,

In a 1T1C nonvolatile memory cell array arranged in a matrix form,

The gate of the cell selection transistor TR of the cell is connected to the word line WL, and the drain thereof is connected to the bit line BL through the capacitor C _B.

The ferroelectric semiconductor capacitor FES connected to the plate line PL is connected to the source of the cell selection transistor TR.

Here, the ferroelectric semiconductor capacitor (FES) is manufactured by growing a ferroelectric semiconductor of Group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, and CdFeSe on the substrate, thereby producing PbTiO3 or PZT (PbZrO3). Or fatigue resistance caused by growing ferroelectrics of solid solution of PbTiO3).

Since the ferroelectric semiconductor structure having a structure in which one of the group 2-6 compounds is further included in the structure of the ferroelectric has a form suitable for the silicon structure, the device loss can be reduced.

This phenomenon occurs in the 1T1C type nonvolatile memory device where the bits are stored by the up (0) / down (1) state of spontaneous polarization, and the read operation is similar to that of the voltage in the 1T1C cell as a normal memory using perovskite. This is indicated by sensing the difference.

Therefore, the advantage of using ferroelectric semiconductors instead of conventional perovskite is that the capacitors are structurally well-suited to the silicon substrate, and have a two-junk blend structure such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, CdFeSe. Group 6 compounds are well-suited to silicon substrates having a diamond structure.

In particular, when the CdZnS having a zinc blend structure is deposited on a silicon substrate, the lattice misalignment can be reduced to less than 1%.

As described above, in the 1T1C nonvolatile memory using the ferroelectric semiconductor of the present invention, the ferroelectric semiconductor capacitor connected to the plate line is connected to the source of the cell selection transistor, so that voltage sensing for read / write is smoothly performed in the cell. It is effective in making it stable for a long time.

1 is a circuit diagram showing an 1T1C type equivalent circuit of a conventional FRAM cell.

Fig. 2 is a hysteresis curve diagram showing a relationship between an applied electric field and a polarization amount of a ferroelectric film used in a conventional FRAM cell.

3 is a circuit diagram illustrating a configuration of a nonvolatile memory according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

TR: Cell select transistor C _B : Capacitor

BL: Bit line FES: Ferroelectric semiconductor capacitor

PL: Plate line WL: Word line

Claims (2)

In a 1T1C nonvolatile memory using a ferroelectric semiconductor, in which a gate of a cell selection transistor is connected to a word line and a drain of the cell selection transistor is connected to a bit line through a capacitor so as to be arranged in a plurality of matrix shapes. And a ferroelectric semiconductor capacitor connected to a plate line as a source of the cell selection transistor. 1T1C nonvolatile memory using a ferroelectric semiconductor. The method of claim 1, wherein the ferroelectric semiconductor capacitor, 1T1C non-volatile memory using a ferroelectric semiconductor characterized in that to grow a ferroelectric semiconductor consisting of a group 2-6 compound on the substrate.