JP2000156472A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a ferroelectric thin film which is capable of constituting a small memory cell and scaling through a simple process and stably holding its polarization state. SOLUTION: A memory cell is equipped with a memory capacitor CM equipped with a first electrode, a second electrode opposed to the first electrode, and a ferroelectric thin film sandwiched in between the electrodes, a reference capacitor CREF equipped with a third electrode connected to the first electrode, a fourth electrode opposed to the third electrode, and a ferroelectric thin film sandwiched in between the electrodes, a rear-out transistor QREAD equipped with a gate electrode connected to both the first and third electrode, and a control transistor for controlling the potential VG of a storage node NS as a connecting point of the first electrode, the third electrode, and the gate electrode, and two or more of the memory cells are arranged in a matrix to form a semiconductor memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of storing an ultra-large capacity of gigabit or more, and more particularly to a nonvolatile semiconductor memory device having a thin film capacitor formed of a ferroelectric thin film.

[0002]

2. Description of the Related Art The integration density of semiconductor memory devices has increased,
When an ultra-large storage capacity of gigabit or more is required, the memory cell becomes smaller and smaller, and the capacity of a conventional storage capacitor using an oxide film becomes insufficient. Therefore, in recent years, storage devices using ferroelectric thin films for storage capacitors and the like (hereinafter referred to as “ferroelectric memories”) have been actively researched and developed, and some of them have already been put into practical use. . A ferroelectric memory is non-volatile, so that the contents stored in the memory are not lost even after the power is turned off, and when the film can be formed sufficiently thin, the spontaneous polarization inversion is fast and as fast as DRAM. It is possible to write and read data.

At present, first and second types of ferroelectric memories, which are roughly classified into the following modes of use of ferroelectric thin films, are considered.

The first ferroelectric memory uses a ferroelectric thin film as a ferroelectric capacitor. The ferroelectric memory stores electric charge at the time of polarization reversal of a ferroelectric capacitor composed of a metal / ferroelectric / metal junction. This is a reading method. Its advantages are that the fabrication process is relatively easy because the ferroelectric capacitor is made separately, and that the polarization is easily maintained because both electrodes of the ferroelectric capacitor are at the same potential during standby. Assuming that the minimum processing dimension is F, DRA
A memory cell area as small as 4F ² is possible in a cell-to-transistor (1T / 1C) type cell similar to M, 8F ² , NAND type cell, and 1T / 1C parallel connected cell (Chain FRAM). And the like. here,
Assuming that the minimum line width L and the minimum space width S of the pattern constituting the semiconductor memory device are the minimum processing size (2F)
Corresponds to the sum of the two (2F = L + S).

A second ferroelectric memory uses a ferroelectric thin film as a ferroelectric gate transistor.
This is a structure in which a ferroelectric thin film is used as a gate insulating film instead of a gate oxide film of a MOS-FET,
“MFS (Metal / Ferroelectric / Semiconductor) -FET (Field
Effect Transistor) ". In this second ferroelectric memory, carriers are generated on the semiconductor surface to compensate for the polarization charge of the ferroelectric thin film, so that an inversion layer and an accumulation layer are formed depending on the polarization direction of the capacitor, and the switching state of the transistor is changed. Can be maintained.

A particular advantage of this device is that the polarization charge can be amplified and read as a gain cell instead of directly reading the polarization charge. Therefore, the absolute value of the amount of polarization electric charge is not required for memory retention, and scaling with the minimum dimension f is possible as long as polarization density can be retained.
Here, the “minimum dimension f” is a so-called feature size f, which is generally given by L = S = f, L = f, S = 1.5f, or the like.

[0007]

In the first ferroelectric memory using the above ferroelectric thin film as a ferroelectric capacitor, the amount of remanent polarization of the ferroelectric capacitor must be more than a certain absolute amount. The disadvantage is that scaling with the minimum dimension f is difficult. In the current reading using a ferroelectric capacitor, the inverted charge of the capacitor is led to the bit line capacitance, and sensing is performed as the potential difference of the bit line. Area and polarization inversion amounts of capacitors with miniaturization whereas reduced in F ^2, since the bit line capacitance is difficult that most decreases, there is a problem that limits the scaling is present.

On the other hand, the second using the above MFS-FET
The ferroelectric memory also has the following first to third disadvantages. A first disadvantage is that the process of forming a ferroelectric thin film directly on Si may be difficult.
The reason is that PZ on Si (silicon) which is easily oxidized
T (lead zirconate titanate: PbZr _x Ti _1-x O ₃ ),
SBT (Strontium bismuth tantalate: SrBi
_{2 Ta 2 O 9), BSTO} ( barium strontium _{titanate: Ba X Sr 1-X TiO} 3) because it directly form an oxide ferroelectric thin film such as the film formation while maintaining good crystallinity It is not easy to do.

Further, when forming a ferroelectric thin film is more or less SiO ₂ layer at the interface between silicon (Si) is generated, even if the SiO ₂ layer is thin as a few nm,
Since the dielectric constant is much smaller than that of the ferroelectric thin film, a considerable portion of the voltage applied to the gate electrode of the MSF-FET is eroded by the SiO ₂ layer, resulting in a high operating voltage. Is included.

Further, unlike the ideal Si / SiO ₂ interface, the interface level existing at the Si / ferroelectric interface or the impurity level of heavy metal in the ferroelectric diffused in Si is determined by MFS. -Becomes a trap of the channel of the FET, lowers the mobility of the carrier, and increases the MFS-F
Varying the threshold voltage of ET in accordance with the interface state density and the impurity state density is also considered as a first disadvantage. These problems are very serious issues for a highly integrated LSI.

As a second disadvantage, there is a problem of an anti-electric field applied to the ferroelectric thin film. That is, since the charge generated by the polarization of the ferroelectric and the charge induced on the Si surface are ideally equal, an accumulation layer and a depletion layer or an inversion layer are generated depending on the direction of the polarization. The shift in the surface potential of Si is applied to the ferroelectric thin film as an anti-electric field. Since this anti-electric field is applied in the direction in which the polarization is inverted, it is difficult to stably maintain the polarization of the MFS-FET.

A third disadvantage is that the memory cell size increases. When memory cells composed of MFS-FETs are arranged in a matrix to constitute a semiconductor memory device, one memory cell usually has a write control transistor and a read control transistor in addition to an MFS-FET for holding information. A control transistor is required. That is, in the case of the MFS-FET, one memory cell is composed of three transistors (3T) and has a cell area of 18F ² or more, and the first ferroelectric thin film is used as a ferroelectric capacitor. The memory cell size is larger than the ferroelectric memory cell used.

As described above, using either the ferroelectric capacitor in the first memory or the MFS-FET in the second memory has advantages and disadvantages.
It is not possible to satisfy all the requirements for a highly integrated semiconductor memory, such as a small memory cell configuration, scalability, stable retention of ferroelectric polarization, and ease of processing.

In view of the above problems, an object of the present invention is to provide a semiconductor memory device using a ferroelectric thin film which can have a small memory cell configuration and can stably maintain ferroelectric polarization. And

Further, in addition to the above-mentioned object, MFS-FE
Another object of the present invention is to provide a semiconductor memory device using a ferroelectric thin film, which has a feature of being capable of scaling, which is an advantage of T, and which can be further integrated.

It is still another object of the present invention to provide a semiconductor memory device using a ferroelectric thin film whose manufacturing process is easy.

[0017]

In order to achieve the above object, a semiconductor memory device according to a first basic structure of the present invention comprises:
A storage capacitor comprising at least a first electrode, a second electrode arranged opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes; A third electrode connected to the first electrode of the storage capacitor and a fourth electrode arranged opposite to the third electrode.
And a reference capacitor comprising at least a dielectric thin film sandwiched between the third and fourth electrodes; and a capacitor connected together to the first electrode of the storage capacitor and the third electrode of the reference capacitor. A plurality of memory cells each including at least a read transistor having a gate electrode provided therein; and a control transistor for adjusting a potential of a storage node which is a connection point between the first electrode, the third electrode, and the gate electrode. It is characterized by being arranged in a matrix. That is, in the semiconductor memory device according to the first basic configuration, a plurality of memory cells each including at least a storage capacitor, a reference capacitor, a read transistor, and a control transistor are arranged in a matrix.

In the present invention, in the following description, a node that is a connection point between the first electrode of the storage capacitor, the third electrode of the reference capacitor, and the gate electrode of the read transistor is referred to as a “storage node”. Call. In the first basic structure of the present invention, across the series circuit of the reference capacitor and the storage capacitor, when applying an external voltage V _A, the potential V _G of the storage node,
It is indicated by the intersection of the polarization-voltage curve (PV curve) of the storage capacitor and the reference capacitor. Since a storage capacitor having a ferroelectric thin film has a ferroelectric hysteresis curve, "1" or "0" is read before the read operation.
Can be kept in a polarization state corresponding to the memory of This, depending on the polarization state previously set, different P-V curve of the storage capacitor, thus, V _G represented by a point of intersection P-V curve can assume two different values. It is possible to output a signal corresponding to the storage state of the by different V _G to the read signal line when the on / off control of the read transistor "1" or "0".

In the first basic configuration of the present invention, it is preferable to connect a control transistor between the first and second electrodes of the storage capacitor. That is, by arranging the control transistor in parallel with the storage capacitor, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed. At the time of reading, first, the storage capacitor is short-circuited by the control transistor, precharging is performed by applying a voltage only to the reference capacitor, and then the control transistor is turned off, and the first and second storage capacitors are turned off. , A low-voltage reverse potential is applied between the electrodes to invert the polarization state, thereby enabling a precharge combined readout method. In the present invention, in the following description, a unit including a storage capacitor and a control transistor connected in parallel to the storage capacitor is referred to as a “memory cell”.

Further, in the first basic configuration of the present invention,
Preferably, a control transistor is connected between the third and fourth electrodes of the reference capacitor. By installing a control transistor in parallel with a reference capacitor,
The floating / short state of the storage node
The operation speed can be increased by quickly switching between read / write and standby. Further, at the time of writing, the third and fourth electrodes of the reference capacitor are short-circuited (passed) by the control transistor, and a voltage is applied only to the storage capacitor, thereby enabling low-voltage writing.
In the present invention, in the following description, a unit including a reference capacitor and a control transistor connected in parallel to the reference capacitor will be referred to as a “reference cell”.

Further, in the first basic configuration of the present invention, a first control transistor connected between the first and second electrodes of the storage capacitor, and a third and fourth electrode of the reference capacitor It is preferable to include a second control transistor connected therebetween. At the time of reading, first, the first control transistor is turned on, the storage capacitor is short-circuited, the second control transistor is turned off, and precharging is performed by applying a voltage only to the reference capacitor. On the other hand, at the time of writing, the second control transistor is turned on, and the third and fourth electrodes of the reference capacitor are short-circuited (passed) by the second control transistor, and the first control transistor is turned off. By turning off the transistor and applying a voltage only to the storage capacitor, low-voltage writing can be performed. Further, by providing the first and second control transistors, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed.

According to the first basic configuration of the present invention, it is possible to provide a scalable high-density semiconductor memory device that is easy to process, has a small memory cell configuration, and is scalable. In particular, for miniaturization, storage capacitors,
Since all of the reference capacitor, the control transistor (first / second control transistor), and the gate capacitor of the read transistor are reduced in proportion, the MFS-
Full scaling is possible as with FETs.

According to a second basic configuration of the present invention, a first electrode, a second electrode disposed opposite to the first electrode, and a first electrode and a second electrode sandwiched between the first and second electrodes are provided. A storage capacitor comprising at least a ferroelectric thin film;
A storage cell array (storage cell chain) in which a plurality of storage cells each including a control transistor connected between the second electrodes are connected in series; and located at an end of the storage cell array (storage cell chain). A third electrode electrically connected to the first electrode of the storage capacitor, a fourth electrode arranged corresponding to the third electrode, and sandwiched between the third and fourth electrodes; A plurality of memory cell blocks including at least a reference capacitor having at least a dielectric thin film; and a read transistor having a gate electrode electrically connected to the first and third electrodes are arranged in a matrix. It is characterized by: Here, “electrically coupled” means that a circuit configuration in which a short-circuited storage capacitor, a storage cell column (storage cell chain), or the like exists between the storage capacitor and the storage device other than the direct connection is allowed. It is. In order to randomly access a memory cell column (memory cell chain) in the second basic configuration of the present invention, a block selection transistor may be connected to each memory cell column.

In the second basic configuration of the present invention, assuming that a storage cell row is composed of a series connection of n storage cells, the storage cell array includes the n storage cells, a block selection transistor, a read transistor, a reference capacitor, and the like. Considering the area of only one block, the memory cell unit has a minimum size of 4F ² , so the size per memory cell is (4 + 20 / n) F ² to (4 + 14 / n) F ²
, And high integration density can be achieved. Further, according to the second feature of the present invention, it is possible to provide a high-integration-density semiconductor memory device in which a manufacturing process is easy and a pattern dimension can be scaled. In particular, with respect to miniaturization, since all of the storage capacitor, the reference capacitor, the control transistor, and the gate capacitor of the read transistor are reduced proportionally, M
Full scaling similar to FS-FET is possible. In order to select a specific storage capacitor in a storage cell column, a control transistor connected in parallel to another storage capacitor to make the control transistor conductive, and a control connected in parallel to the target specific storage capacitor It is sufficient that only the use transistor is turned off. In this case, when a storage capacitor far from the reference capacitor in the storage cell column is selected, the parasitic capacitance of the control transistor of the storage cell existing between the reference capacitor and the selected storage capacitor becomes the capacitance of the reference capacitor. In some cases, it may affect the operation of reading stored information. In this case, the capacitance of the storage cell at each position is determined by the sum of the capacitance of the reference capacitor and the parasitic capacitance of the control transistor.
The problem can be solved by adjusting the ratio as close to 1: 1 as possible. Specifically, the remanent polarization of the storage capacitor of the storage cell farther from the reference capacitor may be gradually increased than the remanent polarization of the storage capacitor of the storage cell closer to the reference capacitor.

In the second basic configuration of the present invention, the control transistor connected in parallel to the storage capacitor is referred to as a “first control transistor”, and the third and fourth reference capacitors are referred to as “first control transistor”. It is preferable to connect a second control transistor between the electrodes. By configuring the reference cell in which the second control transistor is provided in parallel with the reference capacitor, the floating / short state of the storage node can be quickly switched between read / write and standby to increase the operation speed. . In addition, at the time of writing, the third and fourth electrodes of the reference capacitor are short-circuited (passed) by the second control transistor to apply a voltage only to the storage capacitor, thereby enabling low-voltage writing. .

It should be noted that although the first and second basic configurations of the present invention have a common feature, the amount of electric charge including a polarization inversion component obtained when a voltage corresponding to a read voltage is applied to a reference capacitor is: It is preferable that the charge amount is not less than 1/4 and not more than 4 times the amount of charge including the domain-inverted component obtained when a voltage corresponding to the read voltage is applied to the storage capacitor. In particular, the effective capacitance of the reference capacitor and ferroelectric memory capacitor by approximately equal, when the inversion voltage of the ferroelectric capacitor and V _C, inverting the ferroelectric capacitor at the operating voltage of approximately 2V _G Can be done. Together with this, depending on the polarization state of the original of the ferroelectric capacitor, it is possible to generate a voltage difference of about V _G to the storage node, it is possible to directly switching the read transistor by the potential of the storage node .

Further, the same applies to both the first and second basic configurations of the present invention, but the dielectric thin film of the reference capacitor may be a paraelectric thin film or a ferroelectric thin film. If the reference capacitor is made of a ferroelectric thin film,
The storage capacitor and the reference capacitor can be simultaneously formed in the same process, so that the process can be simplified and the manufacturing yield can be improved, which is a great advantage.

When the semiconductor memory device according to the first and second basic configurations of the present invention is compared with an existing DRAM or FeRAM, the following advantages can be listed. That is, (1) the memory cell unit has a minimum size of 4F ² , (2) the absolute value of the stored charge is unnecessary, and scaling for area reduction is possible, and (3) the ferroelectric capacitor is set at the same potential during standby. (4)
It is not sensitive to capacitor leakage or transistor junction leakage, which facilitates cell separation, and (5)
Random access becomes possible, (6) operation speed comparable to that of DRAM can be secured, and (7) read / write (R / W) only for cross-point cells, low power consumption and (8) ) Since the reading is at the bus level, it is less sensitive to noise. There is no need for a sense amplifier for each bit line because it is included in a block. In addition, there is a concern that fatigue deterioration of the ferroelectric capacitor due to destructive readout is concerned. However, a BSTO ferroelectric capacitor which has been epitaxially grown recently has been developed, and the fatigue deterioration has no problem.

Next, the semiconductor device according to the third basic configuration of the present invention faces a plurality of selection MOS transistors connected in series and storage electrodes connected to common common electrodes of these selection transistors. NAND consisting of a storage capacitor consisting of a dielectric thin film sandwiched between plate electrodes
A type storage cell column, a reference capacitor electrically coupled to a main electrode of a selection transistor located at an end of the storage cell column, and an electrical connection to a connection between the main electrode of the selection transistor and the reference capacitor. And a plurality of memory cell blocks each including at least a read transistor having a gate electrode coupled thereto.

The main feature of the third basic configuration is that a NAND-type memory cell array using a dielectric capacitor and a reference capacitor are connected in series, and the potential of a storage node, which is a connection point between the two, is read by a read transistor. Readout for each memory cell block. In other words, across the series circuit of the one memory capacitor which is selected by the transistors in the NAND cell column and the reference capacitor, when applying an external voltage V _A, the potential of the storage node N _S V
_G is indicated by the intersection of the polarization-voltage curve (PV curve) of the storage capacitor and the reference capacitor.

In the third basic configuration, since the storage capacitor having the ferroelectric thin film has a ferroelectric hysteresis curve, it is set in a polarization state corresponding to the storage of "1" or "0" before the read operation. be able to. According to the preset polarization state, the P-
V curves are different, and therefore V indicated by the intersection of the PV curves
_G can take two different values. It is possible to output a signal corresponding to the storage state of the by different V _G to the read signal line when the on / off control of the read transistor "1" or "0".

On the other hand, in the storage capacitor having a paraelectric thin film, the charge corresponding to the storage of "1" or "0" is stored in the storage capacitor and the selection transistor is turned off, so that the refresh cycle is reduced. Can hold the stored state. Check the selection transistor during reading, by connecting the reference capacitor and the storage capacitor, the voltage V _G of the storage node N _S in accordance with the pre-charge amount of accumulated memory capacitor can take two different values it can. It is possible to output a signal corresponding to the storage state of the by different V _G to the read signal line when the on / off control of the read transistor "1" or "0".

As described above, the NAND memory cell is
While it is possible area of minimum 4F ^2, in the conventional circuit for determining the sense amplifier reads the charge accumulated in the dielectric capacitor in a memory cell in the bit line capacitance, the accumulation of a predetermined ratio with respect to the bit line capacitance A charge capacity is required, which makes it difficult to miniaturize. On the other hand, according to the semiconductor device of the third basic configuration of the present invention, the charge stored in the storage capacitor is read by the capacitance of the reference capacitor, and the determination is made by the read transistor in the block. Therefore, storage capacitors, reference capacitors,
Since all of the gate capacitors of the transistors can be proportionally reduced, the area can be completely scaled in the same manner as the MFS-FET, and a highly integrated semiconductor memory device of the gigabit class can be realized. it can.

Further, since only one reference capacitor and one read transistor need be added to the NAND type memory cell block composed of a large number of memory cells, a small memory cell area close to 4F ² as a whole is required. Becomes possible.

When the semiconductor memory device according to the third basic configuration of the present invention is compared with an existing DRAM or FeRAM, the following advantages can be listed. That is, (1) the memory cell unit has a minimum size of 4F ² , (2) the absolute value of the accumulated charge is unnecessary, so that scaling for area reduction is possible, and (3) the ferroelectric capacitor is used during standby. (4) If a ferroelectric capacitor is used as a storage capacitor, storage is less sensitive to capacitor leakage and transistor junction leakage, and cell isolation is facilitated.
(5) The same operation speed as that of the DRAM can be secured, and (6)
Since the read to the bit line is at the bus level, the bit line is not sensitive to noise.
(8) Since the read amplifier is provided in the block, a sense amplifier for each bit line is not required. (9) Since one of the storage capacitors is commonly connected to the plate electrode, the cell structure and process are easy. Yes, etc.

If the disadvantages are to be mentioned, the NAND
Because of the structure, random access for each bit cannot be performed, and R / W is performed in block units. In addition, the fatigue readout of the ferroelectric capacitor is feared due to the destructive readout. However, a BSTO ferroelectric capacitor which has been epitaxially grown recently has been developed. However, such a problem of fatigue deterioration has been considerably reduced.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor memory device according to the present invention will be described below in detail with reference to the accompanying drawings. Before describing a specific embodiment, the basic operation of the present invention will be described in more detail with reference to FIGS.

In the equivalent circuit diagram shown in FIG. 1, the semiconductor memory device includes a first electrode, a second electrode opposed to the first electrode, and a first electrode and a second electrode. a memory capacitor C _M for a ferroelectric thin film sandwiched between the at least includes, a third electrode connected to a first electrode of the memory capacitor C _M, which is arranged to face the third electrode fourth electrode, and the these three and the reference capacitor C _REF that at least and a dielectric film sandwiched between the fourth electrode, the first electrode and the reference capacitor C _REF of the memory capacitor C _M A read transistor Q _READ having a gate electrode connected to the third electrode of the storage capacitor C _M, a first electrode of the storage capacitor C _M , and a reference capacitor C _REF
, A control transistor Q _C where the source or drain connected to a connection point between the third electrode of which is at least provided with a memory cell.

FIG. 2 (a) (b) includes a storage capacitor C _M shown in FIG. 1, between the A-B terminal of the cell to the reference capacitor C _REF with paraelectric thin film are connected in series To
The operation diagram of the memory “1” read operation and the memory “0” read operation when an external voltage is applied is shown. Here, the polarization-voltage curves (P) shown in FIGS.
-V curve), the horizontal axis represents voltage (V) and the vertical axis represents dielectric polarization (P). The inversion voltage of the ferroelectric capacitor C _M as a storage capacitor V _C, the externally applied voltage V _A,
The potential of the storage node N _S is the connecting point of the capacitors and V _G. P-V curve of the ferroelectric capacitor C _M will have a ferroelectric hysteresis curve as shown in FIG. 2 (a) (b). 2 (a) is, in the case where the ferroelectric capacitor C _M is, in advance before the read operation, are the polarization state corresponding to a storage of "1", FIG. 2 (b), the ferroelectric capacitor C _M Shows a case in which a polarization state corresponding to storage of “0” is set. The reference capacitor C _REF using a paraelectric thin film is represented by a straight line having a slope corresponding to the capacitance.

[0040] When adding an external voltage V _A between the cells of the A-B terminal, the potential V _G of the storage node N _S is represented by a point of intersection P-V curve of the reference capacitor and the storage capacitor. As can be seen from FIGS. 2 (a) and 2 (b),
Since the PV curves are different, the potential V of the storage node in the case where the polarization state corresponding to the storage of “1” is set in advance.
Different from the electric potential V _G ⁰ of the storage node when it is in the polarization state corresponding to the storage in _G ¹ and "0".

The voltage V _A for inverting the storage capacitor C _M becomes lower as the capacitance of the reference capacitor C _REF is larger (the slope is larger in FIGS. 2A and 2B). It is desirable that the capacitance of the reference capacitor C _{REF be} large. On the other hand, V difference by the storage state of the voltage read at V _G when the plus ^{_{A △ V G = V G 1}} -V G 0 becomes more capacitance of the reference capacitor C _REF conversely small increase. In this regard, it is desirable that the capacity of the reference capacitor be small. Therefore, when considering both the inversion voltage and the read voltage obtained when substantial capacitance of the reference capacitor C _REF and the storage capacitor C _M is plus comparable, i.e. inversion voltage in the storage capacitor C _M inverted It is desirable that the polarization charge and the charge obtained when the same voltage as the inversion voltage is applied to the reference capacitor C _REF are substantially the same. More broadly, a substantial capacity ratio of about 1/4 or more and up to about 4 times is allowed.

The volume ratio of the storage capacitor C _M and the reference capacitor C _REF is 1: When 1, V _A is two times the V _G, also the difference △ V _G of V _G by the storage state is approximately V _It is about the same as _C. Thus, if the memory capacitor C _M of the inverting voltage 1V, V _A becomes about 2V, △ V _G
As a result, a difference of about 1 V is obtained.

Next, the storage node N _S connects the gate electrode of the read transistor Q _READ, discriminates storage state due to a difference △ V _G of V _G. The gate capacitance of the read transistor Q _READ at this time is to be connected in parallel with the storage capacitor C _M and reference capacitor C _REF, the residual polarization as the memory capacitor C _M is 1
When a normal ferroelectric capacitor of about 0 μC / cm ² or more is used, the read transistor Q _{READ having the} same area is used.
Since the gate capacitance is 1/10 or less, it has little change in the potential of the storage node N _S. In the example described above, since the resulting about 1V as the difference △ V _G of V _G,
Becomes larger than the threshold value of about 700 mV of the MOS transistor used as the read transistor Q _READ ,
Reading can be directly performed by controlling ON / OFF of the MOS transistor Q _READ by the gate voltage.

[0044] The storage capacitor C _M of ferroelectric hysteresis reference capacitor when the squareness ratio is good for curve C
By reusing the charge read to _REF , rewriting can be performed following the reading operation. That is, as shown in FIG. 3, the read voltage V _R by adding a suitable rewrite voltage V _W to the opposite direction, the polarization of the memory capacitor C _M, can be returned to approximately the read operation state before .

FIG. 3A shows a ferroelectric capacitor C
_MBefore the read operation, an amount equivalent to the storage of “1” in advance.
FIG. 3 (b) shows a case in which the electrodes are in a pole state.
Body capacitor C_MIs the polarization state corresponding to the memory of "0"
Shows the case where 3A and FIG.
In the case where continuous rewriting as in (b) is not performed,
As shown in FIG. 7A, the reference capacitor C_REFControl
Control transistors in parallel, and this control transistor
In the conductive state (ON state), the reference capacitor C _REF
Is short-circuited and the capacitor C for direct storage is_MApply voltage only to
You can write.

The dielectric thin film forming the reference capacitor C _REF is not limited to the paraelectric thin film as shown in FIG. 1, but may be a ferroelectric thin film as shown in FIG. . First, a method of using a ferroelectric material as the reference capacitor C _{REF and applying a} voltage directly between the A and B terminals in the circuit diagram shown in FIG. When a ferroelectric capacitor is used as the reference capacitor, it is necessary to polarize the reference capacitor in one direction before reading. In the circuit diagram shown in FIG. 4, the control transistor is turned on, and a negative voltage is applied between the B and C terminals to polarize the reference capacitor in one direction. Next, the control transistor is turned off, and a negative read voltage V is serially connected between the AB terminal and the storage capacitor and the reference capacitor.
Add _A.

FIG. 5A shows a storage capacitor C_MIs a figure
Read operation when written to the state of "1" in
FIG. Negative read voltage V is applied to terminal B
_AIs added to the storage node N_SPotential V_GIs
The storage capacitor PV curve and the reference capacitor
It is indicated by the intersection with the PV straight line, and the potential at that time is V _G ¹When
Become. If the storage capacitor is polarized in the opposite direction
In other words, when reading is performed in the state of “0”,
FIG. 5B shows an operation diagram in the dispensing operation. Exactly the same
From the analysis, the potential V of the storage node_G ⁰Sought
You. Thus, the inversion voltage of the storage capacitor and the reference voltage
Read voltage V approximately equivalent to the sum of capacitors_AAdd
As a result, the paraelectric thin film was used as a reference capacitor.
As before, the storage node is sufficient depending on the storage state
Voltage difference V_G ¹-V_G ⁰Can be obtained.

Next, reading in the precharge mode when a ferroelectric thin film is used as the reference capacitor C _REF will be described. In the circuit diagram shown in FIG.
The control transistor is turned on, and a positive voltage V _pree is applied to the terminal B while the terminals A and C are kept at the same potential to invert the reference capacitor and perform a precharge operation. Next, the control transistor is turned off, the precharge voltage is set to 0, and the terminal B is returned to the same potential as the terminals A and C. The operation diagram at this time is shown in FIGS.
(B). In the case of a ferroelectric capacitor, since the dielectric constant after the polarization inversion is small, the charge stored by the precharge is small, and the polarization of the storage capacitor cannot be inverted only by the precharge. However, in order to P-V curve by the polarization direction of the memory capacitor are different, a potential difference V _G ¹ -V _G ⁰ of the storage node
Can be obtained similarly. This read method also has the advantage that the ferroelectric capacitor can be read without inversion while using the ferroelectric capacitor.

[0049] Incidentally, as the storage capacitor C _M, PZ
It is possible to use a thin film capacitor made of a T-based, SBT-based (particularly, SrBi ₂ Ta ₂ O ₉ containing bismuth (Bi) as a main component), or a Ba-rich composition epitaxial BSTO-based ferroelectric thin film. Of these, epitaxial BSTO-based capacitors are particularly excellent in terms of stability and film thickness. Further, as a reference capacitor C _REF ,
Silicon oxide (SiO ₂ ), tantalum oxide (Ta
₂ O _5), it can be used or paraelectric capacitor using BSTO the Sr-rich composition, the ferroelectric capacitor described above.

FIGS. 7A and 7B are circuit diagrams for explaining the basic configuration of the present invention. FIG.
(A) is a circuit diagram when a control transistor is connected between the third and fourth electrodes of the reference capacitor C _REF . By installing a control transistor in parallel with the reference capacitor C _REF, the storage node of the floating / short state of the N _S, it is possible to increase the operating speed quickly switched during write time and standby. Further, by adding the third and fourth between the electrodes by short-circuit the control transistor (to pass) voltage only to the memory capacitor C _M of the reference capacitor C _REF when writing, to enable low voltage writing Become.

[0051] Further, FIG. 7 (b) shows a case of connecting the control transistor between the first and second electrode of the memory capacitor C _M, as described above. Storage capacitor C
By installing a control transistor in parallel with _M ,
The floating / short state of the storage node
The operation speed can be increased by quickly switching between read / write and standby. Further, at the time of reading, firstly short the memory capacitor C _M in the control transistor,
Energized only to the reference capacitor C _REF performs precharging, then the control transistor in the blocked state,
By applying a low-voltage reverse potential between the first and second electrodes of the storage capacitor C _M , a precharge-combination read method of inverting the polarization state becomes possible.

[0052] Then, FIG. 7 (c), a first control transistor coupled between the first and second electrode of the memory capacitor C _M, the reference capacitor C _REF of the third and fourth FIG. 4 is a circuit diagram in a case where a second control transistor connected between electrodes is provided. At the time of reading, first, the first control transistor is turned on, the storage capacitor _CM is short-circuited, the second control transistor is turned off, and precharging is performed by applying a voltage only to the reference capacitor _CREF. . On the other hand, at the time of writing, the second control transistor is turned on, and the third and fourth electrodes of the reference capacitor C _REF are short-circuited (passed) by the second control transistor. Then, the first control transistor and the cut-off state, only by applying a voltage to the storage capacitor C _M, allowing low voltage writing. Further, by providing the first and second control transistor, the storage node of the floating / short state of the N _S, it is possible to increase the operating speed quickly switched during write time and standby.

FIG. 8A and FIG. 8B show the present invention.
Specific configuration for higher integration of semiconductor memory device
FIG. The description shown in FIG.
The storage device is disposed opposite to the first electrode and the first electrode
Second electrode, and these first and second electrodes
A plurality of notes comprising at least a ferroelectric thin film sandwiched between
Storage capacitor C_M0, C_M1, C_M2, C_M3, ... and each memory
Capacitor C_M0, C _M1, C_M2, C_M3, ...
A control transistor connected between the first and second electrodes
TA Q_CA memory in which a plurality of storage cells consisting of
Cell column (storage cell chain); this storage cell column (storage
Storage capacitor C located at the end of the cell chain)_M0
A third electrode electrically coupled to the first electrode of the third
And a fourth electrode disposed opposite to the electrode of
Of the dielectric thin film sandwiched between the third and fourth electrodes
Reference capacitor C having_REFAnd the first and third
Having a gate electrode electrically coupled to a second electrode
Transistor Q_READA memory cell having at least
Indicates a lock block.

The semiconductor memory device of the present invention
Arrange multiple memory cell blocks in a matrix
I have. A storage cell column is composed of a series connection of n storage cells
, The other end of the memory cell column (memory cell chain)
Storage capacitor C located in the section_Mn-1For the second electrode
Is the selection transistor (block selection transistor) Q
_SIs connected. These n memory cells, block selection
Selection transistor Q_S, Read transistor Q_READ,
And reference capacitor C_REFOne block containing etc.
Considering the area of the memory cell unit, the minimum is 4F^Two
The size per memory cell is (4
+ 20 / n) F^TwoOr (4 + 14 / n) F^TwoAbout
And high integration density can be achieved. Memory center
Specific storage capacitor C in the array_MyTo choose
Is used for control connected in parallel with other storage capacitors.
The word line WL of the transistor (nMOSFET) is set high.
The level is set to the conductive state, and the specific storage key
The control transistor (n) connected in parallel with the capacitor
MOSFET) word line WL_yOnly low level and
And only the control transistor (nMOSFET)
What is necessary is just to make it a cutoff state.

Further, as shown in FIG.
Japashita C_M0, C_M1, C_M2, C_M3, ... connected in parallel
Control transistor Q_CTo the first control transistor
The reference capacitor C_REFThird and
A second control transistor Q between the fourth electrodes_C2Connect
The following shows the case. Reference capacitor C_REFSecond in parallel with
Control transistor Q_C2By installing
Storage node N_SFloating / short state
Switch quickly between read / write and standby
Speed can be increased. When writing,
Illumination capacitor C _REFBetween the third and fourth electrodes
Control transistor Q_C2Short-circuit with (pass)
Constant storage capacitor C_MyBy applying voltage only to
Thus, writing at a low voltage becomes possible.

FIG. 9A and FIG. 9B show FIG.
FIG. 9 is a circuit diagram when the reference capacitors C _REF of FIG. 8A and FIG. 8B are each formed of a ferroelectric thin film. That is, FIG. 9 (b), in the case where in parallel with the reference capacitor C _REF to constitute a second reference cell by installing a control transistor Q _{C 2,} FIG. 9 (a), reference capacitor C
Against _{RE F} is the case does not have the second control transistor Q _C2 in parallel. If the reference capacitor C _REF is made of a ferroelectric thin film, the storage capacitors C _M0 , C _M1 , C
_M2, C _M3, ... and it is possible to create simultaneously the reference capacitor C _REF in the same process, the improvement of process simplification and production yield is achieved, there is a very big advantage.

FIG. 10 shows a semiconductor memory device of the present invention.
FIG. 2 is a circuit diagram for high integration, including a storage capacitor and
This is an example in which a ferroelectric capacitor is used. Sand
That is, a plurality of selection MOS transistors Q connected in series
_M0−Q_MN(Q in the figure_M0−Q_M2Only) and these selections
Storage electrode connected to each common main electrode of the selection transistor
From the ferroelectric thin film sandwiched between the
Storage capacitor C _M0-C_MN(Similarly, C in the figure
_M0-C_M2Only shown)).
And the selection transformer located at the end of the memory cell row.
Jista Q_M0Reference capacity electrically coupled to the main electrode
TA C_REFAnd a main electrode of the selection transistor and a reference electrode.
Straight node N, which is the connection between the electrodes of the capacitor_S
Readout tiger having a gate electrode electrically coupled to the
Transistor Q_READMemory cell block having at least
Have a check.

[0058] In this example, the other electrode of the connected to the storage node of the reference capacitor electrode disposed to face is connected to a plate electrode PE, the storage node N _S is, R / W control transistor It is connected to the bit line BL via _{QR / W.}

Now, the first capacitor C in the memory cell row
The read operation of _M0 will be described. Transistor Q _{R / W} is turned on, and turns off the Q _M0 and Q _M1, the precharge voltage V _P to the reference capacitor C _REF is applied by a bit line BL precharged with. Next, the transistor Q _{R / W
Is} turned off, the transistor Q _M0 is turned on, and the read operation is performed.

After reading out the memory contents of the first capacitor C _M0 of the NAND type memory cell column, the same sequence is repeated, whereby the capacitors C _M1 , C _M1,.
C _M2 ,... C _{Mk ,.} That is, when reading the memory contents of the capacitor C _Mk , all the transistors QR _{/ W} and Q _M0 to Q _Mk-1 are turned on, the transistor and Q _Mk are turned off, and the reference capacitor C _REF and from the storage capacitor C _M0 to C _Mk-1 to apply the precharge voltage V _P performs precharge. Next, the transistor Q
_The read operation is performed with the _{R / W} turned off and the transistor Q _M0 turned off.

At this time, when the memory content of the capacitor C _Mk is read as a characteristic of the NAND cell row, the capacitance of the paraelectric component of the capacitor from C _M0 to C _Mk−1 in the procedure that has already been read is equal to Adding as parasitic capacitance is a problem. If the parasitic capacitance becomes too large, the read operation is hindered. Therefore, in order to use a NAND cell array having a large number of storage cells, it is necessary to reduce the parasitic capacitance as much as possible. That is, it is effective to increase the squareness ratio of the storage ferroelectric capacitor to reduce the paraelectric component.

On the other hand, in writing, data is written in order from the capacitor farthest from the bit line, commonly to memories having a NAND type memory cell column. Capacitor C _Mk
When writing to the transistor, all the transistors Q _{R / W} and Q _M0 to Q _Mk are turned on, and Q _{Mk + 1} is turned off.
The write voltage V is applied to the plate electrode by the bit line BL.
By applying _A, writing by applying the coercive voltage or higher voltage to the memory ferroelectric capacitor.

According to the present invention, various circuit configurations can be added to the basic circuit configuration including the memory cell column, the reference capacitor, and the read transistor. FIGS. 15A to 15D show some examples thereof.

In the circuit shown in FIG.
(1) of the reference capacitor C _REF storage node _{N S}
Connected to the plate electrode PE of the other electrode provided opposite to the electrode connected to the R / W control transistor Q
Was installed _{R / W} between the storage node N _S and the bit line BL.

In this circuit, only a read operation by precharge is possible, but in a write operation, a write voltage can be directly applied to the storage capacitor.

In the circuit shown in FIG.
(2) of the reference capacitor C _REF storage node _{N S}
The other electrode installed opposite to the electrode connected to
(May be referred to as drive lines, may be complementary bit line BL-) of the drive line DL is connected to, R / W control transistor Q _{R / W} storage node N _S and the bit line BL
It is installed between and.

In this circuit, during the precharge operation, a potential complementary to the plate electrode potential is set to B
Since it is possible to add between L and DL, it is possible to lower the operating voltage and increase the operating speed by precharging with a large voltage. In the write operation,
It becomes possible to directly apply a write voltage to the storage capacitor.

In the circuit shown in FIG.
(3) Reference capacitor C_REFStorage node N_S
The other electrode installed opposite to the electrode connected to
R / W control transistor Q _{R / W}
Reference capacitor C_REFStorage node N in parallel with
_SAnd the bit line BL.

In this circuit, only the read operation by applying the read voltage is possible, but in the write operation, the write voltage can be directly applied to the storage capacitor.

[0070] Further, in the circuit shown in FIG. 15 (d) connects the (4) the storage node N _S and the connected electrode and opposite to the installed other electrode of the reference capacitor C _REF to the bit lines BL , while disposed between the first R / W control transistor _Q storage the _{R / W1} in parallel with the reference capacitor C _REF node _{N S} and the bit line BL, and the second R / W control transistor Q _R the _{/ W2} are disposed between the storage node N _S and the plate electrode PE.

In this circuit, a read operation using precharge is possible, and further, a write voltage can be directly applied to the storage capacitor.

As described above, by adding a few elements to the basic configuration, it is possible to cope with various reading and writing modes.

In the circuit shown in FIG.
A ferroelectric capacitor may be used instead of the paraelectric capacitor as the reference capacitor _CREF . In this case, the first capacitor C _M0 of the memory cell row
Will be described as an example. Turn on Q _{R / W2} off transistor Q _{R / W1,} the precharge voltage V _P of the ferroelectric capacitor coercive voltage above the reference is applied between the plate electrode PE and the bit line BL, and for reference Polarize the capacitor in one direction. Next, the potential of the bit line BL is returned to the same potential as the plate electrode PE, the transistor Q _M0 is turned on, and the bit line BL connects the reference capacitor C _REF and the storage capacitor C _M0 in series with the plate electrode potential. _A read operation is performed by applying a read voltage _{VA in a} direction opposite to the precharge voltage. Operation diagram of the storage node N _S at this time can be understood that the reference capacitor basically similar operation using the paraelectric. In advance in accordance with the polarization state corresponding to a storage of "1" of the memory capacitor or "0", different voltage V _G ¹ or V _G ⁰ of the storage node N _S has is can be seen that to obtain. The storage node N read transistor has a gate electrode connected to the _S Q _READ discriminates storage state.

In writing, the transistor Q_{R / W1}To
Turn on the transistor Q _{R / W2}Off and
Transistor Q_M0Is turned on, and the
Storage capacitor C_M0To the write voltage V_ABy directly applying
Perform a write operation.

Next, as a storage capacitor, FIG.
As shown in FIG. 11A and FIG. 11B, a case where an asymmetric ferroelectric capacitor in which the center of ferroelectric hysteresis is shifted from 0 V will be described. Such asymmetric ferroelectric capacitors are often observed when using epitaxial ferroelectric films (eg, K. Abe, S. et al.
Komatsu, N. Yanase, K. Sano and T. Kawakubo: 'As
ymmetric Ferroelectricity and Anomalous Current Co
nduction in Heteroepitaxial BaTiO ₃ Thin Films', J
apan Journal of Applied Physics, Vol. 36, Part 1, N
o.9B, pp.5846-53 (1997)).

In an asymmetric capacitor, FIG.
As shown in (a), one polarization state is stable and the other polarization state is metastable, so that it cannot be used as a nonvolatile memory. However, FIG.
As shown in (2), by applying the voltage _Vf corresponding to the shift of the center of the hysteresis, the polarization in two directions can be stably held in the same manner as a normal ferroelectric capacitor. Therefore, the circuit of the present invention can be used as an SRAM (Static Random Access Memory) that statically holds a memory.

In other words, the standby
At the time, transistor Q_M0To Q _MNTurn on all
The capacitor C through the bit line_M0To C_MNAlways
The voltage V corresponding to the shift of the center of the hysteresis_fApply
To keep the memory stable. Meanwhile, read
When writing, the transistor Q_M0To Q_MNAll of
Turn off once and use the normal ferroelectric capacitor described above.
Read / write by the same sequence as when using
Can do it. FIG. 11A and FIG.
The center voltage has shifted positively as shown in FIG.
In a ferroelectric capacitor, the read voltage is set to a negative voltage,
For ferroelectric capacitors with center voltage shifted to negative,
It is advantageous in terms of circuit operation to make the output voltage a positive voltage.

Next, a paraelectric key is used as a storage capacitor.
A case where a capacitor is used will be described. FIG.
In the circuit shown in FIG.
_MNon-linear accumulation as a ferroelectric capacitor instead
Circuit example when a paraelectric capacitor with capacitance is used
It is. In the circuit shown in FIG.
1st capacitor C_M0The read operation is explained using an example.
I do. Transistor Q _{R / W}Is turned on and the transistor Q_M0
Is turned off, and the reference capacitor C is connected by the bit line BL.
_REFPrecharge voltage V_PTo apply precharge
Now. Next, the potential of the bit line BL is set to the plate electrode PE.
Return to the same potential, transistor Q_{R / W}Turn off and run
Jista Q_M0Is turned on to perform a read operation. This and
Storage node N_SThe operation diagram of FIG.
And FIG. 13 (b), where a ferroelectric
Behaves essentially the same as a storage capacitor
It can be understood. The storage capacitor "1" or
Depending on the polarization state corresponding to the storage of “0”, different
Storage node N_SVoltage V_G ¹Or V_G ⁰Can be obtained
I understand. Storage node N_SConnect the gate electrode to
Read transistor Q_READThe memory status judgment
Do another.

After reading out the memory contents of the first capacitor C _M0 of the NAND type memory cell column, the same sequence is repeated, whereby the capacitors C _M1 , C _M0,.
C _M2 ,... C _{Mk ,.} That is, when reading the memory contents of the capacitor C _Mk , all of the transistors Q _{R / W} and transistors Q _M0 to Q _{Mk = 1} are turned on, Q _Mk is turned off, and the bit line BL precharges the reference capacitor C _REF . applying a charge voltage V _P performs precharging. Next, the transistor QR _{/ W} is turned off and the transistor _QMk is turned on to perform a read operation.

Note that N using a paraelectric capacitor
As a problem of the AND-type cell column, when reading the memory content of the capacitor C _Mk , the read C _M0 of the capacitor C _Mk has already been read.
To C _Mk−1 are added as parasitic capacitance. If the parasitic capacitance becomes too large, the read operation is hindered. Therefore, in order to use a NAND cell array having a large number of storage cells, it is necessary to reduce the parasitic capacitance as much as possible.

In a normal capacitor using a silicon oxide film or a silicon nitride film, the dielectric constant is always constant irrespective of the bias voltage, so that each storage capacitor in the NAND cell row is used as a memory cell. The storage capacitance and the parasitic capacitance when acting as a parasitic capacitor on the front side of the memory cell are the same. Therefore, when the capacities of all the storage capacitors and the reference capacitors are set to be the same, the total capacity including the reference capacitors and the parasitic capacitors at the time of reading increases in proportion to the position of the storage capacitors to be read. become. That is,
When reading the k-th capacitor, the total capacitance of the read-side capacitor becomes k times the reference capacitor capacitance, and the read voltage decreases almost in inverse proportion to the increase in the total capacitance, so that the read transistor does not operate. .

One way to alleviate this problem is to use a dielectric film with a non-linear capacitance. The dielectric constant of a silicon oxide film or a silicon nitride film is constant because it is electronically polarizable, but an ionic polarizable dielectric such as a perovskite oxide ferroelectric has a bias voltage dependence of the dielectric constant, A capacitor having a non-linear capacitance characteristic can be created. FIG. 14 shows a large characteristic of a paraelectric capacitor having a large non-linearity measured by an epitaxial BSTO paraelectric film. become. Therefore, it is possible to effectively use a region having a large capacitance near 0 V when storing electric charges, and to apply a bias voltage by precharging and use a small capacitance region when acting as a parasitic capacitor. Become. By using such a non-linear capacitance capacitor, the N cell including many paraelectric capacitor memory cells can be used.
The use of an AND type memory cell column becomes possible. It is desirable that the peak capacitance value be at least twice the minimum capacitance value within the operating voltage range.

The write operation is the same as that of a ferroelectric capacitor. Transistor Q from the _{R / W} and Q _M0 turns on the Q _Mk, the storage capacitor C _Mk to the write voltage V _A applied directly by a bit line BL writing operation. As described above, the dielectric film of the reference capacitor may be a paraelectric or a ferroelectric. Even if the ferroelectric film is polarized in one direction in advance by precharging before the read operation, the read operation can be performed in the same manner as the paraelectric film. If the storage capacitor is a ferroelectric capacitor, the reference capacitor is also a ferroelectric capacitor, and if the storage capacitor is a paraelectric capacitor, the reference capacitor is also a paraelectric capacitor, and the storage capacitor is referred to as a ferroelectric capacitor. Capacitors can be created in the same process,
The simplification of the process and the improvement of the manufacturing yield can be achieved, and there is a great advantage.

Further, as described above, when a memory far from the reference capacitor is selected in the NAND type memory cell column, the paraelectric component of the storage capacitor existing between the reference capacitor and the selected storage capacitor is changed. Depending on the read mode, the data may be added to the capacitance of the reference capacitor or added to the capacitance of the selected storage capacitor, which may affect the storage read operation. In this case, the capacitance of the storage capacitor at each position is made as close as possible to 1: 1 with respect to the sum of the capacitance of the reference capacitor and the parasitic capacitance of the paraelectric component of the storage capacitor according to the read mode. It can be solved by adjusting to. Specifically, the remanent polarization amount of the storage capacitor farther from the reference capacitor is gradually increased or gradually reduced depending on the read mode, than the remanent polarization amount of the storage capacitor close to the reference capacitor. That is.

The ferroelectric capacitors for storage include PZT (lead zirconate titanate), SBT (strontium bismuth titanate), and epitaxial B
It is possible to use a thin film capacitor made of a ferroelectric curtain of STO (barium titanate / stringentium) type.
STO type capacitors are excellent.

It is also possible to use a dielectric film such as silicon oxide or tantalum oxide as the storage paraelectric capacitor. However, considering the absolute value of the capacitance and the magnitude of the nonlinearity, it is possible to use a dielectric film. BSTO-based paraelectric capacitors are particularly excellent. As a reference capacitor, silicon oxide, tantalum oxide, BSTO
And a ferroelectric capacitor described above.

The basic matter of the present invention has been understood above. Next, first to twelfth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. It goes without saying that the drawings include portions having different dimensional relationships and ratios.

(First Embodiment) FIG. 16 shows a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a circuit configuration of a main part of the semiconductor memory device according to the embodiment. As shown in FIG. 16, the semiconductor memory device according to a first embodiment of the present invention, capacitor C _M0 for a plurality of memories connected in series, C _M1, C _M2, ..., and C _{M1 5,} for the storage A storage cell array (storage cell chain) including control transistors connected in parallel to the capacitors C _M0 , C _M1 , C _M2 ,..., C _M15 , and a storage capacitor located at an end of the storage cell chain. C _M15 and reference capacitor C _REF which is connected to the read transistor Q having a gate electrode connected to a connection point of the reference capacitor C _REF and the storage capacitor C _M15 (connection node)
And _READ, constitute selection transistors connected with the memory capacitor C _M0 is positioned at the other end of the storage cell chain (block select transistor) Q _S at least provided with a memory cell block as the basic unit.

Each of the storage capacitors C _M0 , C _M1 , C _M2 ,
.., _CM15 are a first electrode, a second electrode disposed opposite to the first electrode, and a first electrode,
A ferroelectric thin film sandwiched between the second electrodes. The reference capacitor C _REF includes a third electrode electrically coupled to the first electrode of the storage capacitor C _M15, a fourth electrode disposed opposite to the third electrode, and a third electrode. At least a dielectric thin film sandwiched between the third and fourth electrodes. 8A and 8B correspond to the storage capacitors C _M0 , C _M1 ,
Note that the order of the arrangement of C _M2 ,..., C _M15 is reversed, but is merely a matter of order. In the semiconductor memory device according to the first embodiment, a plurality of memory cell blocks are arranged in a matrix.
Only two blocks [A] and two blocks [B] are shown. Block selection transistor Q _S of the upper column (column) of the block [A] is connected to the bit line BL0, the block select transistors Q _S of the lower column of the block [A] is connected to the bit line BL1. Further, the block selection transistor _{Q S} of the block [B] the upper column,
The bit line BL0, the block select transistors Q _S of the lower column is connected to the bit line BL1.

The storage capacitor C of the block [A]_M0,
C_M1, C_M2, ..., C_M15Are connected in parallel to
Each gate electrode of the control transistor has a word line WL0
^A, WL1^A, WL2^A, ..., WL15^AIs connected
I have. Similarly, the storage capacitor C of the block [B]_M0,
C_M1, C_M2, ..., C_M15Are connected in parallel to
Each gate electrode of the control transistor has a word line WL0
^B, WL1^B, WL2 ^B, ..., WL15^BIs connected
I have. Block selection transistor Q of block [A]_S
Each gate electrode of the
Do line BS^AIs the block selection transition of block [B].
Star Q_SEach gate electrode has a block select transistor
Word line BS^BIs connected. Block [A]
Reference capacitor C_REFHas a reference key on the gate electrode.
Capacitor control transistor Q_REFWord line WR^AContact
Connected control transistor Q_REFIs the block [B]
Reference capacitor C_REFHas a reference capacitor on the gate electrode.
Word line WR of the transistor for transistor control^BWas connected
Control transistor Q_REFIs connected.

One main electrode of the read transistor Q _READ of each memory cell block has a read power supply line V
L ^A and V L ^B are provided on the other main electrode, and the read output line SL is provided on the other main electrode.
^A, is connected SL ^B. In this embodiment, 2 are alternately connected to the read transistor Q _{RE AD}
A set of read output lines SL ^A and SL ^B is provided. Further, a plate line PL is connected to a connection point between the reference capacitor control transistor of the block [A] and the reference capacitor control transistor of the block [B]. In FIG. 16, the storage capacitors C _M0 ,
C _M1, C _M2, ..., each parallel-connected control transistor, the read transistor Q _{R EAD,} block select transistors _{Q S,} and the reference capacitor control transistor Q _REF of C _{M1 5} is indicated by nMOSFET However, it is also possible to use a pMOSFET.

FIG. 17 shows a connection diagram including peripheral circuits. Each word line WL0 ^A , WL of block [A]
^{1 A, WL2 A, ...,} WL15 A , the row decoder A4
02, each word line WL0 ^B , WL1 of block [B]
^{B, WL2 B, ..., WL15} B is the row decoder B401
, Each bit line BL0, BL1,.
11 is connected.

In the configuration shown in FIGS. 16 and 17,
BLx (x = 0, 1) and WLy in block [A]
^{A (y = 0,1,2, ...,} 15) to select the desired memory cell specified by the intersection of the word line BS ^A "1
Block selected as the (high level) "transistor _{Q S}
Is turned on, only WLy ^A is set to “0 (low level)”, the control transistor connected to the storage capacitor C _My is turned off, the other WL ^{A is set} to “1”, and the potential is kept constant {for example, (1) / 2) to the plate line PL V _G}, it is achieved by adding a potential to BLx. At the time of reading, off the word line WR ^A reference capacitor control transistor to turn on the word line WR ^A at the time of writing. Similarly, BLx (x = 0, x = 0) in block [B]
1) and WLy ^B (y = 0, 1, 2,..., 15) to select a desired memory cell specified by the word line B
Turn on the block selection transistors _{Q S} as the S ^B "1", only WLy ^B "0" as to clear the connected control transistor in the storage capacitor C _My, the other WL ^B "1" And constant potential ｛for example (1/2)
To the plate line PL of V _G}, is achieved by adding a potential to BLx. At the time of reading, the word line WR ^B of the reference capacitor control transistor "0", when writing to "1" to the word line WR ^B.

FIG. 18 shows a read / write sequence when the “precharge read method” is further employed. That is, in the precharge read method, before selecting WLy ^A and WLy ^B , a reverse voltage is applied to the capacitor of the reference capacitor C _REF to select WLy ^A and WLy ^A.
By applying a positive voltage after selecting WLy ^B , a voltage approximately twice that of the storage capacitor C _My is substantially applied and the storage capacitor C _My is inverted.

FIG. 19A shows a memory cell block.
FIG. 19B is a plan view showing a section shown in FIG.
Only the layer below the level of line A-A 'in the figure is shown.
In FIG. 19A, n⁺Source / drain region 2
Word lines BS serving as polysilicon gate electrodes 1 and 22
^BAnd the block selection transistor Q of the block [B]
_SIs configured. Here, "n⁺Source / drain
"Region" means the source region or drain of the MOSFET
Any meaning of the application area. Usually, MOSFET saw
The source and drain regions are centered on the gate electrode.
Since it is formed symmetrically,
Or MOSFET drain region
Is just a matter of name. n⁺Source / Dre
The in region 21 functions as a “bit line connection unit”.
Similarly, n⁺Source / drain regions 22 and 23 and policy
Word line WL0 serving as a recon gate electrode^BAnd the block
[B] storage capacitor C_M0Control connected in parallel
Transistors are configured. Furthermore, n⁺Source
/ Drain regions 23, 24 and word line WL1^BAnd
Storage capacitor C_M1Control transistors connected in parallel
Is n⁺Source / drain regions 24, 25 and word line
WL2^BAnd the storage capacitor C_M2Connected in parallel
The control transistors are ..., n⁺Source / drain regions
26 (not shown), 27 and word line WL15^BAnd
Storage capacitor C_M15Control transistors connected in parallel to
A star is formed. n⁺Source / drain region 2
, 26, each storage capacitor C_M0, C
_M1, C_M2, ..., C_M15The first electrode or the second electrode
, 44 are connected.
ing. And n⁺The source / drain regions 31 and 32 are
The silicon gate electrode 531 or the regions 32 and 33
And the gate electrode 532, the read transistor Q_{RE AD}
Are formed. n⁺The source / drain region 31
The readout output line SL formed along the column (row) direction
^BAnd n⁺Source / drain regions 32 are also columns
(Power supply line VL)^BCum
I'm sleeping. And n⁺Source / drain regions 28, 2
9 and word line WR^BWith the reference capacitor control transformer
A resistor is formed. n⁺Source / drain region 2
9 functions as a "plate line connection part",
PL is connected. This plate line PL is for reference.
Capacitor C_REFLower electrode functioning as a fourth electrode
Also serves as 45. Mainly on block [B]
As will be described, block [A] has the same structure as block [B].
It is equipped with

As shown in FIG. 19A, one block [A] sandwiched between the bit line connection portion and the plate line connection portion
Or in the block [B], respectively block select transistors _Q S, n pieces of the memory capacitor C _M0, C _M1,
C _M2 , C _M3 ,..., C _M15 and n control transistors connected in parallel to them, readout transistor Q
_READ , a reference capacitor C _REF , and a reference capacitor control transistor. Storage cell size is 4F
^2, a region other than the memory cell including the contact portion per block since it is 28F ^2, it becomes 1 per memory cell (4 + 28 / n) F 2. In the first embodiment, since a ferroelectric capacitor having a residual polarization of ²⁰ μC / cm ² was used, it was found that stable operation was achieved even when 16 memory cells were connected in series. Therefore, the size was 5.8F ² per piece.

FIG. 19B is a cross-sectional view taken along the line BB ′ of the plan view shown in FIG. 19A. As shown in FIG. 19B, in the semiconductor memory device according to the first embodiment of the present invention, a p-well 12 is formed on a semiconductor substrate 11, and n ⁺ source / drain regions are formed on the surface of the p-well 12. 2
, 30 are provided. Then, p on the gate oxide film on the surface of the well 12, a polysilicon gate electrode word lines ^{BS B, WL0 B, WL1 B} ,
WL2 ^B, ..., have WL15 ^B, WR ^B and WR ^A. The cross section of the wiring portion of the polysilicon gate electrode 532 is also exposed in the cross-sectional view of FIG. FIG. 19B shows a single-layer polysilicon gate electrode, but instead of the single-layer polysilicon gate electrode,
A two-layer structure including a polysilicon gate layer and a W gate layer may be used. In addition to the W gate layer, a refractory metal such as Ti, Mo, or Co, or WSi ₂ , TiSi ₂ , MoS
Silicide of a high melting point metal such as i ₂ or CoSi ₂ may be used.

N⁺Source / drain regions 21 and 22
Lead wire BS^BAnd the block selection transistor Q_SBut
Has been established. n⁺Source / drain regions 22 and 23
Word line WL0^BAnd the storage capacitor C_M0Parallel connection
A continuous control transistor is configured. Further
And n⁺Source / drain regions 23, 24 and word line W
L1^BAnd the storage capacitor C_M1Connected in parallel to
Your transistor is n ⁺Source / drain regions 24,
25 and word line WL2^BAnd the storage capacitor C_M2To
The control transistors connected in parallel are..., N⁺Source
/ Drain regions 26 (not shown), 27 and word line WL
Fifteen^BAnd the storage capacitor C_M15Connected in parallel
A control transistor is formed. And n⁺Seo
Source / drain regions 28 and 29 and word line WR^BAnd
A reference capacitor control transistor is formed.
Word line BS^B, WL0^B, WL1^B, WL2^B,…,
WL15^B, WR^BAnd WR^AAn oxide film (Si
O_TwoFilm), PSG film, BPSG film, nitride film (Si3N4
A first interlayer insulating film 13 made of a film or the like is formed.
Each storage capacitor is provided on the first interlayer insulating film 13.
C_M0, C_M1, C_M2, C_{M3 3}, ..., C_M15First electrode of
Alternatively, lower electrodes 42 and 4 functioning as second electrodes
3,... And 45 are formed. In addition, the first
On the interlayer insulating film 13, a reference
Illumination capacitor C_REFLower part functioning as the fourth electrode of
An electrode 45 is also formed. , Lower electrodes 42, 43,.
And 45 are components provided in the first interlayer insulating film 13.
Contact formed to fill contact hole
By the plugs 73, 75 and 80, n⁺Source / drain
, 29 are connected. These
Contact plug is made of polycrystalline silicon with impurities
(Doped polysilicon), high melting point metal or high melting point metal
What is necessary is just to comprise with silicide etc. The lower electrode 42 is
Capacitor C_M0First electrode and storage capacitor
C_M1Function as a second electrode. The lower electrode 43 is
Storage capacitor C_M2First electrode and storage capacity
TA C_M3Function as a second electrode. ... Lower electrode 44
Is the storage capacitor C_M14First electrode for storage
Capacitor C_M15Function as a second electrode. Lower part
The poles 42, 43,..., 44, 45 have a film thickness of 10 nm (T
i, Al) N lower barrier metal layer and 20 n film thickness
m of SrRuO_ThreeComposed of a two-layer structure with a lower electrode made of
do it. Then, the lower electrodes 42, 43,.
4, for example, a B-rich composition B having a thickness of 25 nm
Forming ferroelectric thin films 51, 52,...
Formed and patterned. Also, the reference capacity
TA C_REFOf Sr having a thickness of 25 nm
Forming a paraelectric thin film 54 such as a BSTO thin film having a rich composition
do it. The reference capacitor C_REFParaelectric for
As the body thin film 54, silicon oxide (SiO 2)_Two), Oxidation
Tantalum (Ta₂O_Five) May be used.
A membrane can be used. Ferroelectric thin films 51, 52,
, 53, the first in which the paraelectric thin film 54 is not formed
An oxide film (SiO 2) is formed on the interlayer insulating film 13._TwoMembrane), PS
G film, BPSG film, nitride film (SI₃N₄Film) etc.
A second interlayer insulating film 14 is formed, and the second interlayer insulating film 14 is formed.
, 63 are formed on the film 14.
Have been. The upper electrode 61 is connected to the storage capacitor C_M0of
Functions as a second electrode. The upper electrode 62 is
Japashita C_M1First electrode and storage capacitor C_M2
Function as a second electrode. ... The upper electrode 63 is a memory
Capacitor C_M15First electrode and reference capacity
TA C_REFFunction as a third electrode. Upper electrode 61,
62,..., 63 are SrRuO having a thickness of 20 nm._ThreeFrom the membrane
Upper electrode and a film thickness of 10 n formed thereon.
m (Ti, Al) N upper barrier metal layer with a two-layer structure
, 63, 64 which may be formed.
Are a first interlayer insulating film 13 and a second interlayer insulating film 14
To fill the contact hole provided through
Contact plugs 72, 74, 77, 79 formed in
Gives n⁺Source / drain regions 22, 24, ..., 2
7 and 28. These contact plugs
72, 74, 77, 79 are doped polysilicon, high
It should be composed of high melting point metal or high melting point metal silicide, etc.
No. Further, the upper electrode 63 is formed on the first interlayer insulating film 13 and
And a contour provided through second interlayer insulating film 14.
The read transistor Q is connected via the
_READConnected to the wiring portion 532 of the polysilicon gate electrode.
ing. The wiring portion 532 of the polysilicon gate electrode is
In order to provide the contact plug 78,
It is patterned thicker than the silicon gate electrode.
An oxide film (Si) is formed on the upper electrodes 61, 62,.
O_TwoFilm), PSG film, BPSG film, nitride film (Si₃N₄
A third interlayer insulating film 15 made of a film or the like is formed.
On the third interlayer insulating film 15, a bit line 16 is formed.
Have been. Bit line 16 and n⁺Source / drain region 2
1 means first to third interlayer insulating films 13, 14, 15
Bit line contact plugs 71 penetrating through
It is connected. The bit line contact plug 71 is
Doped polysilicon, high melting point metal or high melting point metal silicator
What is necessary is just to comprise with an id etc. Although illustration is omitted,
An oxide film (SiO 2) is formed on the bit line 16._TwoMembrane), PS
G film, BPSG film, nitride film (Si₃N₄Membrane) or
Forming a passivation film such as a polyimide film
Is preferred. Mainly explained about block [B]
However, the block [A] has a similar configuration.
With such a circuit configuration, a highly integrated nonvolatile memory
The operation of the moly was confirmed.

(Second Embodiment) FIG. 20 shows a second embodiment of the present invention.
FIG. 21 shows a circuit configuration of a main part of the semiconductor memory device according to the embodiment, and FIG. 21 is a diagram showing a main configuration including peripheral circuits as in FIG. The second embodiment has a structure in which an operating voltage is applied between adjacent bit lines without using the plate line shown in the first embodiment.

[0100] As shown in FIG. 20, the semiconductor memory device according to the second embodiment, the capacitor C _M0 for a plurality of memories connected in series, C _M1, C _M2, ..., and C _M15, the storage capacitor A memory cell array (memory cell chain) composed of control transistors connected in parallel to each of C _M0 , C _M1 , C _M2 ,..., C _M15 , and a “reference” the cell and selection transistor series circuit (block select transistor) Q _S ", the sub-blocks and a read transistor Q _rEAD having a gate electrode connected to the other end of the memory cell chain constructed as a basic unit ing. Here, the “reference cell” is, as already defined, a reference capacitor C
It comprises a parallel circuit of _REF and a reference capacitor control transistor. The storage capacitors C _M0 , C _M1 , C _M2 ,..., C
_M15 includes at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes. I have. The reference capacitor C _REF is connected to a third electrode,
And a dielectric thin film sandwiched between the third and fourth electrodes. The "reference cell and the selection transistor series circuit (block select transistor) Q _S" is
There are two combinations, and when the third electrode of the reference capacitor C _REF is connected to the first electrode of the memory capacitor C _M0, block selection transistor Q _S is the first storage capacitor C _M0 It may be connected to an electrode.

In the semiconductor device according to the second embodiment, a plurality of the memory cell blocks are arranged in a matrix, but one read transistor Q _{READ is provided.}
Is divided into two sub-blocks, a sub-block [A] on the right and a sub-block [B] on the left. FIG.
In FIG. 3, only two sub-blocks [A] and two sub-blocks [B] are shown. FIG.
In the first sub-block [A] and the second sub-block [B], the third electrode of the reference capacitor C _{REF is connected to} the first electrode of the storage capacitor C _M0 . It is connected. On the other hand, the column of the second stage sub-block [A], and the sub-block [B] of the first stage of the column, block selection transistor Q _S is connected to a first electrode of the memory capacitor C _M0. The fourth electrode of the reference capacitor _CREF of the sub-block [B] of the first column is connected to the bit line BL0. Reference capacitor C of sub-block [A] of the second column
The the _REF 4 electrodes, and block selecting transistors Q _S of the first stage of the column sub-block [A] is the bit line B
L1. Further, the fourth electrode of the reference capacitor C _REF in the sub-block [B] of the second column is connected to the bit line BL2.

The block of the first column of the sub-block [A]
Lock selection transistor Q_SGate electrode and two stages
The gate of the reference capacitor control transistor in the eye column
Are connected to the word line WR0, respectively.^AIs connected
You. Also, referencing the first column of the sub-block [A]
Gate electrode of capacitor control transistor for
Block select transistor Q of the second column_SIn the
Each word line WR1 ^AIs connected. Meanwhile, sub
Reference capacitor system for the first column of block [B]
The gate electrode of the control transistor and the second stage column
Block select transistor Q_SEach has a word line
WR0^BIs connected. And the sub-block
Block select transistor Q in the first column of [B]
_SGate electrode and reference capacity of the second column
Each of the gate electrodes of the
Wire WR1^BIs connected.

Storage capacitor C of sub-block [A]
_M0, C_M1, C_M2, ..., C_M15Are connected in parallel to each
Each gate electrode of the control transistor has a word line W
L0 ^A, WL1^A, WL2^A, ..., WL15^AIs connected
Have been. Similarly, the storage capacity of the sub-block [B]
TA C_M0, C_M1, C_M2, ..., C_M15Connected in parallel to each
A word is applied to each gate electrode of the
Line WL0^B, WL1^B, WL2^B, ..., WL15^BContact
Has been continued. Sub-block [A] and sub-block
Read transistor Q located at the center of [B]
_READThe read power line VL is connected to one of the main electrodes.
The read output line SL is connected to the other main electrode.
In this embodiment, two sets of read output lines SL are used.
In other words, they are connected alternately for each column. FIG.
0, the storage capacitor C_M0, C _M1, C_M2,…,
C_M15Control transistors connected in parallel to each other
Data, readout transistor Q_READ, Block selection tiger
Transistor Q_SAnd reference capacitor control transistors
Are shown as nMOSFETs, but pMOSFE
It is also possible to configure with T.

FIG. 22 shows a read / write sequence of the semiconductor memory device according to the second embodiment. In the semiconductor memory according to the second embodiment of the present invention, FIG.
In the circuit configuration shown in FIG. 21, an operation voltage is applied between adjacent bit numbers BLx and BLx + 1. Therefore, it has a structure in which one word line is driven alternately reference capacitor control transistor and block select transistors Q _S for each column.

[0105] As an example, consider a case of selecting a memory capacitor C _M1 of the second stage of the column located at the intersection between the bit line and the word line WL1 ^A sub-block [A]. Word lines WR0 ^A and WR1 of sub-block [A]
The ^A, as "1", the reference capacitor control transistors and block selection transistor Q _S of the column of the second stage sub-block _[A], and a conductive state (ON). At the same time, the word line WR0 ^B sub-block [B] is set to "1", and on the block selection transistors _{Q S} of the column of the second stage sub-block [B]. At this time, only the word line WR1 ^B of the sub-block [B] is set to “0”. That is, only the reference capacitor control transistor in the sub-block [B] of the second column is cut off (off).
And the reference capacitor C _REF is selected. This state is the equivalent circuit shown in FIG. 8 (a) block selection transistor Q _S corresponds to the case on. Then only WL1 ^A "0", and WL of the ^A "1" otherwise, selects the memory capacitor C _M1 of the column in the second stage. This state is equivalent circuit shown in FIG. 1 or FIGS. 7 (a) through FIG. 7 (c), the connected control transistor in parallel with the storage capacitor C _M is equivalent to the case of off. That is, the first electrode, the second electrode, and the first of these, a storage capacitor C _M for a ferroelectric thin film sandwiched between the at least comprising the second electrode, the first storage capacitor C _M At least a third electrode connected to the third electrode, a fourth electrode facing the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes. a reference capacitor C _REF, the first electrode and the equivalent circuit composed of a capital the read transistor Q _rEAD having a third gate electrode connected to the electrode of the reference capacitor C _REF of the memory capacitor C _M is realized It will be. In this state, a read / write voltage may be applied between the bit lines BL1 and BL2. That is, the bit line BL1 is set to “1”.
If the bit line BL2 is set to "0", a voltage of "1" can be applied between the storage capacitor _CM1 and the reference capacitor _CREF .

[0106] At this time, between the bit lines BL0-BL1, and although a voltage is also applied between the bit lines BL2-BL3, the word line WR1 ^B is the first and third stages of the column because it is "0" block selection transistor Q _S of the sub-block [B] is in the oFF state, no voltage applied to the storage capacitor C _M1 of the column of the first and third stages. That is, the block select transistors Q _S of the upper and lower columns in the column as an object is turned off, the voltage applied to the bit line is not applied to the blocks of these adjacent column.

When selecting the storage cell of the sub-block [B], the reference capacitor of the sub-block [A] is selected, and the equivalent circuit shown in FIG. 1 or FIGS. 7 (a) to 7 (c) is selected. in the circuit, connected control transistor in parallel with the storage capacitor C _M that is of course to achieve the case of off.

[0108] In the semiconductor memory device according to a second embodiment of the present invention, advantage since it is possible to apply a voltage between two adjacent bit lines, a voltage can be applied substantially ± V _C to the cell There is. The write operation is also performed via the reference capacitor _CREF . Others are almost the same as the semiconductor memory device according to the first embodiment.

FIG. 23A is a plan view showing a memory cell block. For simplification, A in FIG.
Only the layer below the level of the -A 'plane is shown. FIG.
In (a), the n ⁺ source / drain regions 281 and 21 of the first column and the word line WR0 ^B form a reference capacitor control transistor of the sub-block [B]. The n ⁺ source / drain region 281 also functions as a connection to the bit line BL0. n ⁺ source /
The fourth region of the reference capacitor C _REF is provided in the drain region 21.
The lower electrode 66 functioning as an electrode is connected.
Then, in the ^{n +} source / drain regions 21 and 22 and the polysilicon gate electrode to become the word lines WL1 ^B, the block select transistors _{Q S1} is formed. Similarly,
In the n ⁺ source / drain regions 22 and 23 and the polysilicon gate electrode to become the word line WL0 ^B, parallel to the storage capacitor C _M0 connected control transistor is configured. Further, n ⁺ source / drain regions 23 and 24
And word line WL1 ^B , form a control transistor connected in parallel to storage capacitor C _M1 . N ⁺ source / drain regions 26 (not shown), 27 and word line WL
In the 15 ^B, parallel to the storage capacitor C _M15 connected control transistor is formed. Each of the n ⁺ source / drain regions 23 and 25 has a storage capacitor C _M0 ,
C _M1, C _M2, ..., the lower electrode 43 functions as a first electrode or the second electrode of the C _M15, ..., 44 are connected. The n ⁺ source / drain regions 31 and 32 and the polysilicon gate electrode 531 form a read transistor Q _READ . The n ⁺ source / drain regions 31 and 32 are formed in parallel with the word lines, and also serve as the read power supply lines VL. And n ⁺ source / drain region 282 of the block select transistor Q _{S 0} of the column of the second stage, the connection electrode and the n ⁺ source / drain region 283 of the reference capacitor control transistor of the third-stage column (not shown) Are connected to each other. Although mainly the block [B] has been described, the block [A] has a similar configuration.

As shown in FIG. 23A, a block selection transistor Q _S and n storage capacitors C _M0 , C _M1 , C are provided in a sub-block [A] or a sub-block [B] of each column, respectively. _M2 ,..., C _M15 and n control transistors connected in parallel to them, a read transistor Q _READ , a reference capacitor C _REF , and a reference capacitor control transistor. The size of one memory cell is 4F ² , and the area other than the memory cell including the contact portion per sub-block is 16F ² , so that one memory cell has (4 + 16 / n) F ² . Second
In the semiconductor memory device according to the first embodiment, since a ferroelectric capacitor having a remanent polarization of ²⁰ μC / cm ² was used, it was found that stable operation was achieved even when 16 memory cells were connected in series. . Therefore, the size of each piece was 5.0 F ² .

FIG. 23B is a plan view showing the plane shown in FIG.
It is sectional drawing along the B-B 'direction of the figure. FIG. 23 (b)
As shown in FIG. 7, a semiconductor memory according to a second embodiment of the present invention
The device forms a p-well 12 on a semiconductor substrate 11 and
N surface of the p-well 12 ⁺Source / drain region 2
81, 21, 22, 23,..., 27 are provided. Soshi
Then, a policy is formed on the gate oxide film on the surface of the p-well 12.
Word line WR0 serving as a recon gate electrode^B, WR1^B,
WL0^B, WL1^B, WL2^B, ..., WL15 ^BHas
ing. Note that the cross-sectional view of FIG.
Transistor Q _READPolysilicon gate electrode
The cross section of the wiring portion 531 is also exposed. Where these
W, Ti, M instead of the polysilicon gate electrode
o, Co or other high melting point metal or WSi₂, TiSi
₂, MoSi₂, CoSi₂Of high melting point metals such as
May be used.

N⁺Source / drain regions 281, 21
Word line WR0^BAnd the reference key for sub-block [B].
A capacitor control transistor is formed. Also, n
⁺Source / drain regions 21, 22 and word line WR1^B
And the block selection transistor Q_S1Is composed of
You. n⁺Source / drain regions 22 and 23 and word line W
L0^BAnd the storage capacitor C_M0Connected in parallel to
A control transistor is configured. Furthermore, n⁺Saw
/ Drain regions 23, 24 and word line WL1 ^BAnd
Storage capacitor C_M1Control transistors connected in parallel to
Star is n⁺Source / drain regions 24, 25 and word
Line WL2^BAnd the storage capacitor C_M2Connected in parallel
, N⁺Source / drain area
Regions 26 (not shown), 27 and word line WL15^BAnd
Storage capacitor C_M15Control transformer connected in parallel to
A resistor is formed. Also, on the cross section in the B-B 'direction
Is not exposed⁺The source / drain regions 31 and 32 are
Read transistor with the silicon gate electrode 531
TA Q_READAre formed. Word line WR0^B, WR1
^B, WL0^B, WL1^B, WL2^B, ..., WL15^B,
An oxide film (SiO 2) is formed on the polysilicon gate electrode 531.
_TwoFilm), PSG film, BPSG film, nitride film (Si₃N
₄A first interlayer insulating film 13 made of a film or the like is formed.
Of the reference capacitor C on the first interlayer insulating film 13 of FIG.
_REFA lower electrode 66 functioning as a fourth electrode of
Each storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C
_M15Function as the first or second electrode of
, 44 are formed. Lower part
The poles 66, 42, 43,..., 44 are the first interlayer insulating film 1
3 so as to fill the contact hole provided in
By the formed contact plugs 83, 73, 75, n
⁺Connected to source / drain regions 21, 23, 25
You. These contact plugs are
Made of high melting point metal or high melting point metal silicide
I just need. The lower electrode 66 is a reference capacitor C_REFThe third
And the lower electrode 42 is a storage capacitor.
C_M0Second electrode and storage capacitor C_M1The first of
Functions as an electrode. The lower electrode 43 is a storage capacitor.
TA C_M2Second electrode and storage capacitor C_M3First
Functions as an electrode. The lower electrode 44 is a storage capacitor.
Sita C_M14Second electrode and storage capacitor C_M15of
It functions as a first electrode. And this lower electrode 4
BSTO of Ba-rich composition
Forming ferroelectric thin films 51, 52,...
What is necessary is just to pattern. Also, the reference capacitor C
_REFA paraelectric thin film 55 is formed on the lower electrode 66 of FIG.
do it. The reference capacitor C_REFParaelectric
What is necessary is just to form the thin film 55. The reference capacitor C
_REFA paraelectric thin film can be used. Paraelectric
The body thin film 55 and the ferroelectric thin films 51, 52,..., 53 are formed.
An oxide film is formed on the unprocessed first interlayer insulating film 13.
(SiO_TwoA second interlayer insulating film 14 made of a film or the like is formed.
The upper electrode 6 is formed on the second interlayer insulating film 14.
5, 61, 62,..., 63 are formed. Upper electrode
65 is a reference capacitor C_REFMachine as the fourth electrode
Works. The upper electrode 61 is connected to the storage capacitor C_M0No.
It functions as one electrode. The upper electrode 62 is
Pasita C_M1Second electrode and storage capacitor C_M2of
It functions as a first electrode. The upper electrode 63 is
Japashita C_M15Function as a second electrode. Upper electrode
, 63 are the first interlayer insulating film 13.
And a capacitor provided through second interlayer insulating film 14.
Formed to fill tact holes
By the lugs 82, 72, 74, 77, n⁺Source / Dre
, 27, 22, 24,..., 27
You. These contact plugs 82, 72, 74, 77
Of doped polysilicon, refractory metals and refractory metals
What is necessary is just to comprise with silicide etc. Further, the upper electrode 63
Are a first interlayer insulating film 13 and a second interlayer insulating film 14
Through a contact plug 78 provided through
Read transistor Q_READPolysilicon gate voltage
It is connected to the wiring part 531 of the pole. Upper electrodes 65, 6
, 63, an oxide film (SiO 2)_TwoMembrane)
A third interlayer insulating film 15 made of
On the interlayer insulating film 15, a bit line 16 is formed.
You. The bit line 16 and the upper electrode 65 are connected to the third interlayer insulating layer 1.
5 through bit line contact plugs 84
It is connected to the. The bit line contact plug 84
Doped polysilicon, refractory metal or silicide of refractory metal
What is necessary is just to comprise with an id etc. Although illustration is omitted,
An oxide film (SiO 2) is formed on the bit line 16._TwoMembrane), PS
G film, BPSG film, nitride film (Si₃N₄Membrane), or
Forming a passivation film such as a polyimide film
Is preferred.

With the circuit configuration shown in FIG. 23B, which is a cross-sectional view corresponding to the plan view shown in FIG. 23A, the operation of a highly integrated nonvolatile memory has been confirmed.

(Third Embodiment) FIG. 24 shows a circuit configuration of a main part of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 25 shows a main part of the semiconductor memory device including peripheral circuits. It is a figure which shows in detail. In the semiconductor memory device according to the third embodiment, one block sandwiched between a pair of drive lines (DL ^A and DL ^B ) is divided into two sub blocks centering on one read transistor. I have.

As shown in FIG. 24, a third embodiment of the present invention
The semiconductor memory device according to the embodiment includes a plurality of serially connected storage devices.
Storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C
_M15And the storage capacitor C_M0, C_M1, C_M2,
C_M3, ..., C_M15Control tors connected in parallel to
A memory cell array composed of transistors (memory cell chain)
And the storage cap located at the end of the storage cell chain.
Pasita C_M15And the reference cell connected to
Readout transistor Q having a broken gate electrode
_READAnd the storage located at the other end of the storage cell chain
Capacitor C_M0Connected to the block selection
Star) Q_SA memory cell block having at least
It is configured as a basic unit. Here, "Reference
Is the reference capacitor C _REFAnd reference capacitor system
It consists of a parallel circuit with a control transistor. Each storage capacity
Sita C_M0, C_M1, C_M2, C_M3, ..., C_M15Respectively
A first electrode, a second electrode disposed opposite to the first electrode;
Electrode, and the strength sandwiched between the first and second electrodes.
At least a dielectric thin film.

The reference capacitor C _REF is connected to the third electrode electrically connected to the first electrode of the storage capacitor C _M15 .
, A fourth electrode disposed opposite to the third electrode, and a dielectric thin film sandwiched between the third and fourth electrodes. In the semiconductor memory device of the present invention, a plurality of the memory cell blocks are arranged in a matrix. 24, four sub-blocks [A] and four sub-blocks [B]
, And only four totals of eight are shown. Block selection transistor Q _S of the block selection transistors Q _S, and the first stage of the column subblock [B] of the second stage of the column sub-block [A] is connected to the bit line BL0. Similarly, the block select transistors Q _S of the block selection transistor Q _S of the column of the second stage sub-block _[A], and the second stage of the column subblock [B] is connected to the bit line BL1. further,
Of the third-stage and fourth-stage column, each two block selection transistors Q _S are respectively connected to the bit line BL2 and bit line BL3. The main electrodes of which is not connected to the memory cell block selection transistors Q _S of the sub-block [A] is the drive line DL ^A, which is not connected to the memory cell block selection transistors Q _S of the sub-block [B] the main electrodes are connected to the drive line DL ^B.

The storage capacitor C of the sub-block [A]
_M0, C_M1, C_M2, ..., C_M15Are connected in parallel to each
Each gate electrode of the control transistor has a word line W
L0 ^A, WL1^A, WL2^A, ..., WL15^AIs connected
Have been. Similarly, the storage capacity of the sub-block [B]
TA C_M0, C_M1, C_M2, ..., C_M15Connected in parallel to each
A word is applied to each gate electrode of the
Line WL0^B, WL1^B, WL2^B, ..., WL15^BContact
Has been continued. Reference capacitor of sub-block [A]
The word line WR is connected to the gate electrode of the control transistor.^ABut
Connected, reference capacitor control of sub-block [B]
The gate electrode of the transistor has a word line WR^BIs connected
Have been. Readout traverse for the first and third columns
Transistor Q_READ ^BOne main electrode has a power supply for reading
The line VL is connected to the read output line SL on the other main electrode.^AContact
Has been continued. On the other hand, reading the second and fourth columns
Transistor Q_READ ^AOne main electrode
Power supply line VL, and the read output line S on the other main electrode.
L^BIs connected. In FIG. 24, the storage capacity
Sita C_M0, C_M1, C_M2, C_M3, ..., C_M15Average for each
Column-connected control transistor, read transistor
Star Q_READ ^A, Q_READ ^B, Block select transistor Q
_S, And the reference capacitor control transistor are nM
Although shown by OSFET, it is constituted by pMOSFET.
It is also possible.

FIG. 26 shows a read / write sequence of the semiconductor memory device according to the third embodiment of the present invention. In the semiconductor memory device according to the third embodiment of the present invention,
The bit number BLx serves to select a block along a specific column, and the application of the read / write voltage is performed through two adjacent drive lines DL ^A and DL ^{B. A} voltage is also applied to the block adjacent on the opposite side, but the word line WR ^A or the word line WR ^{B is set} to “0”.
If the reference capacitor control transistor in the block is turned off, no problem occurs.

When selecting the memory cell of the sub-block [A], the reference capacitor of the sub-block [B] is selected, and when selecting the memory cell of the sub-block [B], the memory of the sub-block [A] is selected. Select a reference capacitor.

In the third embodiment, two drive lines DL ^A
And a voltage can be applied between DL ^B and
There is an advantage that a voltage of substantially ± V _C can be applied to the cell. Others are almost the same as the first embodiment.

For example, in the circuit configuration shown in FIG.
Subblock To select memory cell C _M1 of the column of the second stage specified by the intersection of BL1 and WL1 ^A in [A] is
The bit line BL1 is set to "1", the block selection transistors _{Q S} of the sub-blocks [A] and the sub-block [B]
Turn on both. Then, a "1" to the word line WR ^A, selects the reference capacitor C _REF of the sub-block [A]. Then, only WL1 ^A sub-block [A] to "0", if only the "1" other WL ^A 2
The storage cell C _{M1 in the} second column can be selected. Then, with the memory cell C _M1 selected, the two drive lines DL ^A
If a voltage is applied between DL and DL ^B, the read output line S
^A signal can be read to LA.

FIG. 27A is a plan view showing a memory cell block. For simplification, AA ′ in FIG. 27B is used.
Only the layers below the plane level are shown. In FIG. 27 (a), the in the ^{n +} source / drain regions 321,22 and the polysilicon gate electrode 331, the block select transistors _{Q S} of the sub-block [B] is formed. The n ⁺ source / drain region 321 functions as a connection with a drive line. Further, n ⁺ source / drain regions 22,
23 and a word line WL0 ^{B serving as} a polysilicon gate electrode
Thus, a control transistor connected in parallel to the storage capacitor _CM0 of the sub-block [B] is configured. Further, a control transistor connected in parallel to the storage capacitor C _M1 by the n ⁺ source / drain regions 23 and 24 and the word line WL1 ^B is connected to the n ⁺ source / drain region 2
4, 25 and the word line WL2 ^B , the storage capacitor C
Parallel-connected control transistor in _M2 is, ..., n ⁺ source / drain regions 26 (not shown), between 322 and word line WL15 ^B, parallel-connected control transistor in the storage capacitor C _M15 is formed Have been. n ⁺ source / drain regions 23 and 25, each of the memory capacitor _{C M0, C M1, C M2} , C M3, ..., the lower electrodes 42 and 43 functioning as the first electrode or the second electrode of the C _M15,
, 44 are connected. Then, in the ^{n +} source / drain regions 322 and 323 and the word line WR ^B, reference capacitor control transistor are formed. And n
^{The +} source / drain regions 324 and 325 and the polysilicon gate electrode 332 form a read transistor Q _READ . The read power line VL is connected to the n ⁺ source / drain region 325. Polysilicon gate electrode 334 corresponds to the read capacitor control transistors in a column of the second stage Q _{RE AD.} Further, the polysilicon gate electrode 333, the block selection transistor Q _S column of the second stage, the polysilicon gate electrode 3
35 is a block select transistor Q of the third stage column
To _S, the polysilicon gate electrode 337 corresponds to the block select transistor Q _S column of the fourth stage. In addition,
The same applies to the sub-block [A].

As shown in FIG. 27A, one sub-block
Each block select transistor in lock [B]
Q_S, N storage capacitors C_M0, C_M1, C_M2,
C_M3, ..., C_M15And n connected in parallel to these
Control transistor, read transistor Q^B _READ,
Reference capacitor C_REF, And reference capacitor control
A transistor is included. Storage cell size is 4F^Two,
Areas other than storage cells, including contact parts per lock
The area is 22F^TwoTherefore, (4 + 2)
2 / n) F^Twobecome. In the third embodiment, a ferroelectric key is used.
20μC / cm as capacitor²Also has a remanent polarization of
Since 16 storage cells were connected in series,
Was also found to work stably. Therefore, one
5.4F ^TwoIt became the size of.

FIG. 27B is a sectional view taken along the line BB ′ of the plan view of the sub-block [B] shown in FIG. 27A. As shown in FIG. 27B, in the semiconductor memory device according to the third embodiment of the present invention, a p-well 12 is formed on a semiconductor substrate 11, and n ⁺ source / drain regions are formed on the surface of the p-well 12. 321, 22, 23, ..., 322
323 are provided. Then, a polysilicon gate electrode 331 and word lines WL0 ^B , WL1 ^B , WL2 ^B ,..., WL1 are formed on the gate oxide film on the surface of the p-well 12.
5 ^B , and a polysilicon gate electrode 332. Further, connected to the ^{n +} source / drain regions 321, the drive line DL ^B are extended in the vertical direction to the paper surface.

N⁺Source / drain regions 321, 22
Block select transistor with polysilicon gate electrode 331
Transistor Q_SIs configured. Also, n⁺Source / de
Rain regions 22, 23 and word line WL0^BAnd for storage
Capacitor C_M0The control transistor connected in parallel to
It is configured. Furthermore, n⁺Source / drain region 2
3, 24 and word line WL1^BAnd the storage capacitor C
_M1The control transistor connected in parallel to⁺Source
/ Drain regions 24, 25 and word line WL2^BAnd
Storage capacitor C_M2Control transistors connected in parallel
Ta, ..., n⁺Source / drain regions 26 (not shown)
), 322 and word line WL15^BAnd the storage capacity
Sita C_M15A control transistor connected in parallel is formed
Have been. And n⁺Source / drain region 32
2,323 and word line WR^BWith the reference capacitor system
A control transistor is formed. Also, in the B-B 'direction
N not shown because it is not exposed on the cross section⁺Source/
The drain regions 324 and 325 (see FIG.
Read transistor with the silicon gate electrode 332
TA Q_READAre formed. Polysilicon gate electrode 3
31, word line WL0^B, WL1^B, WL2^B, ..., W
L15^B, WR^BAbove the polysilicon gate electrode 332
Has an oxide film (SiO_TwoFirst interlayer insulating film made of a film or the like
13 is formed on the first interlayer insulating film 13.
Storage capacitor C_M0, C_M1, C_M2, C_M3, ..., C_M15of
Lower electrode functioning as first electrode or second electrode
42, 43,..., 44, reference capacitor C_REF4th of
A lower electrode 351 functioning as an electrode is formed.
You. The lower electrodes 42, 43,...
Fill the contact hole provided in the interlayer insulating film 13
Contact plugs 73, 75, 3
According to 42, n⁺Source / drain regions 23, 25,
, 323 are connected. Further, the lower electrode 351
Is a contour provided through the first interlayer insulating film 13.
The read transistor Q is connected via the
_READOf polysilicon gate electrode 332.
These contact plugs are made of doped polysilicon, high
It should be composed of high melting point metal or high melting point metal silicide, etc.
No. The lower electrode 42 is connected to the storage capacitor C_M0The first
Pole and storage capacitor C_M1Function as the second electrode of
I do. The lower electrode 43 is connected to the storage capacitor C _M2The first of
Electrode and storage capacitor C_M3Machine as the second electrode
Works. ... The lower electrode 44 is a storage capacitor C_M14of
First electrode and storage capacitor C_{M 15}Second electrode
Function as The lower electrodes 42, 43,
, 44, predetermined ferroelectric thin films 51, 52,.
53 may be formed and patterned. Also for reference
Capacitor C_REFOn the lower electrode 351 of
What is necessary is just to form the thin film 352. Note that the reference capacitor
C_REFFerroelectric thin film instead of the paraelectric thin film 352 for
A membrane can also be used. Ferroelectric thin films 51, 52,
, 53 and the paraelectric thin film 352 are not formed.
An oxide film (SiO 2) is formed on the first interlayer insulating film 13.
_TwoA second interlayer insulating film 14 made of a film or the like is formed.
The upper electrodes 372, 6
, 353 are formed. The upper electrode 372 is
Storage capacitor C_M0Function as a second electrode. Up
The unit electrode 62 is connected to the storage capacitor C_M1First electrode and
And storage capacitor C_M2Function as a second electrode.
... The upper electrode 353 is a storage capacitor C_M15The first of
Electrode and reference capacitor C_REFAs the third electrode of
Function. , 353 are the first electrodes.
Through the first interlayer insulating film 13 and the second interlayer insulating film 14.
Formed to fill the contact hole provided by
The contact plugs 72, 74, 341⁺
Connected to the source / drain regions 22, 24,.
ing. These contact plugs 72, 74, 341
Of doped polysilicon, refractory metals and refractory metals
What is necessary is just to comprise with silicide etc. Further, the upper electrode 37
, 353, readout output line SL ^B,and
Read output line SL^AAn oxide film (SiO 2)_Twofilm)
A third interlayer insulating film 15 made of
A bit line is formed on interlayer insulating film 15 of FIG.
You. Although not shown in the figure, a bit line has
Oxide film (SiO_TwoFilm), PSG film, BPSG film, nitride film
(Si₃N₄Film) or passivation such as polyimide film
Of course, it is preferable to form a passivation film.
You. Although the sub-block [B] has been mainly described,
Block [A] also has a similar configuration. Such times
Circuit configuration enables the use of highly integrated non-volatile memory.
Operation was confirmed.

(Fourth Embodiment) FIG. 28 shows a fourth embodiment of the present invention.
Semiconductor using a ferroelectric capacitor for storage according to an embodiment
FIG. 2 is a diagram illustrating a circuit configuration of a main part of the body storage device. FIG.
As shown in FIG. 8, the semiconductor memory according to the fourth embodiment of the present invention
The storage device includes a plurality of selection MOS transistors connected in series.
Jista Q_M0, Q_M1, Q_M2, Q_M3, ..., Q_M15And these
Multiple connected for each common main electrode of the selection transistor
Ferroelectric capacitor C for storage_M0, C _M1, C_M2, C_M3,
…, C_M15And a NAND-type memory cell string
Selection transistor Q located at the end of the memory cell row_M0Lord of
Reference capacitor C connected to the electrode_REFAnd the tiger for selection
Transistor Q_M0And reference capacitor C_REFConnection point with
Storage node N_SHaving a gate electrode connected to
Read transistor Q _READAnd the storage node N
_SR / W control transistor Q connected to_{R / W}Less
As a basic unit
Make up.

Each storage capacitor C _M0 , C _M1 , C _M2 , C
_M3 ,..., C _M15 are a first electrode connected to the common main electrode of the selection transistor, a second electrode provided opposite to the first electrode and connected to the plate electrode,
And a ferroelectric thin film sandwiched between the first and second electrodes. Also, reference capacitor C _REF, the third electrode connected to the storage node N _S, is disposed to face the third electrode, a fourth electrode connected to the plate electrode PL, and the third of these And a dielectric thin film sandwiched between the fourth electrodes. Further, one main electrode of the R / W control transistor Q _{R / W} to the storage node N _S, the other main electrode connected to the bit line BL.

A plurality of the NAND type memory cell columns are arranged in a matrix. With one reference capacitor C _REF , readout transistor Q _READ , and control transistor Q _{R / W} at the center, It is divided into two sub-blocks, a sub-block [A] on the right and a sub-block [B] on the left. FIG. 28 shows only two blocks [A] and two sub-blocks [B].

[0129] selecting transistor Q _M0 sub-block _{[A], Q M1, Q} M2, Q M3, ..., each gate electrode of Q _{M1 5,} the word line ^{WL0 A, WL1 A, WL2 A} , WL
3 ^A, ..., WL15 ^A is connected. Similarly, the selection transistors Q _M0 , Q _M1 ,
Q _M2, Q _M3, ..., to the gates of Q _M15, the word line WL
^{0 B, WL1 B, WL2 B} , WL3 B, ..., WL15 B
Is connected. A read power supply line VL is connected to one main electrode of the read transistor Q _READ of each memory cell block, and a read output line SL is connected to the other main electrode. The word line RL of the R / W control transistor is connected to the gate electrode of the R / W control transistor QR _{/ W} of each memory cell block.

FIG. 29 is a connection diagram of a peripheral circuit. Each word line WL0A, WL1A, WL of sub-block [A]
, WL15A are row decoders A
The word lines WL0B, WL1 of the sub-block [B]
, WL15B are connected to a row decoder B, and each bit line BL0, BL1,... Is connected to a column decoder.

In the circuit configurations shown in FIGS. 28 and 29, BLx (x = 0, 1) and W
To select a desired storage cell indicated by the intersection of LyA (y = 0, 1, 2,..., 15), WL0A to WLyA
All word lines up to Q _M0 are set to “1 (high level)”.
Turn on all the selection transistors to Q _My from off the selection transistor Qmy + 1 word lines WLy + 1A as "0 (low level)", to the plate line PL potential constant (e.g. 1 / V _C C) , BLx by applying a potential. Similarly, BLx (x = 0, 1) and WLyB (y = 0,
To select a desired memory cell indicated by the intersection of (1, 2,..., 15), all word lines from WL0B to WLyB are set to “1 (high level)” and transistors for selection from Q _M0 to Q _My are selected. Are turned on and the word line WLy + 1
B is set to “0 (low level)” and the selection transistor Q
This is achieved by turning off my + 1 and applying a potential to BLx with respect to a plate line PL having a constant potential (eg, 1/2 V _G ).

FIG. 30 shows a read / write sequence when the "read / direct write method with precharge" is employed. First, in the precharge combined readout method, before selecting WL0 ^A to WLy ^A or WL0 ^B to WLy ^B , R / W
The control transistor QR _{/ W} is turned on, and a reverse voltage is applied to the reference capacitor _CREF with respect to the plate line PL having a constant potential to perform precharge. Then, turn off the R / W control transistor Q _{R / W,} WL0 After selecting from up WLy ^A or WL0 ^B to WLy ^B from ^A, by applying a positive voltage, substantially in the storage capacitor C _My The voltage is inverted by applying about twice the voltage.

Next, when writing to the storage capacitor C _My , first, the R / W control transistor QR _{/ W} is turned on, a write voltage is applied to the bit line BL, and WL0 ^A to WLy ^A or WL0 ^B by selecting to WLy ^B from those for inverting the addition of voltage directly to the memory capacitor C _My.

FIG. 31A shows a fourth embodiment of the present invention.
In the plan view, for easy viewing, the cut-off shown in FIG.
Only the layer below the level A-A 'in the plan view is shown.
In one block connected to a bit line, 16
Two sub-blocks with memory cells, read transistor
TA Q_READAnd control transistor Q_{R / W}Contains
You. Storage cell size is 4F^TwoMemory blocks per block
26F is the area other than^TwoTherefore, one memory cell
(4 + 26/32) F^Twobecome. In the present embodiment,
20μC / cm as dielectric capacitor ²The remanent polarization of
Used, the 32 memory cells were connected in series.
It turned out that it operates stably even if it continues. Therefore,
4.8F per piece^TwoIt became the size of.

FIG. 31B is a plan view of FIG.
It is sectional drawing along B-B 'of a front view. On silicon substrate
Are formed from nMOS transistors. each
Selection transistor Q_M0, Q_M1, Q_M2, Q_M3, ..., Q
_M15The lower electrode LE, upper electrode TE and
C made of ferroelectric film_M0, C_M1, C_M2, C
_M3, ..., C_M15Are formed. Also, a NAND cell
Selection transistor Q at the end of the memory column_M0Another of
On the main electrode, a reference capacitor C_REFFormed
Have been. Very high integration with such a circuit configuration
The operation of the nonvolatile memory performed was confirmed.

(Fifth Embodiment) FIG. 32 shows a fifth embodiment of the present invention.
FIG. 33 shows a circuit configuration of a main part of a semiconductor storage device using a paraelectric storage capacitor according to the embodiment, and FIG. 33 is a diagram showing a main part of the semiconductor storage device including peripheral circuits in detail. As shown in FIG. 32, the semiconductor memory device according to the fifth embodiment of the present invention includes a plurality of selection MOS transistors Q _M0 , Q _M1 , Q _M2 , Q _M3,.
Q _M15 and a plurality of storage ferroelectric capacitors C _M0 , C _M0 connected to each common main electrode of these selection transistors.
_M1, C _M2, C _M3, ..., a NAND-type memory cell column consisting of C _M15 Prefecture, reference capacitor C connected to the main electrode of the selection transistor Q _M0 located at the end of the storage cell train
_REF , selection transistor Q _M0 and reference capacitor C
A read transistor Q _READ having a gate electrode connected to the storage node N _S is the connecting point between the _REF,
Two of the R / W control transistor Q _{R / W1} and Q memory cell blocks characterized by at least _{R / W2} connected to the storage node N _S is constructed as a basic unit.

Each storage capacitor C _M0 , C _M1 , C _M2 , C
_M3 ,..., C _M15 are a first electrode connected to the common main electrode of the selection transistor, a second electrode provided opposite to the first electrode and connected to the plate electrode,
And a ferroelectric thin film sandwiched between the first and second electrodes. Further, the reference capacitor C _REF is provided on a third electrode connected to the storage node NS, and opposed to the third electrode.
And a dielectric thin film sandwiched between the third and fourth electrodes. Further, one main electrode of the first R / W control transistor Q _{R / W1} in the storage node N _S, the other main electrode connected to the bit line BL. One main electrode of the second R / W control transistor QR _{/ W2} is a storage node N
_{At S} , the other main electrode is connected to the plate electrode PE.

Although a plurality of NAND type memory cell columns are arranged in a matrix, one reference capacitor C
_REF , a read transistor Q _READ , and two Rs
The sub-block is divided into two sub-blocks, the sub-block [A] on the right and the sub-block [B] on the left, centering on the / W control transistors QR _{/ W1} and QR _{/ W2} . FIG. 32 shows only two blocks [A] and two sub-blocks [B].

Transistor for selecting sub-block [A]
Q_M0, Q_M1, Q_M2, Q_M3, ..., Q_{M1 Five}For each gate electrode
Is the word line WL0^A, WL1^A, WL2^A, WL
3^A, ..., WL15^AIs connected. Similarly, sub
Selection transistor Q of block [B]_M0, Q_M1,
Q_M2, Q_M3, ..., Q_M15Each gate electrode has a word line
WL0 ^B, WL1^B, WL2^B, WL3^B, ..., WL1
5^BIs connected. Read each memory cell block
Transistor Q_READOne main electrode
Power supply line VL and a read output line SL on the other main electrode.
^AOr SL^BIs connected. Each memory cell block
Two R / W control transistors Q_{R / W1}And Q
_{R / W2}Of the R / W control transistor is
Lead wire RL₁And RL₂Is connected. FIG.
32, the selection transistor Q_M0, Q _M1, Q_M2,
Q_M3, ..., Q_M15, Read transistor Q_READ,
ぴ Two R / W control transistors Q_{R / W1}And Q
_{R / W2}Is shown as nMOSFET, but pMOSF
It is also possible to configure with ET.

FIG. 33 shows a connection diagram of the peripheral circuit. Each word line WL0 ^A , WL1 ^A , W of the sub-block [A]
^{L2 A, WL3 A, ...,} WL 15A , the row decoder A
Each of the word lines WL0 ^B and WL of the sub-block [B].
^{1 B, WL2 B, WL3 B} , ..., WL15 B to row decoder B, the bit lines BL0, BL1, ...... are connected to the column decoder.

In the circuit configurations shown in FIGS. 32 and 33, BLx (x = 0, 1) and W
To select a desired memory cell indicated by the intersection of Ly ^A (y = 0, 1, 2,..., 15), WL0 ^A to WLy ^A
All word lines up to Q _M0 are set to “1 (high level)”.
To Q _My , all the selection transistors are turned on, the word line WLy + 1 ^{A is set} to “0 (low level)”, the selection transistor Q _{my +1} is turned off, and the potential of the plate line is fixed (for example, Ｖ V _G ). This is achieved by applying a potential to BLx with respect to PL.

FIG. 34 shows a read / write sequence when the “precharge read / direct write method” is further employed. That is, in the precharge read method, before selecting WLy ^A or WLy ^B , the second R / W control transistor QR _{/ W2} is turned on, and the reference capacitor C _REF and WL0 ^A to W before the cell to be selected
Precharge is performed by applying a voltage to Ly-1 ^A or from WL0 ^B to WLy-1 ^B. Then, R /
By turning off the W control transistor QR _{/ W} and selecting WLy ^A or WLy ^B , the storage capacitor C
_It reads out the charge of _My . Storage capacitor C _My
First, the first R / W control transistor QR _{/ W1} is turned on to supply a write voltage to the bit line BL, and the first R / W control transistor QR _{/ W1} is turned on from WL0 ^A to WLy-1 ^A or from WL0 ^B to WLy. to select up to -1 ^B. Therefore, the voltage is inverted by directly applying a voltage to the storage capacitor C _My .

FIG. 35 (a) shows a fifth embodiment of the present invention.
In the plan view, for ease of viewing, the cutoff shown in FIG.
Only the layer below the level A-A 'in the plan view is shown.
Eight memories are stored in one block connected to a bit line.
Two sub-blocks with cells, read transistors
Q_READ, And two transistors Q for R / W control
_{R / W1}And Q_{R / W2}Is included. Storage cell size is 4
F^TwoThe area other than the memory cell per block is 22F^Twoso
Therefore, (4 + 22/16) F per memory cell
^Twobecome. In this embodiment, a paraelectric capacitor of 20
mF / cm²Use a strong non-linear
Therefore, it is safe to connect 16 memory cells in series.
It turned out to work. Therefore, per one
5.4F^TwoIt became the size of.

FIG. 35B is a sectional view taken along the line BB 'of the plan view of FIG. 35A. It is formed from an nMOS type transistor on a silicon substrate. Each of the selection transistors Q _M0 , Q _M1 , Q _M2 , Q _M3 ,.
_In the main electrode region of _M15 , storage capacitors C _M0 , C _M1 , C composed of a lower electrode LE, an upper electrode TE and a ferroelectric film are provided.
_M2 , _CM3 , ..., _CM15 are formed. Also, NAN
A reference capacitor C _REF is similarly formed on another main electrode of the selection transistor Q _M0 at the end of the D cell memory column. With such a circuit configuration, the operation of a very highly integrated semiconductor memory was confirmed.

(Sixth Embodiment) FIGS. 36A to 36D are schematic sectional views of a Chain type semiconductor memory device according to a sixth embodiment of the present invention in the order of steps. In each figure, reference numeral 1 denotes a first conductivity type semiconductor substrate, 2 denotes a second conductivity type impurity diffusion layer, 3 denotes an element isolation insulating film, 4 denotes a gate oxide film, 5 denotes a word line, and 6 denotes a single crystal Si epitaxial growth layer. , 7, 8, and 9 are insulating films, 11 and 15 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 23 is an internal wiring, and 24 is a via plug.

First, in FIG. 36A, after a transistor portion of a memory cell is formed by a known process, a single crystal Si layer 6 is selectively epitaxially grown, and flattened by a chemical mechanical polishing (CMP) method. I just did it. At this time, a silicon oxide film was used as an insulating film of the word line 5. Further, in order to remove a damaged layer on the surface of the electrode on the Si substrate caused by the RIE process, after etching using hydrogen fluoride vapor, the substrate is directly transferred to a CVD chamber in a vacuum, and is subjected to SiH ₄ gas at a pressure of 1 mTorr and SiH ₄ gas. Using 0.1 mTorr of AsH ₃ gas added as a donor, 7
Selective epitaxial growth was performed at 50 ° C.

Next, as shown in FIG. 36 (b), the single crystal Si layer 6 is provided with a CMP (Chemical and Mechanical Polishing).
g) After etching using hydrogen fluoride vapor, the barrier metal 11
TiN is deposited at 600 ° C. by the reactive sputtering method,
At 0 ° C., a SrTiO ₃ (hereinafter abbreviated as “SRO”) film is laminated, and subsequently BaTiO ₃ (hereinafter abbreviated as “BTO”) is deposited.
The ferroelectric thin film 13 is sputtered at 600 ° C. for 40 n.
m, a SrTiO ₃ (hereinafter abbreviated as “SRO”) film was deposited at 600 ° C. by sputtering as the upper electrode 14, and TiN was deposited at 600 ° C. by reactive sputtering as a barrier metal 15. By the way. At this time, all of the barrier metal 11, the lower electrode 12, the ferroelectric thin film 13, and the upper electrode 14 were epitaxially grown on the single-crystal Si layer 6 to be single-crystal.

Next, as shown in FIG. 36C, known lithography and RIE (Reactive Ion Etching)
The barrier metal 11, the lower electrode 12, the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the single crystal Si layer 6 were patterned by the method. Next, a silicon oxide insulating film 7 was conformally formed by a plasma CVD method using TEOS as a source gas, and an insulating film side wall of the capacitor was formed by anisotropic etching. Next, a via plug 24 made of tungsten (W) is buried by a CVD (Chemical Vapor Deposition) method, and the CMP using the barrier metal 15 as a stopper is performed.
Flattening was performed by the method.

Next, as shown in FIG. 36D, an internal wiring 23 made of W is formed by sputtering, and the ferroelectric film 13 is formed by known lithography and RIE.
Upper electrode 14, barrier metal 15, and internal wiring 23
Was patterned. Next, the silicon oxide insulating film 8 was buried by a plasma CVD method using TEOS as a source gas, and flattened by a CMP method using the internal wiring 23 as a stopper. Furthermore, interlayer insulating film 9
It was created.

After the film was formed in such a process, the film orientation was measured by an X-ray diffraction apparatus.
It was confirmed that the RO electrode film and the BTO dielectric film were all epitaxially grown in the (001) direction.
The lattice constant of the TO film in the thickness direction was as large as 0.434 nm. When the dielectric characteristics of the formed ferroelectric thin film capacitor were measured, the residual polarization amount was 0.42.
A large value of C / m ² was obtained, and it was confirmed that the film functioned as a ferroelectric capacitor.

(Seventh Embodiment) FIGS. 37A to 37C and FIGS. 38D and 38E are schematic sectional views of a Chain type semiconductor memory device according to a seventh embodiment of the present invention in the order of steps. is there. Reference numeral 1 denotes a first conductivity type semiconductor substrate, and 2 denotes a second conductivity type semiconductor substrate.
Conductivity type impurity diffusion layer, 5 is a word line, 6 is a single crystal Si epitaxial growth layer, 7, 8, 9, and 10 are insulating films, 11
Is a lower barrier metal film, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 15 is an upper barrier metal film, 20 is a plate electrode, 21 is a single crystal Si growth node, 22 is a capacitor contact part, 23 is an internal wiring.

First, as shown in FIG. 37A, a plate electrode 2 made of a second conductivity type impurity diffusion layer having a depth of about 0.1 μm is formed on the surface of a first conductivity type Si (100) substrate 1.
After the formation of the lower barrier metal layer 11,
(Ti, Al) N having a thickness of 20 nm as the lower electrode 12.
nm SRO, RF or DC at substrate temperature 600 ° C
It was epitaxially grown continuously by sputtering without being exposed to the atmosphere. Then, patterning is performed by etching such as lithography and RIE until the substrate 1 is reached, the element isolation insulating film 3 is buried by plasma CVD using TEOS gas as a raw material, and planarized by CMP using the lower electrode as a stopper. did. next,
After removing the damaged layer caused by flattening the lower electrode surface by wet etching or the like, a BaTiO ₃ thin film having a thickness of 20 nm as the dielectric film 13, an SRO film having a thickness of 20 nm as the upper electrode 14, and an upper barrier metal layer 15.
(Ti, Al) N with a film thickness of 10 nm
The epitaxial growth was carried out continuously at 00 ° C. by RE or DC sputtering without being exposed to the air, and the first insulating film 7 was formed by plasma CVD using TEOS gas as a raw material.

Next, as shown in FIG. 37B, a single crystal Si growth node 21 was formed by lithography and etching by RIE or the like. Next, a second insulating film 8 was formed conformally. Next, the first insulating film 7
And the second insulating film 8 was removed by anisotropic RIE, so that the insulating film was also left on the side wall of the single crystal Si growth node by self-alignment. Next, in order to remove the damaged layer on the Si surface, after etching using hydrogen fluoride vapor, the wafer is directly transported to a CVD chamber in a vacuum and
750 ° C. using SiH ₄ gas at a pressure of mTorr and AsH ₃ gas at a pressure of 0.1 mTorr added as a donor.
Thus, the single crystal Si layer 6 was formed from the single crystal Si growth node 21 by selective epitaxial growth. Next, the first insulating film 7 was used as a stop layer, and flattened by a CMP method (chemical mechanical polishing).

Next, as shown in FIG. 37 (c), the capacitor is patterned by using photolithography and plasma etching such as RIE to form a contact hole 26 to the upper electrode. Then, the capacitor was patterned using plasma etching such as RIE to form a contact hole 27 to the upper electrode, and the insulating film 9 was formed conformally. Next, by removing the insulating film 9 by anisotropic RIE while leaving the first insulating film 7, the insulating film on the side wall portion was left by self-alignment. Next, via plugs 24 and 25 made of tungsten (W) were buried by a CVD method, and planarization was performed by a CMP method using the first insulating film 7 as a stopper.

Next, as shown in FIG. 38D, a transistor including the impurity diffusion layer 2, the gate oxide film (not shown), and the word line 5 was formed using a known process.

Next, as shown in FIG. 38 (e), for example, a poly-Si film containing an N + type impurity is deposited to a thickness of about 200 nm, and photolithography and plasma etching such as RIE are used. By patterning, an internal wiring 23 connecting the via plugs 24 to 25 and the main electrode of the transistor was formed.

By such a process, a Chain type memory cell comprising a capacitor and a transistor using a ferroelectric film could be formed, and the operation as an FRAM was confirmed.

(Eighth Embodiment) Next, a semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIGS. 39 (a) to 39 (c) and FIGS. 40 (d) and 40 (e). This will be described with reference to the drawings. In each figure, reference numeral 1 denotes a first conductivity type semiconductor substrate, 2 denotes a second conductivity type impurity diffusion layer, 3 denotes an element isolation insulating layer, 4 denotes a gate oxide film, 5 denotes a word line, 6
Is a single crystal Si epitaxial growth layer, 7 and 8 are insulating films,
11 and 15 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 20 is a plate electrode, 3
0 is a contact plug, 31 is a first bonding layer, 32
Denotes a second Si (100) substrate, and 33 denotes a bonding layer.

First, as shown in FIG. 39A, a first Si (100) substrate 1 is formed by using a known process.
A transistor including an impurity diffusion layer 2, a gate oxide film 4, and a word line 5, a device isolation insulating film 3, and a contact plug 30 with a capacitor are formed and planarized by a method such as chemical mechanical polishing (CMP). did. Next, an Al film was formed as a first bonding layer 31 on the entire surface.

Next, as shown in FIG. 39B, a 10 nm (Ti, Al) N film as the lower barrier metal layer 11 and a 20 nm film thickness as the lower electrode 12 are formed on the second Si (100) substrate 32. SrRuO ₃ , Ba as the dielectric film 13
A BSTO thin film having a molar fraction of 70% and a thickness of 20 nm, an SrRuO ₃ film having a thickness of 20 nm as the upper electrode 14, and a 10 nm thick (Ti, A) film as the upper barrier metal layer 15.
1) N was continuously epitaxially grown at a substrate temperature of 600 ° C. by RF or DC sputtering without being exposed to the air. Next, Al is used as a second bonding layer 33 on the surface.
A film was formed on the entire surface.

Next, as shown in FIG. 39C, the first bonding layer and the second bonding layer were formed at a degree of vacuum of 3 × 10 ^−8.
The first bonding layer and the second bonding layer are exposed without removing the oxide layer generated on the surface by sputtering of Ar gas in an ultra-high vacuum of Torr or more without exposing it to the atmosphere. Were joined together by pressing at 400 ° C. for 30 minutes.

Next, as shown in FIG. 40D, the bonded second substrate was polished from the back surface by CMP or the like to leave a capacitor layer and a Si layer of about 0.2 μm. Thereafter, alignment was performed using the first substrate, and the capacitor was patterned for each memory cell. As an etching condition at this time, it is preferable to use an oxide layer as an etching stop layer. Next, an insulating film 7 was formed conformally. Next, by removing the insulating film 7 by anisotropic RIE, the insulating film on the side wall of the capacitor was left by self-alignment. Next, for example, poly S containing N ⁺ type impurities
An i film is buried to a thickness of about 200 nm, and a Si layer 32 is formed.
The via plug 24 was formed by planarization by a CMP method using as a stopper.

Next, as shown in FIG. 30E, an internal wiring 23 made of TiN is formed by sputtering, and the ferroelectric film 1 is formed by known lithography and RIE.
3. Patterning of the upper electrode 14, the barrier metal 15, and the internal wiring 23 was performed. Next, the silicon oxide insulating film 8 was buried by a plasma CVD method using TEOS as a source gas, planarized by a CMP method using the internal wiring 23 as a stopper, and an interlayer insulating film 9 was formed.

Through these steps, a memory cell including a capacitor and a transistor using a ferroelectric film can be formed with a high yield, and the operation as an FRAM has been confirmed.

(Ninth Embodiment) FIGS. 41A to 41C are schematic sectional views in the order of steps of a NAND cell in a semiconductor memory device according to a ninth embodiment of the present invention. In each figure, reference numeral 1 denotes a first conductivity type semiconductor substrate, and reference numeral 2 denotes a second semiconductor substrate.
Conductivity type impurity diffusion layer, 3 is an element isolation insulating film, 4 is a gate oxide film, 5 is a word line, 6 is a single crystal Si epitaxial growth layer, 7, 8, and 9 are insulating films, 11 and 14 are barrier metals, 12 Is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, and 20 is a plate electrode.

FIG. 41 (a) shows a state where a transistor portion of a memory cell is formed by a known process, and then a single crystal Si layer 6 is selectively epitaxially grown and flattened by a chemical mechanical polishing (CMP) method. . At this time, a silicon oxide film was used as an insulating film of the word line 5. Further, in order to remove a damaged layer on the surface of the electrode on the Si substrate caused by the RIE process, after etching using hydrogen fluoride vapor, the substrate is directly transferred to a CVD chamber in a vacuum, and
Selective epitaxial growth was performed at 750 ° C. using SiH ₄ gas at a pressure of mTorr and AsH ₃ gas at a pressure of 0.1 mTorr added as a donor.

Next, as shown in FIG. 41B, in order to remove a damaged layer on the surface of the single crystal Si layer 6 generated by the CMP process, after etching using hydrogen fluoride vapor, the barrier metal 11 is formed. by reactive sputtering TiN stacked at 600 ° C., subsequently (abbreviated hereinafter as SRO) SrTiO ₃ at 600 ° C. by sputtering as the lower electrode 12 film is laminated, (abbreviated BTO and beyond) continue BaTiO ₃ ferroelectric The body thin film 13 is formed by sputtering
At a temperature of 600 ° C. by sputtering to form SrTiO ₃ (hereinafter, referred to as the upper electrode 14).
(Abbreviated as SRO), and then TiN was deposited as a barrier metal 15 at 600 ° C. by a reactive sputtering method. At this time, all of the barrier metal 11, the lower electrode 12, the ferroelectric thin film 13, and the upper electrode 14 were epitaxially grown on the single-crystal Si layer 6 to be single-crystal. All grew as polycrystals on the top.

Next, as shown in FIG. 41C, the barrier metal 1 is formed by known lithography and RIE.
1. Patterning of the lower electrode 12, the ferroelectric film 13, the upper electrode 14, the barrier metal 15, and the single crystal Si layer 6 was performed. At this time, the insulating film was used as a stopper. Silicon oxide insulating film 7 is formed in the patterned groove by plasma CVD using TEOS as a source gas.
Was planarized by a CMP method using the barrier metal 15 as a stopper. Thereafter, TiN was laminated as a plate electrode 20 by a sputtering method, and an interlayer insulating film 8 was further formed.

After the film was formed in such a process, the film orientation was measured by an X-ray diffraction apparatus.
It was confirmed that the RO electrode film and the BTO dielectric film were all epitaxially grown in the (001) direction.
The lattice constant of the TO film in the thickness direction was as large as 0.434 nm. When the dielectric characteristics of the formed ferroelectric thin film capacitor were measured, the residual polarization amount was 0.42.
A large value of C / m ² was obtained, and it was confirmed that the capacitor functioned as a ferroelectric capacitor.

(Tenth Embodiment) FIGS. 42 (a) to (c) and FIGS. 43 (d) to (f) are schematic diagrams showing the order of steps of a NAND cell in a semiconductor memory device according to a tenth embodiment of the present invention. It is sectional drawing. A paraelectric capacitor was prepared as a storage capacitor. In each figure, reference numeral 1 denotes a first conductivity type semiconductor substrate, 2 denotes a second conductivity type impurity diffusion layer, 5 denotes a word line, 6 denotes a single crystal Si epitaxial growth layer, 7, 8, 9, and 10 denotes an insulating film, and 11 denotes an insulating film. Lower barrier metal, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 15 is an upper barrier metal film, 20 is a plate electrode, 2
1 is a single crystal Si growth node, 22 is a contact portion of a capacitor, and 23 is an internal wiring.

First, as shown in FIG. 42A, a plate electrode 2 made of a second conductivity type impurity diffusion layer having a depth of about 0.1 μm is formed on the surface of a first conductivity type Si (100) substrate 1.
After the formation of the lower barrier metal layer 11,
(Ti, Al) N having a thickness of 20 nm as the lower electrode 12.
SRO having a thickness of 20 nm and (B
a _0.2 Sr _0.8 ) TiO ₃ thin film, SRO film having a thickness of 20 nm as upper electrode 14, and upper barrier metal layer 1
5, a 10 nm-thick (Ti, Al) N is epitaxially grown continuously at a substrate temperature of 600 ° C. by RF or DC sputtering without being exposed to the air, and the first insulating film 7 is formed using TEOS gas as a raw material. It was formed by a plasma CVD method or the like.

Next, as shown in FIG. 42B, a single crystal Si growth node 21 was formed by lithography and etching by RIE or the like. Next, a second insulating film 8 was formed conformally.

Next, as shown in FIG. 42C, the second insulating film 8 is formed by anisotropic RIE while leaving the first insulating film 7.
, The insulating film was also left on the side wall portion of the single crystal Si growth node by self-alignment. next,
In order to remove the damaged layer on the Si surface, after etching using hydrogen fluoride vapor, the wafer was directly transported to a CVD chamber in a vacuum, and SiH ₄ gas at a pressure of 1 mTorr and AsH ₃ gas at a pressure of 0.1 mTorr added as a donor were used. Use 7
At 50 ° C., single-crystal Si layer 6 was formed by selective epitaxial growth from single-crystal Si growth node 21. Next, the insulating film was used as a stop layer, and flattened by a CMP method (chemical mechanical polishing).

Next, as shown in FIG. 43D, the capacitor is patterned by using photolithography and plasma etching such as RIE, and the insulating film is buried and planarized by CMP to form a capacitor insulating film. 9 was formed.

Next, as shown in FIG. 43E, a transistor including an impurity diffusion layer 2, a gate oxide film (not shown), and a word line 5 was formed using a known process.

Next, as shown in FIG. 43 (f), the contact portion 22 of the capacitor was opened by photolithography and plasma etching such as RIE.
At this time, the upper barrier metal layer 1 was used as an etching condition.
It is preferable to selectively stop using any one of the fifth to upper electrodes 14 as a stopper. Next, a poly-Si film containing, for example, N ⁺ -type impurities is deposited on the entire surface to a thickness of about 200 nm, and the entire surface is etched by a method such as CMP and RIE to connect the contact portion 22 to the main electrode of the transistor. The internal wiring 23 was formed. Further, an interlayer insulating film 10 was formed.

Through these steps, a NAND memory cell comprising a capacitor and a transistor using a ferroelectric film could be formed, and the operation as a NAND FRAM was confirmed.

(Eleventh Embodiment) A semiconductor memory device according to an eleventh embodiment of the present invention will be described with reference to FIGS. 44A to 44C and FIGS. Will be explained. Reference numeral 1 denotes a first conductivity type semiconductor substrate, 2 denotes a second conductivity type impurity diffusion layer, 3 denotes an element isolation insulating layer, 4 denotes a gate oxide film, 5 denotes a word line, 6 denotes a single crystal Si epitaxial growth layer, and 7, 8 Is an insulating film, 11 and 14 are barrier metals, 12 is a lower electrode, 13 is a dielectric thin film, 14 is an upper electrode, 20 is a plate electrode, 30 is a contact plug, 31 is a first bonding layer, and 32 is a second bonding layer. Si (10
0) Substrate 33 is a second bonding layer.

First, as shown in FIG. 44A, a first Si (100) substrate 1 is formed by using a known process.
A transistor including an impurity diffusion layer 2, a gate oxide film 4, and a word line 5, a device isolation insulating film 3, and a contact plug 30 with a capacitor are formed and planarized by a method such as chemical mechanical polishing (CMP). did. Next, an Al film was formed as a first bonding layer 31 on the entire surface.

Next, as shown in FIG. 44B, a 10 nm (Ti, Al) N film as the lower barrier metal layer 11 and a 20 nm film thickness as the lower electrode 12 are formed on the second Si (100) substrate 32. SrRuO ₃ , Ba as the dielectric film 13
A BSTO thin film having a molar fraction of 70% and a thickness of 20 nm, an SrRuO ₃ film having a thickness of 20 nm as the upper electrode 14, and a 10 nm thick (Ti, A) film as the upper barrier metal layer 15.
1) N was continuously epitaxially grown at a substrate temperature of 600 ° C. by RF or DC sputtering without being exposed to the air. Next, Al is used as a second bonding layer 33 on the surface.
A film was formed on the entire surface.

Next, as shown in FIG. 44C, the first bonding layer and the second bonding layer were formed at a degree of vacuum of 3 × 10 ^−8.
The first bonding layer and the second bonding layer are exposed without removing the oxide layer generated on the surface by sputtering of Ar gas in an ultra-high vacuum of Torr or more without exposing it to the atmosphere. Were joined together by pressing at 400 ° C. for 30 minutes.

Next, as shown in FIG. 45 (d), the bonded second substrate was polished from the back surface by CMP or the like to leave a capacitor layer and a Si layer of about 0.2 μm. Thereafter, alignment was performed using the first substrate, and the capacitor was patterned for each memory cell. As an etching condition at this time, it is preferable to use an oxide layer as an etching stop layer. Further, after the insulating film 7 is buried by a plasma CVD method using TEOS gas as a raw material, CMP is performed again.
It was flattened by a method or the like.

Finally, as shown in FIG. 45E, after forming a Ti / TiN / Al layer as the plate electrode 20, the insulating layer 8 was covered.

Through these steps, a memory cell including a capacitor and a transistor using a ferroelectric film could be formed with a high yield, and the operation as an FRAM was confirmed.

(Twelfth Embodiment) FIGS. 46 (a), (b) and FIGS. 47 (c), (d) are step-by-step schematic sectional views of a NAND cell according to a twelfth embodiment of the present invention. 1 is a first conductivity type semiconductor substrate, 2 is a second conductivity type impurity diffusion layer, 3
Is an element isolation insulating layer, 4 is a gate oxide film, 5 is a word line, 6 is a single crystal Si layer, 7, 8, and 9 are insulating films, 11 is a first barrier metal, 12 is a first electrode, 13 Is a dielectric thin film, 14 is a second electrode, 15 is a second barrier metal layer, 2
0 is a plate electrode, 30 is a contact plug, 31 is a first bonding layer, 32 is a second Si (100) substrate, 3
3 is a second bonding layer.

First, as shown in FIG. 46A, a 10 nm-thick (Ti, Al) N film as a first barrier metal 11 is formed on a first surface of a first conductivity type Si (100) substrate 1.
SRO having a thickness of 20 nm as the film and the first electrode 12 and a thickness of 20 nm as the ferroelectric film 13 with a molar fraction of Ba of 70%.
A 20 nm thick SRO film as the second electrode 14 and a 10 nm thick film as the second barrier metal layer 15
Was epitaxially grown at a substrate temperature of 600 ° C. by RF or DC sputtering, respectively. Further, 200 nm Ti at room temperature is used as the plate electrode 20.
An N film was formed. Next, BPSG was formed to a thickness of, for example, about 500 nm as the first bonding insulating film 31, and then planarized by, for example, a CMP method.

Next, a second Si substrate 32 was prepared, and a BPSG layer was formed as a second bonding layer 33 on the surface and flattened. Next, the first bonding insulating film 31 and the second bonding layer 33 were bonded to each other. The bonding was performed by a known method, for example, a heat treatment at about 900 ° C.

Next, as shown in FIG. 46 (b), assuming that the second surface of the first Si substrate 1 is polished,
The illustration is omitted. A thin silicon layer having a thickness of, for example, about 10 nm is formed using a polishing stopper layer around the cell region. Other SOI forming methods such as smart cut bonding and polishing may be used.

Next, the ordinary photolithography method and R
Grooves for element isolation were opened using plasma etching such as the IE method. As an etching condition at this time, it is preferable to selectively stop using the dielectric film 13 of the capacitor as a stopper. Next, a buried insulating film 7 was formed and planarized by CMP. Further, after the buried insulating film 7 is selectively etched shallowly by RIE or the like, a second-conductivity-type single-crystal silicon layer 6 is formed and planarized again. A method of forming a silicon layer conformally and then crystallizing from a side wall portion by a heat treatment such as RTP to form a single crystal, a method of selectively embedding single crystal silicon by a selective growth CVD method, and the like are given.

Next, as shown in FIG. 47C, a second groove for separating the elements is formed by lithography and RI.
It was formed by etching using E or the like. At this time, it is preferable to use the dielectric film 5 of the capacitor as an etching stop layer. Next, a buried insulating film 8 was formed and planarized by CMP or the like.

Finally, as shown in FIG. 47 (d), the second conductivity type impurity diffusion layer 2,
A transistor including a gate oxide film 4 and a word line 5,
An interlayer insulating film 9 was formed.

Through these steps, a memory cell including a capacitor and a transistor using a ferroelectric film can be formed with high yield, and the operation as an FRAM has been confirmed.

(Other Embodiments) As described above, the present invention has been described with reference to the first to twelfth embodiments.
It is not to be understood that the description and drawings which are a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the above description of the first to twelfth embodiments, the nMOSFET is formed in the p well, but the nMOSFET may be formed in the p substrate. Further, a pMOSFET may be used instead of the nMOSFET. When a pMOSFET is used, the polarity of the read / write sequence shown in FIG. 18, FIG. 22, or FIG.

Further, it goes without saying that the semiconductor memory devices according to the first to 123rd embodiments described above may be formed on an SOI substrate. Further, in FIG. 27B, the bit lines are not shown on the cross section in the BB 'direction and therefore are not shown in the drawing. However, the plane is such that the bit lines are exposed on the cross section in the BB' direction. Of course, a layout may be used. Conversely, in FIGS. 19B and 23B, it is also possible to adopt a planar layout such that the bit lines are not exposed on the cross section.

As described above, it should be understood that the present invention includes various embodiments and the like which are not described herein. Accordingly, the present invention is limited only by the invention and the specified items as set forth in the reasonable claims from this disclosure.

According to the embodiment described in detail above, it is possible to provide a semiconductor memory element having a small memory cell configuration, which can be scaled by the minimum dimension f. In particular, according to the above embodiment of the present invention, it is possible to provide a semiconductor memory element capable of stably maintaining ferroelectric polarization and having an ultra-high integration. Further, according to the present invention, it is possible to realize an ultra-highly integrated semiconductor storage element that is easy to manufacture.
The industrial value is extremely large.

[0198]

As described above in detail, according to the present invention, it is possible to provide a semiconductor memory device having a small memory cell configuration, which can be scaled by the first dimension f. In addition, an ultra-high-integrated semiconductor memory device having the feature that a small memory cell can be formed in a groove, and the ferroelectric polarization can be stably maintained and scaling can be performed despite the ease of the process. Can be realized, and the industrial value of the present invention is extremely large.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell for describing a basic configuration of the present invention.

FIG. 2 shows (a) storage “1” of the semiconductor storage device of the present invention;
FIG. 3B is a schematic diagram illustrating a read operation in storage “0”.

FIG. 3 shows (a) storage “1” of the semiconductor storage device of the present invention;
FIG. 3B is a schematic diagram illustrating a read / write operation in storage “0”.

FIG. 4 is an equivalent circuit diagram of the memory cell of the present invention when the reference capacitor C _REF is a ferroelectric thin film.

FIG. 5 is a schematic diagram for explaining a read operation of (a) storage “1” and (b) storage “0” by a read operation of serial voltage application in the circuit of FIG. 4;

FIG. 6 is a schematic diagram showing a read operation of (a) storage “1” and (b) storage “0” in a precharge mode of a reference ferroelectric capacitor.

FIGS. 7A and 7B show basic configurations (a) and (b) of the present invention, respectively.
FIG. 4 is an equivalent circuit diagram of a memory cell for explaining (c).

FIGS. 8A and 8B are circuit diagrams respectively showing specific configurations (a) and (b) for further increasing the integration of the semiconductor memory device of the present invention.

FIG. 9 is a circuit diagram showing a specific configuration (a) or (b) of the present invention suitable for high integration when the reference capacitor C _REF is formed of a ferroelectric thin film.

FIG. 10 is an equivalent circuit diagram of a memory cell for describing a basic configuration of the present invention using a scalable NAND-FRAM.

FIGS. 11A and 11B are schematic diagrams illustrating polarization states (a) and (b) of a ferroelectric capacitor having asymmetric ferroelectric hysteresis.

FIG. 12 is an equivalent circuit diagram of a memory cell for describing a basic configuration in the case where a paraelectric capacitor is used in the circuit of FIG. 10;

FIG. 13 is a schematic diagram for explaining a read operation (a) and a read operation (b) when a paraelectric capacitor is used.

FIG. 14 is a schematic diagram illustrating a polarization state of a paraelectric capacitor having a non-linear capacitance characteristic.

FIG. 15 is an equivalent circuit diagram of a memory cell for explaining several circuit configurations (a) to (d) of the present invention.

FIG. 16 is a circuit configuration diagram of a main part of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 17 is a circuit configuration diagram of a main part including peripheral circuits of the semiconductor memory device according to the first embodiment;

FIG. 18 is a timing chart showing a read / write sequence of the semiconductor memory device according to the first embodiment.

FIG. 19A shows the semiconductor memory device according to the first embodiment;
Plan view and (b) sectional view.

FIG. 20 is a circuit configuration diagram of a main part of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 21 is a circuit configuration diagram of a main part including peripheral circuits of the semiconductor memory device according to the second embodiment.

FIG. 22 is a timing chart showing a read / write sequence of the semiconductor memory device according to the second embodiment.

FIG. 23A illustrates a semiconductor memory device according to a second embodiment;
Plan view and (b) sectional view.

FIG. 24 is a circuit configuration diagram of a main part of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 25 is a circuit configuration diagram of main parts including peripheral circuits of the semiconductor memory device according to the third embodiment.

FIG. 26 is a timing chart showing a read / write sequence of the semiconductor memory device according to the third embodiment.

FIG. 27A illustrates a semiconductor memory device according to a third embodiment;
Plan view and (b) sectional view.

FIG. 28 is a circuit configuration diagram of a main part of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 29 is a circuit configuration diagram of main parts including peripheral circuits of a semiconductor memory device according to a fourth embodiment.

FIG. 30 is a timing chart showing a read / write sequence of the semiconductor memory device according to the fourth embodiment.

FIG. 31A shows a semiconductor memory device according to a fourth embodiment;
Plan view and (b) sectional view.

FIG. 32 is a circuit configuration diagram of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 33 is a circuit configuration diagram of a main part including peripheral circuits of a semiconductor memory device according to a fifth embodiment.

FIG. 34 is a timing chart showing a read / write sequence of the semiconductor memory device according to the fifth embodiment.

FIG. 35A shows a semiconductor memory device according to a fifth embodiment;
Plan view and (b) sectional view.

FIG. 36 is a schematic sectional view of a memory cell of a semiconductor memory device according to a sixth embodiment of the present invention in the order of (a)-(d) steps.

FIG. 37 is a schematic sectional view of a memory cell of a semiconductor memory device according to a seventh embodiment in the order of (a)-(c) steps.

FIG. 38 is a sectional view showing steps (d) and (e) subsequent to FIG. 37 in the seventh embodiment;

FIG. 39 is a schematic sectional view of a memory cell of a semiconductor memory device according to an eighth embodiment of the present invention in the order of (a)-(c) steps.

FIG. 40 is a sectional view showing steps (d) and (e) subsequent to FIG. 39 in the seventh embodiment;

FIG. 41 is a schematic sectional view of a memory cell of a semiconductor memory device according to a ninth embodiment in the order of (a)-(c) steps.

FIG. 42 is a schematic sectional view of the memory cell of the semiconductor memory device according to the tenth embodiment in the order of (a)-(c) steps.

FIG. 43 is a sectional view showing steps (d) to (f) subsequent to FIG. 42 in the tenth embodiment;

FIG. 44 is a schematic sectional view of a memory cell of a semiconductor memory device according to an eleventh embodiment in the order of (a)-(c) steps.

FIG. 45 is a sectional view showing steps (d) and (e) subsequent to FIG. 44 in the eleventh embodiment;

FIG. 46 is a schematic cross-sectional view showing steps (a) and (b) of a memory cell of a semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 47 is a sectional view showing steps (d) and (e) subsequent to FIG. 46 in the twelfth embodiment;

[Explanation of symbols]

C _M0 -C _MN memory capacitor C _REF reference capacitor Q _READ read transistor Q _M0 to Q _MN selecting MOS transistor Q _C control transistor Q _S block selection transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8247 29/788 29/792

Claims (18)

[Claims] 1. A memory comprising at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric thin film sandwiched between the first and second electrodes. A capacitor, a third electrode connected to the first electrode, a fourth electrode arranged opposite to the third electrode, and a dielectric sandwiched between the third and fourth electrodes. A reference capacitor comprising at least a thin film; a read transistor having a gate electrode connected to the first and third electrodes; a first electrode of the storage capacitor; And a control transistor provided to adjust the potential of a storage node, which is a connection point of the three electrodes and the gate electrode of the read transistor. A semiconductor memory device characterized by being arranged in a matrix. 2. The semiconductor memory device according to claim 1, wherein said control transistor is connected between said first electrode and said second electrode of said storage capacitor. 3. The semiconductor memory device according to claim 2, wherein said control transistor is connected between said third electrode and said fourth electrode of said reference capacitor. 4. The semiconductor memory device according to claim 1, wherein said control transistor is connected between said third electrode and said fourth electrode of said reference capacitor. 5. A charge amount including a domain-inverted component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor is obtained when a voltage corresponding to a read voltage is applied to the storage capacitor. 2. The semiconductor memory device according to claim 1, wherein the charge amount is not less than 1/4 and not more than 4 times the charge amount including the polarization inversion component. 6. A storage device including at least a first electrode, a second electrode disposed opposite to the first electrode, and a ferroelectric film sandwiched between the first and second electrodes. A storage cell array in which a plurality of storage cells each including a capacitor and a control transistor connected between the first and second electrodes are connected in series; and the storage capacitor located at an end of the storage cell array A third electrode electrically coupled to the first electrode, a fourth electrode disposed opposite to the third electrode,
And a readout transistor having a gate electrode electrically coupled to the first and third electrodes; and a memory cell having at least a readout transistor having a gate electrode electrically coupled to the first and third electrodes. A semiconductor memory device comprising a plurality of blocks arranged in a matrix. 7. A control transistor connected between the first electrode and the second electrode of the memory cell column is a first transistor.
7. The semiconductor memory according to claim 6, wherein a second control transistor is provided between the third electrode and the fourth electrode of the reference capacitor. 8. apparatus. 8. An electric charge including a domain-inverted component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor is obtained when a voltage corresponding to a read voltage is applied to the storage capacitor. 7. The semiconductor memory device according to claim 6, wherein the charge amount is not less than 1/4 and not more than 4 times the electric charge including the polarization inversion component. 9. The semiconductor memory device according to claim 6, wherein the dielectric thin film of the reference capacitor is a paraelectric thin film. 10. The semiconductor memory device according to claim 6, wherein the dielectric thin film of the reference capacitor is a ferroelectric thin film. 11. A storage capacitor comprising a plurality of selection MOS transistors connected in series, and a dielectric film sandwiched between plate electrodes facing storage electrodes connected to respective common main electrodes of the selection MOS transistors. And a reference capacitor electrically coupled to a main electrode of a selection transistor located at an end of the storage cell column; and a main electrode of the selection MOS transistor and the reference. A read-out transistor having a gate electrode electrically coupled to a connection portion of an electrode of a storage capacitor; and a plurality of memory cell blocks including at least a read-out transistor arranged in a matrix. 12. A control transistor for supporting a potential of a storage node, which is a connection point between a main electrode of the selection MOS transistor, one electrode of the reference capacitor, and a gate electrode of the read transistor. The semiconductor memory device according to claim 11, further comprising: 13. A charge amount including a domain-inverted component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor is obtained when a voltage corresponding to a read voltage of the storage capacitor is applied. 12. The semiconductor memory device according to claim 11, wherein the charge amount is not less than 1/4 and not more than 4 times the electric charge including the polarization inversion component. 14. The semiconductor memory device according to claim 11, wherein the dielectric film of said storage capacitor is a ferroelectric film. 15. The storage capacitor according to claim 1, wherein the dielectric film of the storage capacitor is a paraelectric film, and the storage capacitor has a non-linear capacitor having a maximum capacitance of at least twice the minimum capacitance within an operating voltage range. 12. The semiconductor memory device according to claim 11, 16. The semiconductor memory device according to claim 11, wherein the dielectric film of said reference capacitor is a ferroelectric film. 17. The semiconductor memory device according to claim 11, wherein the dielectric film of said reference capacitor is a paraelectric film. 18. An electric charge including a domain-inverted component obtained when a voltage corresponding to a read voltage is applied to the reference capacitor is obtained when a voltage corresponding to a read voltage is applied to the storage capacitor. 12. The semiconductor memory device according to claim 11, wherein the charge amount is not less than 1/4 and not more than 4 times the charge amount including the polarization inversion component.