JP3925839B2 - Semiconductor memory device and test method thereof - Google Patents
Semiconductor memory device and test method thereof Download PDFInfo
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【0001】
【発明の属する技術分野】
本発明は、ボード等に実装された後に、外部端子のコンタクト状態を容易にチェックすることができる半導体記憶装置およびその試験方法に関する。
【0002】
【従来の技術】
半導体記憶装置(半導体チップ)をパッケージに搭載してボード等に実装した後に、その半導体記憶装置において外部と接続されて信号が入出力される各端子(外部端子)のコンタクト状態をチェックするためには、以下のような方法が挙げられる。
【0003】
最も原始的な方法は、各外部端子の半田付け状態を目視で確認する方法である。また、半導体記憶装置をボード等に実装した後に、実際にデバイスを動作させることによっても確認することができる。さらに、ゲートアレイ等のロジックデバイスにおいては、JTAGで規定されているバウンダリスキャン(boundary scan)等を行なうための試験回路を別途搭載して判断する方法もある。
【0004】
また、特開2000−206197号公報には、DRAM等のメモリデバイスをボードに実装した状態で、上記方法に比べて簡易に外部端子のコンタクトチェックを行なうための試験回路および試験方法が提案されている。この従来技術は、専用の試験用端子を設けることなく、デバイスに通常使用される電圧範囲内で、簡単なタイミング設定によって試験を行なうことを目的としている。試験を行う際には、デバイスに電源電圧を印加した後に、外部端子に特定の信号を入力することによって、試験回路を起動させる。実際にはチップ選択用端子を非選択状態から選択状態にすることによって試験回路を起動させることができる。さらに、外部端子を用途によって複数にグループ分けして、それぞれのグループに対して、試験を順次行う。
【0005】
【発明が解決しようとする課題】
近年、電子機器の小型化・薄型化が進み、半導体装置のパッケージについても、より実装面積の少ないCSP(Chip Size Package)、BGA(Ba11 Grid Array)等が主流になってきている。これらのパッケージでは、パッケージの底面に外部端子がマトリクス状態に配置されており、ボード等に実装後に各端子の半田付け状態を目視で確認することは実質的に不可能である。
【0006】
また、デバイスを実際に動作させることによって外部端子のコンタクト状態を判定する場合には、簡易な動作だけで全ての端子のコンタクト状態をチェックすることは非常に困難である。この方法によって検出精度を向上させるためには、多数のパターンで半導体記憶装置に動作を行なわせる必要がある。このため、全ての外部端子のコンタクト状態を確実に検出できる試験を行うためには、デバイスの外部に試験装置を設けて必要な数のパターンで動作を実行させる必要があり、試験のためのコストが高くなる。
【0007】
また、バウンダリスキャン等を行なうためには、一般に、専用の試験回路を起動させるための端子を別途設ける必要があり、また、試験回路を追加することによって回路規模が大きく、複雑になる。従って、小型化、低コスト化が要求される一般的な半導体記憶装置には、バウンダリスキャンを行う方法は適していない。
さらに、半導体記憶装置が実装されるボード自体も集積化が進んできているため、外部試験回路を半導体記憶装置に接続して試験を行なうことも困難になってきている。
【0008】
これらの問題を解決するために、上記特開2000−206197号公報では、各端子を複数のグループ、例えばDRAMの場合にはチップ選択端子、アドレス入力端子、データ入出力端子の3つに分けて試験を行っている。しかしながら、この公報に開示されている方法では、グループ数の回数だけ試験を行う必要があり、また、グループ中の端子毎に入力信号を変化させて試験を行うため、全端子のコンタクト状態をチェックするためには、端子数だけ試験を行う必要がある。
【0009】
さらに、DRAM等の比較的端子数が少ないデバイスの場合には問題は少ないが、例えばNOR型フラッシュメモリ等のようにランダムアクセスが行われる、端子数が多いデバイスに上記公報の技術を適用するためには、容易に端子のコンタクト状態をチェックすることができない。例えば、アドレス入力端子等のテストを行う場合、上記公報の図4に示すように、複数の入力パターンを用いてテストを行うため、端子数が増えると入力パターンも増えるからである。さらに、このようなデバイスは大容量化が進んでいるため、端子数は増加する一方である。
【0010】
従って、上記公報の技術は、どのアドレス入力端子に問題があるのかを特定するためには有効であるが、実装後の外部端子のコンタクト状態を簡易にチェックするためには不向きである。
【0011】
さらに、上記公報の技術は、チップ選択用端子を非選択状態から選択状態にすることによって試験回路を起動させており、試験回路を停止させて通常の状態で使用するためには、デバイスを立ち上げる度に、グループ数の回数だけチップ選択用端子にダミー信号を入力して、通常動作モードに移行させる必要があり、汎用的ではない。
【0012】
本発明は、このような従来技術の課題を解決するためになされたものであり、半導体記憶装置をボード等に実装後に、、専用の試験用端子を追加しなくても、通常動作と同じ簡易なタイミングによって、容易に精度良く、外部端子のコンタクト状態を判定することができる半導体記憶装置とその試験方法を提供することを目的とする。
【0013】
【課題を解決するための手段】
上記課題を解決するために、本発明の半導体記憶装置は、外部と接続されて信号が入出力される外部端子と内部の記憶領域との間の信号の入出力を制御すると共に、半導体記憶装置をボードに実装後に、外部端子に特定の信号を入力することによって各端子のコンタクト状態を判定するコントローラと、該記憶領域内に該特定の信号の期待値データが記憶されている記憶部とを備え、該コントローラは、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識する認識部と、該認識部にて判定実行コマンドであると認識された場合に、アドレス入力端子から入力された信号と、該記憶部に記憶されている期待値データとを比較して、一致している場合には合格とし、一致しない場合には不合格として判定結果を出力する比較判定結果出力部とを有することを特徴とする。
【0014】
上記構成によれば、外部から予め定められた特定の信号を入力して、データ入出力端子に入力されたコマンド信号によって判定を実行するか否かを判断して、判定を実行する場合には、アドレス入力端子から入力された信号(そのデータ値)とコントローラによって記憶部に記憶されている期待値とを比較することによって、ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、従来技術よりも簡単に精度良くチェックすることができる。期待値は、デバイスの出荷テスト等の際にデバイス内部の記憶領域に書き込むことができる。または、デバイスの製造段階から書き込んでおくことも可能である。この機能は、デバイスを通常使用する際のライトタイミングおよびリードタイミングによって実現することができるので、この機能をシステムボード上のコントローラに搭載することによって、他に試験装置を設けなくても、システムボード単体でコンタクト状態をチェックすることができる。
【0015】
前記記憶部には、さらに、コマンド信号に対する期待値データが記憶されており、前記認識部は、データ入出力端子から入力されたコマンド信号と、該記憶ブロックに記憶されているコマンド信号に対する期待値データとを比較して、一致している場合には判定実行コマンドであると判断し、一致しない場合には判定実行コマンドではないと判断することができる。
【0016】
上記構成によれば、外部から予め定められた特定の信号(コマンド信号)をデータ入出力端子に入力して、コマンド信号(そのデータ値)とコントローラによって記憶部に記憶されている期待値とを比較するだけで、判定を実行するか否かを容易に判断することができる。
【0017】
前記記憶部には、様々なパッケージに対応するために、予め必要な複数の期待値が記憶されているのが好ましい。
【0018】
上記構成によれば、試験が行われるデバイスによって最適な期待値を格納しておくことができるため、様々なパッケージ、端子配置等に対応することができる。
【0019】
本発明の半導体記憶装置の試験方法は、本発明の半導体記憶装置を実装後に、外部と接続されて信号が入出力される外部端子のコンタクト状態を判定する試験方法であって、各外部端子に外部から特定の信号を入力し、前記認識部によって、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識するステップと、判定実行コマンドであると認識された場合に、前記比較判定結果出力部によって、アドレス入力端子から入力された信号と予め記憶部に記憶されている期待値データとを比較判定するステップとを含むことを特徴とする。
【0020】
上記方法によれば、電源端子に電源を印加して通常にデバイスを立ち上げた後、外部から予め定められた特定の信号を入力する。データ入出力端子からのコマンド信号が記憶部に記憶されている期待値と比較されて、判定実行コマンドとして認識されると、続いて入力されるアドレス入力端子からの信号と記憶部に記憶されている期待値とが比較されて判定結果が出力される。この判定結果によって、従来技術よりも簡易な方法で、ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、精度良くチェックすることができる。また、この機能は、デバイスを通常使用する際のライトタイミングおよびリードタイミングによって実現することができるので、この機能をシステムボード上のコントローラに搭載することによって、他に試験装置を設けなくても、システムボード単体でコンタクト状態をチェックすることができる。
【0021】
前記特定の信号には、少なくとも2種類のパターンが含まれ、各外部端子に対して、少なくとも2回、コンタクト状態の判定を行うのが好ましい。
【0022】
上記方法によれば、2種類以上のパターンの信号によって試験を行うことによって、検出精度をより向上させることができる。
【0023】
【発明の実施の形態】
以下に、本発明の実施の形態について、図面に基づいて説明する。
【0024】
図1は、本発明の一実施形態である半導体記憶装置の概略構成について説明するためのブロック図である。図1では、半導体記憶装置の試験方法について説明するために、半導体記憶装置の端子部近傍のみを示しているが、各入出力端子および入力端子は、コントローラ1を介して、図示しないメモリセルに接続されている。各入出力端子および入力端子のコンタクト状態を判定する判定処理を行わない通常動作時には、コントローラ1は、各入出力端子および入力端子と、メモリセルとの間の信号の入出力を制御して、メモリセルへの情報の書き込みおよびメモリセルからの情報の読み出しを制御するようになっている。
【0025】
この半導体記憶装置は、外部と接続されて信号が入力または入出力される端子として、アドレス信号が入力されるアドレス入出力端子A0〜Amと、データ信号が入出力されるデータ入出力端子DQ0〜DQnと、チップイネーブル信号が入力されるチップ選択用端子CE#と、ライトイネーブル信号が入力されるコマンド制御用端子WE#と、アウトプットイネーブル信号が入力されるデータ出力制御用端子OE#と、リセット動作および超省消費電力モード制御用信号が入力されるリセットパワーダウンピンRP#とを有している。なお、各端子記号の後ろの#は、その端子に入力される信号がアクティブローの信号であることを示している。
【0026】
各アドレス入力端子A0〜Amから入力される信号は、それぞれ、入力バッファ2を介してコントローラ1に入力される。また、各データ入出力端子DQ0〜DQnから入出力される信号は、それぞれ、入出力バッファ3を介してコントローラ1に入出力される。チップイネーブル信号(CE#)、ライトイネーブル信号(WE#)、アウトプットイネーブル信号(OE#)、リセット動作および超省消費電力モード制御用信号(RP#)は、それぞれ、コントローラ1に入力される。また、デバイス内部の記憶領域4には、アドレス端子およびデータ端子から入力される各信号の期待値がそれぞれ記憶されており、コントローラ1に供給されるようになっている。コントローラ1の内部には、データ端子から入力された信号DQ0〜DQnと記憶領域4から供給された信号の期待値とを比較して、コンタクト状態を判定するための判定実行コマンドであるか否かを認識する認識部と、アドレス端子から入力された信号A0〜Amと記憶領域4から供給された信号の期待値とを比較して判定結果を出力する比較判定結果出力部とが設けられている。
【0027】
以下に、図2に示すようなCSP(Chip Size Package)デバイスを例として、本実施形態の半導体記憶装置の試験方法について説明する。このデバイスにおいて、各端子は、図2に示すように、マトリックス状に配置されている。この図2において、5Eに配置されているVccは電源端子であり、1Eおよび8Eに配置されているGNDは接地端子である。また、A0〜A17はアドレス入力端子であり、DQ0からDQ15はデータ入出力端子であり、CE#はチップイネーブル信号入力端子であり、WE#はライトイネーブル信号入力端子であり、OE#はアウトプットイネーブル信号入力端子でありRP#はリセット動作および超省消費電力モード制御用信号入力端子である。さらに、4Bに配置されているVppは電源端子であり、4A、3B、6B、4C、5C、8Fに配置されているNCはノンコネクト端子である。
【0028】
ここで、アドレス端子およびデータ端子に入力される信号としては、図3および図4に示すように、隣り合う端子(例えば1Aに配置されている端子と2Aに配置されている端子など)に対して、別のレベル(”L”および”H”)の信号を入力した方が効果的である。これによって、その端子の接続状態(コンタクト状態)だけでなく、隣接する端子との短絡も同時に試験することができる。なお、図4は図3に示す入力信号レベル”H”および”L”を反転させた例を示す。
【0029】
図3に示す入力信号に対応するアドレス端子、データ端子への入力値は、それぞれ、図6に(1)で示すような値になり、図4に示す入力信号に対応したアドレス端子、データ端子への入力値は、それぞれ、図6に(2)で示すような値になる。これらの値は、期待値として使用するために、図1に示すデバイス内部の記憶領域4に予め格納されている。この記憶領域4は、メインメモリセルとは別領域に設けられており、構造はメインメモリセルと同じであっても異なっていてもよい。
【0030】
デバイスに電源電圧を印加した後で、図5に示すタイミングチャートにおいて(1)の部分で示すように、ライトイネーブル信号WE#を用いたタイミングによって、図6に(1)で示す値AmおよびDQnが、アドレス端子およびデータ端子からそれぞれ入力される。
【0031】
このとき、データ端子から入力された値が正しく図1に示す入出力バッファ3に格納され、コントローラ1内部の認識部において記憶領域4からの期待値と比較され、判定実行コマンドであるか否かが判断される。そして、判定実行コマンドとして認識されると、アドレス端子から入力された値が格納されている入力バッファ2の値と記憶領域4からの期待値とがコントローラ1内部の認識部において比較される。この比較結果が一致すれば、コントローラ1の比較判定結果出力部から、予め決められた合格を示す値(例えば0×80)が、一致しなければ不合格を示す値(例えば0×80以外の値)が出力され、入出力バッファ3を介してデータ入出力端子から判定結果として出力される。
【0032】
出力された判定結果は、図5に示すタイミングチャートにおいて(2)の部分で示すように、OE#端子に”L”の信号を印加することによって、データ端子から出力される判定結果がリードされて確認される。
【0033】
続いて、コンタクト状態が不良である端子でも、入力信号が偶然に一致して判定結果が不正確になることを避けるために、図6に示す(1)とは”H”と”L”の論理を逆にした図6に(2)で示す値を使用して、同様の方法によって再度、コンタクト状態を判定する。
【0034】
ここで、例えばデータ入出力端子にコンタクト不良がある場合には、データ入出力端子から入力された値が判定実行コマンドとして認識されないため、アドレス入力端子から入力された値と期待値との比較自体が行われず、出力結果が合格を示す値ではないことから、コンタクト不良があると判定することができる。また、アドレス入力端子にコンタクト不良がある場合には、アドレス入力端子から入力された値と期待値との比較は行なわれるが、入力バッファ2に格納される値は期待値とは異なる値になり、不合格の判定結果が出力されることから、コンタクト不良があると判定することができる。さらに、ライトイネーブル信号入力端子WE#にコンタクト不良がある場合には、デバイスに対してデータ入出力端子からの入力が行なわれず、入出力バッファ3に値が格納されないため、判定実行コマンドとして認識されず、比較は行なわれないことから、コンタクト不良があると判定することができる。また、アウトプットイネーブル信号入力端子OE#にコンタクト不良がある場合には、比較判定結果が出力されないことから、コンタクト不良があると判定することができる。また、リセット動作および超消費電力モード制御信号入力端子RP#にコンタクト不良がある場合には、デバイスがリセットされないことから、コンタクト不良があると判定することができる。さらに、チップイネーブル信号入力端子CE#にコンタクト不がある場合には、デバイスが動作しないことから、コンタクト不良があると判定することができる。
【0035】
以上のように、本実施形態によれば、従来よりも簡単な方法で効率よく、外部端子のコンタクト状態をチェックすることができる。
【0036】
【発明の効果】
以上詳述したように、本発明によれば、外部から予め定められた特定の信号を入力し、内部のコントローラによって記憶部に記憶されている期待値と比較することによって、ボード等に半導体記憶装置が実装された後で、各外部端子のコンタクト状態を、従来技術よりも簡単に精度良くチェックすることができる。また、半導体記憶装置が実装されるシステムボードのコントローラに、信号の入力と比較結果の判定機能とを持たせることによって、試験用装置を別に設けなくても、システムボード単体で外部端子のコンタクト状態をチェックすることができる。
【0037】
また、本発明によれば、外部からコマンド信号として入力された値を内部のコントローラによって記憶部に記憶されている期待値とを比較するだけで、従来よりも簡単な方法によって、各外部端子のコンタクト状態をチェックすることができる。
【0038】
また、本発明によれば、試験が行われるデバイスによって最適な期待値を格納しておくことができるため、様々なパッケージ、端子配置等に対応することができる。
【0039】
また、本発明によれば、従来技術よりも簡易な方法で、ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、精度良くチェックすることができる。
【0040】
さらに、本発明によれば、2種類以上のパターンの信号によって試験を行うことによって、検出精度をより向上させることができる。
【図面の簡単な説明】
【図1】本発明の一実施形態である半導体記憶装置の概略構成を説明するためのブロック図である。
【図2】本発明の一実施形態である半導体記憶装置において、CSPパッケージを例とした端子配置例を示す図である。
【図3】本発明の一実施形態である半導体記憶装置における、入力信号の一例を示す図である。
【図4】本発明の一実施形態である半導体記憶装置における、入力信号の他の例を示す図である。
【図5】本発明の一実施形態である半導体記憶装置の試験方法を説明するためのタイミングチャートである。
【図6】本発明の一実施形態である半導体記憶装置の試験方法における、入力信号の期待値の例である。
【符号の説明】
1 デバイス内部のコントローラ
2 アドレス入力バッファ
3 データ入出力バッファ
4 デバイス内部の期待値記憶領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device that can easily check a contact state of an external terminal after being mounted on a board or the like, and a test method thereof.
[0002]
[Prior art]
In order to check the contact state of each terminal (external terminal) that is connected to the outside and inputs / outputs signals in the semiconductor memory device after the semiconductor memory device (semiconductor chip) is mounted on a board or the like after being mounted on a package The following methods are mentioned.
[0003]
The most primitive method is a method of visually confirming the soldering state of each external terminal. It can also be confirmed by actually operating the device after mounting the semiconductor memory device on a board or the like. Further, in a logic device such as a gate array, there is a method of determining by separately mounting a test circuit for performing a boundary scan or the like defined by JTAG.
[0004]
Japanese Patent Laid-Open No. 2000-206197 proposes a test circuit and a test method for performing a contact check of external terminals more easily than the above method in a state where a memory device such as a DRAM is mounted on a board. Yes. This prior art is intended to perform a test by simple timing setting within a voltage range normally used for a device without providing a dedicated test terminal. When a test is performed, a test signal is activated by applying a specific signal to an external terminal after applying a power supply voltage to the device. Actually, the test circuit can be activated by switching the chip selection terminal from the non-selected state to the selected state. Further, the external terminals are divided into a plurality of groups according to the use, and the test is sequentially performed on each group.
[0005]
[Problems to be solved by the invention]
In recent years, electronic devices have become smaller and thinner, and semiconductor packages such as CSP (Chip Size Package) and BGA (Ba11 Grid Array), which have a smaller mounting area, have become mainstream. In these packages, external terminals are arranged in a matrix state on the bottom surface of the package, and it is virtually impossible to visually confirm the soldered state of each terminal after mounting on a board or the like.
[0006]
Further, when the contact state of the external terminal is determined by actually operating the device, it is very difficult to check the contact state of all the terminals only with a simple operation. In order to improve detection accuracy by this method, it is necessary to operate the semiconductor memory device with a large number of patterns. For this reason, in order to perform a test that can reliably detect the contact state of all the external terminals, it is necessary to provide a test apparatus outside the device to execute the operation in the required number of patterns, and the cost for the test Becomes higher.
[0007]
In order to perform boundary scan or the like, generally, it is necessary to separately provide a terminal for starting a dedicated test circuit, and adding the test circuit increases the circuit scale and complexity. Therefore, the method of performing the boundary scan is not suitable for a general semiconductor memory device that is required to be reduced in size and cost.
Further, since the board itself on which the semiconductor memory device is mounted has been integrated, it has become difficult to perform a test by connecting an external test circuit to the semiconductor memory device.
[0008]
In order to solve these problems, in Japanese Patent Laid-Open No. 2000-206197, each terminal is divided into a plurality of groups, for example, in the case of DRAM, a chip selection terminal, an address input terminal, and a data input / output terminal. I am testing. However, in the method disclosed in this publication, it is necessary to perform the test as many times as the number of groups, and since the test is performed by changing the input signal for each terminal in the group, the contact state of all terminals is checked. In order to do this, it is necessary to test as many terminals as possible.
[0009]
Furthermore, in the case of a device having a relatively small number of terminals such as a DRAM, there are few problems. However, in order to apply the technique of the above publication to a device having a large number of terminals, such as a NOR flash memory, in which random access is performed. Therefore, the contact state of the terminal cannot be easily checked. For example, when testing an address input terminal or the like, as shown in FIG. 4 of the above publication, since a test is performed using a plurality of input patterns, the number of input patterns increases as the number of terminals increases. Furthermore, since the capacity of such devices is increasing, the number of terminals is increasing.
[0010]
Therefore, the technique of the above publication is effective for specifying which address input terminal has a problem, but is not suitable for simply checking the contact state of the external terminal after mounting.
[0011]
Further, in the technique of the above publication, the test circuit is started by changing the chip selection terminal from the non-selected state to the selected state. To stop the test circuit and use it in a normal state, the device is turned on. Each time it is raised, it is necessary to input a dummy signal to the chip selection terminal as many times as the number of groups to shift to the normal operation mode, which is not general purpose.
[0012]
The present invention has been made in order to solve such a problem of the prior art, and after mounting a semiconductor memory device on a board or the like, it is as simple as normal operation without adding a dedicated test terminal. An object of the present invention is to provide a semiconductor memory device and a test method thereof that can easily and accurately determine the contact state of an external terminal at a precise timing.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device of the present invention controls input / output of a signal between an external terminal connected to the outside and through which a signal is input / output and an internal storage area, and a semiconductor memory device A controller that determines a contact state of each terminal by inputting a specific signal to an external terminal after mounting the board on a board, and a storage unit in which expected value data of the specific signal is stored in the storage area The controller recognizes whether the command signal input from the data input / output terminal indicates a determination execution command, and an address when the recognition unit recognizes the determination execution command. The signal input from the input terminal is compared with the expected value data stored in the storage unit, and if they match, the determination result is accepted, and if they do not match, the determination result is rejected. And having a comparison determination result output unit that force.
[0014]
According to the above configuration, when a predetermined signal is input from the outside, it is determined whether or not to execute the determination based on the command signal input to the data input / output terminal, and the determination is performed. After the semiconductor memory device is mounted on the board or the like by comparing the signal (its data value) input from the address input terminal with the expected value stored in the storage unit by the controller, the contact of each terminal The status can be checked more easily and accurately than in the prior art. The expected value can be written in a storage area inside the device at the time of a device shipment test or the like. Alternatively, it can be written from the manufacturing stage of the device. This function can be realized by the write timing and read timing when the device is used normally. By installing this function in the controller on the system board, the system board can be installed without any other test equipment. You can check the contact status by itself.
[0015]
The storage unit further stores expected value data for the command signal, and the recognition unit receives the command signal input from the data input / output terminal and the expected value for the command signal stored in the storage block. By comparing with the data, if they match, it can be determined that the command is a determination execution command, and if they do not match, it can be determined that the command is not a determination execution command.
[0016]
According to the above configuration, a specific signal (command signal) determined in advance from the outside is input to the data input / output terminal, and the command signal (its data value) and the expected value stored in the storage unit by the controller are obtained. It is possible to easily determine whether or not to execute the determination only by comparing.
[0017]
It is preferable that the storage unit stores a plurality of expected values necessary in advance in order to cope with various packages.
[0018]
According to the above configuration, since an optimum expected value can be stored depending on the device to be tested, it is possible to deal with various packages, terminal arrangements, and the like.
[0019]
A test method for a semiconductor memory device of the present invention is a test method for determining a contact state of an external terminal that is connected to the outside and inputs / outputs a signal after the semiconductor memory device of the present invention is mounted. When a specific signal is input from the outside and the recognition unit recognizes whether the command signal input from the data input / output terminal indicates a determination execution command, and when it is recognized as a determination execution command The comparison determination result output unit includes a step of comparing and determining the signal input from the address input terminal and the expected value data stored in the storage unit in advance.
[0020]
According to the above method, a predetermined signal is input from the outside after applying power to the power supply terminal to normally start up the device. When the command signal from the data input / output terminal is compared with the expected value stored in the storage unit and recognized as a determination execution command, the signal input from the address input terminal that is subsequently input and stored in the storage unit The result is compared with the expected value. Based on the determination result, the contact state of each terminal can be checked with high accuracy after the semiconductor memory device is mounted on a board or the like by a simpler method than the prior art. Also, this function can be realized by the write timing and read timing when the device is normally used, so by installing this function in the controller on the system board, no other test equipment is provided, The contact status can be checked with a single system board.
[0021]
The specific signal includes at least two types of patterns, and it is preferable that the contact state is determined at least twice for each external terminal.
[0022]
According to the above method, the detection accuracy can be further improved by performing the test with signals of two or more types of patterns.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0024]
FIG. 1 is a block diagram for explaining a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, only the vicinity of the terminal portion of the semiconductor memory device is shown in order to explain the test method of the semiconductor memory device, but each input / output terminal and input terminal are connected to a memory cell (not shown) via the
[0025]
This semiconductor memory device is connected to the outside, and as input / output terminals for signals, address input / output terminals A0 to Am to which address signals are input, and data input / output terminals DQ0 to DQ0 to which data signals are input / output. DQn, a chip selection terminal CE # to which a chip enable signal is input, a command control terminal WE # to which a write enable signal is input, a data output control terminal OE # to which an output enable signal is input, A reset power down pin RP # to which a signal for reset operation and super power saving mode control is input. The # after each terminal symbol indicates that the signal input to that terminal is an active low signal.
[0026]
Signals input from the address input terminals A0 to Am are input to the
[0027]
Hereinafter, a test method for the semiconductor memory device according to the present embodiment will be described by taking a CSP (Chip Size Package) device as shown in FIG. 2 as an example. In this device, the terminals are arranged in a matrix as shown in FIG. In FIG. 2, Vcc arranged at 5E is a power supply terminal, and GND arranged at 1E and 8E is a ground terminal. A0 to A17 are address input terminals, DQ0 to DQ15 are data input / output terminals, CE # is a chip enable signal input terminal, WE # is a write enable signal input terminal, and OE # is an output. An enable signal input terminal RP # is a signal input terminal for reset operation and super power saving mode control. Further, Vpp arranged in 4B is a power supply terminal, and NC arranged in 4A, 3B, 6B, 4C, 5C, 8F is a non-connect terminal.
[0028]
Here, as shown in FIGS. 3 and 4, the signals input to the address terminal and the data terminal are connected to adjacent terminals (for example, the terminal disposed at 1A and the terminal disposed at 2A). Therefore, it is more effective to input signals of different levels (“L” and “H”). Thereby, not only the connection state (contact state) of the terminal but also a short circuit with an adjacent terminal can be tested simultaneously. FIG. 4 shows an example in which the input signal levels “H” and “L” shown in FIG. 3 are inverted.
[0029]
The input values to the address terminal and data terminal corresponding to the input signal shown in FIG. 3 are values as indicated by (1) in FIG. 6, and the address terminal and data terminal corresponding to the input signal shown in FIG. Each of the input values to is a value as indicated by (2) in FIG. These values are stored in advance in the storage area 4 inside the device shown in FIG. 1 for use as an expected value. The storage area 4 is provided in a different area from the main memory cell, and the structure may be the same as or different from the main memory cell.
[0030]
After applying the power supply voltage to the device, the values Am and DQn shown in FIG. 6 (1) according to the timing using the write enable signal WE #, as shown in the part (1) in the timing chart shown in FIG. Are respectively input from the address terminal and the data terminal.
[0031]
At this time, the value input from the data terminal is correctly stored in the input /
[0032]
As shown in part (2) in the timing chart of FIG. 5, the output determination result is read from the data terminal by applying an “L” signal to the OE # terminal. Is confirmed.
[0033]
Subsequently, in order to avoid an inaccurate determination result due to an accidental coincidence of input signals even with a terminal having a poor contact state, (1) shown in FIG. 6 is “H” and “L”. Using the value indicated by (2) in FIG. 6 in which the logic is reversed, the contact state is determined again by the same method.
[0034]
Here, for example, when there is a contact failure in the data input / output terminal, the value input from the data input / output terminal is not recognized as a determination execution command, so the comparison between the value input from the address input terminal and the expected value itself Is not performed and the output result is not a value indicating acceptance, so that it can be determined that there is a contact failure. If the address input terminal has a contact failure, the value input from the address input terminal is compared with the expected value, but the value stored in the
[0035]
As described above, according to this embodiment, it is possible to check the contact state of the external terminal more efficiently by a simpler method than in the past.
[0036]
【The invention's effect】
As described above in detail, according to the present invention, a specific signal predetermined from the outside is input and compared with an expected value stored in a storage unit by an internal controller, so that a semiconductor memory is stored in a board or the like. After the device is mounted, the contact state of each external terminal can be checked more easily and accurately than in the prior art. In addition, by providing the controller of the system board on which the semiconductor memory device is mounted with signal input and comparison result judgment functions, the contact state of the external terminals can be achieved with a single system board without the need for a separate test device. Can be checked.
[0037]
In addition, according to the present invention, it is possible to simply compare the value input as a command signal from the outside with the expected value stored in the storage unit by the internal controller, by a simpler method than conventional methods. You can check the contact status.
[0038]
Further, according to the present invention, since an optimum expected value can be stored depending on the device to be tested, it is possible to cope with various packages, terminal arrangements, and the like.
[0039]
Further, according to the present invention, the contact state of each terminal can be checked with high accuracy after the semiconductor memory device is mounted on a board or the like by a simpler method than the prior art.
[0040]
Furthermore, according to the present invention, the detection accuracy can be further improved by performing a test using signals of two or more types of patterns.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a schematic configuration of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a diagram showing a terminal arrangement example using a CSP package as an example in the semiconductor memory device according to the embodiment of the present invention;
FIG. 3 is a diagram showing an example of an input signal in the semiconductor memory device according to one embodiment of the present invention.
FIG. 4 is a diagram showing another example of an input signal in the semiconductor memory device according to one embodiment of the present invention.
FIG. 5 is a timing chart for explaining a test method for a semiconductor memory device according to an embodiment of the present invention;
FIG. 6 is an example of an expected value of an input signal in the method for testing a semiconductor memory device according to an embodiment of the present invention.
[Explanation of symbols]
1 Controller inside
Claims (4)
アドレス信号が入力されるアドレス入力端子と、データが入出力されるデータ入出力端子とを有する外部端子と、
前記外部端子と内部の記憶領域との間の信号の入出力を制御するコントローラと、
前記記憶領域内に設けられ、前記データ入出力端子から入力される第1特定信号に対する第1期待値データと、前記アドレス入力端子から入力される第2特定信号に対する第2期待値データとが記憶されている記憶部とを備え、
前記コントローラは、
前記データ入出力端子から入力される前記第1特定信号と、前記記憶部に記憶された前記第1期待値データとを比較して両者が一致するかの第1認識動作と、該第1認識動作の結果、前記第1特定信号と前記第1期待値データとが一致する場合に、前記アドレス入力端子から入力される前記第2特定信号と前記記憶部に記憶された前記第2期待値データとを比較して両者が一致するかの第2認識動作とを実行する認識部と、
前記認識部における前記第2認識動作の判定結果を出力する比較判定結果出力部と、
を有することを特徴とする半導体記憶装置。 A semiconductor storage device mounted on a board,
An external terminal having an address input terminal to which an address signal is input and a data input / output terminal to which data is input / output;
A controller for controlling input / output of signals between the external terminal and an internal storage area ;
Provided in the storage area, the data and the first expected value data for a first specific signal input from the input-output terminal, a second expected value data for a second specific signal input from the address input terminal memory A storage unit,
The controller is
A first recognition operation for comparing the first specific signal input from the data input / output terminal with the first expected value data stored in the storage unit to determine whether they match, and the first recognition As a result of the operation, when the first specific signal matches the first expected value data, the second specific value input from the address input terminal and the second expected value data stored in the storage unit A recognizing unit that performs a second recognizing operation as to whether the two match each other,
A comparison determination result output unit for outputting a determination result of the second recognition operation in the recognition unit,
A semiconductor memory device comprising:
前記認識部が、前記データ入出力端子から入力される前記第1特定信号と、前記記憶部に記憶された前記第1期待値データとを比較して両者が一致するかの第1認識動作を実行するステップと、
前記認識部が、前記第1特定信号と前記第1期待値データとが一致すると認識した場合に、前記アドレス入端子から入力される第2特定信号と、前記記憶部に記憶された前記第2期待値データとを比較して両者が一致するかの第2認識動作を実行するステップと、
前記比較判定結果出力部が、前記第2認識動作の結果、合格または不合格の判定結果を出力するステップと、
を包含することを特徴とする半導体記憶装置の試験方法。 A test method for determining a contact state of an external terminal of the semiconductor memory device according to claim 1 ,
The recognition section includes a first specific signal input from the data input-output terminal, whether the first recognition operation both by comparing the first expected value data stored in the storage unit matches Steps to perform ;
The recognition unit, when recognizing the first specific signal and the first expected value data matches, the address and the second specific signal input from input terminal, said second stored in the storage unit A step of comparing the expected value data and executing a second recognition operation to determine whether they match ,
The comparison determination result output unit outputs the determination result of pass or fail as a result of the second recognition operation;
A method for testing a semiconductor memory device, comprising:
前記第1認識動作が、前記複数の第1特定信号と前記複数の第1期待値データとがそれぞれ一致するかの認識動作であり、前記第2認識動作が、前記複数の第2特定信号と前記複数の第2期待値データとがそれぞれ一致するかの認識動作である、請求項3に記載の半導体記憶装置の試験方法。 The storage unit stores a plurality of first expected value data corresponding to each of the plurality of first specific signals, and a plurality of the first expected data corresponding to each of the plurality of second specific signals. 2 Expected value data is stored,
The first recognizing operation is a recognizing operation as to whether the plurality of first specific signals and the plurality of first expected value data respectively match, and the second recognizing operation is performed with the plurality of second specific signals. 4. The test method for a semiconductor memory device according to claim 3, wherein the operation is a recognition operation as to whether each of the plurality of second expected value data matches .
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