JP3925839B2 - Semiconductor memory device and test method thereof - Google Patents

Semiconductor memory device and test method thereof Download PDF

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Publication number
JP3925839B2
JP3925839B2 JP2001274247A JP2001274247A JP3925839B2 JP 3925839 B2 JP3925839 B2 JP 3925839B2 JP 2001274247 A JP2001274247 A JP 2001274247A JP 2001274247 A JP2001274247 A JP 2001274247A JP 3925839 B2 JP3925839 B2 JP 3925839B2
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Prior art keywords
input
terminal
expected value
value data
plurality
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JP2003086000A (en
Inventor
真治 石川
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シャープ株式会社
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device that can easily check a contact state of an external terminal after being mounted on a board or the like, and a test method thereof.
[0002]
[Prior art]
In order to check the contact state of each terminal (external terminal) that is connected to the outside and inputs / outputs signals in the semiconductor memory device after the semiconductor memory device (semiconductor chip) is mounted on a board or the like after being mounted on a package The following methods are mentioned.
[0003]
The most primitive method is a method of visually confirming the soldering state of each external terminal. It can also be confirmed by actually operating the device after mounting the semiconductor memory device on a board or the like. Further, in a logic device such as a gate array, there is a method of determining by separately mounting a test circuit for performing a boundary scan or the like defined by JTAG.
[0004]
Japanese Patent Laid-Open No. 2000-206197 proposes a test circuit and a test method for performing a contact check of external terminals more easily than the above method in a state where a memory device such as a DRAM is mounted on a board. Yes. This prior art is intended to perform a test by simple timing setting within a voltage range normally used for a device without providing a dedicated test terminal. When a test is performed, a test signal is activated by applying a specific signal to an external terminal after applying a power supply voltage to the device. Actually, the test circuit can be activated by switching the chip selection terminal from the non-selected state to the selected state. Further, the external terminals are divided into a plurality of groups according to the use, and the test is sequentially performed on each group.
[0005]
[Problems to be solved by the invention]
In recent years, electronic devices have become smaller and thinner, and semiconductor packages such as CSP (Chip Size Package) and BGA (Ba11 Grid Array), which have a smaller mounting area, have become mainstream. In these packages, external terminals are arranged in a matrix state on the bottom surface of the package, and it is virtually impossible to visually confirm the soldered state of each terminal after mounting on a board or the like.
[0006]
Further, when the contact state of the external terminal is determined by actually operating the device, it is very difficult to check the contact state of all the terminals only with a simple operation. In order to improve detection accuracy by this method, it is necessary to operate the semiconductor memory device with a large number of patterns. For this reason, in order to perform a test that can reliably detect the contact state of all the external terminals, it is necessary to provide a test apparatus outside the device to execute the operation in the required number of patterns, and the cost for the test Becomes higher.
[0007]
In order to perform boundary scan or the like, generally, it is necessary to separately provide a terminal for starting a dedicated test circuit, and adding the test circuit increases the circuit scale and complexity. Therefore, the method of performing the boundary scan is not suitable for a general semiconductor memory device that is required to be reduced in size and cost.
Further, since the board itself on which the semiconductor memory device is mounted has been integrated, it has become difficult to perform a test by connecting an external test circuit to the semiconductor memory device.
[0008]
In order to solve these problems, in Japanese Patent Laid-Open No. 2000-206197, each terminal is divided into a plurality of groups, for example, in the case of DRAM, a chip selection terminal, an address input terminal, and a data input / output terminal. I am testing. However, in the method disclosed in this publication, it is necessary to perform the test as many times as the number of groups, and since the test is performed by changing the input signal for each terminal in the group, the contact state of all terminals is checked. In order to do this, it is necessary to test as many terminals as possible.
[0009]
Furthermore, in the case of a device having a relatively small number of terminals such as a DRAM, there are few problems. However, in order to apply the technique of the above publication to a device having a large number of terminals, such as a NOR flash memory, in which random access is performed. Therefore, the contact state of the terminal cannot be easily checked. For example, when testing an address input terminal or the like, as shown in FIG. 4 of the above publication, since a test is performed using a plurality of input patterns, the number of input patterns increases as the number of terminals increases. Furthermore, since the capacity of such devices is increasing, the number of terminals is increasing.
[0010]
Therefore, the technique of the above publication is effective for specifying which address input terminal has a problem, but is not suitable for simply checking the contact state of the external terminal after mounting.
[0011]
Further, in the technique of the above publication, the test circuit is started by changing the chip selection terminal from the non-selected state to the selected state. To stop the test circuit and use it in a normal state, the device is turned on. Each time it is raised, it is necessary to input a dummy signal to the chip selection terminal as many times as the number of groups to shift to the normal operation mode, which is not general purpose.
[0012]
The present invention has been made in order to solve such a problem of the prior art, and after mounting a semiconductor memory device on a board or the like, it is as simple as normal operation without adding a dedicated test terminal. An object of the present invention is to provide a semiconductor memory device and a test method thereof that can easily and accurately determine the contact state of an external terminal at a precise timing.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device of the present invention controls input / output of a signal between an external terminal connected to the outside and through which a signal is input / output and an internal storage area, and a semiconductor memory device A controller that determines a contact state of each terminal by inputting a specific signal to an external terminal after mounting the board on a board, and a storage unit in which expected value data of the specific signal is stored in the storage area The controller recognizes whether the command signal input from the data input / output terminal indicates a determination execution command, and an address when the recognition unit recognizes the determination execution command. The signal input from the input terminal is compared with the expected value data stored in the storage unit, and if they match, the determination result is accepted, and if they do not match, the determination result is rejected. And having a comparison determination result output unit that force.
[0014]
According to the above configuration, when a predetermined signal is input from the outside, it is determined whether or not to execute the determination based on the command signal input to the data input / output terminal, and the determination is performed. After the semiconductor memory device is mounted on the board or the like by comparing the signal (its data value) input from the address input terminal with the expected value stored in the storage unit by the controller, the contact of each terminal The status can be checked more easily and accurately than in the prior art. The expected value can be written in a storage area inside the device at the time of a device shipment test or the like. Alternatively, it can be written from the manufacturing stage of the device. This function can be realized by the write timing and read timing when the device is used normally. By installing this function in the controller on the system board, the system board can be installed without any other test equipment. You can check the contact status by itself.
[0015]
The storage unit further stores expected value data for the command signal, and the recognition unit receives the command signal input from the data input / output terminal and the expected value for the command signal stored in the storage block. By comparing with the data, if they match, it can be determined that the command is a determination execution command, and if they do not match, it can be determined that the command is not a determination execution command.
[0016]
According to the above configuration, a specific signal (command signal) determined in advance from the outside is input to the data input / output terminal, and the command signal (its data value) and the expected value stored in the storage unit by the controller are obtained. It is possible to easily determine whether or not to execute the determination only by comparing.
[0017]
It is preferable that the storage unit stores a plurality of expected values necessary in advance in order to cope with various packages.
[0018]
According to the above configuration, since an optimum expected value can be stored depending on the device to be tested, it is possible to deal with various packages, terminal arrangements, and the like.
[0019]
A test method for a semiconductor memory device of the present invention is a test method for determining a contact state of an external terminal that is connected to the outside and inputs / outputs a signal after the semiconductor memory device of the present invention is mounted. When a specific signal is input from the outside and the recognition unit recognizes whether the command signal input from the data input / output terminal indicates a determination execution command, and when it is recognized as a determination execution command The comparison determination result output unit includes a step of comparing and determining the signal input from the address input terminal and the expected value data stored in the storage unit in advance.
[0020]
According to the above method, a predetermined signal is input from the outside after applying power to the power supply terminal to normally start up the device. When the command signal from the data input / output terminal is compared with the expected value stored in the storage unit and recognized as a determination execution command, the signal input from the address input terminal that is subsequently input and stored in the storage unit The result is compared with the expected value. Based on the determination result, the contact state of each terminal can be checked with high accuracy after the semiconductor memory device is mounted on a board or the like by a simpler method than the prior art. Also, this function can be realized by the write timing and read timing when the device is normally used, so by installing this function in the controller on the system board, no other test equipment is provided, The contact status can be checked with a single system board.
[0021]
The specific signal includes at least two types of patterns, and it is preferable that the contact state is determined at least twice for each external terminal.
[0022]
According to the above method, the detection accuracy can be further improved by performing the test with signals of two or more types of patterns.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0024]
FIG. 1 is a block diagram for explaining a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, only the vicinity of the terminal portion of the semiconductor memory device is shown in order to explain the test method of the semiconductor memory device, but each input / output terminal and input terminal are connected to a memory cell (not shown) via the controller 1. It is connected. During normal operation in which the determination process for determining the contact state of each input / output terminal and input terminal is not performed, the controller 1 controls the input / output of signals between the input / output terminals and input terminal and the memory cell, Information writing to the memory cell and information reading from the memory cell are controlled.
[0025]
This semiconductor memory device is connected to the outside, and as input / output terminals for signals, address input / output terminals A0 to Am to which address signals are input, and data input / output terminals DQ0 to DQ0 to which data signals are input / output. DQn, a chip selection terminal CE # to which a chip enable signal is input, a command control terminal WE # to which a write enable signal is input, a data output control terminal OE # to which an output enable signal is input, A reset power down pin RP # to which a signal for reset operation and super power saving mode control is input. The # after each terminal symbol indicates that the signal input to that terminal is an active low signal.
[0026]
Signals input from the address input terminals A0 to Am are input to the controller 1 via the input buffer 2, respectively. Signals input / output from the data input / output terminals DQ0 to DQn are input / output to / from the controller 1 via the input / output buffer 3, respectively. The chip enable signal (CE #), the write enable signal (WE #), the output enable signal (OE #), the reset operation and the super power saving mode control signal (RP #) are input to the controller 1, respectively. . The storage area 4 inside the device stores the expected value of each signal input from the address terminal and data terminal, and supplies it to the controller 1. Whether the controller 1 has a determination execution command for determining the contact state by comparing the signals DQ0 to DQn input from the data terminal with the expected value of the signal supplied from the storage area 4. And a comparison / determination result output unit that compares the signals A0 to Am input from the address terminal with the expected value of the signal supplied from the storage area 4 and outputs a determination result. .
[0027]
Hereinafter, a test method for the semiconductor memory device according to the present embodiment will be described by taking a CSP (Chip Size Package) device as shown in FIG. 2 as an example. In this device, the terminals are arranged in a matrix as shown in FIG. In FIG. 2, Vcc arranged at 5E is a power supply terminal, and GND arranged at 1E and 8E is a ground terminal. A0 to A17 are address input terminals, DQ0 to DQ15 are data input / output terminals, CE # is a chip enable signal input terminal, WE # is a write enable signal input terminal, and OE # is an output. An enable signal input terminal RP # is a signal input terminal for reset operation and super power saving mode control. Further, Vpp arranged in 4B is a power supply terminal, and NC arranged in 4A, 3B, 6B, 4C, 5C, 8F is a non-connect terminal.
[0028]
Here, as shown in FIGS. 3 and 4, the signals input to the address terminal and the data terminal are connected to adjacent terminals (for example, the terminal disposed at 1A and the terminal disposed at 2A). Therefore, it is more effective to input signals of different levels (“L” and “H”). Thereby, not only the connection state (contact state) of the terminal but also a short circuit with an adjacent terminal can be tested simultaneously. FIG. 4 shows an example in which the input signal levels “H” and “L” shown in FIG. 3 are inverted.
[0029]
The input values to the address terminal and data terminal corresponding to the input signal shown in FIG. 3 are values as indicated by (1) in FIG. 6, and the address terminal and data terminal corresponding to the input signal shown in FIG. Each of the input values to is a value as indicated by (2) in FIG. These values are stored in advance in the storage area 4 inside the device shown in FIG. 1 for use as an expected value. The storage area 4 is provided in a different area from the main memory cell, and the structure may be the same as or different from the main memory cell.
[0030]
After applying the power supply voltage to the device, the values Am and DQn shown in FIG. 6 (1) according to the timing using the write enable signal WE #, as shown in the part (1) in the timing chart shown in FIG. Are respectively input from the address terminal and the data terminal.
[0031]
At this time, the value input from the data terminal is correctly stored in the input / output buffer 3 shown in FIG. 1 and compared with the expected value from the storage area 4 in the recognition unit in the controller 1 to determine whether or not it is a determination execution command. Is judged. When the determination execution command is recognized, the value in the input buffer 2 storing the value input from the address terminal and the expected value from the storage area 4 are compared in the recognition unit inside the controller 1. If this comparison result matches, a value indicating a predetermined pass (for example, 0 × 80) from the comparison determination result output unit of the controller 1 is not determined, and if it does not match, a value indicating a failure (for example, other than 0 × 80). Value) is output from the data input / output terminal via the input / output buffer 3 as a determination result.
[0032]
As shown in part (2) in the timing chart of FIG. 5, the output determination result is read from the data terminal by applying an “L” signal to the OE # terminal. Is confirmed.
[0033]
Subsequently, in order to avoid an inaccurate determination result due to an accidental coincidence of input signals even with a terminal having a poor contact state, (1) shown in FIG. 6 is “H” and “L”. Using the value indicated by (2) in FIG. 6 in which the logic is reversed, the contact state is determined again by the same method.
[0034]
Here, for example, when there is a contact failure in the data input / output terminal, the value input from the data input / output terminal is not recognized as a determination execution command, so the comparison between the value input from the address input terminal and the expected value itself Is not performed and the output result is not a value indicating acceptance, so that it can be determined that there is a contact failure. If the address input terminal has a contact failure, the value input from the address input terminal is compared with the expected value, but the value stored in the input buffer 2 is different from the expected value. Since the determination result of failure is output, it can be determined that there is a contact failure. Further, when there is a contact failure at the write enable signal input terminal WE #, no input from the data input / output terminal is made to the device, and no value is stored in the input / output buffer 3, so that it is recognized as a determination execution command. Since no comparison is made, it can be determined that there is a contact failure. In addition, when there is a contact failure at the output enable signal input terminal OE #, the comparison determination result is not output, so it can be determined that there is a contact failure. Further, when there is a contact failure in the reset operation and super power consumption mode control signal input terminal RP #, the device is not reset, so it can be determined that there is a contact failure. Further, when there is no contact at the chip enable signal input terminal CE #, the device does not operate, so it can be determined that there is a contact failure.
[0035]
As described above, according to this embodiment, it is possible to check the contact state of the external terminal more efficiently by a simpler method than in the past.
[0036]
【The invention's effect】
As described above in detail, according to the present invention, a specific signal predetermined from the outside is input and compared with an expected value stored in a storage unit by an internal controller, so that a semiconductor memory is stored in a board or the like. After the device is mounted, the contact state of each external terminal can be checked more easily and accurately than in the prior art. In addition, by providing the controller of the system board on which the semiconductor memory device is mounted with signal input and comparison result judgment functions, the contact state of the external terminals can be achieved with a single system board without the need for a separate test device. Can be checked.
[0037]
In addition, according to the present invention, it is possible to simply compare the value input as a command signal from the outside with the expected value stored in the storage unit by the internal controller, by a simpler method than conventional methods. You can check the contact status.
[0038]
Further, according to the present invention, since an optimum expected value can be stored depending on the device to be tested, it is possible to cope with various packages, terminal arrangements, and the like.
[0039]
Further, according to the present invention, the contact state of each terminal can be checked with high accuracy after the semiconductor memory device is mounted on a board or the like by a simpler method than the prior art.
[0040]
Furthermore, according to the present invention, the detection accuracy can be further improved by performing a test using signals of two or more types of patterns.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a schematic configuration of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a diagram showing a terminal arrangement example using a CSP package as an example in the semiconductor memory device according to the embodiment of the present invention;
FIG. 3 is a diagram showing an example of an input signal in the semiconductor memory device according to one embodiment of the present invention.
FIG. 4 is a diagram showing another example of an input signal in the semiconductor memory device according to one embodiment of the present invention.
FIG. 5 is a timing chart for explaining a test method for a semiconductor memory device according to an embodiment of the present invention;
FIG. 6 is an example of an expected value of an input signal in the method for testing a semiconductor memory device according to an embodiment of the present invention.
[Explanation of symbols]
1 Controller inside device 2 Address input buffer 3 Data input / output buffer 4 Expected value storage area inside device

Claims (4)

  1. A semiconductor storage device mounted on a board,
    An external terminal having an address input terminal to which an address signal is input and a data input / output terminal to which data is input / output;
    A controller for controlling input / output of signals between the external terminal and an internal storage area ;
    Provided in the storage area, the data and the first expected value data for a first specific signal input from the input-output terminal, a second expected value data for a second specific signal input from the address input terminal memory A storage unit,
    The controller is
    A first recognition operation for comparing the first specific signal input from the data input / output terminal with the first expected value data stored in the storage unit to determine whether they match, and the first recognition As a result of the operation, when the first specific signal matches the first expected value data, the second specific value input from the address input terminal and the second expected value data stored in the storage unit A recognizing unit that performs a second recognizing operation as to whether the two match each other,
    A comparison determination result output unit for outputting a determination result of the second recognition operation in the recognition unit,
    A semiconductor memory device comprising:
  2. The storage unit stores a plurality of first expected value data corresponding to each of the plurality of first specific signals, and a plurality of the first expected data corresponding to each of the plurality of second specific signals. 2. The semiconductor memory device according to claim 1, wherein two expected value data is stored .
  3. A test method for determining a contact state of an external terminal of the semiconductor memory device according to claim 1 ,
    The recognition section includes a first specific signal input from the data input-output terminal, whether the first recognition operation both by comparing the first expected value data stored in the storage unit matches Steps to perform ;
    The recognition unit, when recognizing the first specific signal and the first expected value data matches, the address and the second specific signal input from input terminal, said second stored in the storage unit A step of comparing the expected value data and executing a second recognition operation to determine whether they match ,
    The comparison determination result output unit outputs the determination result of pass or fail as a result of the second recognition operation;
    A method for testing a semiconductor memory device, comprising:
  4. The storage unit stores a plurality of first expected value data corresponding to each of the plurality of first specific signals, and a plurality of the first expected data corresponding to each of the plurality of second specific signals. 2 Expected value data is stored,
    The first recognizing operation is a recognizing operation as to whether the plurality of first specific signals and the plurality of first expected value data respectively match, and the second recognizing operation is performed with the plurality of second specific signals. 4. The test method for a semiconductor memory device according to claim 3, wherein the operation is a recognition operation as to whether each of the plurality of second expected value data matches .
JP2001274247A 2001-09-10 2001-09-10 Semiconductor memory device and test method thereof Expired - Fee Related JP3925839B2 (en)

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