JP2003086000A - Semiconductor memory and its test method - Google Patents

Semiconductor memory and its test method

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JP2003086000A
JP2003086000A JP2001274247A JP2001274247A JP2003086000A JP 2003086000 A JP2003086000 A JP 2003086000A JP 2001274247 A JP2001274247 A JP 2001274247A JP 2001274247 A JP2001274247 A JP 2001274247A JP 2003086000 A JP2003086000 A JP 2003086000A
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semiconductor memory
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JP3925839B2 (en
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Shinji Ishikawa
真治 石川
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Sharp Corp
シャープ株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can easily and accurately discriminate a contact state of an external terminal by same simple timing as that in normal operation without adding an exclusive terminal for test after mounting a semiconductor chip on a board. SOLUTION: This memory is provided with a controller 1 inputting a specific signal to an external terminal and discriminating a contact state of each terminal and a storage section 4 of expected value data, the controller 1 has a recognizing section recognizing whether command data inputted from data input/ output terminals DQ0-DGn are a discrimination executing command or not, and a comparison discrimination result outputting section comparing data inputted from address input terminals A0-Am with expected value data stored in the storage section 4 when the command data is recognized as a discrimination executing command, when they are coincident, a discrimination result is outputted as acceptance, and when they are not coincident, a discrimination result is outputted as non-acceptance.

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、ボード等に実装された後に、外部端子のコンタクト状態を容易にチェックすることができる半導体記憶装置およびその試験方法に関する。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention is, after being mounted on a board or the like, a semiconductor memory device and its testing method can easily check the contact state of the external terminals . 【0002】 【従来の技術】半導体記憶装置(半導体チップ)をパッケージに搭載してボード等に実装した後に、その半導体記憶装置において外部と接続されて信号が入出力される各端子(外部端子)のコンタクト状態をチェックするためには、以下のような方法が挙げられる。 [0002] Semiconductor memory device after mounting to be mounted (semiconductor chip) in a package board or the like, each terminal is connected to the outside signal at its semiconductor memory device is input (external terminal) to check the contact state include the following methods. 【0003】最も原始的な方法は、各外部端子の半田付け状態を目視で確認する方法である。 The most primitive method is to check the soldering state of the external terminals visually. また、半導体記憶装置をボード等に実装した後に、実際にデバイスを動作させることによっても確認することができる。 Further, after mounting the semiconductor memory device in the board or the like, it can be confirmed by operating the actual device. さらに、 further,
ゲートアレイ等のロジックデバイスにおいては、JTA In logic device such as a gate array, JTA
Gで規定されているバウンダリスキャン(bounda Boundary-Scan (bounda that are defined in the G
ry scan)等を行なうための試験回路を別途搭載して判断する方法もある。 ry scan) like there is a method of testing circuit determines separately mounted for performing. 【0004】また、特開2000−206197号公報には、DRAM等のメモリデバイスをボードに実装した状態で、上記方法に比べて簡易に外部端子のコンタクトチェックを行なうための試験回路および試験方法が提案されている。 Further, JP-A-2000-206197, in a state of mounting the memory device such as DRAM on the board, test circuit and test method for performing contact check of the external terminal easily as compared with the above method Proposed. この従来技術は、専用の試験用端子を設けることなく、デバイスに通常使用される電圧範囲内で、 This prior art, without providing a dedicated test terminals, in a voltage range that is normally used for device,
簡単なタイミング設定によって試験を行なうことを目的としている。 It is intended to be tested by a simple timing setting. 試験を行う際には、デバイスに電源電圧を印加した後に、外部端子に特定の信号を入力することによって、試験回路を起動させる。 When performing the test, after applying the supply voltage to the device, by entering a specific signal to the external terminal, to start the test circuit. 実際にはチップ選択用端子を非選択状態から選択状態にすることによって試験回路を起動させることができる。 In practice, it is possible to start the test circuit by the selected chip select terminal from the non-selected state. さらに、外部端子を用途によって複数にグループ分けして、それぞれのグループに対して、試験を順次行う。 Further, grouped into a plurality by the application of external terminals, for each group, sequentially performing a test. 【0005】 【発明が解決しようとする課題】近年、電子機器の小型化・薄型化が進み、半導体装置のパッケージについても、より実装面積の少ないCSP(Chip Size [0005] [0006] In recent years, the miniaturization and thinning of electronic devices, for the package of the semiconductor device, with less footprint CSP (Chip Size
Package)、BGA(Ba11 Grid Arr Package), BGA (Ba11 Grid Arr
ay)等が主流になってきている。 ay) and the like are becoming mainstream. これらのパッケージでは、パッケージの底面に外部端子がマトリクス状態に配置されており、ボード等に実装後に各端子の半田付け状態を目視で確認することは実質的に不可能である。 In these packages, the external terminals on the bottom surface of the package are arranged in a matrix state, it is virtually impossible to check the soldering state of each terminal visually after mounting on the board or the like. 【0006】また、デバイスを実際に動作させることによって外部端子のコンタクト状態を判定する場合には、 Further, when determining the contact state of the external terminal by actually operating the device,
簡易な動作だけで全ての端子のコンタクト状態をチェックすることは非常に困難である。 It is very difficult to check the contact state of all of the terminals in only a simple operation. この方法によって検出精度を向上させるためには、多数のパターンで半導体記憶装置に動作を行なわせる必要がある。 In order to improve the detection accuracy by this method, it is necessary to perform the operation in the semiconductor memory device in a number of patterns. このため、全ての外部端子のコンタクト状態を確実に検出できる試験を行うためには、デバイスの外部に試験装置を設けて必要な数のパターンで動作を実行させる必要があり、試験のためのコストが高くなる。 Therefore, in order to reliably detect can be tested for contact state of all of the external terminal, it is necessary to perform the operation by the number of patterns required to provide a testing device external to the device, the cost for the test It increases. 【0007】また、バウンダリスキャン等を行なうためには、一般に、専用の試験回路を起動させるための端子を別途設ける必要があり、また、試験回路を追加することによって回路規模が大きく、複雑になる。 Further, in order to perform the boundary scan or the like, generally, there additionally is necessary to provide a terminal for activating a dedicated test circuit and a large circuit scale by adding a test circuit is complicated . 従って、小型化、低コスト化が要求される一般的な半導体記憶装置には、バウンダリスキャンを行う方法は適していない。 Accordingly, miniaturization, the general semiconductor memory device cost reduction is required, a method of performing boundary scan is not suitable.
さらに、半導体記憶装置が実装されるボード自体も集積化が進んできているため、外部試験回路を半導体記憶装置に接続して試験を行なうことも困難になってきている。 Furthermore, since the board itself on which the semiconductor memory device is mounted has been progressed integration, also it has become difficult to perform the test by connecting the external test circuit in a semiconductor memory device. 【0008】これらの問題を解決するために、上記特開2000−206197号公報では、各端子を複数のグループ、例えばDRAMの場合にはチップ選択端子、アドレス入力端子、データ入出力端子の3つに分けて試験を行っている。 [0008] To solve these problems, in JP-A-2000-206197, three chip select terminal, an address input terminal, a data input-output terminal in the case of the terminals of the plurality of groups, for example, DRAM divided into doing the test to. しかしながら、この公報に開示されている方法では、グループ数の回数だけ試験を行う必要があり、また、グループ中の端子毎に入力信号を変化させて試験を行うため、全端子のコンタクト状態をチェックするためには、端子数だけ試験を行う必要がある。 However, the check in the method disclosed in this publication, it is necessary to perform only the number of tests of the number of groups, also for testing by changing the input signal for each terminal in the group, the contact state of all terminals to, it is necessary to test only the number of terminals. 【0009】さらに、DRAM等の比較的端子数が少ないデバイスの場合には問題は少ないが、例えばNOR型フラッシュメモリ等のようにランダムアクセスが行われる、端子数が多いデバイスに上記公報の技術を適用するためには、容易に端子のコンタクト状態をチェックすることができない。 Furthermore, although fewer problems in the case of relatively terminals fewer devices such as DRAM, for example, a random access as such NOR type flash memory is performed, the technique of the above publication to the device number of terminals is large to apply can not check the contact state of easily terminal. 例えば、アドレス入力端子等のテストを行う場合、上記公報の図4に示すように、複数の入力パターンを用いてテストを行うため、端子数が増えると入力パターンも増えるからである。 For example, when testing the address input terminals and the like, as shown in FIG. 4 of the above publication, for testing by using a plurality of input patterns, because also increases the input pattern number of terminals increases. さらに、このようなデバイスは大容量化が進んでいるため、端子数は増加する一方である。 Further, such devices because it advanced large capacity, which is one of the number of terminals increases. 【0010】従って、上記公報の技術は、どのアドレス入力端子に問題があるのかを特定するためには有効であるが、実装後の外部端子のコンタクト状態を簡易にチェックするためには不向きである。 Accordingly, the above publication techniques, which address is in order to identify the problem lies in the input terminal are valid, it is not suitable for checking in a simple contact state of the external terminals after mounting . 【0011】さらに、上記公報の技術は、チップ選択用端子を非選択状態から選択状態にすることによって試験回路を起動させており、試験回路を停止させて通常の状態で使用するためには、デバイスを立ち上げる度に、グループ数の回数だけチップ選択用端子にダミー信号を入力して、通常動作モードに移行させる必要があり、汎用的ではない。 Furthermore, the above publication techniques, in order to use and to activate the test circuit by the selected chip select terminal from the non-selected state, to stop the test circuit in the normal state, every time launch devices, many times the number of groups by entering a dummy signal to the chip select terminal, it is necessary to shift to the normal operation mode, it is not universal. 【0012】本発明は、このような従来技術の課題を解決するためになされたものであり、半導体記憶装置をボード等に実装後に、、専用の試験用端子を追加しなくても、通常動作と同じ簡易なタイミングによって、容易に精度良く、外部端子のコンタクト状態を判定することができる半導体記憶装置とその試験方法を提供することを目的とする。 [0012] The present invention has been made to solve the problems of the conventional art, without adding a test terminal of ,, dedicated after mounting the semiconductor memory device in the board or the like, the normal operation the same simple timing as, easily and precisely, and to provide a semiconductor memory device and its testing method capable of determining a contact state of the external terminals. 【0013】 【課題を解決するための手段】上記課題を解決するために、本発明の半導体記憶装置は、外部と接続されて信号が入出力される外部端子と内部の記憶領域との間の信号の入出力を制御すると共に、半導体記憶装置をボードに実装後に、外部端子に特定の信号を入力することによって各端子のコンタクト状態を判定するコントローラと、 [0013] In order to solve the above object, according to an aspect of the semiconductor memory device of the present invention, between the external terminal and the internal storage region signal is connected to the outside are input and output It controls the input and output of signals, after mounting the semiconductor memory device in the board, and the controller determines the contact state of each terminal by inputting a specific signal to the external terminal,
該記憶領域内に該特定の信号の期待値データが記憶されている記憶部とを備え、該コントローラは、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識する認識部と、該認識部にて判定実行コマンドであると認識された場合に、アドレス入力端子から入力された信号と、該記憶部に記憶されている期待値データとを比較して、一致している場合には合格とし、一致しない場合には不合格として判定結果を出力する比較判定結果出力部とを有することを特徴とする。 And a storage unit the expected value data of the specific signal in the storage area are stored, the controller recognizes whether the command signal inputted from the data input-output terminal indicates a decision execution command a recognition unit, if it is recognized as a determination execution command in the recognition unit compares the signal input from the address input terminal with the expected value data stored in the storage unit, consistent If it is in a pass, if they do not match characterized by having a comparison determination result output unit for outputting a determination result as unacceptable. 【0014】上記構成によれば、外部から予め定められた特定の信号を入力して、データ入出力端子に入力されたコマンド信号によって判定を実行するか否かを判断して、判定を実行する場合には、アドレス入力端子から入力された信号(そのデータ値)とコントローラによって記憶部に記憶されている期待値とを比較することによって、ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、従来技術よりも簡単に精度良くチェックすることができる。 With the above arrangement, by entering a specific signal to a predetermined externally, to determine whether or not to execute the decision by the command signal inputted to the data input terminal, to execute the determination in this case, by comparing the expected value stored in the storage unit address input terminal is input from the signal (data value) by the controller, after the semiconductor memory device is mounted on a board or the like, each the contact state of the terminal, more easily than the prior art can be accurately checked. 期待値は、デバイスの出荷テスト等の際にデバイス内部の記憶領域に書き込むことができる。 Expected value may be written to the device inside the storage area at the time of shipping test, and the like of the device. または、デバイスの製造段階から書き込んでおくことも可能である。 Or, it is also possible to be written from the manufacturing stage of the device. この機能は、デバイスを通常使用する際のライトタイミングおよびリードタイミングによって実現することができるので、この機能をシステムボード上のコントローラに搭載することによって、他に試験装置を設けなくても、システムボード単体でコンタクト状態をチェックすることができる。 This feature can realize the write timing and read timing to normally use the device, by mounting this function controller on the system board, without providing a test device to another, the system board it is possible to check the contact state by itself. 【0015】前記記憶部には、さらに、コマンド信号に対する期待値データが記憶されており、前記認識部は、 [0015] The storage section further has stored expected value data to the command signal, the recognition unit,
データ入出力端子から入力されたコマンド信号と、該記憶ブロックに記憶されているコマンド信号に対する期待値データとを比較して、一致している場合には判定実行コマンドであると判断し、一致しない場合には判定実行コマンドではないと判断することができる。 A command signal input from the data input-output terminal is compared with the expected value data for the command signal stored in the storage block, it is determined that if they match is the determination execution command does not match it can be determined not to be the determination execution command if. 【0016】上記構成によれば、外部から予め定められた特定の信号(コマンド信号)をデータ入出力端子に入力して、コマンド信号(そのデータ値)とコントローラによって記憶部に記憶されている期待値とを比較するだけで、判定を実行するか否かを容易に判断することができる。 According to the above configuration, the input specific signal to a predetermined externally (command signal) to the data input-output terminal, expected stored in the storage unit and the controller command signal (data value) simply comparing the values, whether to execute the judgment can be easily determined. 【0017】前記記憶部には、様々なパッケージに対応するために、予め必要な複数の期待値が記憶されているのが好ましい。 [0017] in the storage unit, in order to accommodate different package, preferably a plurality of expected values ​​a prerequisite is stored. 【0018】上記構成によれば、試験が行われるデバイスによって最適な期待値を格納しておくことができるため、様々なパッケージ、端子配置等に対応することができる。 According to the above configuration, it is possible to store the optimum expected value by devices test is performed can correspond to various packages, terminal arrangement and the like. 【0019】本発明の半導体記憶装置の試験方法は、本発明の半導体記憶装置を実装後に、外部と接続されて信号が入出力される外部端子のコンタクト状態を判定する試験方法であって、各外部端子に外部から特定の信号を入力し、前記認識部によって、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識するステップと、判定実行コマンドであると認識された場合に、前記比較判定結果出力部によって、アドレス入力端子から入力された信号と予め記憶部に記憶されている期待値データとを比較判定するステップとを含むことを特徴とする。 The method of testing a semiconductor memory device of the present invention, after mounting the semiconductor memory device of the present invention, there is provided a determining test method the contact state of the external terminal to which a signal is connected to the outside is input, the enter the specific signal from the external to the external terminal, by the recognition unit are recognized and recognizing whether the command signal inputted from the data input-output terminal indicates a determination execution command, as is the determination execution command If the, by the comparison judgment result output unit, characterized in that it comprises a comparison step of determining the expected value data stored in advance in the storage unit and the signal input from the address input terminal. 【0020】上記方法によれば、電源端子に電源を印加して通常にデバイスを立ち上げた後、外部から予め定められた特定の信号を入力する。 According to the above method, after usually launched the device in applying a power to the power supply terminal, and inputs a specific signal to a predetermined externally. データ入出力端子からのコマンド信号が記憶部に記憶されている期待値と比較されて、判定実行コマンドとして認識されると、続いて入力されるアドレス入力端子からの信号と記憶部に記憶されている期待値とが比較されて判定結果が出力される。 Command signal from the data input-output terminal is compared with an expected value stored in the storage unit, when it is recognized as the determination execution command, it is subsequently stored in the signal storage unit from the address input terminal of the input expected value results determined are compared there are outputted.
この判定結果によって、従来技術よりも簡易な方法で、 This determination result, in a simple manner than the prior art,
ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、精度良くチェックすることができる。 After the semiconductor memory device is mounted on a board or the like, the contact state of the terminals can be accurately checked. また、この機能は、デバイスを通常使用する際のライトタイミングおよびリードタイミングによって実現することができるので、この機能をシステムボード上のコントローラに搭載することによって、他に試験装置を設けなくても、システムボード単体でコンタクト状態をチェックすることができる。 This feature also can be realized by the write timing and read timing to normally use the device, by mounting this function controller on the system board, without providing a test device to another, it is possible to check the contact state on the system board alone. 【0021】前記特定の信号には、少なくとも2種類のパターンが含まれ、各外部端子に対して、少なくとも2 [0021] wherein the specific signal, includes at least two kinds of patterns, for each external terminal, at least 2
回、コンタクト状態の判定を行うのが好ましい。 Times, it is preferable to carry out the determination of the contact condition. 【0022】上記方法によれば、2種類以上のパターンの信号によって試験を行うことによって、検出精度をより向上させることができる。 According to the above method, by performing a test by the signal of two or more patterns, it is possible to further improve the detection accuracy. 【0023】 【発明の実施の形態】以下に、本発明の実施の形態について、図面に基づいて説明する。 [0023] DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. 【0024】図1は、本発明の一実施形態である半導体記憶装置の概略構成について説明するためのブロック図である。 FIG. 1 is a block diagram for explaining a schematic configuration of a semiconductor memory device which is an embodiment of the present invention. 図1では、半導体記憶装置の試験方法について説明するために、半導体記憶装置の端子部近傍のみを示しているが、各入出力端子および入力端子は、コントローラ1を介して、図示しないメモリセルに接続されている。 In Figure 1, in order to describe the test method of the semiconductor memory device, it shows only the terminal portion near the semiconductor memory device, the input and output terminals and input terminals, via the controller 1, the memory cell (not shown) It is connected. 各入出力端子および入力端子のコンタクト状態を判定する判定処理を行わない通常動作時には、コントローラ1は、各入出力端子および入力端子と、メモリセルとの間の信号の入出力を制御して、メモリセルへの情報の書き込みおよびメモリセルからの情報の読み出しを制御するようになっている。 During normal operation is not performed determination processing of the contact status of each input and output terminals and input terminals, the controller 1, each input-output terminal and an input terminal, and controls input and output of signals between the memory cell, and it controls the reading of information from the write and memory cell information in the memory cell. 【0025】この半導体記憶装置は、外部と接続されて信号が入力または入出力される端子として、アドレス信号が入力されるアドレス入出力端子A0〜Amと、データ信号が入出力されるデータ入出力端子DQ0〜DQn [0025] The semiconductor memory device as a terminal for signal connected to the external is input or output, and address output terminals A0~Am the address signal is input, the data input and output data signals are input and output terminal DQ0~DQn
と、チップイネーブル信号が入力されるチップ選択用端子CE#と、ライトイネーブル信号が入力されるコマンド制御用端子WE#と、アウトプットイネーブル信号が入力されるデータ出力制御用端子OE#と、リセット動作および超省消費電力モード制御用信号が入力されるリセットパワーダウンピンRP#とを有している。 If, chip and chip select terminal CE # enable signal is input, a command control terminal WE # to the write enable signal is input, a data output control terminal OE # which output enable signal is input, a reset operation and ultra power saving mode control signal and a reset power-down pin RP # input. なお、 It should be noted that,
各端子記号の後ろの#は、その端子に入力される信号がアクティブローの信号であることを示している。 # Behind each terminal symbol, the signal input to the terminal indicates that it is a signal of active low. 【0026】各アドレス入力端子A0〜Amから入力される信号は、それぞれ、入力バッファ2を介してコントローラ1に入力される。 The signal input from the address input terminal A0~Am are respectively input to the controller 1 through the input buffer 2. また、各データ入出力端子DQ In addition, each of the data input-output terminal DQ
0〜DQnから入出力される信号は、それぞれ、入出力バッファ3を介してコントローラ1に入出力される。 Signals input to or output from 0~DQn are respectively input to the controller 1 through the input-output buffer 3. チップイネーブル信号(CE#)、ライトイネーブル信号(WE#)、アウトプットイネーブル信号(OE#)、 Chip enable signal (CE #), write enable signal (WE #), output enable signal (OE #),
リセット動作および超省消費電力モード制御用信号(R Reset operation and ultra power saving mode control signal (R
P#)は、それぞれ、コントローラ1に入力される。 P #), respectively, are input to the controller 1. また、デバイス内部の記憶領域4には、アドレス端子およびデータ端子から入力される各信号の期待値がそれぞれ記憶されており、コントローラ1に供給されるようになっている。 Further, the device inside the storage area 4, so that the expected value of the signal input from the address terminals and data terminals are stored respectively, are supplied to the controller 1. コントローラ1の内部には、データ端子から入力された信号DQ0〜DQnと記憶領域4から供給された信号の期待値とを比較して、コンタクト状態を判定するための判定実行コマンドであるか否かを認識する認識部と、アドレス端子から入力された信号A0〜Amと記憶領域4から供給された信号の期待値とを比較して判定結果を出力する比較判定結果出力部とが設けられている。 Inside the controller 1 compares the expected value of the signal supplied signal DQ0~DQn input from the data terminal and from the storage area 4, whether a determination execution command for determining a contact state provided a recognition unit for recognizing, the comparison determination result output unit for outputting a result determined by comparing the expected value of the signal supplied from the signal A0~Am a storage area 4, which is inputted from the address terminals . 【0027】以下に、図2に示すようなCSP(Chi [0027] Hereinafter, CSP as shown in FIG. 2 (Chi
p Size Package)デバイスを例として、本実施形態の半導体記憶装置の試験方法について説明する。 Examples of p Size Package) device, will be described testing method of the semiconductor memory device of the present embodiment. このデバイスにおいて、各端子は、図2に示すように、マトリックス状に配置されている。 In this device, the terminals, as shown in FIG. 2, are arranged in a matrix. この図2において、5Eに配置されているVccは電源端子であり、1 In FIG. 2, Vcc arranged on 5E is a power supply terminal, 1
Eおよび8Eに配置されているGNDは接地端子である。 GND disposed in E and 8E is a ground terminal. また、A0〜A17はアドレス入力端子であり、D Further, A0 to A17 is an address input terminal, D
Q0からDQ15はデータ入出力端子であり、CE#はチップイネーブル信号入力端子であり、WE#はライトイネーブル信号入力端子であり、OE#はアウトプットイネーブル信号入力端子でありRP#はリセット動作および超省消費電力モード制御用信号入力端子である。 Q0 from DQ15 are data input and output terminals, CE # is a chip enable signal input terminal, WE # is the write enable signal input terminal, OE # is the output enable signal input terminal RP # is reset operation and an ultra power saving mode control signal input terminal. さらに、4Bに配置されているVppは電源端子であり、 Further, Vpp, which is disposed 4B is a power supply terminal,
4A、3B、6B、4C、5C、8Fに配置されているNCはノンコネクト端子である。 4A, 3B, 6B, 4C, 5C, the NC disposed in 8F is a non-connection terminal. 【0028】ここで、アドレス端子およびデータ端子に入力される信号としては、図3および図4に示すように、隣り合う端子(例えば1Aに配置されている端子と2Aに配置されている端子など)に対して、別のレベル(”L”および”H”)の信号を入力した方が効果的である。 [0028] Here, the signal inputted to the address terminals and data terminals, as shown in FIGS. 3 and 4, etc. are disposed in the terminal which is disposed adjacent the terminal (e.g., 1A and 2A terminal ) relative to, those who enter a signal of another level ( "L" and "H") is effective. これによって、その端子の接続状態(コンタクト状態)だけでなく、隣接する端子との短絡も同時に試験することができる。 This not only connection state of the terminals (contact state), short-circuit between adjacent terminals can be tested simultaneously. なお、図4は図3に示す入力信号レベル”H”および”L”を反転させた例を示す。 Incidentally, FIG. 4 shows an example obtained by inverting the input signal level "H" and "L" shown in FIG. 【0029】図3に示す入力信号に対応するアドレス端子、データ端子への入力値は、それぞれ、図6に(1) The address terminals corresponding to the input signal shown in FIG. 3, the input values ​​to the data terminals, respectively, in FIG. 6 (1)
で示すような値になり、図4に示す入力信号に対応したアドレス端子、データ端子への入力値は、それぞれ、図6に(2)で示すような値になる。 The value shown by the address terminals corresponding to the input signal shown in FIG. 4, the input values ​​to the data terminals, respectively, a value as shown in FIG. 6 (2). これらの値は、期待値として使用するために、図1に示すデバイス内部の記憶領域4に予め格納されている。 These values, for use as an expected value, previously stored in the device's internal memory area 4 shown in FIG. この記憶領域4は、メインメモリセルとは別領域に設けられており、構造はメインメモリセルと同じであっても異なっていてもよい。 The storage area 4, the main memory cell is provided in a different region, the structure may be different be the same as the main memory cell. 【0030】デバイスに電源電圧を印加した後で、図5 [0030] After applying the power supply voltage to the device, FIG 5
に示すタイミングチャートにおいて(1)の部分で示すように、ライトイネーブル信号WE#を用いたタイミングによって、図6に(1)で示す値AmおよびDQn As shown in the portion of (1) in the timing chart shown in, the timing with the write enable signal WE #, the value Am and DQn shown in FIG. 6 (1)
が、アドレス端子およびデータ端子からそれぞれ入力される。 There are input from the address terminals and data terminals. 【0031】このとき、データ端子から入力された値が正しく図1に示す入出力バッファ3に格納され、コントローラ1内部の認識部において記憶領域4からの期待値と比較され、判定実行コマンドであるか否かが判断される。 [0031] At this time, input from the data terminal value is stored in the output buffer 3 correctly shown in FIG. 1, is compared with the expected values ​​from the memory area 4 the controller 1 interior recognition unit is the determination execution command it is determined whether or not the. そして、判定実行コマンドとして認識されると、アドレス端子から入力された値が格納されている入力バッファ2の値と記憶領域4からの期待値とがコントローラ1内部の認識部において比較される。 When it is recognized as the determination execution command, the value of the input buffer 2 value input from the address terminal is stored and the expected value from the storage area 4 are compared in the controller 1 interior recognition unit. この比較結果が一致すれば、コントローラ1の比較判定結果出力部から、 If the comparison result is a match, the comparison determination result output unit of the controller 1,
予め決められた合格を示す値(例えば0×80)が、一致しなければ不合格を示す値(例えば0×80以外の値)が出力され、入出力バッファ3を介してデータ入出力端子から判定結果として出力される。 Predetermined value indicating a pass (e.g. 0 × 80) is matched unless value indicating the failure (e.g., 0 × 80 except value) is outputted from the data input-output terminal via the output buffer 3 It is output as the determination result. 【0032】出力された判定結果は、図5に示すタイミングチャートにおいて(2)の部分で示すように、OE [0032] the determination result output, as shown in the portion of (2) in the timing chart shown in FIG. 5, OE
#端子に”L”の信号を印加することによって、データ端子から出力される判定結果がリードされて確認される。 # By applying a signal of "L" to the terminal, the determination result output from the data terminal is confirmed is read. 【0033】続いて、コンタクト状態が不良である端子でも、入力信号が偶然に一致して判定結果が不正確になることを避けるために、図6に示す(1)とは”H” [0033] Then, in the terminal contact condition is poor, in order to avoid that the result determined input signal is coincidentally becomes inaccurate, shown in FIG. 6 (1) is "H"
と”L”の論理を逆にした図6に(2)で示す値を使用して、同様の方法によって再度、コンタクト状態を判定する。 When using the values ​​indicated by the logic in FIG. 6 in which the reversed (2) of the "L", again by the same method, determining a contact state. 【0034】ここで、例えばデータ入出力端子にコンタクト不良がある場合には、データ入出力端子から入力された値が判定実行コマンドとして認識されないため、アドレス入力端子から入力された値と期待値との比較自体が行われず、出力結果が合格を示す値ではないことから、コンタクト不良があると判定することができる。 [0034] Here, when there is a contact failure in the example data input-output terminal, since the input from the data input-output terminal value is not recognized as the determination execution command, and the value input from the address input terminal with the expected value comparison itself is not performed, the output result from not a value indicating a pass, it can be determined that there is a contact failure. また、アドレス入力端子にコンタクト不良がある場合には、アドレス入力端子から入力された値と期待値との比較は行なわれるが、入力バッファ2に格納される値は期待値とは異なる値になり、不合格の判定結果が出力されることから、コンタクト不良があると判定することができる。 When there is a contact failure to the address input terminal, although the comparison with the expected value and the value input from the address input terminal is performed, the values ​​stored in the input buffer 2 becomes a value different from the expected value may be determined from the failure of the determination result is output, the contact with the poor there. さらに、ライトイネーブル信号入力端子WE#にコンタクト不良がある場合には、デバイスに対してデータ入出力端子からの入力が行なわれず、入出力バッファ3に値が格納されないため、判定実行コマンドとして認識されず、比較は行なわれないことから、コンタクト不良があると判定することができる。 Further, when there is a contact failure in the write enable signal input terminal WE # is is not performed input from the data input-output terminal to the device, since the values ​​in the output buffer 3 is not stored, it is recognized as the determination execution command not, the comparison since not performed, it can be determined that there is a contact failure. また、アウトプットイネーブル信号入力端子OE#にコンタクト不良がある場合には、比較判定結果が出力されないことから、コンタクト不良があると判定することができる。 When there is a contact failure in the output enable signal input terminal OE #, since the comparison determination result is not output, it can be determined that there is a contact failure. また、リセット動作および超消費電力モード制御信号入力端子RP Further, the reset operation and the ultra-power consumption mode control signal input terminal RP
#にコンタクト不良がある場合には、デバイスがリセットされないことから、コンタクト不良があると判定することができる。 If there is a contact failure in the #, since the device is not reset, it can be determined that there is a contact failure. さらに、チップイネーブル信号入力端子CE#にコンタクト不がある場合には、デバイスが動作しないことから、コンタクト不良があると判定することができる。 Further, when the chip enable signal input terminal CE # is not the contact, since the device does not work, it can be determined that there is a contact failure. 【0035】以上のように、本実施形態によれば、従来よりも簡単な方法で効率よく、外部端子のコンタクト状態をチェックすることができる。 [0035] As described above, according to this embodiment, than conventional in a simple way can be efficiently check the contact state of the external terminals. 【0036】 【発明の効果】以上詳述したように、本発明によれば、 [0036] As has been described above in detail, according to the present invention,
外部から予め定められた特定の信号を入力し、内部のコントローラによって記憶部に記憶されている期待値と比較することによって、ボード等に半導体記憶装置が実装された後で、各外部端子のコンタクト状態を、従来技術よりも簡単に精度良くチェックすることができる。 Enter a specific signal to a predetermined externally by comparing the expected value stored in the storage unit by an internal controller, after the semiconductor memory device is mounted on a board or the like, the contact of the external terminals state, than the prior art can be checked easily and accurately. また、半導体記憶装置が実装されるシステムボードのコントローラに、信号の入力と比較結果の判定機能とを持たせることによって、試験用装置を別に設けなくても、システムボード単体で外部端子のコンタクト状態をチェックすることができる。 Furthermore, the controller of the system board to the semiconductor memory device is mounted, by having the comparison result determination function and the input signal, without providing separately a test device, the contact state of the external terminals on the system board alone it is possible to check. 【0037】また、本発明によれば、外部からコマンド信号として入力された値を内部のコントローラによって記憶部に記憶されている期待値とを比較するだけで、従来よりも簡単な方法によって、各外部端子のコンタクト状態をチェックすることができる。 Further, according to the present invention, by simply comparing the expected value stored values ​​entered as a command signal from the outside by the inside of the controller in the storage unit, by a simple method than the prior art, the it is possible to check the contact state of the external terminals. 【0038】また、本発明によれば、試験が行われるデバイスによって最適な期待値を格納しておくことができるため、様々なパッケージ、端子配置等に対応することができる。 Further, according to the present invention, it is possible to store the optimum expected value by devices test is performed can correspond to various packages, terminal arrangement and the like. 【0039】また、本発明によれば、従来技術よりも簡易な方法で、ボード等に半導体記憶装置が実装された後で、各端子のコンタクト状態を、精度良くチェックすることができる。 Further, according to the present invention, over the prior art in a simple manner, after the semiconductor memory device is mounted on a board or the like, the contact state of the terminals can be accurately checked. 【0040】さらに、本発明によれば、2種類以上のパターンの信号によって試験を行うことによって、検出精度をより向上させることができる。 [0040] Further, according to the present invention, by performing a test by the signal of two or more patterns, it is possible to further improve the detection accuracy.

【図面の簡単な説明】 【図1】本発明の一実施形態である半導体記憶装置の概略構成を説明するためのブロック図である。 It is a block diagram for explaining a schematic structure of a semiconductor memory device according to an embodiment of the BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] present invention. 【図2】本発明の一実施形態である半導体記憶装置において、CSPパッケージを例とした端子配置例を示す図である。 In the semiconductor memory device according to an embodiment of the present invention; FIG diagrams showing a terminal arrangement example of the example CSP package. 【図3】本発明の一実施形態である半導体記憶装置における、入力信号の一例を示す図である。 In a semiconductor memory device according to an embodiment of the present invention; FIG is a diagram showing an example of an input signal. 【図4】本発明の一実施形態である半導体記憶装置における、入力信号の他の例を示す図である。 In a semiconductor memory device according to an embodiment of the present invention; FIG is a diagram showing another example of the input signal. 【図5】本発明の一実施形態である半導体記憶装置の試験方法を説明するためのタイミングチャートである。 5 is a timing chart for explaining a testing method of the semiconductor memory device according to an embodiment of the present invention. 【図6】本発明の一実施形態である半導体記憶装置の試験方法における、入力信号の期待値の例である。 In the test method for a semiconductor memory device which is one embodiment of the invention; FIG is an example of an expected input signal. 【符号の説明】 1 デバイス内部のコントローラ2 アドレス入力バッファ3 データ入出力バッファ4 デバイス内部の期待値記憶領域 [EXPLANATION OF SYMBOLS] 1 inside the device controller 2 address input buffer 3 data output buffer 4 inside the device the expected value storage area

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 外部と接続されて信号が入出力される外部端子と内部の記憶領域との間の信号の入出力を制御すると共に、半導体記憶装置をボードに実装後に、外部端子に特定の信号を入力することによって各端子のコンタクト状態を判定するコントローラと、 該記憶領域内に該特定の信号の期待値データが記憶されている記憶部とを備え、 該コントローラは、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識する認識部と、 該認識部にて判定実行コマンドであると認識された場合に、アドレス入力端子から入力された信号と、該記憶部に記憶されている期待値データとを比較して、一致している場合には合格とし、一致しない場合には不合格として判定結果を出力する比較判定結 With Patent Claims 1] it is connected to the outside signal to control the input and output of signals between the external terminal and the internal storage area is input and output, after mounting the semiconductor memory device in the board , comprising a controller determining a contact state of each terminal by inputting a specific signal to the external terminal, and a storage unit the expected value data of the specific signal in the storage area are stored, the controller , when the command signal inputted from the data input-output terminal is recognized and the recognition unit for recognizing whether shows the determination execution command, that the determination execution command in the recognition unit, is inputted from the address input terminal and signal is compared with the expected value data stored in the storage unit, and pass if they match, the comparison determination binding if they do not match for outputting a determination result as unacceptable 出力部とを有することを特徴とする半導体記憶装置。 The semiconductor memory device according to an outputting section. 【請求項2】 前記記憶部には、さらに、コマンド信号に対する期待値データが記憶されており、 前記認識部は、データ入出力端子から入力されたコマンド信号と、該記憶ブロックに記憶されているコマンド信号に対する期待値データとを比較して、一致している場合には判定実行コマンドであると判断し、一致しない場合には判定実行コマンドではないと判断することを特徴とする請求項1に記載の半導体記憶装置。 To wherein said storage section further has stored expected value data to the command signal, the recognition unit, and a command signal input from the data input-output terminal and is stored in the storage block by comparing the expected value data to the command signal, it is determined that if they match is the determination execution command, it is determined that not the determination execution command when no match to claim 1, wherein the semiconductor memory device according. 【請求項3】 前記記憶部には、様々なパッケージに対応するために、予め必要な複数の期待値が記憶されていることを特徴とする請求項1または請求項2に記載の半導体記憶装置。 The method according to claim 3, wherein the storage unit, in order to accommodate different package, a semiconductor memory device according to claim 1 or claim 2 the plurality of expected values ​​a prerequisite is characterized in that it is stored . 【請求項4】 請求項1乃至請求項3のいずれかに記載の半導体記憶装置を実装後に、外部と接続されて信号が入出力される外部端子のコンタクト状態を判定する試験方法であって、 各外部端子に外部から特定の信号を入力し、前記認識部によって、データ入出力端子から入力されたコマンド信号が判定実行コマンドを示すか否かを認識するステップと、 判定実行コマンドであると認識された場合に、前記比較判定結果出力部によって、アドレス入力端子から入力された信号と予め記憶部に記憶されている期待値データとを比較判定するステップとを含むことを特徴とする半導体記憶装置の試験方法。 4. After mounting the semiconductor memory device according to any one of claims 1 to 3, a determining test method the contact state of the external terminal to which a signal is connected to the outside are input and output, enter the specific signal from the outside to the external terminal, by the recognition unit, and recognizing whether the command signal inputted from the data input-output terminal indicates a determination execution command, that the decision execution command recognition If it is, the comparison determination by the result output unit, a semiconductor memory device which comprises a comparison step of determining the expected value data stored in advance in the storage unit and the signal inputted from the address input terminal test methods. 【請求項5】 前記特定の信号には、少なくとも2種類のパターンが含まれ、各外部端子に対して、少なくとも2回、コンタクト状態の判定を行うことを特徴とする請求項4に記載の半導体記憶装置の試験方法。 The method according to claim 5 wherein said specific signal, includes at least two kinds of patterns, for each external terminal, at least two semiconductor according to claim 4, characterized in that for determining the contact state the method of testing a storage device.
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