JP2003086000A - Semiconductor memory and its test method - Google Patents

Semiconductor memory and its test method

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Publication number
JP2003086000A
JP2003086000A JP2001274247A JP2001274247A JP2003086000A JP 2003086000 A JP2003086000 A JP 2003086000A JP 2001274247 A JP2001274247 A JP 2001274247A JP 2001274247 A JP2001274247 A JP 2001274247A JP 2003086000 A JP2003086000 A JP 2003086000A
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JP
Japan
Prior art keywords
input
terminal
signal
command
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001274247A
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Japanese (ja)
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JP3925839B2 (en
Inventor
Shinji Ishikawa
真治 石川
Original Assignee
Sharp Corp
シャープ株式会社
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Priority to JP2001274247A priority Critical patent/JP3925839B2/en
Publication of JP2003086000A publication Critical patent/JP2003086000A/en
Application granted granted Critical
Publication of JP3925839B2 publication Critical patent/JP3925839B2/en
Expired - Fee Related legal-status Critical Current
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can easily and accurately discriminate a contact state of an external terminal by same simple timing as that in normal operation without adding an exclusive terminal for test after mounting a semiconductor chip on a board. SOLUTION: This memory is provided with a controller 1 inputting a specific signal to an external terminal and discriminating a contact state of each terminal and a storage section 4 of expected value data, the controller 1 has a recognizing section recognizing whether command data inputted from data input/ output terminals DQ0-DGn are a discrimination executing command or not, and a comparison discrimination result outputting section comparing data inputted from address input terminals A0-Am with expected value data stored in the storage section 4 when the command data is recognized as a discrimination executing command, when they are coincident, a discrimination result is outputted as acceptance, and when they are not coincident, a discrimination result is outputted as non-acceptance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ボード等に実装さ
れた後に、外部端子のコンタクト状態を容易にチェック
することができる半導体記憶装置およびその試験方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of easily checking the contact state of an external terminal after being mounted on a board or the like, and a test method for the same.

【0002】[0002]

【従来の技術】半導体記憶装置(半導体チップ)をパッ
ケージに搭載してボード等に実装した後に、その半導体
記憶装置において外部と接続されて信号が入出力される
各端子(外部端子)のコンタクト状態をチェックするた
めには、以下のような方法が挙げられる。
2. Description of the Related Art After a semiconductor memory device (semiconductor chip) is mounted on a package and mounted on a board or the like, the contact state of each terminal (external terminal) connected to the outside and inputting / outputting signals in the semiconductor memory device. The following methods can be used to check.

【0003】最も原始的な方法は、各外部端子の半田付
け状態を目視で確認する方法である。また、半導体記憶
装置をボード等に実装した後に、実際にデバイスを動作
させることによっても確認することができる。さらに、
ゲートアレイ等のロジックデバイスにおいては、JTA
Gで規定されているバウンダリスキャン(bounda
ry scan)等を行なうための試験回路を別途搭載
して判断する方法もある。
The most primitive method is to visually check the soldering state of each external terminal. It can also be confirmed by actually operating the device after mounting the semiconductor memory device on a board or the like. further,
For logic devices such as gate arrays, JTA
Boundary scan (boundary scan) specified in G
There is also a method of making a judgment by separately mounting a test circuit for performing a ry scan) or the like.

【0004】また、特開2000−206197号公報
には、DRAM等のメモリデバイスをボードに実装した
状態で、上記方法に比べて簡易に外部端子のコンタクト
チェックを行なうための試験回路および試験方法が提案
されている。この従来技術は、専用の試験用端子を設け
ることなく、デバイスに通常使用される電圧範囲内で、
簡単なタイミング設定によって試験を行なうことを目的
としている。試験を行う際には、デバイスに電源電圧を
印加した後に、外部端子に特定の信号を入力することに
よって、試験回路を起動させる。実際にはチップ選択用
端子を非選択状態から選択状態にすることによって試験
回路を起動させることができる。さらに、外部端子を用
途によって複数にグループ分けして、それぞれのグルー
プに対して、試験を順次行う。
Further, Japanese Unexamined Patent Publication No. 2000-206197 discloses a test circuit and a test method for making a contact check of an external terminal more easily than the above method with a memory device such as a DRAM mounted on a board. Proposed. This conventional technology, without providing a dedicated test terminal, within the voltage range normally used for devices,
The purpose is to conduct a test with a simple timing setting. When performing a test, a test circuit is activated by applying a power supply voltage to the device and then inputting a specific signal to an external terminal. In practice, the test circuit can be activated by changing the chip selection terminal from the non-selected state to the selected state. Further, the external terminals are divided into a plurality of groups according to the use, and the test is sequentially performed for each group.

【0005】[0005]

【発明が解決しようとする課題】近年、電子機器の小型
化・薄型化が進み、半導体装置のパッケージについて
も、より実装面積の少ないCSP(Chip Size
Package)、BGA(Ba11 Grid Arr
ay)等が主流になってきている。これらのパッケージ
では、パッケージの底面に外部端子がマトリクス状態に
配置されており、ボード等に実装後に各端子の半田付け
状態を目視で確認することは実質的に不可能である。
In recent years, electronic devices have been made smaller and thinner, and CSP (Chip Size) of a semiconductor device package has a smaller mounting area.
Package), BGA (Ba11 Grid Arr)
ay) etc. are becoming mainstream. In these packages, the external terminals are arranged in a matrix on the bottom surface of the package, and it is virtually impossible to visually confirm the soldering state of each terminal after mounting on a board or the like.

【0006】また、デバイスを実際に動作させることに
よって外部端子のコンタクト状態を判定する場合には、
簡易な動作だけで全ての端子のコンタクト状態をチェッ
クすることは非常に困難である。この方法によって検出
精度を向上させるためには、多数のパターンで半導体記
憶装置に動作を行なわせる必要がある。このため、全て
の外部端子のコンタクト状態を確実に検出できる試験を
行うためには、デバイスの外部に試験装置を設けて必要
な数のパターンで動作を実行させる必要があり、試験の
ためのコストが高くなる。
When the contact state of the external terminal is determined by actually operating the device,
It is very difficult to check the contact state of all terminals with only a simple operation. In order to improve the detection accuracy by this method, it is necessary to operate the semiconductor memory device with a large number of patterns. For this reason, in order to perform a test that can reliably detect the contact state of all external terminals, it is necessary to install a test device outside the device and execute the operation in the required number of patterns. Becomes higher.

【0007】また、バウンダリスキャン等を行なうため
には、一般に、専用の試験回路を起動させるための端子
を別途設ける必要があり、また、試験回路を追加するこ
とによって回路規模が大きく、複雑になる。従って、小
型化、低コスト化が要求される一般的な半導体記憶装置
には、バウンダリスキャンを行う方法は適していない。
さらに、半導体記憶装置が実装されるボード自体も集積
化が進んできているため、外部試験回路を半導体記憶装
置に接続して試験を行なうことも困難になってきてい
る。
Further, in order to perform boundary scan or the like, it is generally necessary to separately provide a terminal for activating a dedicated test circuit, and the addition of the test circuit makes the circuit scale large and complicated. . Therefore, the method of performing the boundary scan is not suitable for a general semiconductor memory device that requires downsizing and cost reduction.
Further, since the board itself on which the semiconductor memory device is mounted is also highly integrated, it is becoming difficult to perform a test by connecting an external test circuit to the semiconductor memory device.

【0008】これらの問題を解決するために、上記特開
2000−206197号公報では、各端子を複数のグ
ループ、例えばDRAMの場合にはチップ選択端子、ア
ドレス入力端子、データ入出力端子の3つに分けて試験
を行っている。しかしながら、この公報に開示されてい
る方法では、グループ数の回数だけ試験を行う必要があ
り、また、グループ中の端子毎に入力信号を変化させて
試験を行うため、全端子のコンタクト状態をチェックす
るためには、端子数だけ試験を行う必要がある。
In order to solve these problems, in the above-mentioned Japanese Patent Laid-Open No. 2000-206197, each terminal is divided into a plurality of groups, for example, in the case of a DRAM, there are three terminals: a chip selection terminal, an address input terminal, and a data input / output terminal. The test is divided into However, in the method disclosed in this publication, it is necessary to perform the test as many times as the number of groups, and since the test is performed by changing the input signal for each terminal in the group, the contact status of all terminals is checked. In order to do so, it is necessary to test the number of terminals.

【0009】さらに、DRAM等の比較的端子数が少な
いデバイスの場合には問題は少ないが、例えばNOR型
フラッシュメモリ等のようにランダムアクセスが行われ
る、端子数が多いデバイスに上記公報の技術を適用する
ためには、容易に端子のコンタクト状態をチェックする
ことができない。例えば、アドレス入力端子等のテスト
を行う場合、上記公報の図4に示すように、複数の入力
パターンを用いてテストを行うため、端子数が増えると
入力パターンも増えるからである。さらに、このような
デバイスは大容量化が進んでいるため、端子数は増加す
る一方である。
Further, although there are few problems in the case of a device having a relatively small number of terminals such as a DRAM, the technique of the above publication is applied to a device having a large number of terminals such as a NOR flash memory which is randomly accessed. In order to apply, it is not possible to easily check the contact state of the terminals. This is because, for example, when a test of an address input terminal or the like is performed by using a plurality of input patterns as shown in FIG. 4 of the above publication, the input pattern increases as the number of terminals increases. Furthermore, since the capacity of such a device is increasing, the number of terminals is increasing.

【0010】従って、上記公報の技術は、どのアドレス
入力端子に問題があるのかを特定するためには有効であ
るが、実装後の外部端子のコンタクト状態を簡易にチェ
ックするためには不向きである。
Therefore, the technique of the above publication is effective for identifying which address input terminal has a problem, but is not suitable for simply checking the contact state of the external terminal after mounting. .

【0011】さらに、上記公報の技術は、チップ選択用
端子を非選択状態から選択状態にすることによって試験
回路を起動させており、試験回路を停止させて通常の状
態で使用するためには、デバイスを立ち上げる度に、グ
ループ数の回数だけチップ選択用端子にダミー信号を入
力して、通常動作モードに移行させる必要があり、汎用
的ではない。
Further, in the technique disclosed in the above publication, the test circuit is started by changing the chip selection terminal from the non-selected state to the selected state. To stop the test circuit and use it in the normal state, Each time the device is started up, it is necessary to input a dummy signal to the chip selection terminal as many times as the number of groups to shift to the normal operation mode, which is not general purpose.

【0012】本発明は、このような従来技術の課題を解
決するためになされたものであり、半導体記憶装置をボ
ード等に実装後に、、専用の試験用端子を追加しなくて
も、通常動作と同じ簡易なタイミングによって、容易に
精度良く、外部端子のコンタクト状態を判定することが
できる半導体記憶装置とその試験方法を提供することを
目的とする。
The present invention has been made in order to solve the problems of the prior art as described above, and after the semiconductor memory device is mounted on a board or the like, normal operation is possible without adding a dedicated test terminal. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of easily and accurately determining the contact state of an external terminal with the same simple timing as in (1) and its testing method.

【0013】[0013]

【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体記憶装置は、外部と接続されて信号
が入出力される外部端子と内部の記憶領域との間の信号
の入出力を制御すると共に、半導体記憶装置をボードに
実装後に、外部端子に特定の信号を入力することによっ
て各端子のコンタクト状態を判定するコントローラと、
該記憶領域内に該特定の信号の期待値データが記憶され
ている記憶部とを備え、該コントローラは、データ入出
力端子から入力されたコマンド信号が判定実行コマンド
を示すか否かを認識する認識部と、該認識部にて判定実
行コマンドであると認識された場合に、アドレス入力端
子から入力された信号と、該記憶部に記憶されている期
待値データとを比較して、一致している場合には合格と
し、一致しない場合には不合格として判定結果を出力す
る比較判定結果出力部とを有することを特徴とする。
In order to solve the above-mentioned problems, a semiconductor memory device of the present invention has a signal input between an external terminal connected to the outside for inputting / outputting a signal and an internal storage area. A controller that controls the output and determines the contact state of each terminal by inputting a specific signal to the external terminal after mounting the semiconductor memory device on the board,
A storage unit in which expected value data of the specific signal is stored in the storage area, and the controller recognizes whether the command signal input from the data input / output terminal indicates a determination execution command. When the recognizing unit and the recognizing unit recognize that the command is a determination execution command, the signal input from the address input terminal is compared with the expected value data stored in the storage unit, and they match. It is characterized by having a comparison determination result output unit that outputs a determination result as a pass if it does not match and a fail if it does not match.

【0014】上記構成によれば、外部から予め定められ
た特定の信号を入力して、データ入出力端子に入力され
たコマンド信号によって判定を実行するか否かを判断し
て、判定を実行する場合には、アドレス入力端子から入
力された信号(そのデータ値)とコントローラによって
記憶部に記憶されている期待値とを比較することによっ
て、ボード等に半導体記憶装置が実装された後で、各端
子のコンタクト状態を、従来技術よりも簡単に精度良く
チェックすることができる。期待値は、デバイスの出荷
テスト等の際にデバイス内部の記憶領域に書き込むこと
ができる。または、デバイスの製造段階から書き込んで
おくことも可能である。この機能は、デバイスを通常使
用する際のライトタイミングおよびリードタイミングに
よって実現することができるので、この機能をシステム
ボード上のコントローラに搭載することによって、他に
試験装置を設けなくても、システムボード単体でコンタ
クト状態をチェックすることができる。
According to the above configuration, a predetermined specific signal is input from the outside, the command signal input to the data input / output terminal is used to determine whether or not to execute the determination, and the determination is executed. In this case, by comparing the signal (the data value thereof) input from the address input terminal with the expected value stored in the storage unit by the controller, the semiconductor storage device is mounted on the board or the like, The contact state of the terminal can be checked more easily and more accurately than in the prior art. The expected value can be written in a storage area inside the device at the time of a device shipping test or the like. Alternatively, it is possible to write the data from the manufacturing stage of the device. This function can be realized by the write timing and read timing when the device is normally used. Therefore, by mounting this function in the controller on the system board, the system board can be installed without any additional test equipment. You can check the contact status by itself.

【0015】前記記憶部には、さらに、コマンド信号に
対する期待値データが記憶されており、前記認識部は、
データ入出力端子から入力されたコマンド信号と、該記
憶ブロックに記憶されているコマンド信号に対する期待
値データとを比較して、一致している場合には判定実行
コマンドであると判断し、一致しない場合には判定実行
コマンドではないと判断することができる。
Expected value data for the command signal is further stored in the storage section, and the recognition section is
The command signal input from the data input / output terminal is compared with the expected value data for the command signal stored in the storage block. If they match, it is determined that the command is a determination execution command, and they do not match. In this case, it can be determined that it is not the determination execution command.

【0016】上記構成によれば、外部から予め定められ
た特定の信号(コマンド信号)をデータ入出力端子に入
力して、コマンド信号(そのデータ値)とコントローラ
によって記憶部に記憶されている期待値とを比較するだ
けで、判定を実行するか否かを容易に判断することがで
きる。
According to the above configuration, a predetermined specific signal (command signal) is externally input to the data input / output terminal, and the command signal (data value thereof) and the expectation stored in the storage unit by the controller. Whether or not to execute the determination can be easily determined only by comparing the value with the value.

【0017】前記記憶部には、様々なパッケージに対応
するために、予め必要な複数の期待値が記憶されている
のが好ましい。
It is preferable that a plurality of expected values necessary in advance for storing various packages are stored in the storage section.

【0018】上記構成によれば、試験が行われるデバイ
スによって最適な期待値を格納しておくことができるた
め、様々なパッケージ、端子配置等に対応することがで
きる。
According to the above configuration, the optimum expected value can be stored depending on the device to be tested, so that various packages, terminal arrangements, etc. can be dealt with.

【0019】本発明の半導体記憶装置の試験方法は、本
発明の半導体記憶装置を実装後に、外部と接続されて信
号が入出力される外部端子のコンタクト状態を判定する
試験方法であって、各外部端子に外部から特定の信号を
入力し、前記認識部によって、データ入出力端子から入
力されたコマンド信号が判定実行コマンドを示すか否か
を認識するステップと、判定実行コマンドであると認識
された場合に、前記比較判定結果出力部によって、アド
レス入力端子から入力された信号と予め記憶部に記憶さ
れている期待値データとを比較判定するステップとを含
むことを特徴とする。
The semiconductor memory device testing method of the present invention is a test method for determining a contact state of an external terminal connected to the outside and receiving and outputting a signal after mounting the semiconductor memory device of the present invention. A step of inputting a specific signal from the outside to the external terminal and recognizing whether or not the command signal input from the data input / output terminal indicates a judgment execution command by the recognition unit; In this case, the step of comparing and determining the signal input from the address input terminal and the expected value data stored in advance in the storage unit by the comparison and determination result output unit is included.

【0020】上記方法によれば、電源端子に電源を印加
して通常にデバイスを立ち上げた後、外部から予め定め
られた特定の信号を入力する。データ入出力端子からの
コマンド信号が記憶部に記憶されている期待値と比較さ
れて、判定実行コマンドとして認識されると、続いて入
力されるアドレス入力端子からの信号と記憶部に記憶さ
れている期待値とが比較されて判定結果が出力される。
この判定結果によって、従来技術よりも簡易な方法で、
ボード等に半導体記憶装置が実装された後で、各端子の
コンタクト状態を、精度良くチェックすることができ
る。また、この機能は、デバイスを通常使用する際のラ
イトタイミングおよびリードタイミングによって実現す
ることができるので、この機能をシステムボード上のコ
ントローラに搭載することによって、他に試験装置を設
けなくても、システムボード単体でコンタクト状態をチ
ェックすることができる。
According to the above method, power is applied to the power supply terminal to normally start up the device, and then a predetermined specific signal is input from the outside. When the command signal from the data input / output terminal is compared with the expected value stored in the storage unit and recognized as a judgment execution command, the signal from the address input terminal that is input subsequently is stored in the storage unit. The expected result is compared and the judgment result is output.
Based on this determination result, in a simpler method than the conventional technology,
After the semiconductor memory device is mounted on the board or the like, the contact state of each terminal can be accurately checked. In addition, this function can be realized by the write timing and read timing when the device is normally used. Therefore, by mounting this function in the controller on the system board, it is possible to provide other test equipment. The contact status can be checked on the system board alone.

【0021】前記特定の信号には、少なくとも2種類の
パターンが含まれ、各外部端子に対して、少なくとも2
回、コンタクト状態の判定を行うのが好ましい。
The specific signal includes at least two types of patterns, and at least two patterns are provided for each external terminal.
It is preferable to judge the contact state once.

【0022】上記方法によれば、2種類以上のパターン
の信号によって試験を行うことによって、検出精度をよ
り向上させることができる。
According to the above method, the detection accuracy can be further improved by performing the test with the signals of two or more types of patterns.

【0023】[0023]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面に基づいて説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【0024】図1は、本発明の一実施形態である半導体
記憶装置の概略構成について説明するためのブロック図
である。図1では、半導体記憶装置の試験方法について
説明するために、半導体記憶装置の端子部近傍のみを示
しているが、各入出力端子および入力端子は、コントロ
ーラ1を介して、図示しないメモリセルに接続されてい
る。各入出力端子および入力端子のコンタクト状態を判
定する判定処理を行わない通常動作時には、コントロー
ラ1は、各入出力端子および入力端子と、メモリセルと
の間の信号の入出力を制御して、メモリセルへの情報の
書き込みおよびメモリセルからの情報の読み出しを制御
するようになっている。
FIG. 1 is a block diagram for explaining a schematic structure of a semiconductor memory device according to an embodiment of the present invention. Although only the vicinity of the terminal portion of the semiconductor memory device is shown in FIG. 1 in order to explain the method of testing the semiconductor memory device, each input / output terminal and input terminal are connected to a memory cell (not shown) via the controller 1. It is connected. During normal operation in which the determination process for determining the contact state of each input / output terminal and input terminal is not performed, the controller 1 controls the input / output of signals between each input / output terminal and input terminal and the memory cell, Writing of information to the memory cell and reading of information from the memory cell are controlled.

【0025】この半導体記憶装置は、外部と接続されて
信号が入力または入出力される端子として、アドレス信
号が入力されるアドレス入出力端子A0〜Amと、デー
タ信号が入出力されるデータ入出力端子DQ0〜DQn
と、チップイネーブル信号が入力されるチップ選択用端
子CE#と、ライトイネーブル信号が入力されるコマン
ド制御用端子WE#と、アウトプットイネーブル信号が
入力されるデータ出力制御用端子OE#と、リセット動
作および超省消費電力モード制御用信号が入力されるリ
セットパワーダウンピンRP#とを有している。なお、
各端子記号の後ろの#は、その端子に入力される信号が
アクティブローの信号であることを示している。
This semiconductor memory device has address input / output terminals A0-Am to which an address signal is input and data input / output to / from which a data signal is input / output, as terminals which are connected to the outside and input or output a signal. Terminals DQ0 to DQn
A chip select terminal CE # to which a chip enable signal is input, a command control terminal WE # to which a write enable signal is input, a data output control terminal OE # to which an output enable signal is input, and a reset It has a reset power down pin RP # to which a signal for operation and super power saving mode control is input. In addition,
The # after each terminal symbol indicates that the signal input to that terminal is an active low signal.

【0026】各アドレス入力端子A0〜Amから入力さ
れる信号は、それぞれ、入力バッファ2を介してコント
ローラ1に入力される。また、各データ入出力端子DQ
0〜DQnから入出力される信号は、それぞれ、入出力
バッファ3を介してコントローラ1に入出力される。チ
ップイネーブル信号(CE#)、ライトイネーブル信号
(WE#)、アウトプットイネーブル信号(OE#)、
リセット動作および超省消費電力モード制御用信号(R
P#)は、それぞれ、コントローラ1に入力される。ま
た、デバイス内部の記憶領域4には、アドレス端子およ
びデータ端子から入力される各信号の期待値がそれぞれ
記憶されており、コントローラ1に供給されるようにな
っている。コントローラ1の内部には、データ端子から
入力された信号DQ0〜DQnと記憶領域4から供給さ
れた信号の期待値とを比較して、コンタクト状態を判定
するための判定実行コマンドであるか否かを認識する認
識部と、アドレス端子から入力された信号A0〜Amと
記憶領域4から供給された信号の期待値とを比較して判
定結果を出力する比較判定結果出力部とが設けられてい
る。
Signals input from the address input terminals A0 to Am are input to the controller 1 via the input buffer 2. In addition, each data input / output terminal DQ
Signals input / output from 0 to DQn are input / output to / from the controller 1 via the input / output buffer 3, respectively. Chip enable signal (CE #), write enable signal (WE #), output enable signal (OE #),
Signal for reset operation and super power saving mode control (R
P #) is input to the controller 1, respectively. Further, the expected value of each signal input from the address terminal and the data terminal is stored in the storage area 4 inside the device, and is supplied to the controller 1. Whether or not it is a judgment execution command for judging the contact state by comparing the signals DQ0 to DQn input from the data terminals with the expected value of the signal supplied from the storage area 4 inside the controller 1 And a comparison determination result output unit that compares the signals A0 to Am input from the address terminals with the expected value of the signal supplied from the storage area 4 and outputs a determination result. .

【0027】以下に、図2に示すようなCSP(Chi
p Size Package)デバイスを例として、本
実施形態の半導体記憶装置の試験方法について説明す
る。このデバイスにおいて、各端子は、図2に示すよう
に、マトリックス状に配置されている。この図2におい
て、5Eに配置されているVccは電源端子であり、1
Eおよび8Eに配置されているGNDは接地端子であ
る。また、A0〜A17はアドレス入力端子であり、D
Q0からDQ15はデータ入出力端子であり、CE#は
チップイネーブル信号入力端子であり、WE#はライト
イネーブル信号入力端子であり、OE#はアウトプット
イネーブル信号入力端子でありRP#はリセット動作お
よび超省消費電力モード制御用信号入力端子である。さ
らに、4Bに配置されているVppは電源端子であり、
4A、3B、6B、4C、5C、8Fに配置されている
NCはノンコネクト端子である。
Below, the CSP (Chi as shown in FIG.
A method of testing the semiconductor memory device according to the present embodiment will be described by taking a p Size Package device as an example. In this device, the terminals are arranged in a matrix as shown in FIG. In FIG. 2, Vcc arranged at 5E is a power supply terminal, and 1
The GNDs arranged at E and 8E are ground terminals. A0 to A17 are address input terminals, and D
Q0 to DQ15 are data input / output terminals, CE # is a chip enable signal input terminal, WE # is a write enable signal input terminal, OE # is an output enable signal input terminal, and RP # is a reset operation and This is a signal input terminal for controlling the super power saving mode. Further, Vpp arranged at 4B is a power supply terminal,
NCs arranged in 4A, 3B, 6B, 4C, 5C and 8F are non-connect terminals.

【0028】ここで、アドレス端子およびデータ端子に
入力される信号としては、図3および図4に示すよう
に、隣り合う端子(例えば1Aに配置されている端子と
2Aに配置されている端子など)に対して、別のレベル
(”L”および”H”)の信号を入力した方が効果的で
ある。これによって、その端子の接続状態(コンタクト
状態)だけでなく、隣接する端子との短絡も同時に試験
することができる。なお、図4は図3に示す入力信号レ
ベル”H”および”L”を反転させた例を示す。
Here, as the signals input to the address terminal and the data terminal, as shown in FIGS. 3 and 4, adjacent terminals (for example, terminals arranged at 1A and terminals arranged at 2A, etc.) ), It is more effective to input signals of different levels (“L” and “H”). As a result, not only the connection state (contact state) of the terminal but also a short circuit with an adjacent terminal can be tested at the same time. 4 shows an example in which the input signal levels "H" and "L" shown in FIG. 3 are inverted.

【0029】図3に示す入力信号に対応するアドレス端
子、データ端子への入力値は、それぞれ、図6に(1)
で示すような値になり、図4に示す入力信号に対応した
アドレス端子、データ端子への入力値は、それぞれ、図
6に(2)で示すような値になる。これらの値は、期待
値として使用するために、図1に示すデバイス内部の記
憶領域4に予め格納されている。この記憶領域4は、メ
インメモリセルとは別領域に設けられており、構造はメ
インメモリセルと同じであっても異なっていてもよい。
The input values to the address terminal and the data terminal corresponding to the input signal shown in FIG. 3 are (1) in FIG. 6, respectively.
6 and the input values to the address terminal and the data terminal corresponding to the input signal shown in FIG. 4 are the values shown in (2) in FIG. 6, respectively. These values are stored in advance in the storage area 4 inside the device shown in FIG. 1 so as to be used as expected values. This storage region 4 is provided in a region different from the main memory cell, and the structure may be the same as or different from that of the main memory cell.

【0030】デバイスに電源電圧を印加した後で、図5
に示すタイミングチャートにおいて(1)の部分で示す
ように、ライトイネーブル信号WE#を用いたタイミン
グによって、図6に(1)で示す値AmおよびDQn
が、アドレス端子およびデータ端子からそれぞれ入力さ
れる。
After applying the power supply voltage to the device, FIG.
As shown in the portion (1) in the timing chart shown in FIG. 6, the values Am and DQn shown in (1) in FIG. 6 are changed depending on the timing using the write enable signal WE #.
Are input from the address terminal and the data terminal, respectively.

【0031】このとき、データ端子から入力された値が
正しく図1に示す入出力バッファ3に格納され、コント
ローラ1内部の認識部において記憶領域4からの期待値
と比較され、判定実行コマンドであるか否かが判断され
る。そして、判定実行コマンドとして認識されると、ア
ドレス端子から入力された値が格納されている入力バッ
ファ2の値と記憶領域4からの期待値とがコントローラ
1内部の認識部において比較される。この比較結果が一
致すれば、コントローラ1の比較判定結果出力部から、
予め決められた合格を示す値(例えば0×80)が、一
致しなければ不合格を示す値(例えば0×80以外の
値)が出力され、入出力バッファ3を介してデータ入出
力端子から判定結果として出力される。
At this time, the value input from the data terminal is correctly stored in the input / output buffer 3 shown in FIG. 1, and is compared with the expected value from the storage area 4 in the recognition section inside the controller 1 to be the judgment execution command. It is determined whether or not. When it is recognized as a determination execution command, the value in the input buffer 2 in which the value input from the address terminal is stored and the expected value from the storage area 4 are compared in the recognition unit inside the controller 1. If the comparison results match, from the comparison determination result output unit of the controller 1,
A predetermined value indicating pass (for example, 0x80) is output if it does not match, a value indicating fail (for example, a value other than 0x80) is output from the data input / output terminal via the input / output buffer 3. It is output as the determination result.

【0032】出力された判定結果は、図5に示すタイミ
ングチャートにおいて(2)の部分で示すように、OE
#端子に”L”の信号を印加することによって、データ
端子から出力される判定結果がリードされて確認され
る。
The output judgment result is OE as shown in part (2) of the timing chart of FIG.
By applying the "L" signal to the # terminal, the determination result output from the data terminal is read and confirmed.

【0033】続いて、コンタクト状態が不良である端子
でも、入力信号が偶然に一致して判定結果が不正確にな
ることを避けるために、図6に示す(1)とは”H”
と”L”の論理を逆にした図6に(2)で示す値を使用
して、同様の方法によって再度、コンタクト状態を判定
する。
Next, in order to avoid that the input signals happen to coincide with each other and the judgment result becomes inaccurate even in a terminal having a bad contact state, "1" shown in FIG. 6 is "H".
The contact state is determined again by the same method using the values shown in (2) in FIG.

【0034】ここで、例えばデータ入出力端子にコンタ
クト不良がある場合には、データ入出力端子から入力さ
れた値が判定実行コマンドとして認識されないため、ア
ドレス入力端子から入力された値と期待値との比較自体
が行われず、出力結果が合格を示す値ではないことか
ら、コンタクト不良があると判定することができる。ま
た、アドレス入力端子にコンタクト不良がある場合に
は、アドレス入力端子から入力された値と期待値との比
較は行なわれるが、入力バッファ2に格納される値は期
待値とは異なる値になり、不合格の判定結果が出力され
ることから、コンタクト不良があると判定することがで
きる。さらに、ライトイネーブル信号入力端子WE#に
コンタクト不良がある場合には、デバイスに対してデー
タ入出力端子からの入力が行なわれず、入出力バッファ
3に値が格納されないため、判定実行コマンドとして認
識されず、比較は行なわれないことから、コンタクト不
良があると判定することができる。また、アウトプット
イネーブル信号入力端子OE#にコンタクト不良がある
場合には、比較判定結果が出力されないことから、コン
タクト不良があると判定することができる。また、リセ
ット動作および超消費電力モード制御信号入力端子RP
#にコンタクト不良がある場合には、デバイスがリセッ
トされないことから、コンタクト不良があると判定する
ことができる。さらに、チップイネーブル信号入力端子
CE#にコンタクト不がある場合には、デバイスが動作
しないことから、コンタクト不良があると判定すること
ができる。
Here, for example, when there is a contact failure in the data input / output terminal, the value input from the data input / output terminal is not recognized as the determination execution command. Since the comparison itself is not performed and the output result is not a value indicating acceptance, it can be determined that there is a contact failure. If the address input terminal has a defective contact, the value input from the address input terminal is compared with the expected value, but the value stored in the input buffer 2 is different from the expected value. Since the result of the judgment of failure is output, it can be judged that there is a contact failure. Further, if the write enable signal input terminal WE # has a defective contact, no input is made from the data input / output terminal to the device and no value is stored in the input / output buffer 3, so it is recognized as a determination execution command. Since no comparison is made, it can be determined that there is a contact failure. Further, if the output enable signal input terminal OE # has a contact failure, it is possible to determine that there is a contact failure because the comparison determination result is not output. In addition, reset operation and super power consumption mode control signal input terminal RP
If there is a contact failure in #, it can be determined that there is a contact failure because the device is not reset. Further, when the chip enable signal input terminal CE # has no contact, it can be determined that there is a contact failure because the device does not operate.

【0035】以上のように、本実施形態によれば、従来
よりも簡単な方法で効率よく、外部端子のコンタクト状
態をチェックすることができる。
As described above, according to this embodiment, it is possible to efficiently check the contact state of the external terminal by a simpler method than the conventional method.

【0036】[0036]

【発明の効果】以上詳述したように、本発明によれば、
外部から予め定められた特定の信号を入力し、内部のコ
ントローラによって記憶部に記憶されている期待値と比
較することによって、ボード等に半導体記憶装置が実装
された後で、各外部端子のコンタクト状態を、従来技術
よりも簡単に精度良くチェックすることができる。ま
た、半導体記憶装置が実装されるシステムボードのコン
トローラに、信号の入力と比較結果の判定機能とを持た
せることによって、試験用装置を別に設けなくても、シ
ステムボード単体で外部端子のコンタクト状態をチェッ
クすることができる。
As described in detail above, according to the present invention,
By inputting a predetermined signal from the outside and comparing it with the expected value stored in the storage section by the internal controller, the contact of each external terminal after the semiconductor storage device is mounted on the board etc. The condition can be checked more easily and more accurately than in the prior art. In addition, by providing the controller of the system board on which the semiconductor memory device is mounted with the function of inputting signals and determining the comparison result, the system board alone does not need to be equipped with a test device to contact the external terminals. Can be checked.

【0037】また、本発明によれば、外部からコマンド
信号として入力された値を内部のコントローラによって
記憶部に記憶されている期待値とを比較するだけで、従
来よりも簡単な方法によって、各外部端子のコンタクト
状態をチェックすることができる。
Further, according to the present invention, by simply comparing the value input as the command signal from the outside with the expected value stored in the storage section by the internal controller, each value can be obtained by a simpler method than before. You can check the contact status of the external terminals.

【0038】また、本発明によれば、試験が行われるデ
バイスによって最適な期待値を格納しておくことができ
るため、様々なパッケージ、端子配置等に対応すること
ができる。
Further, according to the present invention, the optimum expected value can be stored depending on the device to be tested, so that various packages, terminal arrangements, etc. can be dealt with.

【0039】また、本発明によれば、従来技術よりも簡
易な方法で、ボード等に半導体記憶装置が実装された後
で、各端子のコンタクト状態を、精度良くチェックする
ことができる。
Further, according to the present invention, the contact state of each terminal can be accurately checked after the semiconductor memory device is mounted on the board or the like by a simpler method than the prior art.

【0040】さらに、本発明によれば、2種類以上のパ
ターンの信号によって試験を行うことによって、検出精
度をより向上させることができる。
Further, according to the present invention, the detection accuracy can be further improved by performing the test with the signals of two or more types of patterns.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態である半導体記憶装置の概
略構成を説明するためのブロック図である。
FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

【図2】本発明の一実施形態である半導体記憶装置にお
いて、CSPパッケージを例とした端子配置例を示す図
である。
FIG. 2 is a diagram showing an example of terminal arrangement using a CSP package as an example in a semiconductor memory device according to an embodiment of the present invention.

【図3】本発明の一実施形態である半導体記憶装置にお
ける、入力信号の一例を示す図である。
FIG. 3 is a diagram showing an example of an input signal in the semiconductor memory device according to the embodiment of the present invention.

【図4】本発明の一実施形態である半導体記憶装置にお
ける、入力信号の他の例を示す図である。
FIG. 4 is a diagram showing another example of an input signal in the semiconductor memory device according to the embodiment of the present invention.

【図5】本発明の一実施形態である半導体記憶装置の試
験方法を説明するためのタイミングチャートである。
FIG. 5 is a timing chart for explaining a test method for a semiconductor memory device according to an embodiment of the present invention.

【図6】本発明の一実施形態である半導体記憶装置の試
験方法における、入力信号の期待値の例である。
FIG. 6 is an example of an expected value of an input signal in the semiconductor memory device testing method according to the embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 デバイス内部のコントローラ 2 アドレス入力バッファ 3 データ入出力バッファ 4 デバイス内部の期待値記憶領域 1 Device internal controller 2 address input buffer 3 data input / output buffer 4 Expected value storage area inside the device

Claims (5)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 外部と接続されて信号が入出力される外
    部端子と内部の記憶領域との間の信号の入出力を制御す
    ると共に、半導体記憶装置をボードに実装後に、外部端
    子に特定の信号を入力することによって各端子のコンタ
    クト状態を判定するコントローラと、 該記憶領域内に該特定の信号の期待値データが記憶され
    ている記憶部とを備え、 該コントローラは、データ入出力端子から入力されたコ
    マンド信号が判定実行コマンドを示すか否かを認識する
    認識部と、 該認識部にて判定実行コマンドであると認識された場合
    に、アドレス入力端子から入力された信号と、該記憶部
    に記憶されている期待値データとを比較して、一致して
    いる場合には合格とし、一致しない場合には不合格とし
    て判定結果を出力する比較判定結果出力部とを有するこ
    とを特徴とする半導体記憶装置。
    1. An input / output of a signal between an external terminal connected to the outside for inputting / outputting a signal and an internal storage area is controlled, and after the semiconductor memory device is mounted on a board, the semiconductor memory device is specified to the external terminal. The controller includes a controller that determines a contact state of each terminal by inputting a signal, and a storage unit in which expected value data of the specific signal is stored in the storage area. A recognition unit that recognizes whether the input command signal indicates a determination execution command, a signal input from the address input terminal when the recognition unit recognizes that the determination execution command, and the storage unit It has a comparison judgment result output unit that compares the expected value data stored in the unit and outputs a judgment result as a pass if it matches and a fail if it does not match. And a semiconductor memory device.
  2. 【請求項2】 前記記憶部には、さらに、コマンド信号
    に対する期待値データが記憶されており、 前記認識部は、データ入出力端子から入力されたコマン
    ド信号と、該記憶ブロックに記憶されているコマンド信
    号に対する期待値データとを比較して、一致している場
    合には判定実行コマンドであると判断し、一致しない場
    合には判定実行コマンドではないと判断することを特徴
    とする請求項1に記載の半導体記憶装置。
    2. The storage section further stores expected value data for a command signal, and the recognition section stores a command signal input from a data input / output terminal and the storage block. The expected value data for the command signal is compared, and if they match, it is determined that the command is a determination execution command, and if they do not match, it is determined that the command is not a determination execution command. The semiconductor memory device described.
  3. 【請求項3】 前記記憶部には、様々なパッケージに対
    応するために、予め必要な複数の期待値が記憶されてい
    ることを特徴とする請求項1または請求項2に記載の半
    導体記憶装置。
    3. The semiconductor memory device according to claim 1, wherein the storage unit stores a plurality of expected values necessary in advance to support various packages. .
  4. 【請求項4】 請求項1乃至請求項3のいずれかに記載
    の半導体記憶装置を実装後に、外部と接続されて信号が
    入出力される外部端子のコンタクト状態を判定する試験
    方法であって、 各外部端子に外部から特定の信号を入力し、前記認識部
    によって、データ入出力端子から入力されたコマンド信
    号が判定実行コマンドを示すか否かを認識するステップ
    と、 判定実行コマンドであると認識された場合に、前記比較
    判定結果出力部によって、アドレス入力端子から入力さ
    れた信号と予め記憶部に記憶されている期待値データと
    を比較判定するステップとを含むことを特徴とする半導
    体記憶装置の試験方法。
    4. A test method for determining a contact state of an external terminal, which is connected to the outside and inputs / outputs a signal, after mounting the semiconductor memory device according to claim 1. A step of inputting a specific signal to each external terminal from the outside and recognizing whether or not the command signal input from the data input / output terminal indicates the judgment execution command by the recognition unit, and recognizes that the judgment execution command In the case of the above, the semiconductor memory device further comprises a step of comparing and judging the signal input from the address input terminal with the expected value data stored in advance in the memory unit by the comparison and judgment result output unit. Test method.
  5. 【請求項5】 前記特定の信号には、少なくとも2種類
    のパターンが含まれ、各外部端子に対して、少なくとも
    2回、コンタクト状態の判定を行うことを特徴とする請
    求項4に記載の半導体記憶装置の試験方法。
    5. The semiconductor according to claim 4, wherein the specific signal includes at least two types of patterns, and the contact state is determined at least twice for each external terminal. Memory device test method.
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