JPS6034199B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable as a programmable ROM in which data can be electrically erased, and more particularly to a semiconductor memory device in which a means for measuring electric charge in a floating gate of a memory cell is added.

EP-ROM (Erasable Programmable
Data can be written or erased after manufacturing (e-ROM), and they can be broadly classified into two types: ultraviolet erasable type and electrically erasable type. Among these, ultraviolet-erasable EP-ROMs can be highly integrated because one memory cell can be configured with one transistor, and products with 32K-bit and 64K-bit integration have been developed to date. has been done. However, this UV erasable type requires a package that allows UV light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E2P-ROM)
lly Erasable P-ROM)],
Since one memory cell is composed of at least two transistors, the degree of integration cannot be increased very high, and so far only devices with a degree of integration of one bit have been announced. However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs. Of these, FIG. 1 is a structural diagram showing one memory cell portion of a conventional E2P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors.

In the figure, 1 is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the Yabu mine point, there is a MOS transistor 4 for bit selection, a control gate and a floating gate for data storage. A double gate type MOS transistor 5 having a gate is connected in series. The gate of one MOS transistor 4 is connected to the selection line 2, and the control gate of the other MOS transistor 5 is connected to the data program line 3. Conventional E2P with this configuration
-ROM has the following drawbacks.

■ As is clear from Figure 1, one memory cell is composed of two transistors, so the number of elements is twice that of the UV-erasable type, and the degree of integration is half that.
Therefore, it is disadvantageous for integration.

■ When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board, etc., a power source with both positive and negative polarities is required to electrically rewrite data.

■ It is difficult to erase data in word units or all bit units at the same time.

■ It is difficult to erase all bits of data in a short time.

■ It is impossible to erase data with a single 5 volt power supply.

The present invention has been made in view of the above-mentioned circumstances, and while it is possible to eliminate the above-mentioned drawbacks, it is also possible to quantitatively measure the amount of injected charge after programming, that is, after injecting charge into the floating gate of a memory cell. It is an object of the present invention to provide a semiconductor memory device in which the amount of attenuation of the charge accumulated in the floating gate after programming can be known quantitatively.

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 2a to 2d show the configuration of a memory cell according to a first embodiment of the present invention, and only 4 bits of memory cells are shown. Of these, Fig. 2a is a pattern plan view, Fig. 2b is a structural cross-sectional view along line 1-1' in Fig. 2a,
Figure 2c is a cross-sectional view of the structure along line 0-RO' in figure a;
Figure d is a structural sectional view taken along line m-m' in figure a. In FIG. 2, 11 is a semiconductor substrate made of P-type silicon, and the surface of this substrate 11 is covered with gate insulating films 12a, 1
2b, 12c, and 12d are arranged in an XY matrix at regular intervals. Further, on the surface of the substrate 11, gate insulating films 12 are formed at two locations adjacent to each other in the vertical direction in the figure.
A and 12c and 12b and 12d are paired, and a field insulating film 13 is formed between the gate insulating film pairs. Moreover, on this field insulating film 13, P or A
A first conductor layer 14 made of polysilicon containing s
is formed. Furthermore, each of the gate insulating films 12a,
Second conductor layers 15a, 15b, 15c, and 15d made of polysilicon are formed separately from each other on the conductor layers 12b, 12c, and 12d. The right end portions of the two second conductor layers 15a and 15c, which are located on the left side of the first conductor layer 14 in the figure, are connected to the It overlaps with the left end of the first conductor layer 14. In addition, there are two second conductor layers 15a located on the right side with respect to the conductor layer 14.
, 15d overlap the right end of the conductive layer 14 with the insulating film 16 interposed therebetween. Furthermore, second conductor layers 15a and 1 adjacent in the left and right direction in the figure
A third conductor layer 18A made of polysilicon and having a width set to be approximately the same as both conductor layers 15a and 15b is formed on the conductor layer 5b via an insulating film 17 so as to cover it. Similarly, on the second conductor layers 15c and 15d adjacent to each other in the left and right directions in the figure, the two conductor layers 15c are coated via the insulating film 17 so as to cover them.
, 15d is formed. Another third conductor layer 18B is formed of polysilicon and has a width set to be approximately the same as that of the conductor layer 18B. Furthermore, an N+ type semiconductor layer 19A is formed in the surface region of the substrate 11 between two gate insulating films 12a and 12c that are adjacent to each other in the vertical direction in the figure.
An N0 type semiconductor layer 19B is formed in the surface region of the substrate 11 between the gate insulating films 12b and 12d. Furthermore, each gate insulating film 12a, 12b, 12c, 12
d, the N+ type semiconductor layer 1 9A or 19
A continuous N0 type semiconductor layer 19C is formed in the surface region of the substrate 11 on the side opposite to the B formation side. Furthermore, fourth conductor layers 21A and 21B made of N are formed on the third conductor layers 18A and 18B with an insulating film 20 interposed therebetween, and one of the conductor layers 21A and 21B is made of N. 21A and the N0-type semiconductor layer 19A are connected by a contact hole 22A, and the other conductor layer 21B and the N↓-type semiconductor layer 19B are connected by another contact hole 22B. And the N+ type semiconductor layer 19C
is connected to a reference potential point, for example, a ground potential point. Furthermore, in FIG. 2a, the area indicated by the symbol ABCD and marked with a broken line indicates a memory cell for one bit of this semiconductor memory device, and as is clear from FIG. 2b, this memory cell is The second conductor layer 15 is a floating gate, the third conductor layer 18 is a control gate, and the first conductor layer 1 is a control gate.
4 as erase gate, N+ type semiconductor layer 1
It is composed of a MOS transistor with 9A as the drain and N+ type semiconductor layer 19C as the source, and when looking at the 2 bits shown in FIG. It is composed of a pair of MOS transistors configured as follows.

The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel within the insulating film sandwiched between the control gate and the substrate 11. There is.
Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Furthermore, as shown in FIG. 2b, in the overlapping portion, the second conductive layer 15
That is, the floating gate is located above the first conductive layer 14, that is, the erase gate, and
and the conductor layer 14 is the distance between the substrate 11 and the conductor layer 15
It is shorter than the distance between. FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above.

In the figure, 31 and 32 are the fourth conductor layer 21A.
, 21B, 33 and 34 are the first digit lines.
Erasing line 3 formed by extending the third conductive layer 14
5 and 36 are selection lines (row lines) formed by extending the third conductor layers 18A and 18B. MI again~
M4 is a memory cell, each memory cell is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D and a source S,
The drains D of the memory cells M1 and M2 are connected to one of the digit lines 31, the drains D of the memory cells M3 and M4 are connected to the other digit line 32, and the sources S of all the memory cells M are connected to the ground potential point. Ru. Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now, paying attention to the memory cell MI in FIG. 3, in the initial state, no electrons are injected into the floating gate FG of the memory cell MI, and the voltage V is in a low state. When writing data to this memory cell MI,
Apply a positive high voltage, for example 120 volts, to the selection line 35.
By applying a positive high voltage, for example, 120 volts, to the digit lines 31, a flow of hot electrons is generated from the source S to the drain D of the memory cell MI.
These hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region.

As a result, the threshold voltage VTH of this memory cell MI
rises.

When writing data, a high voltage pulse of, for example, 120 volts, a DC voltage of 15 volts or 0 volts may be applied to the erase line 33, or it may be left open. Next, when data is to be continued from this memory cell MI, the selection line 35 is selected and a high level signal (15 volts) is applied to the control gate CG of the memory cell MI.

When this high level signal is applied, the voltage VT
If H is low, this memory cell MI is turned on, and a current flows from one digit line 31 through the memory cell MI toward the ground potential point. On the other hand, if the voltage VTH is high when the high level signal is applied, this memory cell MI is turned off and no current flows. At this time,
The state in which current flows through the memory cell MI is set to logic “1”.
If the state in which no current flows is set to the logic "0" level, this device can be used as a memory device.Also, as mentioned above, the flowing gate FG can be surrounded by an insulating film. Since it is insulated and isolated from other parts, once it is injected into the memory, the electrons cannot escape under normal usage conditions, so it can be used as a non-volatile data storage device. If you want to delete the data,
The selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of 140 volts, is applied to the erase line 33.

By applying such a voltage, the memory cell M
Field emission occurs between floating gate FG and erase gate EG of I,
The electrons that have been accumulated in the floating gate FG' are leaked to the outside via the erase gate EG and the erase line 33. As a result, the voltage VTH of this memory cell MI returns to a low state similar to the initial state. In this way, in the semiconductor memory device of the above embodiment, the erase gate is arranged in parallel to the floating gate of a normal double gate type MOS transistor to configure a memory cell for one bit. Various effects can be obtained.

(1) One memory cell can be composed of one transistor, and data can be electrically erased.

Therefore, it is possible to realize an electrically erasable EP-ROM having a degree of integration comparable to that of the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low. ■ Data can be written, erased, and read using a single polarity power supply.

That is, for example, a positive polarity power supply of 120 volts for writing, 140 volts for erasing, and 15 volts for reading is required, and it is also possible to obtain 120 volts and 140 volts from a voltage of 15 volts using a booster circuit. If you do this, you can use just one 15 volt power source.
Therefore, data can be written, erased, and read while mounted on a printed broken line board or the like. - Since there is no transistor for bit selection, data can be erased simultaneously in word units and all bit units.

■ Field emission is used to erase data, so data can be erased in a short time.

(2) Since no other process is required except for forming a three-layer polysilicon structure, it can be manufactured using a normal silicon gate process. Next, an example of the manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 will be described. This will be explained using a cross-sectional view taken along the line '. First, as shown in FIGS. 4a and 5a, an insulating film of 1 Am is grown on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography to form field insulating films 13 and 13'. Furthermore, P or As is diffused into the shaded region in FIG.
C' is formed. After the completion of the diffusion, the surface of the substrate 11 in areas other than the field insulating films 13, 13' is exposed, and then a thermal oxidation method is applied to
A relatively thin oxide film of 00A is formed to form the gate insulating film 12. Next, apply 600 to the entire board 11.
After growing polysilicon with a thickness of 0△ and doping it with P or As, a photolithographic method was used to form a polysilicon film as shown in Fig. 4b.
A first conductor layer 14 is formed in the solid line area. Although an example is shown in which the first conductive layer 14 is not formed on the adjacent field insulating films 13', it may be formed if necessary. Next, after forming the first conductive layer, as shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500A is grown by thermal oxidation, and then CVD A polysilicon film having a thickness of 5,000 Å is grown by a method, and a photolithography method is applied to this to form second conductor layers 15a, 15b, 15c, and 15d as floating gates. As is clear from the figure, in FIG. An example is shown in which at least a portion thereof overlaps with the first conductor layer 14. The other ends of the conductor layers 15a and 15b do not overlap with the conductor layer 14. After forming the floating gate FG, as shown in FIGS. 4 d and 5 d, an insulating film 17 with a thickness of 1000 to 2000 Å is formed by thermal oxidation, and polysilicon is deposited thereon. By applying the photoengraving method, the third conductor layers 18A, 18B which will become control gates are formed, and at the same time, the second conductor layers 15a, 15b, 15c, 1 are formed.
5d self-alignment. Next, P or $ is diffused into the shaded areas in FIG. 4e to form N+ type semiconductor layers 19A, 19B, and 19C. Furthermore, the fourth
As shown in FIG. e and FIG. 21A, 21B
This semiconductor memory device is completed by forming and connecting to the N+ type semiconductor layers 19A and 19B through contact portions 22A and 22B, respectively. 6a to 6c show the structure of a memory cell according to a second embodiment of the present invention, FIG. 6a is a pattern plan view, and FIG. 6b is taken along line 1-1' of FIG. 6a. FIG. 6c is a structural sectional view taken along the row 0' line in FIG. 6a.

In FIG. 6, 111 is a semiconductor substrate made of P-type silicon, and a gate insulating film 11 is formed on the surface of this substrate 111.
2a to 112f are arranged in an XY7 trix shape at regular intervals.

Further, on the surface of the substrate 111, gate insulating films 112a, 112d, and 112 are formed at respective locations adjacent to each other in the vertical direction in the figure.
b and 112e and 112c and 112f are paired, and feed insulating films 113 and 113' are formed between the gate insulating film pairs.
is formed. Further, a first conductor layer 114 made of polysilicon containing P or As is formed on the field insulating bran 113 at one location. Further, on each of the gate insulating films 112a to 112f, a second conductor layer 115a to 115 made of polysilicon is formed.
f are formed separately from each other. An insulating film 116 is provided at each right end of the second conductive layer 115b and 115e, which are located on the left side of the first conductive layer 114 in the figure. It overlaps with the left end of the first conductor layer 114. Further, the left end portions of the two second conductive layers 115c and 115f located on the right side with respect to the conductive layer 114 are connected to the right end portions of the conductive layer 114 via the insulating film 116. It overlaps with Furthermore, on the second conductor layers 115a, 115b, 115c adjacent to each other in the left and right direction in the figure, each of these conductor layers 115a, 115b, 115c is placed through an insulating film 117 so as to cover the second conductor layers 115a, 115b, 115c. A third conductor layer 11 made of polysilicon and set to approximately the same width.
8A is formed, and similarly second conductor layers 115d, 115e, 1 adjacent to each other in the left and right direction in the figure are formed.
15f-, each of these conductive layers 115d, 115e, 115 are placed on the insulating film 117 so as to cover it.
Another third conductor layer 118B made of polysilicon and having a width set to be approximately the same as f is formed.
Furthermore, an N0-type semiconductor layer 119A is formed in the surface region of the substrate 111 between two gate insulating films 112a and 112d that are adjacent to each other in the vertical direction in the figure, and two gate insulating films 112b and 112e are formed in the surface region of the substrate 111. An N+ type semiconductor layer 119B is formed on the surface area of the substrate 111 between the gate insulating films 1 12c and 112e.
An N+ type 0 semiconductor layer 119C is formed in the first front area. Further, for each of the gate insulating films 112a to 112e, the N+ type semiconductor layers 119A, 119B, 1 1
A continuous N+ type semiconductor layer 119D is formed on the surface region of the substrate 111 on the side opposite to the side where 9C is formed.
Further, on the third conductor layers 118A and 118B, wiring layers 121A and 121A, 1
21B, 121C, and 121D are formed, among which one wiring layer 121A and the N+ type semiconductor layer 119A are formed.
are connected by the contact hole 122A, the wiring layer 121B and the N+ type semiconductor layer 119B are connected by the contact hole 122B, and the wiring layer 121C and the first conductive layer 114 are connected by the contact hole 122.
The wiring layer 121D and the N+ type semiconductor layer 119C are connected by a contact hole 122D. The N+ type semiconductor layer 1190 is connected to a reference potential point, for example, a ground potential point. In addition, in FIG. 6a, the area surrounded by a broken line with the symbol ABCD indicates a 1-bit memory cell of this semiconductor memory device, and this memory cell is connected to the second conductor layer 11.
5 as a floating gate, the third conductor layer 118 as a control gate,
The first conductor layer 114 is connected to an erase gate.
g), is composed of a MOS transistor with the N+ type semiconductor layer 119B as the drain and the N+ type semiconductor layer 119D as the source, and further looking at the 2 bits shown in FIG. 6b, the control gate and erase gate are as follows. They are common to each other and are composed of a pair of MOS transistors configured symmetrically with respect to the erase gate.

The control gate is provided on the semiconductor substrate 111 via an insulating film, and the floating gate and erase gate are provided on the semiconductor substrate 111 with an insulating film interposed therebetween.
The structure is such that they are arranged in parallel within an insulating film sandwiched by. Furthermore, since the erase gate is formed on the field insulating film 113, the overlapping portion of each flow gate and erase gate exists within the field region. Furthermore, as shown in Figure 6b,
In the overlapping portion, the second conductive layer 115, that is, the floating gate, is located above the first conductive layer 114, that is, the erase gate, and the substrate 111 and the conductive layer 114 are located above the first conductive layer 114, that is, the erase gate. The distance between
11 and the conductor layer 115. Further, as is clear from FIG. 6a, the first conductor layer 114 has one
The conductor layer 114 at each location is provided at only one location.
The wiring layer 121C is connected to the contact hole 122C at the location.
is connected to. The equivalent circuit diagram of the semiconductor memory device shown in FIG. 6 is the same as that shown in FIG. 3, and its operation is also the same, so a description thereof will be omitted.

In addition to the effects (1) to (2) of the device of the above embodiment, the semiconductor memory device of the above embodiment can also obtain the following effects (1) to (4).

■ Instead of wiring using polysilicon that constitutes the erase gate (first conductive layer) 114,
Since the erase line is formed using the wiring layer 121C made of I, the thickness of the insulating film between the erase line and the substrate can be made relatively thick, and therefore a high voltage can be applied to the erase line with EO. However, no leaks will occur.

(2) One contact hole connecting the erase gate and the wiring layer 121C needs to be provided for every 4 bits of the memory cell, so the number of contacts per 1 bit is 1/4, and high integration is possible. ■ Thermionic injection is used when writing data, and field emission is used when erasing data.

A relatively thick insulating film can be used around the routing gate, and non-volatile properties, that is, data retention properties are good. Next, an example of the manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 6 will be explained. This will be explained using a cross-sectional view taken along the line '.

First, as shown in FIGS. 7a and 8a, an insulating film 1 is grown on the surface of a semiconductor substrate 111 made of P-type silicon by photolithography, and field insulating films 113, 1
13' is formed. Note that at this time, the field insulating film 1
A thin insulating film 123 is formed between 13 and 113'. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 111, and after doping it with P or As, the field insulating film 111 is formed at one location as shown by the solid line in FIG. A first conductor layer 114 is formed thereon. Although an example is shown in which the conductor layer 114 is not formed on the adjacent field insulating film 113', it may be formed as necessary. Next, after forming the first conductor layer 114, the seventh conductor layer 114 is formed.
As shown in Figure c and Figure 8c, 5
The gate insulating film 1 is grown by growing an oxide film with a thickness of 00A.
12a to 1 12f and an insulating film 116 are formed, and then polysilicon is grown to a thickness of 5000△ by the CVD method, and then a second layer as a floating gate is formed by applying a photolithography method. conductor layer 115a of
~115f is formed. As is clear from the figure, FIG. 8c shows a conductor layer 1 which becomes a floating gate.
An example has been shown in which only one end of each of the field insulating films 113 extending over the field insulating film 113 at least partially overlaps with the first conductive layer 114 with the insulating film 116 interposed therebetween. The ends of the conductive layers 115b and 115c do not overlap with the conductive layer 114. After forming the floating gate, as shown in FIGS. 7d and 8d, an insulating film 117 with a thickness of 1000 to 2000 A is formed by a thermal oxidation method, and polysilicon is deposited thereon. A photolithography method is applied to form third conductor layers 118A and 118B serving as control gates, and at the same time, second conductor layers 115a to 115f are formed by self-alignment. Next, P or Trinary is diffused into the shaded region in FIG. 7e to form N+ type semiconductor layers 119A, 119B, 119C which will become drains and an N+ type semiconductor layer 119D which will serve as a source.
Furthermore, as shown in FIGS. 7e and 8e, the substrate I1
An insulating film 120 and a mountain film are successively deposited over the entirety of 1, and a photolithography method is applied to this AI film to form wiring layers 121A, 1.
21B, 121C, and 121D are formed. At this time, contact holes 122A, 122B, 122C,
1220 is opened, contact holes 122A,
N+ type semiconductor layer 1 by 122B and 122D, respectively.
19A, 119B, 119C and wiring layers 121A, 121
This semiconductor memory device is completed by connecting the first conductor layer 114 and the wiring layer 121C through contact holes 122C. FIG. 9 shows an embodiment of the present invention, in which an MXN-bit semiconductor memory device is constructed using the semiconductor memory device shown in FIG. 2 or FIG. 6.

In the figure, M, . ,......MIM,...・・・．・・・
MN......NNM are 1-bit memory cells each arranged in a matrix of N in the column direction and M in the row direction, and each of these memory cells is the same as above. It consists of a control gate CG, a flow gate FG, an erase gate EG, a drain D, and a source S. The drain D of each memory cell arranged in the same column is connected to each N digit line 4.
1, to 41N are commonly connected to each other. In addition, when a column address is input to the N digit lines 41, to 41N, one output terminal is selected according to the column address when reading or writing data, and only the selected output terminal outputs a high level. Signal, for example 15,
It is connected to the output of a column decoder 42 which outputs 120 volts and outputs a low level signal, e.g. 0 volts, from all unselected outputs. Furthermore, the control gates CG of N memory cells arranged in the same row are
It is commonly connected to each of M row selection lines 43, to 43M. Furthermore, the M row selection lines 43, to 43M are
When a row address is input and data is read or written, one output terminal is selected according to the row address, a high level signal is output only from this selected output terminal, and a low level signal is output from all unselected output terminals. It is connected to the output terminal of the output row decoder 44. Furthermore, the erase gates EG of all memory cells are commonly connected and further connected to an erase terminal 46 via a protection resistor 45. The sources S of all memory cells are commonly connected and further connected to a ground potential point. A data erase voltage, for example 140 volts, is applied to the erase terminal 46 when erasing data stored in each memory cell.

In a memory device having such a configuration, the floating gate F
If the capacitance between G and the control gate CG is CFc, if a charge (electron) of -Q enters the floating gate FG, the change in the function voltage of the transistor of the memory cell ΔVT is
△vT: Rare...・・・． ...Becomes a immortal.

Therefore, when a charge of 1Q is introduced, the related voltage changes as shown in equation '1}, so that it is possible to determine whether the data stored in the memory cell is "1" or "0". On the other hand, the erase terminal 46
When voltage VE is applied to the erase gate EG via △V
T is indicated by △VT: Live poisonous pest.

Here, CF8 is the capacitance between the floating gate FO and the erase gate EG. In this way, △VT is expressed by equation '2), and the apparent charge -Q accumulated in the floating gate can be reduced or increased by applying voltage VB to the erase gate EG. The amount of voltage injected into the floating gate FG can be quantitatively known from the voltage applied to the erase gate EG. That is, the erase gate applied voltage VE required to obtain a certain ΔVT can be measured, and Q can be found from the equation '2-. A specific example of the method for measuring the amount of charge Q is as follows:
It is sufficient to select a memory cell by the decoders 42 and 44, change the voltage V8 of the erase terminal 46, and find out the voltage VE at which the data on the digit line of the selected memory cell is inverted.

In addition, by first measuring the amount of charge Q immediately after writing data, and then measuring the amount of charge Q again after a predetermined period of time, it is possible to quantitatively predict the amount of charge attenuation due to aging from the results of both measurements. Therefore, since the retention characteristics of each memory cell can be estimated, bits with poor retention characteristics of memory cells can be screened in advance. On the other hand, in order to efficiently know the amount of charge Q, use the formula CFE～～CF
c......【3}
is better, but from the point of view of write efficiency, CFC>CF
......The larger the tendency of t41 is, the better. Therefore, the capacitance C wind is required to have a size below a certain level. Therefore, from the above writing efficiency and charge amount check, cFC > cFE ≧ ．．
・・・．・・・． ...It is desirable to satisfy [5'].

FIG. 10 is a configuration diagram of a first modified example of the embodiment shown in FIG. The ends are connected.

With this configuration, when data is not erased, the erase terminal 4
Even if memory cell 6 becomes open, the erase gate EG of each memory cell is set to the ground potential by the resistor 47 and does not become floating, thereby preventing malfunctions due to noise. Furthermore, when data is not erased, the erase gate EG is set to the ground potential, so the coupling in the overlapping portion between the floating gate FO and the erase gate EG causes the floating gate FG to be at a potential closer to the ground potential. As a result, the threshold voltage VTH of the memory cell becomes deeper. FIG. 11 is a configuration diagram of a second modification of the embodiment shown in FIG. 9, in which, instead of the resistor 47 in FIG. The other end of the resistor 48 is connected to the point where the power supply voltage Vcc (15 volts) is applied.

With this configuration, even if the erase terminal 46 is open when data is not erased, the erase gate EG of each memory cell is set to Vc by the resistor 48, as described above. Since the voltage is not set to a floating state, malfunctions due to noise can be prevented. Also, when data is not erased, the erase gate EG is Vc. Since the floating gate FG is set to the potential Vcc, the coupling at the overlapping portion between the floating gate FG and the erase gate EG causes the floating gate FG to be biased to a potential closer to the Vcc potential, as described above. As a result, the threshold voltage of the memory cell becomes shallower. FIG. 12 is a block diagram of a third modification of the embodiment shown in FIG. 9, in which both the resistor 47 in FIG. 10 and the resistor 48 in FIG. 11 are provided in the circuit in FIG. This is what I did.

With this configuration, when data is not erased, the erase gate EG is set to a certain potential between the ground potential and the Vcc potential. Note that the present invention is not limited to the above-mentioned embodiments, and various applications are possible.

For example, in FIG. 2 or FIG. 6, only the right end portion or the left end portion of the second conductive layer 15 or 115 overlaps at least a portion of the first conductive layer 14 or 114. In this case, both ends of the conductive layer 15 or 115 are connected to the conductive layer 14 or 1.
It may be made to overlap with 14. As explained above, the semiconductor memory device of the present invention can consist of one memory cell with one transistor, and data can be erased electrically, so it is superior to conventional devices in terms of integration degree and cost. Problems can be improved, and since the amount of charge injected into the memory cell can be measured, the state of charge injection and data retention characteristics can be determined.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a secondary E-tsubo ROM, and FIGS. 2a is a pattern plan view, FIG. 2b is a structural sectional view taken along line 1-1' in FIG. 2a, FIG. 2c is a structural sectional view taken along low D' line in FIG. 3 is an equivalent circuit diagram of the device shown in FIG. 2, and FIGS. 4 a to 5 e and 5 a to e are respectively similar to the above FIG. This figure is for explaining an example of the manufacturing method for manufacturing the device shown in FIG.
Figures a to e are cross-sectional views taken along lines 1-1' in Figures 4 a to e, and Figures 6 a to e show the structure of a memory cell according to a second embodiment of the present invention. 6a is a pattern plan view, FIG. 6b is a structural sectional view taken along line 1-1' in FIG. 6a, FIG. 6c is a structural sectional view taken along row 0' line in FIG. 8a to 8e are for explaining an example of a manufacturing method for manufacturing the apparatus shown in FIG. 6, respectively, and FIGS.
Figures 8a to 8e are the same as those in Figures 7a to 7e.
-1' line, FIG. 9 is a circuit configuration diagram of an embodiment of the present invention, FIG. 10 is a circuit diagram of a first modification of the above embodiment, and FIG. 11 is a circuit diagram of the above embodiment. FIG. 12 is a circuit diagram of a second modification of the example, and FIG. 12 is a circuit diagram of a third modification of the above embodiment. 11,111...Semiconductor substrate, 12,112...
...Gate insulating film, 13,113...Field insulating film, 14,1 14...First layer conductor layer (erase gate), 15,115...Second layer Eye conductor layer (floating gate), 16, 116, 17
, 117, 20, 120, 123... insulating film,
18,118...Third conductor layer (control gate), 19,119...N0-type semiconductor layer, 21...Fourth conductor layer body layer, 121・
...Wiring layer, 22,122...Contact hole, 31,32...Digital line, 33,34...
...Erasure line, 35, -36...Selection line, M1
, M2, M3, M4... Memo IJ cell, CG...
...Control gate (control gate), FG...
Floating gate, EG...
・Erase gate, D...Drain, S
... Source, M. ~M, M~MN, ~MNM...memory cell, 41...digit line, 42...column decoder, 43...row selection line, 44...row decoder, 45,
47, 48... Resistor, 46... Erase terminal. Figure 1 Figure 2 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1. A control gate provided on a semiconductor substrate via an insulating film, an erase gate provided in the insulating film sandwiched between the control gate and the base, and an erase gate provided in the insulating film. A memory cell is provided, which includes a floating gate that is placed in parallel with the erase gate and whose end portion overlaps at least a portion of the erase gate via an insulating film, and a source and a drain, and erases the memory cell. 1. A semiconductor memory device comprising means for varying the voltage applied to the gate and measuring the amount of charge accumulated in the floating gate. 2. The semiconductor memory device according to claim 1, wherein the means measures the voltage at which the operation of the memory cell is reversed when the voltage applied to the erase gate of the memory cell is changed. .