JPS623994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
It is possible to write or erase data after manufacturing, and there are two main types of devices: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32K bits and 64K bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
Since one memory cell (referred to as ROM) is composed of at least two transistors, the degree of integration cannot be increased very high, and so far only 16K bits have been announced. However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure 1
is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point, there is a MOS transistor 4 for bit selection, a control gate and a floating gate for data storage. A double gate type MOS transistor 5 is connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2.
The control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

This invention was made in consideration of the above circumstances, and its purpose is to eliminate the drawbacks of the conventional technology, and in particular to provide a semiconductor memory device that can simultaneously erase data column by column. It is about providing.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2d show the structure of a memory cell according to a first embodiment of the present invention, and only four bits of memory cells are shown. Of these, Fig. 2a is a pattern plan view, Fig. 2b is a structural sectional view taken along line -' in Fig. 2a, and Fig. 2c is a structural sectional view taken along -' line in Fig. 2a. a is same figure a
FIG.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon. On the surface of this substrate 11, gate insulating films 12a, 12b, 12c, and 12d are arranged at regular intervals in an XY matrix.
Further, on the surface of the substrate 11, two gate insulating films 12a and 12 are formed adjacent to each other in the vertical direction in the figure.
c, 12b and 12d are paired, and a field insulating film 13 is formed between the pair of gate insulating films. Moreover, on this field insulating film 13, P
Alternatively, a first conductor layer 14 made of polysilicon containing As is formed. Furthermore, each of the gate insulating films 12a, 12b, 12c, 12d
Above, second conductive layers 15a, 15b, 15c, and 15d made of polysilicon are formed separately from each other. 2 located on the left side of the first conductor layer 14 in the figure.
The right end portions of the second conductive layers 15a and 15c overlap the left end portions of the first conductive layer 14 with the insulating film 16 interposed therebetween. Further, the left end portions of the two second conductive layers 15b and 15d located on the right side with respect to the conductive layer 14 are connected to the right end portions of the conductive layer 14 via the insulating film 16. It overlaps with Furthermore, second conductor layers 15a and 1 adjacent in the left and right direction in the figure
A third conductor layer 18A made of polysilicon and having a width set to be approximately the same as both conductor layers 15a and 15b is formed on the conductor layer 5b via an insulating film 17 so as to cover it. Similarly, the second conductor layer 1 adjacent in the left and right direction in the figure
5c, 15d are covered with conductive layers 15c, 15d via the insulating film 17.
Another third conductor layer 18B made of polysilicon and having a width set to be approximately the same as that is formed. And also, 2 adjacent vertically in the figure
An N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between the gate insulating films 12a and 12c at two locations, and similarly, the gate insulating film 12 at two locations
In the surface area of the substrate 11 between b and 12d,
An N ⁺ type semiconductor layer 19B is formed. Furthermore, each gate insulating film 12a, 12b, 12c, 12d
In contrast, the N ⁺ type semiconductor layer 19A or 1
A continuous N ⁺ type semiconductor layer 19C is formed in the surface region of the substrate 11 on the side opposite to the side where the layer 9B is formed. Further, the third conductive layer 18A, 18
A fourth layer made of Al is placed on B with an insulating film 20 interposed therebetween.
Conductive layers 21A and 21B are formed, one of which is connected to the N + type semiconductor layer 19A through a contact hole 22A, and the other conductive layer 21B is connected to the N ⁺ type semiconductor layer 19A through a contact hole 22A. N ⁺
type semiconductor layer 19B through another contact hole 22B. and said
The N ⁺ type semiconductor layer 19c is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 2a, the area surrounded by broken lines with the symbol ABCD is 1 of this semiconductor memory device.
As is clear from FIG. 2b, this memory cell has a second conductive layer 15 with a floating gate.
The third conductor layer 18 is a control gate, the first conductor layer 14 is an erase gate, the N ⁺ type semiconductor layer 19A is a drain, and the N ⁺ type semiconductor layer 19C is an erase gate. source
It is composed of MOS transistors, and when looking at the 2 bits shown in Figure 2b, the control gate and erase gate are each common, and it is composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. . The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductor layers 21A and 21B, and 33 and 34 are the first conductor layers M.
Erasing lines formed by extending 14, 35, 36
is a selection line formed by extending the third conductor layers 18A and 18B. Also M1 to M4
is a memory cell, and each memory cell is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D and a source S. The drains D of the memory cells M1 and M2 are connected to one of the digit lines 31 and Cell M3,
The drain D of M4 is connected to the other digit line 32,
The sources S of all memory cells are respectively connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now paying attention to memory cell M1 in FIG. 3, in the initial state the floating gate of this memory cell M1 is
No electrons are injected into FG, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and the hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. Note that when writing data, a high voltage pulse of, for example, +20 volts may be applied to the erase line 33, a DC voltage of +5 volts or 0 volts may be applied, or it may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
A high level signal (for example, +5 volts) is applied to the control gate CG of No. 1. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on, and a current flows from one digit line 31 through the memory cell M1 toward the ground potential point. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows.
At this time, if the state in which current flows through the memory cell M1 is set to a logic "1" level, and the state in which no current flows is set to a logic "0" level, this device can be used as a memory device. Furthermore, as mentioned above, the floating gate FG is surrounded by an insulating film and is insulated from other parts, so the electrons once injected here are not released during normal use. It cannot escape and therefore can be used as a data non-volatile storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is leaked to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to the resistance state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP−
It is possible to realize a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and continuing data can be performed using a single polarity power supply. In other words, for example, you only need a positive polarity power supply of +20 volts for writing, +40 volts for erasing, and +5 volts for continuing data, and from +5 volts to +20 volts and +40 volts using a booster circuit.
If you get volts, you can use only one +5 volt power source. Therefore, it is possible to write data while mounted on a printed circuit board, etc.
Erasing and continuing are possible.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Next, an example of the manufacturing method for manufacturing the semiconductor memory device shown in FIG. 2 will be explained with pattern plan views shown in FIGS. Explain using. First, as shown in FIGS. 4a and 5a, an insulating film is grown to a thickness of 1 mm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography to form feed insulating films 13 and 13'. Further, P or As is diffused into the shaded area in FIG. 4a by implantation or diffusion to form an N-type semiconductor layer 19C'. After the above diffusion is completed, the surface of the substrate 11 in the area other than the area where the field insulating films 13 and 13' are formed is exposed, and then a relatively thin oxide film of 1000 Å to 2000 Å is formed thereon by thermal oxidation. The gate insulating film 1
form 2. Next, polysilicon with a thickness of 6000 Å is grown on the entire substrate 11, and P or
After doping with As, the fourth
A first conductor layer 14 is formed in the solid line area in FIG. b. Although an example is shown in which the first conductor layer 14 is not formed on the adjacent field insulating films 13', it may be formed if necessary. Next, after forming the first conductor layer,
As shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500 Å is grown by thermal oxidation,
Subsequently, a polysilicon film with a thickness of 5000 Å was grown by the CVD method, and this was applied to the photolithographic method to form the second conductor layers 15a, 15b, 15c, and 15d as floating gates. form. As is clear from the figure, FIG. 5c shows a conductor layer 15 which becomes a floating gate.
An example has been shown in which only one end of each of a and 15b extending on the field insulating film 13 at least partially overlaps with the first conductive layer 14 with the insulating film 16 interposed therebetween. The other ends of the conductive layers 15a and 15b do not overlap with the conductive layer 14.
After forming the floating gate, as shown in Fig. 4a and Fig. 5d, 1000~
An insulating film 17 with a thickness of 2000 Å is formed, polysilicon is deposited on it, and a photolithographic method is applied to this to form third conductor layers 18A and 18B that will become control gates. At the same time, second conductor layers 15a, 15b, 15c, and 15d are formed by self-alignment. Next, P or As is diffused into the shaded areas in FIG. 4e to form N ⁺ type semiconductor layers 19A, 19B, and 19C. Furthermore, as shown in FIG. 4e and FIG.
In addition to forming the conductor layers 21A and 21B, the contact portions 22A and 22B
This semiconductor memory device is completed by connecting each of the N ⁺ type semiconductor layers 19A and 19B.

6a to 6c show the configuration of a memory cell according to a second embodiment of the present invention, FIG. 6a is a pattern plan view, and FIG. 6b is a structure taken along the line -' in FIG. 6a. The sectional view, Fig. 6c, is at -' in Fig. 6a.
FIG. 3 is a cross-sectional view of the structure along the line.

In FIG. 6, 111 is a semiconductor substrate made of P-type silicon, and gate insulating films 112a to 112f are formed at regular intervals on the surface of this substrate 111.
They are arranged in an XY matrix. Further, on the surface of the substrate 111, gate insulating films 112a and 112d are formed at respective locations adjacent to each other in the vertical direction in the figure.
112b and 112e and 112c and 112f are paired, and field insulating films 113 and 113' are formed between the gate insulating film pairs. Further, a first conductive layer 114 made of polysilicon containing P or As is formed on the field insulating film 113 at one location. Further, on each of the gate insulating films 112a to 112f, second conductor layers 115a to 115a made of polysilicon are formed.
115f are formed separately from each other. The right end portions of the two second conductor layers 115b and 115e located on the left side with respect to the first conductor layer 114 in the figure are connected to the insulating film 1.
It overlaps with the left end portion of the first conductor layer 114 via the conductor layer 16 . In addition, the conductor layer 114
The left end portions of the two second conductor layers 115c and 115f located on the right side of the conductor layer 115 overlap the right end portion of the conductor layer 114 with the insulating film 116 interposed therebetween. . Furthermore, second conductor layers 115a and 11 adjacent in the left and right direction in the figure
5b, 115c are covered with conductor layers 115a, 115c via an insulating film 117.
A third conductive layer 118A made of polysilicon and having a width set to be approximately the same as that of 15b and 115c is formed, and similarly a second conductive layer 118A adjacent to the third conductive layer 118A in the left and right direction in the figure is formed. 115d, 115
The conductor layers 115d, 115f are formed on the conductor layers 115d, 115f via the insulating film 117 so as to cover them.
Another third conductor layer 118B made of polysilicon is formed and has approximately the same width as 115e and 115f. Furthermore, there are two gate insulating films 112 adjacent to each other in the vertical direction in the figure.
In the surface area of the substrate 111 between a and 112d,
An N ⁺ type semiconductor layer 119A is formed, and an N ⁺ type semiconductor layer 119B is formed in the surface region of the substrate 111 between the two gate insulating films 112b and 112e.
However, similarly, two gate insulating films 112c and 11
An N ⁺ type semiconductor layer 119c is formed in the surface region of the substrate 111 between the substrate 111 and the substrate 2e. Furthermore, the above N ⁺
A continuous N ⁺ type semiconductor layer 119D is formed in the surface region of the substrate 111 on the side opposite to the side where the type semiconductor layers 119A, 119B, and 119C are formed. Further, a wiring layer 1 made of Al is provided on the third conductive layer 118A, 118B with an insulating film 120 interposed therebetween.
21A, 121B, 121C, and 121D are formed, of which one wiring layer 121A and the above wiring layer 121A are formed.
Contact hole 1 is connected to N ⁺ type semiconductor layer 119A.
22A, and is connected to the wiring layer 121B by N ⁺
type semiconductor layer 119B is the contact hole 122.
B, and the wiring layer 121C and the first
The contact hole 12 is connected to the conductor layer 114 of the second layer.
2C, and is also connected to the wiring layer 121D.
The contact hole 1 is connected to the N ⁺ type semiconductor layer 119C.
22D. and said N ⁺
The type semiconductor layer 119D is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 6a, the area surrounded by broken lines with the symbol ABCD is 1 of this semiconductor memory device.
This memory cell has a second conductor layer 115 as a floating gate, a third conductor layer 118 as a control gate, and a first layer as a control gate. It is composed of a MOS transistor whose conductor layer 114 is an erase gate, whose drain is an N ⁺ type semiconductor layer 119B, and whose source is an N ⁺ type semiconductor layer 119D. As seen, the control gate and erase gate are common to each other, and are composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. The control gate is connected to the semiconductor substrate 111 via an insulating film.
The floating gate and erase gate are provided on the control gate and the substrate 11.
The structure is such that they are arranged in parallel within an insulating film sandwiched by 1. Furthermore, since the erase gate is formed on the field insulating film 113, the overlapping portion of each floating gate and erase gate exists within the field region. Furthermore, as shown in FIG. 6b, in the overlapping portion, the second conductive layer 11
5, that is, the floating gate is located above the first conductive layer 114, that is, the erase gate, and the distance between the substrate 111 and the conductive layer 114 is the same as the distance between the substrate 111 and the conductive layer 115. It's shorter than that. Further, as is clear from FIG. 6a, the first conductive layer 114 is provided only at one location for a 4-bit memory cell,
Each one of the conductor layers 114 is connected to the wiring layer 121C through one contact hole 122C.

The equivalent circuit diagram of the semiconductor memory device shown in FIG. 6 is the same as that shown in FIG. 3, and its operation is also the same, so a description thereof will be omitted.

Further, in addition to the effects of the semiconductor memory device of the embodiment described above, the following effects can also be obtained.

Erase gate (first conductor layer) 11
Since the wiring layer 121C made of Al is used to form the erase line instead of using the polysilicon that constitutes 4, the thickness of the insulating film between the erase line and the substrate is can be made relatively thick, so even if a high voltage is applied to the erase line, leakage will not occur.

Since one contact hole connecting the erase gate and the wiring layer 121C needs to be provided for every four bits of the memory cell, the number of contacts per one bit is 1/4, and high integration is possible.

Since hot electron injection is used when writing data and field emission is used when erasing data, a relatively thick insulating film can be used around the floating gate, resulting in good non-volatile characteristics, that is, data retention characteristics.

Next, an example of the manufacturing method for manufacturing the semiconductor memory device shown in FIG. 6 will be explained with pattern plan views shown in FIGS. Explain using. First, as shown in FIGS. 7a and 8a, field insulating films 113 and 113' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 111 made of P-type silicon by photolithography. Note that at this time, the field insulating films 113, 113'
A thin insulating film 123 is formed between them. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 111, and after doping it with P or As, the field insulation is formed in the above one place as shown by the solid line in FIG. Membrane 1
A first conductor layer 114 is formed on 13.
Although an example is shown in which the conductive layer 114 is not formed on the adjacent field insulating films 113', it may be formed as necessary. Next, after forming the first conductor layer 114, as shown in FIGS. 7c and 8c, 500%
The gate insulating films 112a to 112f and the insulating film 116 are formed by growing an oxide film with a thickness of 5000 Å, and then polysilicon is grown to a thickness of 5000 Å by CVD, and this is photolithographically etched. Second conductor layers 115a to 115f as floating gates are formed by applying the method. Here, as is clear from the figure, FIG.
An example has been shown in which only one end of the field insulating film 113 extending over the field insulating film 113 at least partially overlaps with the first conductive layer 114 with the insulating film 116 interposed therebetween. The other ends of the conductive layers 115b and 115c do not overlap with the conductive layer 114. After forming the floating gate, Figure 7d
and by thermal oxidation method as shown in Figure 8d.
Forming an insulating film 117 with a thickness of 1000 Å to 2000 Å,
Polysilicon is deposited thereon, and a photolithography method is applied thereto to form third conductor layers 118A and 118B that will serve as control gates.At the same time, second conductor layers 115a to 115A are formed. 115f is formed by self-alignment. Next, P or As is diffused into the shaded area in ^FIG .
B, 119C and an N ⁺ type semiconductor layer 119D which will serve as a source are respectively formed. Furthermore, as shown in FIGS. 7e and 8e, an insulating film 120 and an Al film are successively deposited over the entire substrate 111,
A wiring layer 121 is formed by applying a photoengraving method to this Al film.
A, 121B, 121C, and 121D are formed.
At this time, the contact holes 122A, 1
Open 22B, 122C, 122D and keep
Contact holes 122A, 122B, 122D
N ⁺ type semiconductor layers 119A and 11, respectively.
9B, 119C and wiring layers 121A, 121B, 1
21D are connected to the first conductive layer 114 and the wiring layer 121 through contact holes 122C.
This semiconductor memory device is completed by connecting C to C.

FIG. 9 shows an embodiment of the semiconductor memory device according to the present invention, in which an M×N bit semiconductor memory device is constructed using the semiconductor memory device shown in FIG. 2 or FIG. 6. . In the figure
M ₁₁ , ......M _1M , ......M _N1 , ......M _NM is
1-bit memory cells each arranged in a matrix of M cells in the column direction and N cells in the row direction;
Each of these memory cells is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S as described above. The drains D of each of the M memory cells arranged in the same column are connected to each of the N digit lines 4.
1 ₁ to 41 _N are commonly connected to each other. Further, the N digit lines 41 ₁ to 41 _N select one output terminal according to the column address when a column address is inputted and the data is read or written, and a high level signal, For example, output +5, +20 volts,
It is connected to the output of a column decoder 42 which outputs a low level signal, e.g. 0 volts, from all unselected outputs. Furthermore, the control gate CG of each N memory cells arranged in the same row is
It is commonly connected to each of the M row selection lines 43 ₁ to 43 _M. The above M row selection lines 43 ₁ ...
...43 _M selects one output terminal according to the row address when a row address is input and data is read or written, and outputs a high level signal only from this selected output terminal, and outputs a high level signal from all unselected output terminals. It is connected to the output end of the row decoder 44 which outputs a low level signal.

Furthermore, the erase gates EG of each of the M memory cells arranged in the same column are connected to each of the N erase lines 50 ₁ to 50 1 .
50 _N are commonly connected to each other. Each of the N erase lines ₅₀₁ to _50N is an enhancement type n-channel MOS transistor 71.
The gates of _{the MOS transistors 71 1 to 71 N are connected} to the output _terminal of the erase decoder 72. Further, the sources S of all memory cells are commonly connected, and this is connected to a ground potential point.

The voltage booster circuit 51 has a +20 volt voltage V _pp or +
One of the 5 volt voltages _Vcc is boosted only during the period when the data erase control signal E is at a high level, that is, during the data erase period, and the +40 volt data erase voltage is output. It's summery. Further, the erase decoder 72 selects one output terminal according to the erase column selection address only during the period when the erase column selection address is input and the data erase control signal E is at a high level. High level signal from output end only,
For example, it outputs +42 to +45 volts, and all unselected output terminals output low level signals, such as 0 volts.

In a storage device having such a configuration, when the data erase control signal E becomes high level during data erasing, the voltage _Vcc of +5 volts or the voltage _Vpp of +20 volts is boosted by the voltage booster circuit 51.
A data erase voltage of +40 volts is output from its boosted voltage output. On the other hand, while the signal E is at a high level, the erasure decoder 72 operates and outputs a high level signal from one output terminal thereof. Now, the erase decoder 72 is connected to the MOS transistor 71 ₁
If a high level signal is output from the output terminal connected to the gate of the MOS transistor 711, only this MOS transistor ₇₁₁ is turned on, and the data erase voltage of +40 volts is applied to only one erase line ₅₀₁ . Become. Therefore, at this time, the data in the M memory cells in the first column are erased at once. Furthermore, the output of the erase decoder 72 selects the column to be erased. Note that during data erasing, all digit lines 41 ₁ to 41 _N and all row selection lines 43 ₁ to 43 _M are at low level. Furthermore, instead of providing a voltage booster circuit, an erase terminal may be provided and a data erase voltage may be applied externally.

In this manner, in the above embodiment, by commonly connecting the erase gates EG in each column, it is possible to erase data in memory cells in each column. This is not possible with ultraviolet removal type products. Furthermore, since the erasure decoder 72 operates only when erasing data and does not operate during other periods, power consumption here is small.

FIG. 10 shows a second embodiment of the present invention, in which data is stored for each M memory cell arranged in the same column in an M×N bit semiconductor memory device, similar to the previous embodiment. It is made erasable. The difference in FIG. 10 from FIG. 9 is that the erase decoder 72 has N erase lines 5.
Instead of selecting 0 ₁ to 50 _N , column decoder 42
The selection is made using the output of .
That is, the digit lines 41 ₁ to 41 _N are connected to the output end of the column decoder 42 via enhancement type n-channel MOS transistors 73 ₁ to 73 _N , and these MOS transistors 73 ₁
An inverted signal of the data erase control signal E is applied in parallel to the gates of _.about.73N . Further, 46 is an erase terminal to which a data erase voltage of +40 volts is applied, and each of the N erase lines 50 ₁ to 50 _N is connected to the erase terminal 46 via each resistor 74 ₁ to 74 _N. Furthermore, each of N erasing lines 50 ₁₁ to 50 _N
and the ground potential point with an enhancement type n
Each MOS transistor 75 ₁ to 75 _N of the channel is inserted, and each of these MOS transistors 75 ₁ to 75 N
The output of each inverter 76 ₁ to 76 _N that inverts the output of the column decoder 42 is given to the gate of 75 _N.

In such a configuration, when data is not erased, for example, when reading or writing data,
When the signal becomes high level, MOS transistor 73
₁ to 73 _N are all turned on. Therefore, at this time, the output of the column decoder 42 is connected to the digit line 41 via each of the MOS transistors 73 ₁ to 73 _N.
1 to 41 _N respectively, and data can be read or written. On the other hand, when erasing data, the signal becomes low level and all MOS transistors 73 ₁ to 73 _N are turned off. Therefore, at this time, the output of the column decoder 42 is not applied to the digit lines 41 ₁ to 41 _N. Also, only the output of the inverter 76 connected to the selected output terminal of the column decoder 42 becomes low level. Therefore, assuming that the output of the inverter 76 ₁ is now at a low level, only the MOS transistor 75 ₁ connected to the erase line 50 ₁ is off, and the other MOS transistors 75 ₂ to 75 _N
are all turned on. Therefore, at this time, if a data erase voltage of +40 volts is applied to the erase terminal 46, this data erase voltage is applied to only one erase line ₅₀₁ via the resistor ₇₄₁ . Also, at this time, erase lines 50 ₂ to 50 _N other than erase line 50 ₁
is set to the ground potential by each MOS transistor 75 ₂ to 75 _N , but since each resistor 74 ₂ to 74 _N is inserted between the erase terminal 46 and each erase line 50 ₂ to 50 _N , , the erase terminal 46 never drops to ground potential. Therefore, the data in the M memory cells in the first column are erased at once. Further, the column in which data is to be erased is selected by the output of the column decoder 42.

FIG. 11 shows a third embodiment of the present invention. Similar to the embodiment shown in FIG. 9 or FIG. 10, in an M×N bit semiconductor memory device,
Data can be erased for each of M memory cells arranged in the same column. The difference in FIG. 11 from FIG. 10 is that the erase line 50 is selected by each of the MOS transistors 75 ₁ to 75 _N inserted between each of the erase lines 50 ₁ to 50 _N and the ground potential point. Instead, each enhancement type n-channel MOS transistor 77 ₁ is connected between the erase terminal 46 and each erase line 50 ₁ to 50 _N.
~77 _N and these MOS transistors 7
The erase line 50 is selected from 7 ₁ to 77 _N. A column decoder 42 is connected to the gate of each of the MOS transistors 77 ₁ to 77 _N.
The boosted voltage output terminals of each of the voltage boosting circuits 78 ₁ to 78 _N that boost the high level output of each output terminal of , for example, to +45 volts are connected.

In such a configuration, when writing and reading data _, the MOS transistors 73 ₁ to 73 _N are all turned on, as in the embodiment circuit shown in FIG _. data can be read or written. On the other hand, when erasing data, the MOS transistor 73 _1
.about.73N are all turned off, and the output of column decoder 42 is not applied to digit lines _41.sub.1 to _41.sub.N.
At this time, only the output of the voltage booster circuit 78 connected to the selected output terminal of the column decoder 42 becomes +45 volts. Therefore, assuming that the output of the voltage booster circuit 78 ₁ is now +45 volts, only the MOS transistor 77 ₁ connected to the erase line 50 ₁ is turned on, and all other MOS transistors 77 ₂ to 77 _N are turned off. Become. Therefore, at this time, if a data erase voltage of +40 volts is applied to the erase terminal 46, this data erase voltage is applied to only one erase line ₅₀₁ via the MOS transistor ₇₇₁ which is turned on. Therefore, the data of M memory cells in the first column are erased at once.

FIG. 12 shows an example of a specific configuration of the voltage booster circuit 78 used in FIG. 11 above. This circuit is an enhancement type booster circuit that utilizes a bootstrap constructed of n-channel MOS transistors and capacitors, and provides an output of, for example, +45 volts.

Note that the present invention is not limited to the above-mentioned embodiments; for example, in FIG. 2 or FIG. eye conductor layer 14,
Although the case where the conductor layers 15 and 11 overlap with at least a part of the conductor layers 114 has been described,
The structure may be such that both ends of the conductor layer 5 overlap the conductor layers 14 and 114.

As explained above, the semiconductor memory device of the present invention can simultaneously erase data column by column.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, and FIGS. 2 a to 2 d show the configuration of a first embodiment of a memory cell used in a semiconductor memory device according to the present invention. Fig. 2a is a pattern plan view, Fig. 2b is a cross-sectional view of the structure taken along line -' in Fig. 2a, and Fig. 2c is a -' line in Fig. 2a.
A cross-sectional view of the structure along the line, Figure 2 d is - in Figure 2 a.
3 is an equivalent circuit diagram of the device shown in FIG. 2, and FIGS. This figure is for explaining an example of the method, and FIGS. 4a to 4e are pattern plan views, and
Figures a to e are cross-sectional views taken along lines -' in Figures 4 a to e, and Figures 6 a to c are cross-sectional views of the second memory cell used in the semiconductor memory device according to the present invention.
Fig. 6a is a pattern plan view, Fig. 6b is a cross-sectional view of the structure taken along the -' line in Fig. 6a, and Fig. 6c is a structural cross-sectional view taken along the -' line in Fig. 6a. 7a-e and 8
Figures a to e are for explaining an example of a manufacturing method for manufacturing the device shown in Figure 6, respectively; Figures 7a to e are pattern plan views, and Figures 8a to 8e are pattern plan views. Each of figures a to e -'
9 is a block diagram of the first embodiment of the present invention, FIG. 10 is a block diagram of the second embodiment of the present invention, and FIG. 11 is a block diagram of the third embodiment of the present invention. An example configuration diagram, FIG. 12, is a specific diagram of a part of the third embodiment. 11,111...Semiconductor substrate, 12,112...
...Gate insulating film, 13,113...Field insulating film, 14,114...First conductor layer (erase gate), 15,115...Second conductor layer (floating gate) , 16, 11
6,17,117,20,120,123...Insulating film, 18,118...Third conductor layer (control gate), 19,119...N ⁺ type semiconductor layer, 21...Fourth layer Conductor layer of layer 121...
Wiring layer, 22, 122...Contact hole, 3
1, 32...digit line, 33, 34...erasure line, 35, 36...selection line, M1, M2, M3,
M4...memory cell, CG...control gate, FG...floating gate, EG...erase gate, D...drain, S...source, _M11 ~
M _1M ~M _N1 ~M _NM ...Memory cell, 41...Digit line, 42...Column decoder, 43...Row selection line, 44...Row decoder, 45, 47, 48...
Resistor, 46... Erasing terminal, 50... Erasing line, 5
1, 78... Voltage booster circuit, 72... Erase decoder, 74... Resistor, 76... Inverter.

Claims (1)

[Claims] 1. A 1-bit memory cell has a control gate provided on a semiconductor substrate via an insulating film, an erase gate provided in the insulating film sandwiched between the control gate and the substrate, and the above-mentioned memory cell in the insulating film. It consists of a floating gate, a source, and a drain, which are arranged in parallel with the erase gate and whose ends overlap at least a portion of the erase gate via an insulating film, and a plurality of memory cells are arranged in a matrix in the row and column directions. a memory matrix in which the erase gates of a plurality of memory cells arranged in the same column are connected in common, and each memory cell in one column is provided for each memory cell in each column and selected at the time of column selection. 1. A semiconductor memory device comprising means for applying a data erase voltage to an erase gate of the semiconductor memory device.