JPS6331112B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32k bits and 64k bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
(referred to as ROM), one memory cell is divided into at least two
Because it consists of one transistor, it is not possible to increase the degree of integration very high, and so far only 16k bits of integration have been announced. However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure 1
is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point, there is a MOS transistor 4 for bit selection, a control gate and a floating gate for data storage. A double gate type MOS transistor 5 is connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2.
The control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

This invention was made in consideration of the above circumstances, and its purpose is to eliminate the above-mentioned drawbacks of the conventional technology, and to efficiently discharge charges from the floating gate especially when erasing data. An object of the present invention is to provide a method for manufacturing a semiconductor memory device that can manufacture a semiconductor memory device that can be manufactured with high performance.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a and 2b show the structure of a first embodiment of the present invention, in which four bits of memory cells are shown. Of these, Fig. 2a is a pattern plan view, Fig. 2b is a structural sectional view taken along line -' in Fig. 2a, and Fig. 2c is a structural sectional view taken along -' line in Fig. 2a. d is a structural cross-sectional view taken along the line -' in a of the same figure. In FIG. 2, 11 is a semiconductor substrate made of P-type silicon, and this substrate 1
1, gate insulating films 12a, 12b, 12
c and 12d are arranged in an XY matrix at regular intervals. Further, on the surface of the substrate 11, two pairs of gate insulating films 12a and 12c, and 12b and 12d, which are adjacent to each other in the vertical direction in the figure, are formed.
A field insulating film 13 is formed between the pair of gate insulating films. Further, on this field insulating film 13, a first conductor layer 14 made of polysilicon containing P or As is formed. Furthermore, each of the gate insulating films 12a, 12
On b, 12c, 12d, second conductor layers 15a, 15b, 15c, made of polysilicon are formed.
15d are formed separately from each other. The right end portions of the two second conductor layers 15a and 15c, which are located on the left side of the first conductor layer 14 in the figure, are connected to the It overlaps with the left end of the first conductive layer 14. In addition, there are two second conductor layers 15 located on the right side of the conductor layer 14.
The left end portions of b and 15d overlap the right end portion of the conductive layer 14 with the insulating film 16 interposed therebetween. Furthermore, an insulating film 17 is provided on the second conductor layers 15a and 15b adjacent to each other in the left and right direction in the figure, so that both conductor layers 15
A third conductor layer 18A made of polysilicon having a width set to be approximately the same as that of a and 15b is formed, and a second conductor layer 18A adjacent to the third conductor layer in the left and right direction in the figure is formed. On 15c and 15d, another third layer of conductive material made of polysilicon is placed, with the insulating film 17 interposed therebetween, so as to cover the conductive layers 15c and 15d. Layer 18B is formed. Also, two gate insulating films 12 adjacent to each other in the vertical direction in the figure
In the surface area of the substrate 11 between a and 12c,
An N ⁺ type semiconductor layer 19A is formed, and similarly, an N ⁺ type semiconductor layer 19B is formed in the surface region of the substrate 11 between the two gate insulating films 12b and 12d. Furthermore, each gate insulating film 12a,
12b, 12c, and 12d, a continuous N ⁺ type semiconductor layer 19C is formed in the surface region of the substrate 11 on the side opposite to the side where the N ⁺ semiconductor layer 19A or 19B is formed. Further, on the third semiconductor layers 18A and 18B, fourth conductor layers 21A and 21 made of Al are placed with an insulating film 20 interposed therebetween.
One of the conductor layers 21A and the N ⁺ type semiconductor layer 19A are connected by a contact hole 22A, and the other conductor layer 21B and the N ⁺ type semiconductor layer 19B are connected to each other by a contact hole 22A. is another one
They are connected through two contact holes 22B. The N ⁺ type semiconductor layer 19C is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 2a, the area surrounded by a broken line with the symbol ABCD is 1 of this semiconductor memory device.
As is clear from FIG. 2b, this memory cell has a second conductive layer 15 with a floating gate.
It is composed of a MOS transistor in which the third conductor layer 18 is a control gate and the first conductor layer 14 is an erase gate, and further includes a 2-bit transistor as shown in FIG. 2b. In terms of details, the control gate and the erase gate are common, and are composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductor layers 21A and 21B, and 33 and 34 are the first conductor layers 1.
4 is an erase line formed by being extended, and 35 and 36 are selection lines formed by extending the third conductor layers 18A and 18B. Further, M1 to M4 are memory cells, and each memory cell is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S, and the drain D of the memory cells M1 and M2 is connected to one of the digit lines. 31, memory cells M3, M
The drain D of memory cell 4 is connected to the other digit line 32, and the sources S of all memory cells are connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. now,
Paying attention to the memory cell M1 in FIG. 3, in the initial state, no electrons are injected into the floating gate FG of the memory cell M1, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and the hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. When writing data, the erase line 33 may be applied with a pulse of a high voltage, for example, +20 volts, or may be applied with a DC voltage of +5 volts or 0 volts, or may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
A high level signal (+
5 volts) is applied. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on and one digit line 31 is turned on.
A current flows from the memory cell M1 toward the ground potential point. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time, the state in which current flows through the memory cell M1 is a logic "1" level, and the state in which no current flows is a logic "0" level.
level, this device can be used as a storage device. Also floating gate
As mentioned above, the FG is surrounded by an insulating film and insulated from other parts, so once the electrons are injected here, they cannot escape during normal use. Therefore, it can be used as a non-volatile data storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is discharged to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to a low state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP−
It is possible to realize a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. That is, +20 volts when writing and +20 volts when erasing.
When reading 40 volts, you only need a +5 volt positive power supply, and if you use a booster circuit to obtain +20 volts and +40 volts from the +5 volt voltage, you can use only one +5 volt power supply. can. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device of the first embodiment shown in FIG. 2 is shown in FIG.
This will be explained using the pattern plan views shown in FIGS. First, Figure 4a and Figure 5a
As shown in FIG. 1, field insulating films 13 and 13' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography.
Furthermore, P or As is diffused into the shaded area in FIG. 4a by an implantation method or a diffusion method to form an N ⁺ type semiconductor layer 19c'. After the completion of the above diffusion, the above field insulating film 1
After exposing the surface of the substrate 11 in areas other than the forming areas 3 and 13', a thermal oxidation film having a relatively thin film thickness of 1000 to 2000 Å is applied thereto by thermal oxidation to form the gate insulating film 12. A film 23 is formed. Next, polysilicon with a thickness of 6000 Å is grown on the entire substrate 11, and after doping it with P or As, a first conductive layer is formed in the solid line area in FIG. 4b by photolithography. form 14. Although an example is shown in which the first conductor layer 14 is not formed on the adjacent field insulating films 13', it may be formed if necessary. Next, after forming the first conductor layer, as shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500 Å is grown by thermal oxidation, and then A polysilicon film with a thickness of 500 Å was grown using the CVD method, and a second conductor layer 15a as a floating gate was formed using a photolithography method.
15b, 15c, and 15d are formed. Here the fifth
As is clear from the figure, in FIG. An example is shown in which at least a portion thereof overlaps with the conductor layer 14. Regarding the other ends of the conductor layers 15a and 15b, the conductor layer 1
It does not overlap with 4. After forming the floating gate, as shown in FIGS. 4d and 5d, an insulating film 17 with a thickness of 1000 to 2000 Å is formed by thermal oxidation.
polysilicon is deposited thereon, and a photolithography method is applied thereto to form third conductor layers 18A and 18B that will become control gates, and at the same time, a second conductor layer is formed. 15a, 15b, 1
5c and 15d are formed by self-alignment.
Next, P or
By diffusing As, N ⁺ type semiconductor layers 19A, 19B, 1
Forms 9C. Furthermore, Figures 4e and 5e
As shown in FIG.
A fourth conductor layer 21A, 21B is formed by continuously depositing an Al film and applying a photolithography method to this Al film.
At the same time, contact holes 22A, 2 are formed.
2B, the above N ⁺ type semiconductor layers 19A, 19B
A semiconductor memory device is completed by connecting each.

6a and 6b show the structure of a second embodiment of the present invention, FIG. 6a is a pattern plan view, FIG. 6b is a structural sectional view taken along the line -' of FIG. 6a, FIG. 6c is a structural sectional view taken along the line -' in FIG. 6a.

In FIG. 6, 111 is a semiconductor substrate made of P-type silicon, and gate insulating films 112a to 112f are formed at regular intervals on the surface of this substrate 111.
They are arranged in an XY matrix. Further, on the surface of the substrate 111, gate insulating films 112a and 112d are formed at respective locations adjacent to each other in the vertical direction in the figure.
112b and 112e and 112c and 112f are paired, and field insulating films 113 and 113' are formed between the gate insulating film pairs. Further, a first conductive layer 114 made of polysilicon containing P or As is formed on the field insulating film 113 at one location. Further, on each of the gate insulating films 112a to 112f, second conductor layers 115a to 115a made of polysilicon are formed.
115f are formed separately from each other. The right end portions of the two second conductor layers 115b and 115e located on the left side with respect to the first conductor layer 114 in the figure are connected to the insulating film 1.
It overlaps with the left end portion of the first conductor layer 114 via the conductor layer 16 . In addition, the conductor layer 114
The left end portions of the two second conductor layers 115c and 115f located on the right side of the conductor layer 115 overlap the right end portion of the conductor layer 114 with the insulating film 116 interposed therebetween. . Furthermore, second conductor layers 115a and 11 adjacent to each other in the left direction in the figure
5b, 115c, each of these conductive layers 115a, 1
A third conductive layer 118A made of polysilicon and having a width set to be approximately the same as that of 15b and 115c is formed, and similarly a second conductive layer 118A adjacent to the third conductive layer 118A in the left and right direction in the figure is formed. 115d, 115
The conductor layers 115d, 115f are formed on the conductor layers 115d, 115f via the insulating film 117 so as to cover them.
Another third conductor layer 118B made of polysilicon is formed and has approximately the same width as 115e and 115f. Furthermore, there are two gate insulating films 112 adjacent to each other in the vertical direction in the figure.
In the surface area of the substrate 111 between a and 112d,
An N ⁺ type semiconductor layer 119A is formed, and an N ⁺ type semiconductor layer 119B is formed in the surface region of the substrate 111 between the two gate insulating films 112b and 112e.
Similarly, there are two gate insulating films 112c and 112e.
An N ⁺ type semiconductor layer 119C is formed in the surface region of the substrate 111 between the substrate 111 and the substrate 111. Furthermore, for each ^gate insulating film 112a to 112e, a continuous
An N ⁺ type semiconductor layer 119D is formed. Further, a wiring layer 1 made of Al is placed on the third conductive layer 118A, 118B with an insulating film 120 interposed therebetween.
21A, 121B, 121C, and 121D are formed, among which one wiring layer 121A and the above wiring layer 121A are formed.
Contact hole 1 is connected to N ⁺ type semiconductor layer 119A.
22A, and is connected to the wiring layer 121B.
Contact hole 1 is connected to N ⁺ type semiconductor layer 119B.
22B, the wiring layer 121C and the first conductor layer 114 are connected through the contact hole 122C, and the wiring layer 121D
and the N ⁺ type semiconductor layer 119C are connected through a contact hole 122D. and said
The N ⁺ type semiconductor layer 119D is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 6a, the area surrounded by a broken line with the symbol ABCD is 1 of this semiconductor memory device.
This memory cell has a second conductor layer 115 as a floating gate, a third conductor layer 118 as a control gate, and a first layer as a control gate. An erase gate (erase gate) for the conductive layer 114 of the eye;
It is composed of a MOS transistor with the N ⁺ type semiconductor layer 119B as the drain and the N ⁺ type semiconductor layer 119D as the source, and when looking at the 2 bits shown in FIG. 6b, the control gate and erase gate are common. , consists of a pair of MOS transistors configured symmetrically with respect to the erase gate. The control gate is provided on the semiconductor substrate 111 via an insulating film, and the floating gate and erase gate are arranged in parallel within the insulating film sandwiched between the control gate and the substrate 111. There is. Furthermore, since the erase gate is formed on the field insulating film 113, the overlapping portion of each floating gate and erase gate exists within the field region.
Further, as shown in FIG. 6b, in the overlapping portion, the second conductor layer 115, ie, the floating gate, is located above the first conductor layer 114, ie, the erase gate. , the distance between the substrate 111 and the conductor layer 114 is shorter than the distance between the substrate 111 and the conductor layer 115. Further, as is clear from FIG. 6a, the first conductor layer 114 is provided at only one location for a 4-bit memory cell, and each conductor layer 114 at each location is provided at one contact point. It is connected to the wiring layer 121C through a hole 122C.

The equivalent circuit diagram of the semiconductor memory device shown in FIG. 6 is the same as that shown in FIG. 3, and its operation is also the same, so a description thereof will be omitted.

Furthermore, in addition to the effects of the above-mentioned embodiment apparatus, the following effects can also be obtained with the above-mentioned embodiment apparatus.

Erase gate (first conductor layer 14)
Since the wiring is formed using the wiring layer 21C made of Al instead of wiring using polysilicon that constitutes the substrate, the thickness of the insulating film between the erasing line and the substrate can be reduced. It can be made relatively thick, so even if a high voltage is applied to the erase line, leakage will not occur.

One contact hole connects the erase gate and the wiring layer 21C for every four bits of the memory cell.
Since the number of contacts per bit is 1/4, it is possible to provide a high degree of integration.

Since hot electron injection is used when writing data and field emission is used when erasing data, a relatively thick insulating film can be used around the floating gate, resulting in good non-volatile characteristics, that is, data retention characteristics.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device of the second embodiment shown in FIG. 6 is shown in FIG.
This will be explained using pattern plan views shown in FIGS. 8a to 8e and sectional views taken along the line -' shown in FIGS. First, Figure 7a and Figure 8a
As shown in FIG. 2, field insulating films 113 and 113' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 111 made of P-type silicon by photolithography. Note that at this time, the field insulating film 11
A thin insulating film 123 is formed between 3 and 113'. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 111, and after doping it with P or As, the field insulation is formed in the above one place as shown by the solid line in FIG. A first conductor layer 114 is formed on the film 113. Here, adjacent field insulating films 11
Although an example is shown in which the conductor layer 114 is not formed on the conductor layer 3', it may be formed if necessary. Next, after forming the first conductor layer 114,
As shown in FIGS. 7c and 8c, an oxide film with a thickness of 500 Å is grown by a thermal oxidation method to form the gate insulating films 112a to 112f and the insulating film 1.
16 is formed, and then polysilicon is grown to a thickness of 5000 Å using the CVD method, and then a second conductor layer 115a to 115f is formed as a floating gate by applying a photolithography method. form. As is clear from the figure, FIG. 8c shows a conductor layer 11 which becomes a floating gate.
An example has been shown in which only one end of each of the field insulating films 113 extending over the field insulating film 113 at least partially overlaps with the first conductive layer 114 with the insulating film 116 interposed therebetween. and conductor layer 115b,
The other end of 115c does not overlap with conductor layer 114. After forming the floating gate, an insulating film 11 with a thickness of 1000 Å to 2000 Å is formed by thermal oxidation as shown in FIGS.
7 is formed, polysilicon is deposited thereon, and a photolithography method is applied to this to form a third conductor layer 118A, 118B which becomes a control gate.
At the same time as forming the second conductor layer 115a
~115f is formed by self-alignment. Next, P or
N ⁺ type semiconductor layer 11 that diffuses As and becomes a drain
9A, 119B, 119C and source
N ⁺ type semiconductor layers 119D are each formed. Further, as shown in FIGS. 7e and 8e, an insulating film 120 and an Al film are successively deposited over the entire substrate 111, and a photolithography method is applied to this Al film to form wiring layers 121A and 121B. , 121C, 121D
form. At this time, contact holes 122A, 122B, 122C, 122D are opened in advance, and contact holes 122A, 122
N ⁺ type semiconductor layer 1 by B and 122D, respectively.
19A, 119B, 119C and wiring layer 121A,
This semiconductor memory device is completed by connecting the first conductor layer 114 and the wiring layer 121C through contact holes 122C.

FIG. 9 is a pattern plan view showing the configuration of a third embodiment of the present invention. The difference between this embodiment device and the first embodiment device shown in FIG. 2 is as follows.
On the field insulating film 13, the first conductor layer 14 and the third conductor layer 18A or 1
Insulating films 24a and 24b are respectively formed between the conductive layer 14 and the conductive layer 18A or 18B.
The thickness of the insulating film interposed between conductor layer 1 and
The thickness of the insulating film 16 is sufficiently thicker than that of the insulating film 16 interposed between the conductor layer 15 and the conductive layer 15. For example, the thickness of the insulating film 16 is
If the thickness is 500 to 1000 Å, the thickness of the insulating film interposed between the conductive layer 14 and the conductive layer 18A or 18B is set to 2000 to 3000 Å or more.

As described above, in this embodiment device, the erase gate (the first conductive layer 14) and the control gate (the third conductive layer 18) are insulated and separated by the thick insulating film. Therefore, when erasing data, that is, when applying a high voltage to the erase gate and ejecting electrons from the floating gate (second conductive layer 15) by field emission, the floating gate electrons can be efficiently discharged from the Furthermore, since no current flows between the floating gate and the control gate, the current capacity for the high voltage, for example +40 volts, required to erase data is small. Therefore, this high voltage can be generated from a power supply of, for example, +5 volts using a voltage booster circuit built into the same chip, and the voltage of, for example, +20 volts used during data writing can also be generated using a voltage booster circuit. If you make it,
Operation is possible with a single power supply. Furthermore, the capacitance C _CE between the conductor layer 14 and the conductor layer 18
can be made extremely small.

The pattern plan views shown in FIGS. 10a to 10e and the cross-sectional views taken along the line -' shown in FIGS. Since most of the manufacturing steps are the same as those of the first embodiment shown in FIG. 2, only the different steps will be extracted and explained. After the formation of the first conductor layer 14, FIGS. 10c and 11c
As shown in FIG.
Form 5b, 15c, 15d, and then
An oxide film of 2000 Å to 3000 Å is formed on the entire surface by CVD method. Then, by photoengraving, the conductive layers 15a and 15b are formed on the field insulating film 13 and the conductive layers 15a and 15b.
and the vicinity of the position where are facing and adjacent to each other and the conductor layer 1
The above is applied only to the vicinity of the position where 5c and 15d are opposite and adjacent, that is, the shaded area in Fig. 10c.
Insulating films 24a and 24b are formed, leaving the oxide film formed by the CVD method. Since the subsequent steps are the same as those in the previous embodiment, the explanation will be omitted.

As described above, according to this manufacturing method, a semiconductor memory device capable of electrically erasing data with high performance can be manufactured by simply adding the step of forming the insulating films 24a and 24b by the CVD method.

FIG. 12 is a pattern plan view showing the configuration of a fourth embodiment of the present invention. This embodiment device is different from the second embodiment device shown in FIG.
Insulating films 124a, 12 between A or 118B
4b, and the thickness of the insulating film interposed between the conductive layer 14 and the conductive layer 118A or 118B is the same as that of the insulating film 116 interposed between the conductive layer 114 and the conductive layer 115. It is made to be sufficiently thicker than the . And for example,
If the thickness of the insulating film 116 is 500 to 1000 Å,
The conductor layer 114 and the conductor layer 118A or 1
The thickness of the insulating film interposed between 18B and 18B is 2000~
It is set to 3000Å or more. Also in this embodiment, like the third embodiment, operation is possible with a single power source that can efficiently discharge electrons from the floating gate. Effects such as capacitance C _CE can be made extremely small can be obtained.

The pattern plan views shown in FIGS. 13a to 13e and the sectional views taken along the line -' shown in FIGS. Since most of the manufacturing steps are the same as those of the second embodiment shown in FIG. 6, only the different steps will be extracted and explained. After forming the first conductive layer 114,
As shown in FIG.
A to 115f are formed, and then an oxide film of 2000 to 3000 Å is formed over the entire surface by CVD.
Next, by photoengraving, the conductor layer 115 is etched near the position on the field insulating film 113 where the conductor layers 115b and 115c are opposite to each other and the conductor layer 115.
The above is applied only to the vicinity of the position where e and 115f are opposite and adjacent, that is, the area marked with diagonal lines in Fig. 13c.
Insulating films 124a and 124b are formed, leaving the oxide film formed by the CVD method. Since the subsequent steps are the same as those in the previous embodiment, the explanation will be omitted.

In this manner, even with the above manufacturing method, a semiconductor memory device capable of electrically erasing data with high performance can be manufactured by simply adding the step of forming the insulating films 124a and 124b by the CVD method.

Note that the present invention is not limited to the embodiments described above; for example, in each of the embodiment devices shown in FIGS. 2, 6, 9, and 12, the second conductor layer 15 or 115 Although the case has been described in which only the right end portion or the left end portion of each of
Both ends of the conductor layer 115 may overlap the conductor layers 14, 114.

As explained above, according to the present invention, a method for manufacturing a semiconductor memory device can eliminate the drawbacks of the conventional method and can also manufacture a semiconductor memory device that can efficiently discharge charge from a floating gate especially when erasing data. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, and FIGS. 2 a to 2 d show the configuration of a first embodiment of the present invention.
is a pattern plan view, and Fig. 2b is -' in Fig. 2a.
A cross-sectional view of the structure along the line, Fig. 2c is - of Fig. 2a.
Figure 2d is a structural cross-sectional view taken along line -' in Figure 2a, Figure 3 is an equivalent circuit diagram of the device shown in Figure 2, Figures 4 a to e and Figure 5. Figures a to e are for explaining an example of the manufacturing method for manufacturing the embodiment device shown in Figure 2 above, Figures 4 a to e are pattern plan views, and Figures 5 a to e are 4a to 4e are cross-sectional views taken along lines -', and FIGS. 6a to 6c show the configuration of a second embodiment of the present invention,
Fig. 6a is a pattern plan view, Fig. 6b is a cross-sectional view of the structure taken along the -' line in Fig. 6a, and Fig. 6c is a pattern plan view in Fig. 6a.
The structural cross-sectional views taken along the line -' of FIGS. Figures 7a to 7e are pattern plan views, and Figures 8a to 8e are pattern plans.
FIG. 9 is a pattern plan view showing the structure of the third embodiment of the present invention, and FIGS. 10A to 10E are pattern plan views, and FIGS. 11A to 11E are along the lines -' of FIGS. 12 is a pattern plan view showing the configuration of the fourth embodiment of the present invention, and FIGS. 13a to 13e and 14a to 14e are diagrams for manufacturing the apparatus shown in FIG. 12, respectively. 13A to 13E are pattern plan views, and FIGS. 14A to 14E are cross-sectional views taken along the lines -' of FIGS. 13A to 13E. 11,111...Semiconductor substrate, 12,112...
...Gate insulating film, 13,113...Field insulating film, 14,114...First conductor layer (erase gate), 15,115...Second conductor layer (floating gate) ,16,116,
17,117,20,120,123,24,1
24...Insulating film, 18,118...Third conductor layer (control gate), 19,119...
... N ⁺ type semiconductor layer, 21 ... fourth conductor layer,
121... Wiring layer, 22, 122... Contact hole, 31, 32... Digit line, 33, 3
4... Erasing line, 35, 36... Selection line, M1, M
2, M3, M4...memory cell, CG...control gate, FG...floating gate, EG...erase gate, D...drain, S...source .

Claims (1)

[Claims] 1. Selectively forming a thick first insulating film on a predetermined region on a semiconductor substrate by photolithography, and forming a first conductive film made of polysilicon on the first insulating film by photolithography. a step of selectively forming a body layer; a step of forming a thin second insulating film by thermal oxidation on the substrate other than the first insulating film formation region; selectively forming a second conductive layer made of polysilicon on the second insulating film by photolithography so as to overlap at least a portion of the first conductive layer through the first conductive layer; After depositing a fourth insulating film on the body layer by CVD and oxidizing the entire surface of the base by thermal oxidation to form an insulating film on the surface, depositing the second insulating film on the surface.
forming a third conductive layer made of polysilicon so as to cover the conductive layer; the first conductive layer forms an erase gate; the second conductive layer forms a floating gate; A control gate is formed by each conductive layer, and the thickness of an insulating film interposed between the first conductive layer and the third conductive layer on the first insulating film is determined by the third insulating layer. A method for manufacturing a semiconductor memory device, characterized in that the thickness is set to be thicker than the film thickness.