JP5606682B2 - Thin film transistor, method for manufacturing polycrystalline oxide semiconductor thin film, and method for manufacturing thin film transistor - Google Patents

Description

  The present invention relates to a thin film transistor, a method for manufacturing a polycrystalline oxide semiconductor thin film, and a method for manufacturing a thin film transistor.

  In recent years, a transparent thin film transistor (which may be referred to as a TFT in the following description) used for an image display device has been actively developed. In particular, the In—Ga—Zn—O system (which may be referred to as IGZO in the following description) has been actively developed due to its wide optical band gap, and activates amorphous IGZO. There are many documents regarding TFTs used as layers (see, for example, Patent Document 1).

  Here, one reason why amorphous IGZO is used in the TFT is that it is amorphous, so that an active layer with a flat surface can be produced, and TFT characteristics due to carrier trapping caused by irregularities on the surface of the active layer. It is possible to avoid a decrease in quality and a variation in quality.

On the other hand, a crystalline semiconductor is generally more effective than an amorphous semiconductor in order to increase carrier mobility, which is one of TFT characteristics. Even in the case of IGZO, which is a kind of semiconductor, since the composition ratio is different, it cannot be generally compared, but the carrier mobility in a TFT using an amorphous InGaZnO ₄ thin film as an active layer is 6-9 cm ² V ⁻¹ S. ⁻¹ (on / off ratio 10 ³ ), whereas the carrier mobility in a TFT using a thin film made of single-crystal InGaO ₃ (ZnO) ₅ as an active layer is 80 cm ² V ⁻¹ S ⁻¹ ( Since the on / off ratio is about 10 ⁶ ), it is presumed that crystalline IGZO has higher carrier mobility than amorphous. Therefore, it is considered that it is more effective to use crystalline IGZO in the TFT in order to increase carrier mobility (for example, see Non-Patent Documents 1 and 2).

JP 2008-53356 A JP 2007-73701 A JP 2003-41362 A Nature, Vol. 432 (2004) 488 pages Science, Vol. 300 (2003) 1269

  However, when a thin film made of crystalline, particularly polycrystalline IGZO is used as the active layer, as shown in Patent Document 2, the surface of the active layer is compared with a case where a thin film made of amorphous IGZO is used as the active layer. However, there is a problem that TFT characteristics are deteriorated and quality is varied due to carrier traps caused by irregularities on the surface of the active layer.

Patent Document 3 discloses a thin film made of polycrystalline In ₂ O ₃ (ZnO) ₂₀ that has been heat-treated at 800 ° C., but does not disclose the surface properties thereof.

  The present invention relates to a thin film transistor in which a thin film made of an oxide semiconductor containing at least one element of the group consisting of In, Ga, and Zn can have high TFT characteristics, a method for manufacturing a polycrystalline oxide semiconductor thin film, Another object is to provide a method for manufacturing a thin film transistor.

<1> A surface roughness Ra value of 1.5 nm or less, comprising an active layer made of a polycrystalline oxide semiconductor containing elements of In, Ga, and Zn, wherein the polycrystalline oxide semiconductor has a crystallinity of 70 Ri transparent oxide der percent or more in-Ga-Zn-O-based, elemental composition ratio of in, Ga, and Zn (in: Ga: Zn) 1: 1: characterized that you containing in 1 Thin film transistor.
<2 > A temperature region in which an amorphous oxide semiconductor thin film containing elements of In, Ga, and Zn is polycrystallized while maintaining its surface roughness Ra value of 1.5 nm or less. A polycrystalline oxide semiconductor comprising a polycrystalline oxide semiconductor thin film that is an In—Ga—Zn—O-based transparent oxide having a degree of crystallinity of 70% or more, including a baking step described below. Thin film manufacturing method.
< 3 > The polycrystalline oxide according to < 2 >, wherein the polycrystallized thin film contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1. Method for manufacturing a semiconductor thin film.
< 4 > The method for producing a polycrystalline oxide semiconductor thin film according to < 2 > or < 3 >, wherein the baking is performed in an oxygen atmosphere.
< 5 > Temperature range of polycrystallizing a layer made of an amorphous oxide semiconductor containing elements of In, Ga and Zn while maintaining the surface roughness Ra value of 1.5 nm or less 660 ° C. or more and 840 ° C. The method includes forming an active layer made of a polycrystalline oxide semiconductor, which is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more, including a step of firing to form an active layer. A method for manufacturing a thin film transistor.
< 6 > The method for producing a thin film transistor according to < 5 >, wherein the active layer contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1.
< 7 > The method for producing a thin film transistor according to < 5 > or < 6 >, wherein the baking is performed in an atmosphere containing oxygen.

  According to the present invention, a thin film transistor and a polycrystalline oxide semiconductor thin film in which a thin film made of an oxide semiconductor containing at least one element of the group consisting of In, Ga, and Zn can have high TFT characteristics. A method and a method of manufacturing a thin film transistor are provided.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

  In addition, what has the substantially same function is attached | subjected and demonstrated through the whole figure, and the description may be abbreviate | omitted depending on the case. Further, in the present embodiment, the term “transparent” means that it is transparent or semi-transparent to visible light, and substantially has a light transmittance of 20% or more for visible light.

  Further, in the present embodiment, the term “polycrystal” refers to a thin film having a crystallinity of 70% or higher, and the term “amorphous” refers to a thin film having a crystallinity of less than 70%.

  FIG. 1 is a schematic view of a polycrystalline oxide semiconductor thin film produced in this embodiment.

  The polycrystalline oxide semiconductor thin film 10 according to this embodiment is provided on the substrate 12.

(Thin film)
The polycrystalline oxide semiconductor thin film 10 of the present invention contains a polycrystalline IGZO-based oxide semiconductor and has high flatness. For this reason, when the polycrystalline oxide semiconductor thin film 10 is used as an active layer of a TFT, it is possible to avoid deterioration in TFT characteristics and variation in quality due to carrier traps caused by unevenness on the surface of the active layer.

  The flatness according to the present embodiment is expressed by the Ra value defined by the following formula in the JIS standard, and this value is 1.5 nm or less, preferably 1.0 nm or less, and more preferably 0. .8 nm or less.

ただし、Ｒａは原子間力顕微鏡による測定値で、Ｌはラインプロファイルの走査距離、Ｆ（ｘ）は測定点ｘの高さである。また、最大高さＲｙも、ＪＩＳ規格で定義される値で、走査範囲における最高点と最低点の高低差である。

However, Ra is a measured value with an atomic force microscope, L is the scanning distance of the line profile, and F (x) is the height of the measuring point x. The maximum height Ry is also a value defined by the JIS standard, and is a difference in height between the highest point and the lowest point in the scanning range.

  The polycrystalline oxide semiconductor thin film 10 only needs to contain polycrystalline IGZO as a main component, and may also contain amorphous IGZO, impurities, and the like.

As the IGZO, for example, an oxide containing at least one of In, Ga, and Zn (for example, an In—O system) is preferable, and an oxide containing at least two of In, Ga, and Zn (for example, In—). Zn-O-based, In-Ga-based, and Ga-Zn-O-based) are more preferable, and an oxide containing In, Ga, and Zn is particularly preferable. In particular, a polycrystalline oxide whose composition in a crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number of less than 6) is preferable, and InGaZnO ₄ is more preferable.

  IGZO has transparency according to the thickness of the thin film 10 not only in an amorphous state but also in a polycrystalline state, and the polycrystalline oxide semiconductor thin film 10 containing IGZO has a thickness of about 80 with respect to visible light. % Or more (see FIG. 10).

  The shape, structure, size and the like of the polycrystalline oxide semiconductor thin film 10 are not particularly limited, and may be selected according to the use and purpose of the thin film.

(substrate)
The material of the board | substrate 12 will not be specifically limited if it has heat resistance with respect to the baking temperature area | region mentioned later, An inorganic material, a metal material, an organic material, etc. are mentioned. In the present embodiment, particularly heat-resistant inorganic materials such as YSZ (zirconia stabilized yttrium), glass, quartz, sapphire, MgO, SiC, ZnO, LiF, and CaF ₂ are particularly preferable.

  The shape, structure, size and the like of the substrate 12 are not particularly limited, and may be selected according to the use and purpose of the thin film.

  Such a polycrystalline oxide semiconductor thin film 10 is suitably applied as an active layer of the following TFT.

(Configuration of TFT)
The TFT according to the present embodiment has at least a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, applies a voltage to the gate electrode, controls a current flowing through the active layer, This is an active element having a function of switching a current between drain electrodes.

  The TFT structure may be either an inverted staggered structure (also called a bottom gate type) or a staggered structure (also called a top gate type).

  FIG. 2 is a schematic diagram illustrating an example of a TFT having an inverted staggered structure according to the present embodiment. The TFT 20 has a gate electrode 24, a gate insulating layer 26, and an active layer 28 stacked in order on the substrate 12, and the source electrode 30 and the drain electrode 32 are separated from each other on the surface of the active layer 28. It is an installed configuration.

  On the other hand, FIG. 3 is a schematic view showing an example of a TFT having a staggered structure, which is a TFT according to the present embodiment. In the TFT 40, an active layer 28 is stacked on the surface of the substrate 12, and a source electrode 30 and a drain electrode 32 are spaced apart from each other on the active layer 28, and a gate insulating layer 26 and a gate electrode 24 are further formed thereon. Are sequentially stacked.

  In addition to the above, the TFT according to the present embodiment can have various configurations, and may have a configuration in which a protective layer is provided on the active layer 28 and an insulating layer is provided on the substrate 12 as appropriate. Good.

(Gate electrode)
The gate electrode 24 controls a current flowing between the source electrode 30 and the drain electrode 32 by applying a voltage. Examples of the material for forming the gate electrode 24 include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al—Nd and APC, tin oxide, zinc oxide, indium oxide, and indium tin oxide. Preferable examples include metal oxide conductors such as (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or a mixture thereof.

  The thickness of the gate electrode 24 is preferably 10 nm or more and 1000 nm or less.

  When the TFT is an inverted stagger type TFT 20, the gate electrode 24 is formed below the active layer 28, and therefore the gate electrode 24 is also baked together with the active layer 28 in a high temperature region as will be described later. It is preferable that the material has heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate electrode 24 is formed above the active layer 28, the gate electrode 24 is not fired in a high temperature region and does not have to have heat resistance.

(Gate insulation layer)
Examples of the material for forming the gate insulating layer 26 include inorganic compounds and organic compounds having a high relative dielectric constant.

  Examples of the inorganic compound include silicon oxide, silicon nitride, germanium oxide, germanium nitride, aluminum oxide, aluminum nitride, yttrium oxide, tantalum oxide, hafnium oxide, silicon oxynitride, silicon oxide carbide, silicon nitride carbide, silicon oxynitride carbide, Examples thereof include germanium oxynitride, germanium oxycarbide, germanium oxynitride, germanium oxynitride, aluminum oxynitride, aluminum oxycarbide, aluminum nitride carbide, aluminum oxynitride carbide, and mixtures thereof.

  Examples of the organic compound include polyimide, polyamide, polyester, polyacrylate, photo radical polymerization system, photo cation polymerization system photo-curing resin, or a copolymer containing an acrylonitrile component, polyvinyl phenol, polyvinyl alcohol, novolac resin, and And cyanoethyl pullulan. Moreover, the particle | grains which coat | covered these polymer fine particles with the inorganic oxide are also mentioned.

  The film thickness of the gate insulating layer 26 is preferably 30 nm to 3 μm, and more preferably 50 nm to 1 μm.

  In the case where the TFT is an inverted stagger type TFT 20, the gate insulating layer 26 is formed below the active layer 28. Therefore, as will be described later, the gate insulating layer 26 is also baked together with the active layer 28 in a high temperature region. Therefore, it is preferable to have heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate insulating layer 26 is formed above the active layer 28, the gate insulating layer 26 is not fired in a high temperature region and does not have to have heat resistance.

(Active layer)

  The active layer 28 has the same configuration as that of the polycrystalline oxide semiconductor thin film 10 described above.

  The thickness of the active layer 28 varies depending on the application and purpose of the TFT, but is preferably 10 nm to 1 μm, more preferably 20 nm to 500 nm, and particularly preferably 30 nm to 200 nm.

(Source electrode and drain electrode)
The source electrode 30 and the drain electrode 32 are formed on the active layer 28 so as to be separated from each other.

  The source electrode 30 and the drain electrode 32 are not particularly limited as long as they are conductive materials. For example, platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, aluminum, zinc, magnesium, Molybdenum, alloys of these metals, conductive metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and inorganic and organic semiconductors whose conductivity has been improved by doping (silicon single crystal, polysilicon, Amorphous silicon, germanium, graphite, polyacetylene, polyparaphenylene, polythiophene, polypyrrole, polyaniline, polythienylene vinylene, polyparaphenylene vinylene, and the like, and composites of these materials. In particular, the electrode material used for the source region and the drain region is preferably a material having a low electrical resistance at the contact surface with the active layer 28 among the above materials.

  The thicknesses of the source electrode 30 and the drain electrode 32 are preferably 10 nm or more and 1 μm or less, more preferably 30 nm or more and 500 nm or less, and particularly preferably 50 nm or more and 200 nm or less.

  Also in the case of the TFTs 20 and 40, since the source electrode 30 and the drain electrode 32 are formed above the active layer 28, they are not fired in a high temperature region and do not have to have heat resistance.

(Method for producing polycrystalline oxide semiconductor thin film)
Hereinafter, the manufacturing method of the polycrystalline oxide semiconductor thin film 10 described above will be described in detail.

  4A to 4C are main partial process diagrams of the method for manufacturing a polycrystalline oxide semiconductor thin film according to this embodiment, and are longitudinal sectional views of the polycrystalline oxide semiconductor thin film 10 shown in FIG. .

1. First Step First, as shown in FIGS. 4A and 4B, a known method, for example, a vapor phase film forming method such as a sputtering method or a pulse laser deposition method (PLD method) is used on the substrate 12. Then, a thin film 10A made of an amorphous oxide semiconductor containing at least one element from the group consisting of In, Ga, and Zn is formed. Here, as a target of the sputtering method or PLD method, a polycrystalline sintered body having an IGZO-based composition may be used alone, or an IGZO-based polycrystalline sintered body and a ZnO target may be used simultaneously, An IGZO-based polycrystalline sintered body and a Ga ₂ O ₃ target may be used simultaneously, or an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target may be used simultaneously.

2. Second Step Next, as shown in FIG. 4B, the thin film 10A made of an amorphous oxide semiconductor is put into an electric furnace, and the surface roughness Ra value is maintained at 1.5 nm or less. Baking in the temperature range where crystallization occurs. This temperature range is 660 ° C. or higher and 840 ° C. or lower, preferably 667 ° C. or higher and 800 ° C. or lower, and particularly preferably 700 ° C. or higher and 800 ° C. or lower.

  As other conditions for the firing, for example, IGZO is preferably fired in an oxygen atmosphere because oxygen vacancies are easily generated.

  By applying the above steps, a polycrystalline oxide semiconductor thin film 10 as shown in FIG. 4C and FIG. 1 can be obtained.

(Inverted stagger type thin film transistor manufacturing method)
Hereinafter, a manufacturing method of the above-described inverted stagger type TFT 20 will be described in detail.

  In this embodiment, since the layers other than the active layer 28 are formed by a known method, description thereof will be omitted as appropriate.

  5A to 5C are main partial process diagrams of the thin film transistor manufacturing method according to the present embodiment, and are longitudinal sectional views of the inverted staggered TFT 20 shown in FIG.

  First, as shown in FIG. 5A, the gate electrode 24 and the gate insulating layer 26 are sequentially formed by the following known method. As a method for forming the gate electrode 24, for example, a gate electrode 24 that is patterned by photolithography is formed on the substrate 12 by sputtering with a material having heat resistance in the temperature range selected from the above. There is a way to do it. As a method for forming the gate insulating layer 26, for example, a physical vapor deposition method such as a vapor deposition method, a sputtering method, or an ion plating method using a material having heat resistance in the above temperature range selected from the above. There are liquid phase growth methods such as a chemical vapor deposition method (PVD), various chemical vapor deposition methods (CVD), plating and a sol-gel method.

  Next, as shown in FIG. 5B, the group consisting of In, Ga, and Zn is formed on the gate insulating layer 26 by the same method as the first step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one element is formed.

  Then, the layer 28A made of an amorphous oxide semiconductor is baked by the same method as the second step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10.

  As a result, an active layer 28 according to the present embodiment as shown in FIG. 5C can be obtained.

  Finally, the source electrode 30 and the drain electrode 32 are formed on the active layer 28 so as to be separated from each other by the same method as that for the gate electrode 24 to obtain the TFT 20 as shown in FIG.

(Method of manufacturing staggered thin film transistor)
Hereinafter, a manufacturing method of the above-described inverted stagger type TFT 40 will be described in detail.

  In this embodiment, since the layers other than the active layer 28 are formed by a known method, description thereof will be omitted as appropriate.

  6A to 6C are main partial process diagrams of the method for manufacturing a thin film transistor according to the present invention, and are longitudinal sectional views of the staggered TFT 40 shown in FIG.

  First, as shown in FIGS. 6A and 6B, a group consisting of In, Ga, and Zn is formed on a substrate 12 by the same method as the first step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one element is formed.

  Then, the layer 28A made of an amorphous oxide semiconductor is baked by the same method as the second step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10.

  As a result, an active layer 28 according to this embodiment as shown in FIG. 6C can be obtained.

  Finally, the source electrode 30, the drain electrode 32, the gate insulating layer 26, and the gate electrode 24 are sequentially formed by the known method as described above to obtain the TFT 40 as shown in FIG.

As mentioned above, although this embodiment was described, this invention is not limited to this embodiment.
For example, according to the active layer 28 to be formed, the manufacturing process includes a step of patterning the layer 28A before baking or the active layer 28 after baking by photolithography, and a hole corresponding to the active layer 28 to be formed. A step of forming the pre-firing layer 28A in a predetermined position and shape through a mask may be included.

  In addition, although the firing of the second step in the TFT 20 or the TFT 40 has been described before the source electrode and the drain electrode or the gate insulating layer 26 and the gate electrode 24 are formed on the active layer 28, In and Ga If an amorphous oxide semiconductor containing at least one element in the group consisting of Zn and Zn can be polycrystallized, it may be formed after all of them are formed. However, in this case, the gate electrode 24, the gate insulating layer 26, the source electrode 30, and the drain electrode 32 are all preferably formed so as to have heat resistance in the temperature range.

  Furthermore, as a method of polycrystallizing the amorphous thin film 10A and the layer 28A, there are methods such as SPC method (Solid Phase Crystallization) and RTA method (Rapid Thermal Annealing) in addition to firing in an electric furnace. However, if laser annealing (ELA: Excimer Laser Annealing) is performed by irradiating an excimer laser beam using XeCl, an increase in substrate temperature can be suppressed, and the substrate 12 having low heat resistance can be used.

Furthermore, IGZO constituting the active layer 28 generally has oxygen nonstoichiometry. For this reason, the IGZO in this embodiment, for example, InGaO ₃ (ZnO) _m or InGaZnO ₄ , may include those in which the amount of oxygen is increased or decreased.

  Examples according to the present invention will be described below.

  An embodiment of the polycrystalline oxide semiconductor thin film 10 according to the present invention will be described with reference to FIGS. Since the embodiments of the active layer 28 of the TFT 20 and TFT 40 are the same in the following, the description thereof is omitted.

(Manufacture of polycrystalline oxide semiconductor thin films)
In this example, the polycrystalline oxide semiconductor thin film 10 made of IGZO was formed by performing the above-described sputtering film formation (first step) and baking in an oxygen atmosphere (second step).

  In the first step, an IGZO (In: Ga: Zn = 1: 1: 1) target and a ZnO target are mixed on a 10 mm square glass substrate 12 by sputtering, and a mixed gas of argon and oxygen (argon IGZO co-sputtered at room temperature in an atmosphere of about 99% and oxygen of about 1%) and having a film thickness of about 150 nm, that is, an amorphous material containing at least one element of the group consisting of In, Ga, and Zn A thin film 10A made of a quality oxide semiconductor was formed. The composition ratio of the thin film 10A was confirmed to be In: Ga: Zn = 1.11: 0.91: 1.00 by a known fluorescent X-ray analysis method.

The reason why the ZnO target is used separately is to compensate for the decrease in the sputtering efficiency of ZnO due to the IGZO target. When the target of IGZO (In: Ga: Zn = 1: 1: 1) is used alone, the composition ratio of the thin film 10A is about 1: 0.9: 0.7, and Ga and Zn are slightly reduced. Accordingly, it is desirable to co-sputter IGZO and a Ga ₂ O ₃ , ZnO target, or IGZO (In: Ga: Zn = 1: 1: 1) by co-sputtering In ₂ O ₃ , Ga ₂ O ₃ and ZnO targets. In this embodiment, IGZO and a ZnO target are used together, and the resulting thin film 10A is apparently treated as an InGaZnO ₄ (In: Ga: Zn = 1: 1: 1) thin film. It was.

  Since eight substrates 12 could be sputtered by one sputtering, the first step was repeated twice to obtain ten thin film samples.

In the second step, one is removed from the thin film sample and the others are placed in an electric furnace, and the temperature is between 600 ° C and 1000 ° C (600 ° C, 633 ° C, 667 ° C, 700 ° C, 733 ° C, 767 ° C, 800 ° C, 833 ° C. and 900 ° C.) for 1 hour. 100% oxygen gas whose flow rate was adjusted to 200 sccm (SI unit system, 0.338 Pa · m ³ / s) was flowed into the electric furnace during firing.

Hereinafter, for convenience of explanation, the name of each sample is described.
Sample 1: Thin film before firing, Sample 2: Thin film fired at 600 ° C, Sample 3: Thin film fired at 633 ° C, Sample 4: Thin film fired at 667 ° C, Sample 5: Thin film fired at 700 ° C, Sample 6 : Thin film fired at 733 ° C, Sample 7: Thin film fired at 767 ° C, Sample 8: Thin film fired at 800 ° C, Sample 9: Thin film fired at 833 ° C, Sample 10: Thin film fired at 900 ° C

(X-ray diffraction measurement)
About each thin film sample 1-10, the measurement intensity | strength was measured by the well-known X-ray-diffraction method using the measuring apparatus Rint-UltimaIII (Rigaku Corporation).

The measurement conditions are as follows.
Measurement angle range: 15deg ~ 80deg
Step width: 0.01deg
Scanning speed: 4 deg / min

  FIG. 7 is a diagram showing X-ray diffraction patterns of the thin film samples 1 to 10 according to this example. This diffraction pattern is obtained by performing a smoothing process on measurement data obtained by performing X-ray diffraction measurement.

The diffraction patterns of the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. are the space group R-3m (166), a-axis lattice constant = about 3.295Å, b-axis lattice constant = about 3.295３, c-axis. Lattice constant = about 26.070Å, interaxial angle α, β = 90 °, and interaxial angle γ = 120 °, which are substantially coincident with the diffraction pattern of InGaZnO ₄ , (101), (104), (10-5), (110) Indexing of crystal planes and the like was performed, and it was confirmed that each of the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. was an oxide semiconductor of IGZO.

(Calculation of crystallinity)
Next, with respect to the diffraction pattern, multiple peak separation was performed in the range of 25 to 40 degrees using analysis software JADE (Rigaku Corporation), and the crystallinity of each sample 1 to 10 was calculated. This crystallinity is expressed by the following equation.

なお、上記多結晶ピークと非晶質ピークの区分けに関しては、上記多重ピーク分離により得られた半値幅により区分けでき、本実施例ではＩＧＺＯの（００９）、（１０１）、（１０４）、（１０−５）結晶面の角度に位置するピークの半値幅が２．０以下のものを多結晶ピークとし、２．０以上のものを非晶質ピークとした。

The polycrystalline peak and the amorphous peak can be classified according to the half width obtained by the multiple peak separation. In this embodiment, (009), (101), (104), (10 -5) A peak located at an angle of the crystal plane with a half width of 2.0 or less was regarded as a polycrystalline peak, and a peak at 2.0 or more was regarded as an amorphous peak.

  Table 1 summarizes the experimental results according to this example.

  As shown in Table 1, the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. were judged to be polycrystalline because the crystallinity was 70% or more.

  On the other hand, the samples before firing and the thin film samples 1 to 3 fired at 600 ° C. to 633 ° C. were judged to be amorphous because the crystallinity was less than 70%.

(Surface roughness measurement)
The surface roughness of each thin film sample was measured using an AFM image of 3 μm square of each sample by an atomic force microscope (AFM, Nano-R manufactured by Pacific Nanotechnology).

  Here, the “surface roughness” is specifically the average value of the surface roughness Ra obtained from three line profiles with a scanning distance of 3 μm in the AFM image of each sample. At the same time, the maximum height Ry was also measured by the same method. Hereinafter, the average value of Ra is referred to as “Ra average”, and the average value of Ry is described as “Ry average”.

  The maximum height Ry is also a value defined by the JIS standard, and is a difference in height between the highest point and the lowest point in the scanning range.

  FIG. 8 is a diagram showing the measurement result of the surface roughness Ra. Moreover, FIG. 9 is a figure which shows the measurement result of maximum height Ry.

  From FIG. 8, FIG. 9 and Table 1 to the thin film sample before firing and the thin film sample fired at 600 ° C. to 800 ° C., the Ra average (also Ra value) is 1.5 nm or less and the Ry average is 8.0 nm. It was as follows and both were confirmed to be relatively small values. On the other hand, as for the sample baked at 833 degreeC or more, it has confirmed that both Ra average and Ry average were increasing rapidly.

  Based on the above results, referring to Table 1, by firing the IGZO-based amorphous oxide semiconductor thin film 10A at 667 ° C. to 833 ° C., polycrystalline oxidation having a surface roughness comparable to that of the thin film 10A The polycrystalline oxide semiconductor thin film 10 can be produced by firing the physical semiconductor thin film 10, that is, the thin film 10A in a temperature region where the thin film 10A is polycrystallized while maintaining the surface roughness Ra value of 1.5 nm or less. I understand that.

  If the polycrystalline oxide semiconductor thin film 10 fired in this temperature region is used for the active layer 28 of the TFT 20 or the TFT 40, the carrier mobility is higher than that of the IGZO amorphous TFT, and the deterioration of the yield due to the unevenness of the channel layer can be reduced. .

(Transparency)
The light transmittance of each thin film sample was measured using a spectrophotometer U-3310 manufactured by Hitachi, Ltd.

The measurement conditions are as follows.
Mode: Wavelength scan Data mode:% T
Scan range: 240-900nm
Scan speed: 600 nm / min
Sampling interval: 1.00 nm
Slit: 2 nm
Photomultiplier voltage: Automatic control Light source switching mode: Automatic switching Light source switching wavelength: 340.00 nm

  FIG. 10 is a diagram showing the measurement results of the light transmittance of the thin film sample according to this example.

  As shown in FIG. 10 and Table 1, it was confirmed that each thin film sample had a light transmittance of about 80% or more with respect to visible light regardless of whether it was amorphous. It has also been found that the light transmittance can be improved on the low wavelength side by increasing the firing temperature.

  10 and Table 1 show the measurement results of the light transmittance of only the thin film samples before firing and the thin film samples 2, 5, and 8 fired at 600 ° C., 700 ° C., and 800 ° C. The sample was also confirmed to be transparent to visible light.

  Similar to the amorphous oxide semiconductor thin film 10A, such a transparent polycrystalline oxide semiconductor thin film 10 can be used for the active layer 28 of the TFT 20 or TFT 40 that requires transparency, and is made of an active material made of other materials. More useful than layer 28.

It is a schematic diagram of the polycrystalline oxide semiconductor thin film produced in this embodiment. FIG. 4 is a schematic diagram illustrating an example of a TFT having an inverted staggered structure according to the present embodiment. FIG. 4 is a schematic diagram illustrating an example of a staggered TFT according to the present embodiment. (A)-(c) is principal part process drawing of the manufacturing method of the polycrystalline oxide semiconductor thin film which concerns on this embodiment, and is a longitudinal cross-sectional view of the polycrystalline oxide semiconductor thin film shown in FIG. (A)-(c) is principal part process drawing of the manufacturing method of the thin-film transistor which concerns on this embodiment, and is a longitudinal cross-sectional view of the reverse stagger type TFT shown in FIG. (A)-(c) is principal part process drawing of the manufacturing method of the thin-film transistor which concerns on this invention, and is a longitudinal cross-sectional view of the stagger type TFT shown in FIG. It is a figure which shows the X-ray-diffraction pattern of the thin film sample which concerns on a present Example. It is a figure which shows the measurement result of surface roughness Ra. It is a figure which shows the measurement result of maximum height Ry. It is a figure which shows the measurement result of the light transmittance of the thin film sample which concerns on a present Example.

10 Polycrystalline oxide semiconductor thin film 10A Amorphous oxide semiconductor thin film 12 Substrate 20, 40 TFT
24 gate electrode 26 gate insulating layer 28 active layer 28A layer 30 source electrode 32 drain electrode

Claims (7)

The surface roughness Ra value is 1.5 nm or less, and includes an active layer made of a polycrystalline oxide semiconductor containing elements of In, Ga, and Zn, and the polycrystalline oxide semiconductor has a crystallinity of 70% or more. in-Ga-Zn-O based transparent oxide der of is, elemental composition ratio of in, Ga, and Zn (in: Ga: Zn) 1: 1: thin film transistor which is characterized that you containing 1.   A thin film of an amorphous oxide semiconductor containing elements of In, Ga, and Zn is baked in a temperature range of 660 ° C. or higher and 840 ° C. or lower while maintaining the surface roughness Ra value of 1.5 nm or lower. A method for producing a polycrystalline oxide semiconductor thin film comprising a step of forming a polycrystalline oxide semiconductor thin film which is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more . 3. The polycrystalline oxide semiconductor thin film according to claim 2 , wherein the polycrystalline thin film contains elements of In, Ga, and Zn in a composition ratio (In: Ga: Zn) 1: 1: 1. Manufacturing method. The method for producing a polycrystalline oxide semiconductor thin film according to claim 2 or 3 , wherein the baking is performed in an oxygen atmosphere.   A layer made of an amorphous oxide semiconductor containing elements of In, Ga, and Zn is polycrystallized while maintaining its surface roughness Ra value of 1.5 nm or less, and fired in a temperature region of 660 ° C. or higher and 840 ° C. or lower. A thin film transistor comprising an active layer made of a polycrystalline oxide semiconductor that is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more Manufacturing method. 6. The method of manufacturing a thin film transistor according to claim 5 , wherein the active layer contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1. Method of manufacturing a thin film transistor according to claim 5 or claim 6 wherein the sintering is characterized by being carried out in an atmosphere containing oxygen.

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