JP5606682B2 - Thin film transistor, method for manufacturing polycrystalline oxide semiconductor thin film, and method for manufacturing thin film transistor - Google Patents

Thin film transistor, method for manufacturing polycrystalline oxide semiconductor thin film, and method for manufacturing thin film transistor Download PDF

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JP5606682B2
JP5606682B2 JP2009018128A JP2009018128A JP5606682B2 JP 5606682 B2 JP5606682 B2 JP 5606682B2 JP 2009018128 A JP2009018128 A JP 2009018128A JP 2009018128 A JP2009018128 A JP 2009018128A JP 5606682 B2 JP5606682 B2 JP 5606682B2
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JP2010177431A (en
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裕樹 奈良
賢一 梅田
文彦 望月
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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Description

本発明は、薄膜トランジスタ、多結晶酸化物半導体薄膜の製造方法、及び薄膜トランジスタの製造方法に関する。   The present invention relates to a thin film transistor, a method for manufacturing a polycrystalline oxide semiconductor thin film, and a method for manufacturing a thin film transistor.

近年、画像表示装置等に用いる透明な薄膜トランジスタ(以後の説明に於いて、TFTと表記する場合がある)の開発が活発に行われている。特に、In−Ga−Zn−O系(以後の説明に於いて、IGZOと表記する場合がある)は、その光学バンドギャップの広さから盛んに開発が行われ、非晶質のIGZOを活性層として用いたTFTに関して多数の文献がある(例えば、特許文献1参照)。   In recent years, a transparent thin film transistor (which may be referred to as a TFT in the following description) used for an image display device has been actively developed. In particular, the In—Ga—Zn—O system (which may be referred to as IGZO in the following description) has been actively developed due to its wide optical band gap, and activates amorphous IGZO. There are many documents regarding TFTs used as layers (see, for example, Patent Document 1).

ここで、TFTにおいて、非晶質のIGZOが用いられる一つの理由は、非晶質であるが故に表面が平坦な活性層を作製でき、活性層表面の凹凸を要因とするキャリアトラップによるTFT特性の低下及び品質のばらつきを回避できることにある。   Here, one reason why amorphous IGZO is used in the TFT is that it is amorphous, so that an active layer with a flat surface can be produced, and TFT characteristics due to carrier trapping caused by irregularities on the surface of the active layer. It is possible to avoid a decrease in quality and a variation in quality.

一方、TFT特性の1つであるキャリア移動度を高めるためには、一般的に、非晶質の半導体より結晶質の半導体の方が有効である。半導体の一種であるIGZOでも、組成比が異なるので一概には比較できないが、非晶質のInGaZnOからなる薄膜を活性層に用いたTFTでのキャリア移動度が6〜9cm2V-1S-1(on/off比10)であるのに対し、単結晶のInGaO(ZnO)からなる薄膜を活性層に用いたTFTでのキャリア移動度は80cm2V-1S-1(on/off比10)程度であることから、非晶質よりも結晶質のIGZOの方がキャリア移動度は高いことが推認される。よって、TFTにおいて、キャリア移動度を高めるためには、結晶質のIGZOを用いる方が有効であると考えられる(例えば、非特許文献1及び2参照)。 On the other hand, a crystalline semiconductor is generally more effective than an amorphous semiconductor in order to increase carrier mobility, which is one of TFT characteristics. Even in the case of IGZO, which is a kind of semiconductor, since the composition ratio is different, it cannot be generally compared, but the carrier mobility in a TFT using an amorphous InGaZnO 4 thin film as an active layer is 6-9 cm 2 V −1 S. −1 (on / off ratio 10 3 ), whereas the carrier mobility in a TFT using a thin film made of single-crystal InGaO 3 (ZnO) 5 as an active layer is 80 cm 2 V −1 S −1 ( Since the on / off ratio is about 10 6 ), it is presumed that crystalline IGZO has higher carrier mobility than amorphous. Therefore, it is considered that it is more effective to use crystalline IGZO in the TFT in order to increase carrier mobility (for example, see Non-Patent Documents 1 and 2).

特開2008−53356号公報JP 2008-53356 A 特開2007−73701号公報JP 2007-73701 A 特開2003−41362号公報JP 2003-41362 A Nature、Vol.432 (2004)488頁Nature, Vol. 432 (2004) 488 pages Sience、Vol.300 (2003)1269頁Science, Vol. 300 (2003) 1269

しかしながら、結晶質、特に多結晶のIGZOからなる薄膜を活性層として用いると、特許文献2に示すように、非晶質のIGZOからなる薄膜を活性層として用いた場合に比べ、活性層の表面性は荒れたものになりやすく、活性層表面の凹凸を要因とするキャリアトラップによるTFT特性の低下及び品質のばらつきが生ずるという問題がある。   However, when a thin film made of crystalline, particularly polycrystalline IGZO is used as the active layer, as shown in Patent Document 2, the surface of the active layer is compared with a case where a thin film made of amorphous IGZO is used as the active layer. However, there is a problem that TFT characteristics are deteriorated and quality is varied due to carrier traps caused by irregularities on the surface of the active layer.

特許文献3には、800℃で熱処理された多結晶のIn(ZnO)20からなる薄膜が開示されているものの、その表面性については開示されていない。 Patent Document 3 discloses a thin film made of polycrystalline In 2 O 3 (ZnO) 20 that has been heat-treated at 800 ° C., but does not disclose the surface properties thereof.

本発明は、InとGaとZnからなる群のうち少なくとも1つの元素を含有する酸化物半導体からなる薄膜が、高いTFT特性を有することが可能な薄膜トランジスタ、多結晶酸化物半導体薄膜の製造方法、及び薄膜トランジスタの製造方法を提供することを目的とする。   The present invention relates to a thin film transistor in which a thin film made of an oxide semiconductor containing at least one element of the group consisting of In, Ga, and Zn can have high TFT characteristics, a method for manufacturing a polycrystalline oxide semiconductor thin film, Another object is to provide a method for manufacturing a thin film transistor.

<1>表面粗さRa値が1.5nm以下であり、InとGaとZnの元素を含有する多結晶酸化物半導体からなる活性層を備え、前記多結晶酸化物半導体は結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物であり、InとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする薄膜トランジスタ。
<2>InとGaとZnの元素を含有する非晶質酸化物半導体の薄膜を、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域660℃以上840℃以下で焼成する工程を含んで、結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物である多結晶酸化物半導体の薄膜とすることを特徴とする多結晶酸化物半導体薄膜の製造方法。
>前記多結晶化された薄膜はInとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする<>に記載の多結晶酸化物半導体薄膜の製造方法。
>前記焼成は酸素雰囲気中で行われることを特徴とする<>又は<>に記載の多結晶酸化物半導体薄膜の製造方法。
>InとGaとZnの元素を含有する非晶質酸化物半導体からなる層を、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域660℃以上840℃以下で焼成して活性層とする工程を含んで、結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物である多結晶酸化物半導体からなる活性層とすることを特徴とする薄膜トランジスタの製造方法。
>前記活性層はInとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする<>に記載の薄膜トランジスタの製造方法。
>前記焼成は酸素を含む雰囲気中で行われることを特徴とする<>又は<>に記載の薄膜トランジスタの製造方法。
<1> A surface roughness Ra value of 1.5 nm or less, comprising an active layer made of a polycrystalline oxide semiconductor containing elements of In, Ga, and Zn, wherein the polycrystalline oxide semiconductor has a crystallinity of 70 Ri transparent oxide der percent or more in-Ga-Zn-O-based, elemental composition ratio of in, Ga, and Zn (in: Ga: Zn) 1: 1: characterized that you containing in 1 Thin film transistor.
<2 > A temperature region in which an amorphous oxide semiconductor thin film containing elements of In, Ga, and Zn is polycrystallized while maintaining its surface roughness Ra value of 1.5 nm or less. A polycrystalline oxide semiconductor comprising a polycrystalline oxide semiconductor thin film that is an In—Ga—Zn—O-based transparent oxide having a degree of crystallinity of 70% or more, including a baking step described below. Thin film manufacturing method.
< 3 > The polycrystalline oxide according to < 2 >, wherein the polycrystallized thin film contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1. Method for manufacturing a semiconductor thin film.
< 4 > The method for producing a polycrystalline oxide semiconductor thin film according to < 2 > or < 3 >, wherein the baking is performed in an oxygen atmosphere.
< 5 > Temperature range of polycrystallizing a layer made of an amorphous oxide semiconductor containing elements of In, Ga and Zn while maintaining the surface roughness Ra value of 1.5 nm or less 660 ° C. or more and 840 ° C. The method includes forming an active layer made of a polycrystalline oxide semiconductor, which is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more, including a step of firing to form an active layer. A method for manufacturing a thin film transistor.
< 6 > The method for producing a thin film transistor according to < 5 >, wherein the active layer contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1.
< 7 > The method for producing a thin film transistor according to < 5 > or < 6 >, wherein the baking is performed in an atmosphere containing oxygen.

本発明によれば、InとGaとZnからなる群のうち少なくとも1つの元素を含有する酸化物半導体からなる薄膜が、高いTFT特性を有することが可能な薄膜トランジスタ、多結晶酸化物半導体薄膜の製造方法、及び薄膜トランジスタの製造方法が提供される。   According to the present invention, a thin film transistor and a polycrystalline oxide semiconductor thin film in which a thin film made of an oxide semiconductor containing at least one element of the group consisting of In, Ga, and Zn can have high TFT characteristics. A method and a method of manufacturing a thin film transistor are provided.

以下、本発明の実施の形態の一例を図面を参照して説明する。   Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

なお、実質的に同様の機能を有するものには、全図面通して同じ符号を付して説明し、場合によってはその説明を省略することがある。また、本実施形態において透明とは、可視光に対して透明或いは半透明であることを示し、実質的に可視光に対して20%以上の光透過率を有することを示す。   In addition, what has the substantially same function is attached | subjected and demonstrated through the whole figure, and the description may be abbreviate | omitted depending on the case. Further, in the present embodiment, the term “transparent” means that it is transparent or semi-transparent to visible light, and substantially has a light transmittance of 20% or more for visible light.

さらに、本実施形態において多結晶とは、後述する薄膜の結晶化度が70%以上のものを指し、非晶質とは、薄膜の結晶化度が70%未満のものを指すものとする。   Further, in the present embodiment, the term “polycrystal” refers to a thin film having a crystallinity of 70% or higher, and the term “amorphous” refers to a thin film having a crystallinity of less than 70%.

図1は、本実施形態で作製した多結晶酸化物半導体薄膜の模式図である。   FIG. 1 is a schematic view of a polycrystalline oxide semiconductor thin film produced in this embodiment.

本実施形態に係る多結晶酸化物半導体薄膜10は、基板12上に設けられる。   The polycrystalline oxide semiconductor thin film 10 according to this embodiment is provided on the substrate 12.

(薄膜)
本発明の多結晶酸化物半導体薄膜10は、多結晶のIGZO系の酸化物半導体を含有しており、かつ、その平坦性が高いものである。このため、多結晶酸化物半導体薄膜10は、TFTの活性層として用いた場合、活性層表面の凹凸を要因とするキャリアトラップによるTFT特性の低下及び品質のばらつきを回避できる。
(Thin film)
The polycrystalline oxide semiconductor thin film 10 of the present invention contains a polycrystalline IGZO-based oxide semiconductor and has high flatness. For this reason, when the polycrystalline oxide semiconductor thin film 10 is used as an active layer of a TFT, it is possible to avoid deterioration in TFT characteristics and variation in quality due to carrier traps caused by unevenness on the surface of the active layer.

なお、本実施形態に係る平坦性は、JIS規格において次式で定義されるRa値で表現し、この値が1.5nm以下であって、好ましくは1.0nm以下であり、さらに好ましくは0.8nm以下である。   The flatness according to the present embodiment is expressed by the Ra value defined by the following formula in the JIS standard, and this value is 1.5 nm or less, preferably 1.0 nm or less, and more preferably 0. .8 nm or less.

Figure 0005606682
ただし、Raは原子間力顕微鏡による測定値で、Lはラインプロファイルの走査距離、F(x)は測定点xの高さである。また、最大高さRyも、JIS規格で定義される値で、走査範囲における最高点と最低点の高低差である。
Figure 0005606682
However, Ra is a measured value with an atomic force microscope, L is the scanning distance of the line profile, and F (x) is the height of the measuring point x. The maximum height Ry is also a value defined by the JIS standard, and is a difference in height between the highest point and the lowest point in the scanning range.

多結晶酸化物半導体薄膜10は、多結晶のIGZOを主成分としていれば良く、その他に非晶質のIGZOや不純物等を含有していても良い。   The polycrystalline oxide semiconductor thin film 10 only needs to contain polycrystalline IGZO as a main component, and may also contain amorphous IGZO, impurities, and the like.

IGZOとしては、例えば、In、Ga及びZnのうちの少なくとも1つを含む酸化物(例えばIn−O系)が好ましく、In、Ga及びZnのうちの少なくとも2つを含む酸化物(例えばIn−Zn−O系、In−Ga系、Ga−Zn−O系)がより好ましく、In、Ga及びZnを含む酸化物が特に好ましい。特に、結晶状態における組成がInGaO(ZnO)(mは6未満の自然数)で表される多結晶酸化物が好ましく、中でも、InGaZnOがより好ましい。 As the IGZO, for example, an oxide containing at least one of In, Ga, and Zn (for example, an In—O system) is preferable, and an oxide containing at least two of In, Ga, and Zn (for example, In—). Zn-O-based, In-Ga-based, and Ga-Zn-O-based) are more preferable, and an oxide containing In, Ga, and Zn is particularly preferable. In particular, a polycrystalline oxide whose composition in a crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number of less than 6) is preferable, and InGaZnO 4 is more preferable.

IGZOは、非晶質状態だけでなく、多結晶状態においても、薄膜10の厚みに応じた透明性を有し、IGZOを含有する多結晶酸化物半導体薄膜10は、可視光に対して約80%以上の光透過率を有する(図10参照)。   IGZO has transparency according to the thickness of the thin film 10 not only in an amorphous state but also in a polycrystalline state, and the polycrystalline oxide semiconductor thin film 10 containing IGZO has a thickness of about 80 with respect to visible light. % Or more (see FIG. 10).

多結晶酸化物半導体薄膜10の形状、構造、大きさ等については特に制限はなく、薄膜の用途、目的等に応じて選択すればよい。   The shape, structure, size and the like of the polycrystalline oxide semiconductor thin film 10 are not particularly limited, and may be selected according to the use and purpose of the thin film.

(基板)
基板12の材質は、後述する焼成温度領域に対して耐熱性を有するものであれば特に限定されることはなく、無機材料、金属材料、及び有機材料等が挙げられる。本実施形態では、特に、耐熱性のある、例えばYSZ(ジルコニア安定化イットリウム)、ガラス、石英、サファイア、MgO、SiC、ZnO、LiF、CaF2等の無機材料が好適に挙げられる。
(substrate)
The material of the board | substrate 12 will not be specifically limited if it has heat resistance with respect to the baking temperature area | region mentioned later, An inorganic material, a metal material, an organic material, etc. are mentioned. In the present embodiment, particularly heat-resistant inorganic materials such as YSZ (zirconia stabilized yttrium), glass, quartz, sapphire, MgO, SiC, ZnO, LiF, and CaF 2 are particularly preferable.

基板12の形状、構造、大きさ等については特に制限はなく、薄膜の用途、目的等に応じて選択すればよい。   The shape, structure, size and the like of the substrate 12 are not particularly limited, and may be selected according to the use and purpose of the thin film.

このような多結晶酸化物半導体薄膜10は、以下のようなTFTの活性層として好適に適用される。   Such a polycrystalline oxide semiconductor thin film 10 is suitably applied as an active layer of the following TFT.

(TFTの構成)
本実施形態に係るTFTは、少なくとも、ゲート電極、ゲート絶縁層、活性層、ソース電極及びドレイン電極を有し、ゲート電極に電圧を印加して、活性層に流れる電流を制御し、ソース電極とドレイン電極間の電流をスイッチングする機能を有するアクテイブ素子である。
(Configuration of TFT)
The TFT according to the present embodiment has at least a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, applies a voltage to the gate electrode, controls a current flowing through the active layer, This is an active element having a function of switching a current between drain electrodes.

TFT構造としては、逆スタガ構造(ボトムゲート型とも呼ばれる)及びスタガ構造(トップゲート型とも呼ばれる)のいずれの態様であってもよい。   The TFT structure may be either an inverted staggered structure (also called a bottom gate type) or a staggered structure (also called a top gate type).

図2は、本実施形態に係るTFTであって、逆スタガ型構造のTFTの一例を示す模式図である。TFT20は、基板12の上にゲート電極24と、ゲート絶縁層26と、活性層28とを順に積層して有し、活性層28の表面上にソース電極30及びドレイン電極32が互いに離間して設置された構成である。   FIG. 2 is a schematic diagram illustrating an example of a TFT having an inverted staggered structure according to the present embodiment. The TFT 20 has a gate electrode 24, a gate insulating layer 26, and an active layer 28 stacked in order on the substrate 12, and the source electrode 30 and the drain electrode 32 are separated from each other on the surface of the active layer 28. It is an installed configuration.

一方、図3は、本実施形態に係るTFTであって、スタガ型構造のTFTの一例を示す模式図である。TFT40は、基板12の表面上に活性層28を積層し、活性層28上にソース電極30及びドレイン電極32が互いに離間して設置され、更にこれらの上にゲート絶縁層26と、ゲート電極24とを順に積層した構成である。   On the other hand, FIG. 3 is a schematic view showing an example of a TFT having a staggered structure, which is a TFT according to the present embodiment. In the TFT 40, an active layer 28 is stacked on the surface of the substrate 12, and a source electrode 30 and a drain electrode 32 are spaced apart from each other on the active layer 28, and a gate insulating layer 26 and a gate electrode 24 are further formed thereon. Are sequentially stacked.

なお、本実施形態に係るTFTは、上記以外にも、様々な構成をとることが可能であり、適宜、活性層28上に保護層や基板12上に絶縁層等を備える構成であってもよい。   In addition to the above, the TFT according to the present embodiment can have various configurations, and may have a configuration in which a protective layer is provided on the active layer 28 and an insulating layer is provided on the substrate 12 as appropriate. Good.

(ゲート電極)
ゲート電極24は、電圧の印加により、ソース電極30とドレイン電極32との間に流れる電流を制御する。ゲート電極24を形成する材料としては、例えば、Al、Mo、Cr、Ta、Ti、Au、Ag等の金属、Al−Nd、APC等の合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫(ITO)、酸化亜鉛インジウム(IZO)等の金属酸化物導電体、ポリアニリン、ポリチオフェン、ポリピロ−ルなどの有機導電性化合物、またはこれらの混合物を好適に挙げられる。
(Gate electrode)
The gate electrode 24 controls a current flowing between the source electrode 30 and the drain electrode 32 by applying a voltage. Examples of the material for forming the gate electrode 24 include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al—Nd and APC, tin oxide, zinc oxide, indium oxide, and indium tin oxide. Preferable examples include metal oxide conductors such as (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or a mixture thereof.

ゲート電極24の厚みは、10nm以上1000nm以下とすることが好ましい。   The thickness of the gate electrode 24 is preferably 10 nm or more and 1000 nm or less.

TFTが逆スタガ型のTFT20の場合は、ゲート電極24は活性層28よりも下側に形成されることから、後述するように、ゲート電極24も活性層28と共に、高温領域で焼成されるため、この温度領域に対して耐熱性を有するものであることが好ましい。一方、スタガ型のTFT40の場合は、ゲート電極24は、活性層28よりも上側に形成されるため、高温領域で焼成されず、耐熱性を有するものでなくても良い。   When the TFT is an inverted stagger type TFT 20, the gate electrode 24 is formed below the active layer 28, and therefore the gate electrode 24 is also baked together with the active layer 28 in a high temperature region as will be described later. It is preferable that the material has heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate electrode 24 is formed above the active layer 28, the gate electrode 24 is not fired in a high temperature region and does not have to have heat resistance.

(ゲート絶縁層)
ゲート絶縁層26を形成する材料としては、比誘電率の高い無機化合物や有機化合物が挙げられる。
(Gate insulation layer)
Examples of the material for forming the gate insulating layer 26 include inorganic compounds and organic compounds having a high relative dielectric constant.

前記無機化合物としては、酸化珪素、窒化珪素、酸化ゲルマニウム、窒化ゲルマニウム、酸化アルミニウム、窒化アルミニウム、酸化イットリウム、酸化タンタル、酸化ハフニウム、酸化窒化珪素、酸化炭化珪素、窒化炭化珪素、酸化窒化炭化珪素、酸化窒化ゲルマニウム、酸化炭化ゲルマニウム、窒化炭化ゲルマニウム、酸化窒化炭化ゲルマニウム、酸化窒化アルミニウム、酸化炭化アルミニウム、窒化炭化アルミニウム、酸化窒化炭化アルミニウムやこれらの混合物が挙げられる。   Examples of the inorganic compound include silicon oxide, silicon nitride, germanium oxide, germanium nitride, aluminum oxide, aluminum nitride, yttrium oxide, tantalum oxide, hafnium oxide, silicon oxynitride, silicon oxide carbide, silicon nitride carbide, silicon oxynitride carbide, Examples thereof include germanium oxynitride, germanium oxycarbide, germanium oxynitride, germanium oxynitride, aluminum oxynitride, aluminum oxycarbide, aluminum nitride carbide, aluminum oxynitride carbide, and mixtures thereof.

前記有機化合物としては、ポリイミド、ポリアミド、ポリエステル、ポリアクリレート、光ラジカル重合系、光カチオン重合系の光硬化性樹脂、あるいはアクリロニトリル成分を含有する共重合体、ポリビニルフェノール、ポリビニルアルコール、ノボラック樹脂、およびシアノエチルプルラン等が挙げられる。また、これらのポリマー微粒子に無機酸化物を被覆した粒子も挙げられる。   Examples of the organic compound include polyimide, polyamide, polyester, polyacrylate, photo radical polymerization system, photo cation polymerization system photo-curing resin, or a copolymer containing an acrylonitrile component, polyvinyl phenol, polyvinyl alcohol, novolac resin, and And cyanoethyl pullulan. Moreover, the particle | grains which coat | covered these polymer fine particles with the inorganic oxide are also mentioned.

ゲート絶縁層26の膜厚としては、30nm〜3μmが好ましく、より好ましくは、50nm〜1μmである。   The film thickness of the gate insulating layer 26 is preferably 30 nm to 3 μm, and more preferably 50 nm to 1 μm.

TFTが逆スタガ型のTFT20の場合は、ゲート絶縁層26は活性層28よりも下側に形成されることから、後述するように、ゲート絶縁層26も活性層28と共に、高温領域で焼成されるため、この温度領域に対して耐熱性を有するものであることが好ましい。一方、スタガ型のTFT40の場合は、ゲート絶縁層26は、活性層28よりも上側に形成されるため、高温領域で焼成されず、耐熱性を有するものでなくても良い。   In the case where the TFT is an inverted stagger type TFT 20, the gate insulating layer 26 is formed below the active layer 28. Therefore, as will be described later, the gate insulating layer 26 is also baked together with the active layer 28 in a high temperature region. Therefore, it is preferable to have heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate insulating layer 26 is formed above the active layer 28, the gate insulating layer 26 is not fired in a high temperature region and does not have to have heat resistance.

(活性層) (Active layer)

活性層28は、上述した多結晶酸化物半導体薄膜10と同一の構成である。   The active layer 28 has the same configuration as that of the polycrystalline oxide semiconductor thin film 10 described above.

活性層28の厚みは、TFTの用途、目的等に応じて異なるが、好ましくは、10nm以上1μm以下、さらに好ましくは20nm以上500nm以下、特に好ましくは30nm以上200nm以下である。   The thickness of the active layer 28 varies depending on the application and purpose of the TFT, but is preferably 10 nm to 1 μm, more preferably 20 nm to 500 nm, and particularly preferably 30 nm to 200 nm.

(ソース電極及びドレイン電極)
ソース電極30とドレイン電極32は活性層28上に互いに離間して形成されている。
(Source electrode and drain electrode)
The source electrode 30 and the drain electrode 32 are formed on the active layer 28 so as to be separated from each other.

ソース電極30及びドレイン電極32は、導電性材料であれば特に限定されず、例えば白金、金、銀、ニッケル、クロム、銅、鉄、錫、アンチモン鉛、タンタル、インジウム、アルミニウム、亜鉛、マグネシウム、モリブデン、これらの金属の合金、酸化インジウム錫(ITO)、酸化亜鉛インジウム(IZO)等の導電性金属酸化物、ドーピング等で導電率を向上させた無機及び有機半導体(シリコン単結晶、ポリシリコン、アモルファスシリコン、ゲルマニウム、グラファイト、ポリアセチレン、ポリパラフェニレン、ポリチオフェン、ポリピロール、ポリアニリン、ポリチエニレンビニレン、ポリパラフェニレンビニレン等)、これらの材料の複合体等が挙げられる。特にソース領域及びドレイン領域に用いる電極の材料は、上記の材料の中でも活性層28との接触面において電気抵抗が少ないものが好ましい。   The source electrode 30 and the drain electrode 32 are not particularly limited as long as they are conductive materials. For example, platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, aluminum, zinc, magnesium, Molybdenum, alloys of these metals, conductive metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and inorganic and organic semiconductors whose conductivity has been improved by doping (silicon single crystal, polysilicon, Amorphous silicon, germanium, graphite, polyacetylene, polyparaphenylene, polythiophene, polypyrrole, polyaniline, polythienylene vinylene, polyparaphenylene vinylene, and the like, and composites of these materials. In particular, the electrode material used for the source region and the drain region is preferably a material having a low electrical resistance at the contact surface with the active layer 28 among the above materials.

ソース電極30及びドレイン電極32の厚みは、好ましくは、10nm以上1μm以下、さらに好ましくは30nm以上500nm以下、特に好ましくは50nm以上200nm以下である。   The thicknesses of the source electrode 30 and the drain electrode 32 are preferably 10 nm or more and 1 μm or less, more preferably 30 nm or more and 500 nm or less, and particularly preferably 50 nm or more and 200 nm or less.

TFT20、40の場合も、ソース電極30及びドレイン電極32は、活性層28よりも上側に形成されるため、高温領域で焼成されず、耐熱性を有するものでなくても良い。   Also in the case of the TFTs 20 and 40, since the source electrode 30 and the drain electrode 32 are formed above the active layer 28, they are not fired in a high temperature region and do not have to have heat resistance.

(多結晶酸化物半導体薄膜の製造方法)
以下、上述した多結晶酸化物半導体薄膜10の製造方法について詳細に説明する。
(Method for producing polycrystalline oxide semiconductor thin film)
Hereinafter, the manufacturing method of the polycrystalline oxide semiconductor thin film 10 described above will be described in detail.

図4(a)〜(c)は、本実施形態に係る多結晶酸化物半導体薄膜の製造方法の主要部分工程図であり、図1に示す多結晶酸化物半導体薄膜10の縦断面図である。   4A to 4C are main partial process diagrams of the method for manufacturing a polycrystalline oxide semiconductor thin film according to this embodiment, and are longitudinal sectional views of the polycrystalline oxide semiconductor thin film 10 shown in FIG. .

1.第1工程
まず、図4(a)及び(b)に示すように、基板12上に、公知の方法、例えば、スパッタリング法、パルスレーザー蒸着法(PLD法)等の気相成膜法を用いて、InとGaとZnからなる群のうち少なくとも1つの元素を含有する非晶質酸化物半導体からなる薄膜10Aを成膜する。ここで、スパッタリング法またはPLD法のターゲットとしては、IGZO系の組成を有する多結晶焼結体を単独で用いても良いが、IGZO系多結晶焼結体とZnOターゲットを同時に用いても良く、IGZO系多結晶焼結体とGaターゲットを同時に用いても良く、あるいはInターゲット、Gaターゲット、ZnOターゲットを同時に用いても良い。
1. First Step First, as shown in FIGS. 4A and 4B, a known method, for example, a vapor phase film forming method such as a sputtering method or a pulse laser deposition method (PLD method) is used on the substrate 12. Then, a thin film 10A made of an amorphous oxide semiconductor containing at least one element from the group consisting of In, Ga, and Zn is formed. Here, as a target of the sputtering method or PLD method, a polycrystalline sintered body having an IGZO-based composition may be used alone, or an IGZO-based polycrystalline sintered body and a ZnO target may be used simultaneously, An IGZO-based polycrystalline sintered body and a Ga 2 O 3 target may be used simultaneously, or an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target may be used simultaneously.

2.第2工程
次に、図4(b)に示すように、非晶質酸化物半導体からなる薄膜10Aを、電気炉へ投入し、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域で焼成する。この温度領域は、660℃以上840℃以下であって、好ましくは、667℃以上800℃以下、特に好ましくは、700℃以上800℃以下である。
2. Second Step Next, as shown in FIG. 4B, the thin film 10A made of an amorphous oxide semiconductor is put into an electric furnace, and the surface roughness Ra value is maintained at 1.5 nm or less. Baking in the temperature range where crystallization occurs. This temperature range is 660 ° C. or higher and 840 ° C. or lower, preferably 667 ° C. or higher and 800 ° C. or lower, and particularly preferably 700 ° C. or higher and 800 ° C. or lower.

上記焼成のその他の条件としては、例えば、IGZOが酸素欠損を生じやすいことから酸素雰囲気中で焼成することが好ましい。   As other conditions for the firing, for example, IGZO is preferably fired in an oxygen atmosphere because oxygen vacancies are easily generated.

以上の工程を適用することにより、図4(c)及び図1に示すような、多結晶酸化物半導体薄膜10を得ることができる。   By applying the above steps, a polycrystalline oxide semiconductor thin film 10 as shown in FIG. 4C and FIG. 1 can be obtained.

(逆スタガ型薄膜トランジスタの製造方法)
以下、上述した逆スタガ型のTFT20の製造方法について詳細に説明する。
(Inverted stagger type thin film transistor manufacturing method)
Hereinafter, a manufacturing method of the above-described inverted stagger type TFT 20 will be described in detail.

本実施形態では、活性層28以外は、公知の方法で形成するため、適宜説明を省略する。   In this embodiment, since the layers other than the active layer 28 are formed by a known method, description thereof will be omitted as appropriate.

図5(a)〜(c)は、本実施形態に係る薄膜トランジスタの製造方法の主要部分工程図であり、図2に示す逆スタガ型TFT20の縦断面図である。   5A to 5C are main partial process diagrams of the thin film transistor manufacturing method according to the present embodiment, and are longitudinal sectional views of the inverted staggered TFT 20 shown in FIG.

まず、図5(a)に示すように、以下のような公知の方法でゲート電極24及びゲート絶縁層26を順次形成する。ゲート電極24の形成方法としては、例えば、基板12上に、上述した中から選択した上記温度領域で耐熱性を有する材料でスパッタリングにより成膜した後、フォトリソグラフィによってパターニングされたゲート電極24を形成する方法がある。また、ゲート絶縁層26の形成方法としては、例えば、上述した中から選択した上記温度領域で耐熱性を有する材料を用いて、蒸着法、スパッタリング法、イオンプレーティング法等の物理的気相成長法(PVD)、種々の化学的気相成長法(CVD)、めっきやゾルゲル法等の液相成長法がある。   First, as shown in FIG. 5A, the gate electrode 24 and the gate insulating layer 26 are sequentially formed by the following known method. As a method for forming the gate electrode 24, for example, a gate electrode 24 that is patterned by photolithography is formed on the substrate 12 by sputtering with a material having heat resistance in the temperature range selected from the above. There is a way to do it. As a method for forming the gate insulating layer 26, for example, a physical vapor deposition method such as a vapor deposition method, a sputtering method, or an ion plating method using a material having heat resistance in the above temperature range selected from the above. There are liquid phase growth methods such as a chemical vapor deposition method (PVD), various chemical vapor deposition methods (CVD), plating and a sol-gel method.

次に、図5(b)に示すように、上記多結晶酸化物半導体薄膜10の製造方法の第1工程と同一の方法で、ゲート絶縁層26上に、InとGaとZnからなる群のうち少なくとも1つの元素を含有する非晶質酸化物半導体からなる層28Aを形成する。   Next, as shown in FIG. 5B, the group consisting of In, Ga, and Zn is formed on the gate insulating layer 26 by the same method as the first step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one element is formed.

そして、非晶質酸化物半導体からなる層28Aを、上記多結晶酸化物半導体薄膜10の製造方法の第2工程と同一の方法で焼成する。   Then, the layer 28A made of an amorphous oxide semiconductor is baked by the same method as the second step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10.

この結果、図5(c)に示すような、本実施形態に係る活性層28を得ることができる。   As a result, an active layer 28 according to the present embodiment as shown in FIG. 5C can be obtained.

最後に、ソース電極30及びドレイン電極32を、ゲート電極24と同様の方法で、活性層28上に互いに離間して形成して、図2に示すようなTFT20を得る。   Finally, the source electrode 30 and the drain electrode 32 are formed on the active layer 28 so as to be separated from each other by the same method as that for the gate electrode 24 to obtain the TFT 20 as shown in FIG.

(スタガ型薄膜トランジスタの製造方法)
以下、上述した逆スタガ型のTFT40の製造方法について詳細に説明する。
(Method of manufacturing staggered thin film transistor)
Hereinafter, a manufacturing method of the above-described inverted stagger type TFT 40 will be described in detail.

本実施形態では、活性層28以外は、公知の方法で形成するため、適宜説明を省略する。   In this embodiment, since the layers other than the active layer 28 are formed by a known method, description thereof will be omitted as appropriate.

図6(a)〜(c)は、本発明に係る薄膜トランジスタの製造方法の主要部分工程図であり、図3に示すスタガ型TFT40の縦断面図である。   6A to 6C are main partial process diagrams of the method for manufacturing a thin film transistor according to the present invention, and are longitudinal sectional views of the staggered TFT 40 shown in FIG.

まず、図6(a)及び(b)に示すように、上記多結晶酸化物半導体薄膜10の製造方法の第1工程と同一の方法で、基板12上に、InとGaとZnからなる群のうち少なくとも1つの元素を含有する非晶質酸化物半導体からなる層28Aを形成する。   First, as shown in FIGS. 6A and 6B, a group consisting of In, Ga, and Zn is formed on a substrate 12 by the same method as the first step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one element is formed.

そして、非晶質酸化物半導体からなる層28Aを、上記多結晶酸化物半導体薄膜10の製造方法の第2工程と同一の方法で焼成する。   Then, the layer 28A made of an amorphous oxide semiconductor is baked by the same method as the second step of the method for manufacturing the polycrystalline oxide semiconductor thin film 10.

この結果、図6(c)に示すような、本実施形態に係る活性層28を得ることができる。   As a result, an active layer 28 according to this embodiment as shown in FIG. 6C can be obtained.

最後に、ソース電極30、ドレイン電極32、ゲート絶縁層26及びゲート電極24を、上記のような公知の方法で順次形成して、図3に示すようなTFT40を得る。   Finally, the source electrode 30, the drain electrode 32, the gate insulating layer 26, and the gate electrode 24 are sequentially formed by the known method as described above to obtain the TFT 40 as shown in FIG.

以上、本実施形態について説明したが、本発明はこの実施形態に限定されるものではない。
例えば、上記製造工程には、形成すべき活性層28に応じて、フォトリソグラフィによって焼成前の層28A又は焼成後の活性層28をパターニングする工程、形成すべき活性層28に対応した孔を有するマスクを介して所定の位置及び形状に焼成前の層28Aを形成する工程を含んでも良い。
As mentioned above, although this embodiment was described, this invention is not limited to this embodiment.
For example, according to the active layer 28 to be formed, the manufacturing process includes a step of patterning the layer 28A before baking or the active layer 28 after baking by photolithography, and a hole corresponding to the active layer 28 to be formed. A step of forming the pre-firing layer 28A in a predetermined position and shape through a mask may be included.

また、TFT20又はTFT40における上記第2工程の焼成は、活性層28上にソース電極及びドレイン電極、又は、ゲート絶縁層26及びゲート電極24を形成する前に行う場合を説明したが、InとGaとZnからなる群のうち少なくとも1つの元素を含有する非晶質酸化物半導体が多結晶化できれば全てを形成した後に行うようにしても良い。ただし、この場合、ゲート電極24、ゲート絶縁層26、ソース電極30及びドレイン電極32全て、上記温度領域で耐熱性を有するように形成する方が良い。   In addition, although the firing of the second step in the TFT 20 or the TFT 40 has been described before the source electrode and the drain electrode or the gate insulating layer 26 and the gate electrode 24 are formed on the active layer 28, In and Ga If an amorphous oxide semiconductor containing at least one element in the group consisting of Zn and Zn can be polycrystallized, it may be formed after all of them are formed. However, in this case, the gate electrode 24, the gate insulating layer 26, the source electrode 30, and the drain electrode 32 are all preferably formed so as to have heat resistance in the temperature range.

さらに、非晶質である薄膜10A及び層28Aを多結晶化する方法としては、電気炉で焼成する以外にも、例えばSPC法( Solid Phase Crystallization)やRTA法( Rapid Thermal Annealing)などといった手法があるが、XeClを用いたエキシマレーザービームを照射することによるレーザアニール(ELA:Excimer Laser Annealing)を行えば、基板温度の上昇が抑えられ、耐熱性が低い基板12を用いることも可能となる。   Furthermore, as a method of polycrystallizing the amorphous thin film 10A and the layer 28A, there are methods such as SPC method (Solid Phase Crystallization) and RTA method (Rapid Thermal Annealing) in addition to firing in an electric furnace. However, if laser annealing (ELA: Excimer Laser Annealing) is performed by irradiating an excimer laser beam using XeCl, an increase in substrate temperature can be suppressed, and the substrate 12 having low heat resistance can be used.

さらにまた、活性層28を構成するIGZOは、一般的に酸素不定比性がある。このため、本実施形態におけるIGZO、例えばInGaO(ZnO)やInGaZnOには、酸素量が増減したものを含んでいても良い。 Furthermore, IGZO constituting the active layer 28 generally has oxygen nonstoichiometry. For this reason, the IGZO in this embodiment, for example, InGaO 3 (ZnO) m or InGaZnO 4 , may include those in which the amount of oxygen is increased or decreased.

以下、本発明に係る実施例について説明する。   Examples according to the present invention will be described below.

本発明に係る多結晶酸化物半導体薄膜10の実施例を、図1及び図4を用いて説明する。なお、TFT20、TFT40の活性層28の実施例についても以下同一となるので説明を省略する。   An embodiment of the polycrystalline oxide semiconductor thin film 10 according to the present invention will be described with reference to FIGS. Since the embodiments of the active layer 28 of the TFT 20 and TFT 40 are the same in the following, the description thereof is omitted.

(多結晶酸化物半導体薄膜の製造)
本実施例では、上述したスパッタリング成膜(第1工程)及び酸素雰囲気中での焼成(第2工程)を経ることにより、IGZOからなる多結晶酸化物半導体薄膜10を形成した。
(Manufacture of polycrystalline oxide semiconductor thin films)
In this example, the polycrystalline oxide semiconductor thin film 10 made of IGZO was formed by performing the above-described sputtering film formation (first step) and baking in an oxygen atmosphere (second step).

第1工程では、スパッタリング法により、10mm角のガラス基板12上に、IGZO(In:Ga:Zn=1:1:1)のターゲットと、ZnOのターゲットを、アルゴンと酸素との混合ガス(アルゴン約99%、酸素約1%)の雰囲気中、室温で共スパッタし、約150nmの膜厚を有したIGZO、すなわち、InとGaとZnからなる群のうち少なくとも1つの元素を含有する非晶質酸化物半導体からなる薄膜10Aを成膜した。この薄膜10Aの組成比は、公知の蛍光X線分析法により確認したところIn:Ga:Zn=1.11:0.91:1.00であった。   In the first step, an IGZO (In: Ga: Zn = 1: 1: 1) target and a ZnO target are mixed on a 10 mm square glass substrate 12 by sputtering, and a mixed gas of argon and oxygen (argon IGZO co-sputtered at room temperature in an atmosphere of about 99% and oxygen of about 1%) and having a film thickness of about 150 nm, that is, an amorphous material containing at least one element of the group consisting of In, Ga, and Zn A thin film 10A made of a quality oxide semiconductor was formed. The composition ratio of the thin film 10A was confirmed to be In: Ga: Zn = 1.11: 0.91: 1.00 by a known fluorescent X-ray analysis method.

なお、ZnOのターゲットを別に用いたのは、IGZOのターゲットによるZnOのスパッタ効率の低下を補填するためである。IGZO(In:Ga:Zn=1:1:1)のターゲットを単独で用いると、薄膜10Aの組成比は約1:0.9:0.7になり、GaとZnが若干減少する。したがって、望ましくはIGZOとGa,ZnOターゲットを共スパッタするか、In、Ga、ZnOターゲットを共スパッタしてIGZO(In:Ga:Zn=1:1:1)の薄膜10Aを得るのが良いが、本実施例ではIGZOとZnOターゲットを併用し、それによって得た薄膜10Aを見かけ上InGaZnO(In:Ga:Zn=1:1:1)の薄膜として扱った。 The reason why the ZnO target is used separately is to compensate for the decrease in the sputtering efficiency of ZnO due to the IGZO target. When the target of IGZO (In: Ga: Zn = 1: 1: 1) is used alone, the composition ratio of the thin film 10A is about 1: 0.9: 0.7, and Ga and Zn are slightly reduced. Accordingly, it is desirable to co-sputter IGZO and a Ga 2 O 3 , ZnO target, or IGZO (In: Ga: Zn = 1: 1: 1) by co-sputtering In 2 O 3 , Ga 2 O 3 and ZnO targets. In this embodiment, IGZO and a ZnO target are used together, and the resulting thin film 10A is apparently treated as an InGaZnO 4 (In: Ga: Zn = 1: 1: 1) thin film. It was.

一度のスパッタで8枚の基板12にスパッタ可能であったため、上記第1工程を2回繰り返して、10個の薄膜試料を得た。   Since eight substrates 12 could be sputtered by one sputtering, the first step was repeated twice to obtain ten thin film samples.

第2工程では、上記薄膜試料から1個を除き、その他を電気炉に入れ、600℃〜1000℃の間(600℃、633℃、667℃、700℃、733℃、767℃、800℃、833℃、900℃)で、1時間焼成した。この電気炉内には、焼成中、流量を200sccm(SI単位系で、0.338Pa・m/s)に調節した100%酸素ガスを流した。 In the second step, one is removed from the thin film sample and the others are placed in an electric furnace, and the temperature is between 600 ° C and 1000 ° C (600 ° C, 633 ° C, 667 ° C, 700 ° C, 733 ° C, 767 ° C, 800 ° C, 833 ° C. and 900 ° C.) for 1 hour. 100% oxygen gas whose flow rate was adjusted to 200 sccm (SI unit system, 0.338 Pa · m 3 / s) was flowed into the electric furnace during firing.

以下、説明の便宜のため、各試料名を記載する。
試料1:焼成前の薄膜、試料2:600℃で焼成した薄膜、試料3:633℃で焼成した薄膜、試料4:667℃で焼成した薄膜、試料5:700℃で焼成した薄膜、試料6:733℃で焼成した薄膜、試料7:767℃で焼成した薄膜、試料8:800℃で焼成した薄膜、試料9:833℃で焼成した薄膜、試料10:900℃で焼成した薄膜
Hereinafter, for convenience of explanation, the name of each sample is described.
Sample 1: Thin film before firing, Sample 2: Thin film fired at 600 ° C, Sample 3: Thin film fired at 633 ° C, Sample 4: Thin film fired at 667 ° C, Sample 5: Thin film fired at 700 ° C, Sample 6 : Thin film fired at 733 ° C, Sample 7: Thin film fired at 767 ° C, Sample 8: Thin film fired at 800 ° C, Sample 9: Thin film fired at 833 ° C, Sample 10: Thin film fired at 900 ° C

(X線回折測定)
各薄膜試料1〜10について、測定装置Rint−UltimaIII(リガク社)を用い、周知のX線回折法により回折強度の測定を行った。
(X-ray diffraction measurement)
About each thin film sample 1-10, the measurement intensity | strength was measured by the well-known X-ray-diffraction method using the measuring apparatus Rint-UltimaIII (Rigaku Corporation).

この測定条件は以下の通りである。
測定角度範囲: 15deg〜80deg
ステップ幅: 0.01deg
走査速度: 4deg/min
The measurement conditions are as follows.
Measurement angle range: 15deg ~ 80deg
Step width: 0.01deg
Scanning speed: 4 deg / min

図7は、本実施例に係る薄膜試料1〜10のX線回折パターンを示す図である。この回折パターンは、X線回折測定を行って得た測定データに対してスムージング処理をした後のものである。   FIG. 7 is a diagram showing X-ray diffraction patterns of the thin film samples 1 to 10 according to this example. This diffraction pattern is obtained by performing a smoothing process on measurement data obtained by performing X-ray diffraction measurement.

667℃〜900℃で焼成した各薄膜試料4〜10の回折パターンは、空間群R−3m(166)、a軸格子定数=約3.295Å,b軸格子定数=約3.295Å、c軸格子定数=約26.070Å、軸間角α、β=90度、軸間角γ=120度のInGaZnOの回折パターンと略一致し、(101)、(104)、(10−5)、(110)結晶面等の指数付けが行え、667℃〜900℃で焼成した各薄膜試料4〜10がIGZOの酸化物半導体であることが確認できた。 The diffraction patterns of the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. are the space group R-3m (166), a-axis lattice constant = about 3.295Å, b-axis lattice constant = about 3.2953, c-axis. Lattice constant = about 26.070Å, interaxial angle α, β = 90 °, and interaxial angle γ = 120 °, which are substantially coincident with the diffraction pattern of InGaZnO 4 , (101), (104), (10-5), (110) Indexing of crystal planes and the like was performed, and it was confirmed that each of the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. was an oxide semiconductor of IGZO.

(結晶化度の算出)
次に、上記回折パターンに対し、解析ソフトJADE(リガク社)を用いて25度〜40度の範囲で多重ピーク分離を行い、各試料1〜10の結晶化度を算出した。この結晶化度は、次式で示される。
(Calculation of crystallinity)
Next, with respect to the diffraction pattern, multiple peak separation was performed in the range of 25 to 40 degrees using analysis software JADE (Rigaku Corporation), and the crystallinity of each sample 1 to 10 was calculated. This crystallinity is expressed by the following equation.

Figure 0005606682
なお、上記多結晶ピークと非晶質ピークの区分けに関しては、上記多重ピーク分離により得られた半値幅により区分けでき、本実施例ではIGZOの(009)、(101)、(104)、(10−5)結晶面の角度に位置するピークの半値幅が2.0以下のものを多結晶ピークとし、2.0以上のものを非晶質ピークとした。
Figure 0005606682
The polycrystalline peak and the amorphous peak can be classified according to the half width obtained by the multiple peak separation. In this embodiment, (009), (101), (104), (10 -5) A peak located at an angle of the crystal plane with a half width of 2.0 or less was regarded as a polycrystalline peak, and a peak at 2.0 or more was regarded as an amorphous peak.

表1は、本実施例に係る実験結果をまとめたものである。   Table 1 summarizes the experimental results according to this example.

表1に示すように、667℃〜900℃で焼成した薄膜試料4〜10は、結晶化度が70%以上であるため、多結晶であると判断した。   As shown in Table 1, the thin film samples 4 to 10 fired at 667 ° C. to 900 ° C. were judged to be polycrystalline because the crystallinity was 70% or more.

一方、焼成前の試料及び600℃〜633℃で焼成した薄膜試料1〜3は、結晶化度が70%未満であるため、非晶質であると判断した。   On the other hand, the samples before firing and the thin film samples 1 to 3 fired at 600 ° C. to 633 ° C. were judged to be amorphous because the crystallinity was less than 70%.

(表面粗さ測定)
各薄膜試料における表面粗さは、原子間力顕微鏡(AFM、Pacific Nanotechnology社製 Nano-R)による各試料の3μm角のAFM像を用いて測定した。
(Surface roughness measurement)
The surface roughness of each thin film sample was measured using an AFM image of 3 μm square of each sample by an atomic force microscope (AFM, Nano-R manufactured by Pacific Nanotechnology).

ここで、「表面粗さ」とは、具体的には各試料のAFM像における、走査距離3μmのラインプロファイル3本から得た表面粗さRaの平均値とした。同時に、同様の方法で最大高さRyの測定も行った。以下では、Raの平均値を「Ra平均」とし、Ryの平均値を「Ry平均」と記載する。   Here, the “surface roughness” is specifically the average value of the surface roughness Ra obtained from three line profiles with a scanning distance of 3 μm in the AFM image of each sample. At the same time, the maximum height Ry was also measured by the same method. Hereinafter, the average value of Ra is referred to as “Ra average”, and the average value of Ry is described as “Ry average”.

なお、最大高さRyもJIS規格で定義される値で、走査範囲における最高点と最低点の高低差である。   The maximum height Ry is also a value defined by the JIS standard, and is a difference in height between the highest point and the lowest point in the scanning range.

図8は、表面粗さRaの測定結果を示す図である。また、図9は、最大高さRyの測定結果を示す図である。   FIG. 8 is a diagram showing the measurement result of the surface roughness Ra. Moreover, FIG. 9 is a figure which shows the measurement result of maximum height Ry.

図8、図9及び表1から、焼成前の薄膜試料及び600℃〜800℃で焼成した薄膜試料までは、Ra平均(Ra値も)が1.5nm以下、かつ、Ry平均が8.0nm以下であり、ともに比較的小さな値であることが確認できた。一方で、833℃以上で焼成した試料は、Ra平均とRy平均が、共に急激に増大していることが確認できた。   From FIG. 8, FIG. 9 and Table 1 to the thin film sample before firing and the thin film sample fired at 600 ° C. to 800 ° C., the Ra average (also Ra value) is 1.5 nm or less and the Ry average is 8.0 nm. It was as follows and both were confirmed to be relatively small values. On the other hand, as for the sample baked at 833 degreeC or more, it has confirmed that both Ra average and Ry average were increasing rapidly.

以上の結果に基づき表1を参照して、IGZO系の非晶質酸化物半導体薄膜10Aを667℃〜833℃で焼成することで、当該薄膜10Aと同程度の表面粗さを持つ多結晶酸化物半導体薄膜10、すなわち、当該薄膜10Aを、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域で焼成することで、多結晶酸化物半導体薄膜10を作製できたことが分かる。   Based on the above results, referring to Table 1, by firing the IGZO-based amorphous oxide semiconductor thin film 10A at 667 ° C. to 833 ° C., polycrystalline oxidation having a surface roughness comparable to that of the thin film 10A The polycrystalline oxide semiconductor thin film 10 can be produced by firing the physical semiconductor thin film 10, that is, the thin film 10A in a temperature region where the thin film 10A is polycrystallized while maintaining the surface roughness Ra value of 1.5 nm or less. I understand that.

この温度領域で焼成した多結晶酸化物半導体薄膜10をTFT20又はTFT40の活性層28に用いれば、IGZO系のアモルファスTFTよりもキャリア移動度が高く、かつチャンネル層の凹凸による歩留まりの悪化を低減できる。   If the polycrystalline oxide semiconductor thin film 10 fired in this temperature region is used for the active layer 28 of the TFT 20 or the TFT 40, the carrier mobility is higher than that of the IGZO amorphous TFT, and the deterioration of the yield due to the unevenness of the channel layer can be reduced. .

(透明度)
各薄膜試料の光透過率を、日立製作所(株)製の分光光度計U−3310を用いて測定した。
(Transparency)
The light transmittance of each thin film sample was measured using a spectrophotometer U-3310 manufactured by Hitachi, Ltd.

この測定条件は、以下の通りである。
モード: 波長スキャン
データモード: %T
スキャン範囲: 240〜900nm
スキャン速度: 600 nm/min
サンプリング間隔:1.00 nm
スリット: 2 nm
ホトマル電圧: 自動制御
光源切換モード: 自動切換
光源切換波長: 340.00 nm
The measurement conditions are as follows.
Mode: Wavelength scan Data mode:% T
Scan range: 240-900nm
Scan speed: 600 nm / min
Sampling interval: 1.00 nm
Slit: 2 nm
Photomultiplier voltage: Automatic control Light source switching mode: Automatic switching Light source switching wavelength: 340.00 nm

図10は、本実施例に係る薄膜試料の光透過率の測定結果を示す図である。   FIG. 10 is a diagram showing the measurement results of the light transmittance of the thin film sample according to this example.

図10及び表1に示すように、各薄膜試料は、非晶質か否かに関わらず、可視光に対して約80%以上の光透過率を有することが確認できた。また、焼成温度を上昇させることにより、低波長側で光透過率を向上させることができることを見出した。   As shown in FIG. 10 and Table 1, it was confirmed that each thin film sample had a light transmittance of about 80% or more with respect to visible light regardless of whether it was amorphous. It has also been found that the light transmittance can be improved on the low wavelength side by increasing the firing temperature.

なお、図10及び表1では、焼成前の薄膜試料並びに、600℃、700℃及び800℃で焼成した薄膜試料2、5、8のみの光透過率の測定結果を示したが、その他の薄膜試料についても可視光に対して透明であることを確認した。   10 and Table 1 show the measurement results of the light transmittance of only the thin film samples before firing and the thin film samples 2, 5, and 8 fired at 600 ° C., 700 ° C., and 800 ° C. The sample was also confirmed to be transparent to visible light.

このような透明な多結晶酸化物半導体薄膜10は、非晶質酸化物半導体薄膜10Aと同様に、透明性が求められるTFT20又はTFT40の活性層28に用いることができ、他の材料からなる活性層28よりも有用なものとなる。   Similar to the amorphous oxide semiconductor thin film 10A, such a transparent polycrystalline oxide semiconductor thin film 10 can be used for the active layer 28 of the TFT 20 or TFT 40 that requires transparency, and is made of an active material made of other materials. More useful than layer 28.

Figure 0005606682
Figure 0005606682

本実施形態で作製した多結晶酸化物半導体薄膜の模式図である。It is a schematic diagram of the polycrystalline oxide semiconductor thin film produced in this embodiment. 本実施形態に係るTFTであって、逆スタガ型構造のTFTの一例を示す模式図である。FIG. 4 is a schematic diagram illustrating an example of a TFT having an inverted staggered structure according to the present embodiment. 本実施形態に係るTFTであって、スタガ型構造のTFTの一例を示す模式図である。FIG. 4 is a schematic diagram illustrating an example of a staggered TFT according to the present embodiment. (a)〜(c)は、本実施形態に係る多結晶酸化物半導体薄膜の製造方法の主要部分工程図であり、図1に示す多結晶酸化物半導体薄膜の縦断面図である。(A)-(c) is principal part process drawing of the manufacturing method of the polycrystalline oxide semiconductor thin film which concerns on this embodiment, and is a longitudinal cross-sectional view of the polycrystalline oxide semiconductor thin film shown in FIG. (a)〜(c)は、本実施形態に係る薄膜トランジスタの製造方法の主要部分工程図であり、図2に示す逆スタガ型TFTの縦断面図である。(A)-(c) is principal part process drawing of the manufacturing method of the thin-film transistor which concerns on this embodiment, and is a longitudinal cross-sectional view of the reverse stagger type TFT shown in FIG. (a)〜(c)は、本発明に係る薄膜トランジスタの製造方法の主要部分工程図であり、図3に示すスタガ型TFTの縦断面図である。(A)-(c) is principal part process drawing of the manufacturing method of the thin-film transistor which concerns on this invention, and is a longitudinal cross-sectional view of the stagger type TFT shown in FIG. 本実施例に係る薄膜試料のX線回折パターンを示す図である。It is a figure which shows the X-ray-diffraction pattern of the thin film sample which concerns on a present Example. 表面粗さRaの測定結果を示す図である。It is a figure which shows the measurement result of surface roughness Ra. 最大高さRyの測定結果を示す図である。It is a figure which shows the measurement result of maximum height Ry. 本実施例に係る薄膜試料の光透過率の測定結果を示す図である。It is a figure which shows the measurement result of the light transmittance of the thin film sample which concerns on a present Example.

10 多結晶酸化物半導体薄膜
10A 非晶質酸化物半導体薄膜
12 基板
20、40 TFT
24 ゲート電極
26 ゲート絶縁層
28 活性層
28A 層
30 ソース電極
32 ドレイン電極
10 Polycrystalline oxide semiconductor thin film 10A Amorphous oxide semiconductor thin film 12 Substrate 20, 40 TFT
24 gate electrode 26 gate insulating layer 28 active layer 28A layer 30 source electrode 32 drain electrode

Claims (7)

表面粗さRa値が1.5nm以下であり、InとGaとZnの元素を含有する多結晶酸化物半導体からなる活性層を備え、前記多結晶酸化物半導体は結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物であり、InとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする薄膜トランジスタ。 The surface roughness Ra value is 1.5 nm or less, and includes an active layer made of a polycrystalline oxide semiconductor containing elements of In, Ga, and Zn, and the polycrystalline oxide semiconductor has a crystallinity of 70% or more. in-Ga-Zn-O based transparent oxide der of is, elemental composition ratio of in, Ga, and Zn (in: Ga: Zn) 1: 1: thin film transistor which is characterized that you containing 1. InとGaとZnの元素を含有する非晶質酸化物半導体の薄膜を、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域660℃以上840℃以下で焼成する工程を含んで、結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物である多結晶酸化物半導体の薄膜とすることを特徴とする多結晶酸化物半導体薄膜の製造方法。   A thin film of an amorphous oxide semiconductor containing elements of In, Ga, and Zn is baked in a temperature range of 660 ° C. or higher and 840 ° C. or lower while maintaining the surface roughness Ra value of 1.5 nm or lower. A method for producing a polycrystalline oxide semiconductor thin film comprising a step of forming a polycrystalline oxide semiconductor thin film which is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more . 前記多結晶化された薄膜はInとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする請求項に記載の多結晶酸化物半導体薄膜の製造方法。 3. The polycrystalline oxide semiconductor thin film according to claim 2 , wherein the polycrystalline thin film contains elements of In, Ga, and Zn in a composition ratio (In: Ga: Zn) 1: 1: 1. Manufacturing method. 前記焼成は酸素雰囲気中で行われることを特徴とする請求項又は請求項に記載の多結晶酸化物半導体薄膜の製造方法。 The method for producing a polycrystalline oxide semiconductor thin film according to claim 2 or 3 , wherein the baking is performed in an oxygen atmosphere. InとGaとZnの元素を含有する非晶質酸化物半導体からなる層を、その表面粗さRa値を1.5nm以下として維持しつつ多結晶化する温度領域660℃以上840℃以下で焼成して活性層とする工程を含んで、結晶化度が70%以上のIn−Ga−Zn−O系の透明酸化物である多結晶酸化物半導体からなる活性層とすることを特徴とする薄膜トランジスタの製造方法。   A layer made of an amorphous oxide semiconductor containing elements of In, Ga, and Zn is polycrystallized while maintaining its surface roughness Ra value of 1.5 nm or less, and fired in a temperature region of 660 ° C. or higher and 840 ° C. or lower. A thin film transistor comprising an active layer made of a polycrystalline oxide semiconductor that is an In—Ga—Zn—O-based transparent oxide having a crystallinity of 70% or more Manufacturing method. 前記活性層はInとGaとZnの元素を組成比(In:Ga:Zn)1:1:1で含有することを特徴とする請求項に記載の薄膜トランジスタの製造方法。 6. The method of manufacturing a thin film transistor according to claim 5 , wherein the active layer contains elements of In, Ga, and Zn at a composition ratio (In: Ga: Zn) of 1: 1: 1. 前記焼成は酸素を含む雰囲気中で行われることを特徴とする請求項又は請求項に記載の薄膜トランジスタの製造方法。 Method of manufacturing a thin film transistor according to claim 5 or claim 6 wherein the sintering is characterized by being carried out in an atmosphere containing oxygen.
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