KR102389220B1 - Thin film transistor including crystalline izto oxide semiconductor and fabrication method for the same - Google Patents

Abstract

A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor is connected to both ends of a gate electrode, a crystalline IZTO channel layer overlapping the upper or lower portions of the gate electrode, a gate insulating film disposed between the gate electrode and the IZTO channel layer, and the IZTO channel layer, respectively and source and drain electrodes.

Description

Thin film transistor having crystalline IZTO oxide semiconductor and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a transistor including an oxide semiconductor film.

As the silicon film used as the semiconductor film of the transistor, an amorphous silicon film or a polycrystalline silicon film is used depending on the purpose. For example, in the case of a transistor included in a large-sized display device, it is preferable to use an amorphous silicon film that can have relatively uniform characteristics even though it is formed in a large area. On the other hand, in the case of an element including a driving circuit or the like, it is preferable to use a polycrystalline silicon film capable of exhibiting high field-effect mobility. As a method for forming the polycrystalline silicon film, a method of heat-treating the amorphous silicon film at a high temperature or using a laser beam is known.

Recently, research using an oxide semiconductor as a channel layer of a transistor is being conducted (JP 2006-165528). However, it is known that the oxide semiconductor layer is mostly an amorphous layer and is not electrically and chemically stable.

An object of the present invention is to provide a thin film transistor having a polycrystalline oxide semiconductor thin film exhibiting high field-effect mobility.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, an aspect of the present invention provides a thin film transistor. The thin film transistor is connected to a gate electrode, a crystalline IZTO channel layer overlapping an upper or lower portion of the gate electrode, a gate insulating film disposed between the gate electrode and the IZTO channel layer, and both ends of the IZTO channel layer, respectively. and source and drain electrodes.

The IZTO channel layer may have polycrystalline properties. The IZTO channel layer may have spherulitic crystallites. The crystal grains may have a percolated shape.

The IZTO channel layer may have all three crystal phases of bixbite, spinel, and SnO ₂ . Specifically, the IZTO channel layer is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ 3 of It can have all of the crystal phases. As an example, the IZTO channel layer is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ may be contained in a molar ratio of 0.15 to 0.25, 0.55 to 0.65, and 0.15 to 0.25, respectively.

The IZTO channel layer may have a thickness of more than 10 nm. The IZTO channel layer may have a thickness of 17 to 35 nm.

In order to achieve the above object, an aspect of the present invention provides a crystalline IZTO manufacturing method. First, an amorphous IZTO layer is formed on a substrate. The amorphous IZTO layer is heat-treated at a heat treatment temperature of more than 600° C. and less than or equal to 1000° C. to change the amorphous IZTO layer into a crystalline IZTO layer.

The heat treatment temperature may be 650 to 900 ℃. The heat treatment may be performed in a state in which the amorphous IZTO layer is exposed to atmosphere, oxygen, or vacuum atmosphere.

The crystalline IZTO layer may have a form in which spherulitic crystallites are percolated. The crystalline IZTO layer is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ Each of 0.15 to It may be contained in a molar ratio of 0.25, 0.55 to 0.65, and 0.15 to 0.25. The crystalline IZTO layer may have a thickness of 17 to 35 nm.

In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a thin film transistor. The thin film transistor may include a gate electrode on a substrate; a channel layer overlapping an upper portion or a lower portion of the gate electrode; a gate insulating layer disposed between the gate electrode and the channel layer; and source and drain electrodes respectively connected to both ends of the channel layer. At this time, the channel layer is a crystalline IZTO layer, and the crystalline IZTO layer forms an amorphous IZTO layer, and then heat-treats the amorphous IZTO layer at a heat treatment temperature of more than 600 ° C. and less than 1000 ° C. to crystallize the amorphous IZTO layer. can be obtained

The heat treatment temperature may be 650 to 900 ℃. The crystalline IZTO layer may have a form in which spherulitic crystallites are percolated. The crystalline IZTO layer is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ Each of 0.15 to It may be contained in a molar ratio of 0.25, 0.55 to 0.65, and 0.15 to 0.25. The crystalline IZTO layer may have a thickness of 17 to 35 nm.

According to embodiments of the present invention, it is possible to provide a thin film transistor having a crystalline oxide semiconductor thin film exhibiting high field-effect mobility.

However, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.
2 is a graph showing transfer characteristics of TFTs according to TFT Preparation Examples 1, 2, and 4. Referring to FIG.
3 shows XRD patterns of IZTO films according to TFT Preparation Examples 1 to 5.
4 shows field emission scanning electron microscope (FE-SEM) images of IZTO films according to TFT Preparation Examples 4, 6 to 9, and 10 to 14;
5 shows a 1D GIXD (grazing-incidence X-ray diffraction) pattern according to the inclination angle of the IZTO film according to TFT Preparation Example 14.
6a shows a cross-sectional TEM image and electron diffraction pattern of the IZTO film according to TFT Preparation Example 7, and FIG. 6b is a planar TEM image (a), cross-sectional TEM image (b) and electrons of the IZTO film according to TFT Preparation Example 4 shows a diffraction pattern, Figure 6c shows an element mapping image of the IZTO film according to TFT Preparation Example 4, and Figure 6d is a cross-sectional TEM image and electron diffraction pattern of the IZTO film according to TFT Preparation Example 9 show
7 shows the transfer characteristics of TFTs according to TFT Preparation Examples 4 and 6 to 14 .
8 shows the transfer characteristics of TFTs according to TFT Preparation Examples 1, 4, 6 to 9 under a positive gate bias stress condition.
9 shows the transfer characteristics of TFTs according to TFT Manufacturing Examples 1, 4, 6 to 9 under a negative gate bias stress condition.

Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, when it is said that a layer is “on” another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In the present embodiments, "first", "second", or "third" is not intended to impose any limitation on the components, but should be understood as terms for distinguishing the components.

thin film transformer

1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 1 , a substrate 10 may be provided. The substrate 10 may be a semiconductor, metal, glass or polymer substrate. In one example, the substrate 10 may be a semiconductor or a metal substrate. An insulating barrier layer 11 may be formed on the substrate 10 . In one example, the substrate 10 may be a silicon substrate, and the insulating barrier layer 11 may be silicon oxide.

A gate electrode G extending in one direction may be formed on the substrate 10 . The gate electrode G may be formed using Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof. A gate insulating layer 30 may be formed on the gate electrode G. The gate insulating film 30 may include, for example, a silicon oxide film, SiO ₂ ; silicon oxynitride film (SiON); aluminum oxynitride film; a high-k insulating film having a higher dielectric constant compared to a silicon oxide film; Or it may be a composite film thereof. As an example of a high-k insulating film having a higher dielectric constant compared to a silicon oxide film, Al ₂ O ₃ , HfO ₂ , or ZrO ₂ may be used.

An indium-zinc-tin oxide layer (In-Zn-Sn oxide, hereinafter referred to as IZTO) disposed to overlap the gate electrode 20 on the gate insulating layer 30 may be formed as a channel layer CH .

The IZTO channel layer (CH) is a metal oxide layer containing indium, zinc, and tin, and may be an electron conductivity, that is, an N-type semiconductor layer. The IZTO semiconductor is polycrystalline, and may include spherulitic crystallites. Furthermore, the spherical crystal grains may have a 2D shape. The grains may be in a percolated form, that is, grain boundaries may be in contact with each other. In addition, the IZTO semiconductor may have all three crystal phases of bixbite, spinel, and SnO ₂ . Specifically, the IZTO semiconductor has three components: In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ . It may have all crystalline phases. In one example, IZTO contains 0.15 each of In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ , respectively. to 0.25, 0.55 to 0.65, and 0.15 to 0.25 in molar ratios. The IZTO channel layer (CH) may be formed to a thickness of several tens of nm, which is a thickness of more than 10 nm, for example, 15 to 70 nm, specifically, 17 to 35 nm. In this case, the spherulitic crystallites described above can be mainly grown on the surface of the channel layer in 2D, reducing the generation of grain boundaries in the thickness direction of the channel layer, improving the charge mobility, and also having low SS ( subthreshold swing) value.

The IZTO channel layer CH may be in an amorphous state in an as-deposited state. The IZTO channel layer (CH) may be formed using various methods used in the art, and specifically, a physical vapor deposition method such as sputtering or a chemical vapor deposition method such as a chemical vapor deposition method, an atomic layer deposition method It can be formed using . In one embodiment, the IZTO channel layer (CH) may be formed using a sputtering method using an IZTO target in an inert gas atmosphere. In addition, the IZTO channel layer (CH) may be patterned using various methods used in the art. The IZTO channel layer (CH) may be formed to a thickness of several tens of nm, for example, 15 to 70 nm, specifically 17 to 35 nm, which can reduce the generation of grain boundaries while sufficiently crystallizing in a heat treatment to be described later.

A source electrode (S) and a drain electrode (D) are formed on both ends of the IZTO channel layer (CH), and the IZTO channel layer (CH) is formed between the source electrode (S) and the drain electrode (D). Some surfaces may be exposed. The source electrode S and the drain electrode D may include at least one of aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo). As an example of a metal of or an alloy containing them, or a metal oxide conductive film, it may be formed using Indium Tin Oxide (ITO).

The substrate on which the source/drain electrodes S and D are formed may be heat-treated. In the heat treatment, the IZTO channel layer (CH) is exposed to the atmosphere, oxygen, or vacuum at a temperature of more than 600 ° C, a temperature of about 630 ° C to 1000 ° C, for example, about 650 to 900 ° C, specifically 670 to 730 °C. In the heat treatment process, the IZTO channel layer (CH) may be crystallized. Also, an ohmic junction between the source/drain electrodes S and D and the IZTO channel layer CH may be improved during the heat treatment process.

The thin film transistor illustrated in FIG. 1 has a bottom gate/top contact structure, but is not limited thereto, and a thin film transistor having a bottom gate/bottom contact structure, a top gate/top contact structure, or a top gate/bottom contact structure may also be implemented. In the top gate structure, the IZTO channel layer is disposed to overlap the gate electrode under the gate electrode, and in the bottom contact structure, the source/drain electrodes are located under the IZTO channel layer to be electrically connected to the IZTO channel layer. .

The n-type thin film transistor may constitute an inverter as an example of a complementary TFT circuit together with the p-type thin film transistor. In this case, the p-type thin film transistor may include a p-type oxide semiconductor as a channel layer, and the p-type oxide semiconductor may be SnO, Cu ₂ O, or NiO, but is not limited thereto.

In addition, the p-type thin film transistor may be used as a switching device electrically connected to a pixel electrode of an organic light emitting diode (OLED) or liquid crystal display, or as an example of a memory device, a resistance change memory (RRAM), a phase change RAM (PRAM) ), or may be used as a switching element electrically connected to one electrode of a magnetic RAM (MRAM). However, the present invention is not limited thereto.

Hereinafter, a preferred experimental example (example) is presented to help the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited by the following experimental examples.

TFT Manufacturing Examples 1

A 100 nm SiO ₂ layer as a gate insulating film was grown on the p-type Si wafer by thermal oxidation of a p-type Si wafer (<0.005 Ω·cm) as a gate electrode. A shadow mask was placed on the SiO ₂ layer, and an amorphous IZTO semiconductor pattern having the thickness indicated in Table 1 below was deposited using RF magnetron sputtering at room temperature. The sputtering IZTO target contains indium oxide (In ₂ O ₃ ), zinc oxide (ZnO) and tin oxide (SnO ₂ ) in a molar ratio of 1:4:4 (the cation atom percentage of In:Zn:Sn is 20:40:40). It was a compound composed of The RF power and operating pressure during sputtering were fixed at 50 W and 3 mtorr, respectively, under Ar atmosphere. A thin film transistor was formed by disposing a shadow mask on the amorphous IZTO semiconductor pattern and depositing the ITO pattern using sputtering in an Ar atmosphere to form source/drain electrodes on both ends of the IZTO semiconductor pattern. Thereafter, the thin film transistor was heat-treated at the temperature indicated in Table 1 below in an atmospheric atmosphere for the time indicated in Table 1 below. The channel width and channel length of the thin film transistor were 1,000 μm and 300 μm, respectively.

IZTO semiconductor pattern thickness crystallization heat treatment temperature crystallization heat treatment time TFT Preparation Example 1 19 nm 350 ℃ 1 hours TFT Preparation Example 2 19 nm 600 ℃ 1 hours TFT Preparation Example 3 19 nm 650 ℃ 1 hours TFT Preparation Example 4 19 nm 700 ℃ 1 hours TFT Preparation Example 5 19 nm 800℃ 1 hours TFT Preparation Example 6 5 nm 700 ℃ 1 hours TFT Preparation Example 7 10 nm 700 ℃ 1 hours TFT Preparation Example 8 30 nm 700 ℃ 1 hours TFT Preparation Example 9 50 nm 700 ℃ 1 hours TFT Preparation Example 10 5 nm 700 ℃ 4 hours TFT Preparation Example 11 10 nm 700 ℃ 4 hours TFT Preparation Example 12 19 nm 700 ℃ 4 hours TFT Preparation Example 13 30 nm 700 ℃ 4 hours TFT Preparation Example 14 50 nm 700 ℃ 4 hours

2 is a graph showing transfer characteristics of TFTs according to TFT Preparation Examples 1, 2, and 4. Referring to FIG.

Referring to FIG. 2 , a TFT (a) having an IZTO film of 19 nm annealed at 350° C. for 1 hour according to TFT Preparation Example 1 as a semiconductor layer had an average μFE value of 35.9 cm ² V ⁻¹ s ⁻¹ , SS is 0.24 V/decade, V _TH is -0.41V, and I _ON/OFF is 9.8 × 10 ⁸ . However, the TFT (b) having an IZTO film of 19 nm annealed at 600° C. for 1 hour according to TFT Preparation Example 2 as a semiconductor layer showed a μFE value similar to that of the TFT according to TFT Preparation Example 1, whereas I _ON/OFF was decreased significantly. As such, it was shown that the deterioration in the case of annealing at 600 °C is mainly related to the phase transition of the IZTO structure to the unintentionally doped phase. On the other hand, the TFT (c) having an IZTO film of 19 nm annealed at 700 ° C for 1 hour according to TFT Preparation Example 4 as a semiconductor layer had an average μFE value of 39.7 cm ² V ^-1 s ^-1 , and SS 0.26 V/ For a decade, V _TH shows -0.21V and I _ON/OFF shows 9.9 × 10 ⁸ , and it can be seen that the optimized transmission characteristics are shown.

3 shows XRD patterns of IZTO films according to TFT Preparation Examples 1 to 5.

Referring to FIG. 3 , it can be seen that the 19 nm thick IZTO film does not show X-ray diffraction peaks up to 600° C., indicating that it is an amorphous film that is not crystallized. It can be seen that the IZTO films annealed at a temperature of more than 650 °C and more than 700 °C were crystallized as they clearly showed X-ray diffraction peaks. In addition, the crystallized IZTO films had X-ray diffraction peaks corresponding to In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4) of Bixbyite structure derived from crystal grains and spinel X-ray diffraction peaks corresponding to the structure of Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45) were shown.

4 shows field emission scanning electron microscope (FE-SEM) images of IZTO films according to TFT Preparation Examples 4, 6 to 9, and 10 to 14;

Referring to FIG. 4 , the 5 nm thick IZTO films (a, f) according to TFT Preparation Examples 6 and 10 showed only small nanoparticles with a diameter of 10 to 20 nm because crystals were difficult to grow due to their very thin thickness. . As the film thickened, it can be seen that the major domains are connected to each other and grow laterally. The IZTO films (b, g) with a thickness of 10 nm according to TFT Preparation Examples 7 and 11 showed embedded sheaf-like crystal grains, and partially exhibited a crystalline structure. 30 nm thick IZTO films (d, i) according to TFT Preparation Examples 8 and 13, including a 19 nm thick IZTO film (c, h) according to TFT Preparation Examples 4 and 12, and TFT Preparation Examples 9 and 14 The 50 nm-thick IZTO films (e, j) according to Fig. 1 showed interconnected 2D spherulitic crystallites. On the other hand, as the annealing time was longer, the grain boundaries became clear and the grain boundary disloctoin defects appeared to increase.

5 shows a 1D GIXD (grazing-incidence X-ray diffraction) pattern according to the inclination angle of the IZTO film according to TFT Preparation Example 14.

Referring to FIG. 5 , it can be seen that the crystallized IZTO film exhibits three crystal phases, that is, SnO ₂ , In ₂ O ₃ and Zn ₂ SnO ₄ crystals. Specifically, Q exhibited anisotropic (not isotropic or Debye) X-ray reflection peaks at 1.540, 2.060, 2.372 and 2.475 Å ⁻¹ . It also showed X-ray reflection peaks when Q was 0.879 and 1.263 Å ⁻¹ and at high Q values of 2 Å ⁻¹ or higher. Such 1D GIXD appeared almost similarly in IZTO films having a height of 19 nm or more and heat-treated at 700 degrees or more for 1 hour or more.

6a shows a cross-sectional TEM image and electron diffraction pattern of the IZTO film according to TFT Preparation Example 7, and FIG. 6b is a planar TEM image (a), cross-sectional TEM image (b) and electrons of the IZTO film according to TFT Preparation Example 4 shows a diffraction pattern, Figure 6c shows an element mapping image of the IZTO film according to TFT Preparation Example 4, and Figure 6d is a cross-sectional TEM image and electron diffraction pattern of the IZTO film according to TFT Preparation Example 9 show

Referring to FIG. 6a, the IZTO film with a thickness of 10 nm annealed at 700 ° C. for 1 hour according to TFT Preparation Example 7 is partially crystalline as a diffused electron diffraction ring pattern appears in its cross section. appear. However, the crystal region clearly showed an aligned plane with a domain-spacing (d-spacing) of about 2.9 Å, which corresponds to that of d ₂₂₂ in the bixbite In ₂ O ₃ crystal.

Referring to FIG. 6b , it can be seen that the IZTO film having a thickness of 19 nm annealed at 700° C. for 1 hour according to TFT Preparation Example 4 is completely occupied by crystal grains. The highly oriented crystal planes in some grains had a d-spacing of 2.9 Å, which is attributed to d ₂₂₂ in the bixbite In ₂ O ₃ crystal. In some other grains, an additional crystal structure with a d-spacing of 2.6 Å appeared, which can be indexed as (311) of the spinel Zn ₂ SnO ₄ crystal. In some other grains, an additional crystal structure with a d-spacing of 3.4 Å appeared, which can be indexed as (110) of the SnO ₂ crystal.

Referring to FIG. 6c , the element mapping image through scanning TEM analysis clearly shows the distribution in which In, Zn, and Sn cations are evenly dispersed without being discernably separated. This is an unexpected result considering that In, Zn, and Sn cations have spatial non-uniformity when SnO ₂ , In ₂ O ₃ and Zn ₂ Sn ₁ O ₄ phases with finite crystal sizes coexist. Therefore, these results show that the chemical formulas of the bixbite and spinel phases, which are thermodynamically stable at high temperature, are not pure In ₂ O ₃ and Zn ₂ SnO ₄ but In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4) and Zn ₂ , respectively. It can be estimated to indicate that _-x Sn _1-x In _2x O ₄ (0≤x≤0.45). This is a sub-solid phase relationship in the InO _1.5 -ZnO-SnO ₂ system. In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4) is Zn and Sn co-dissolved on bixbyite In ₂ O ₃ , and two trivalent In cations (In ³⁺ ) are one divalent The cations Zn ²⁺ and one 4 are substituted with Sn ⁴⁺ cations, and Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45) is In dissolved on the spinel, and one The divalent cation Zn ²⁺ and one tetravalent Sn ⁴⁺ cation are substituted with two trivalent In cations (In ³⁺ ).

Referring to FIG. 6d , highly oriented crystal planes in some crystal grains of a 50 nm thick IZTO film annealed at 700° C. for 1 hour according to TFT Preparation Example 9 had a d-spacing of 4.12 Å, which was It is due to (211) in the _2-2x Zn _x Sn _x O ₃ crystal. In some other grains, additional crystal structures with a d-spacing of 4.3 Å appeared, which can be indexed as (200) of spinel Zn _2-x Sn _1-x In _2x O ₄ crystals. In some other grains, an additional crystal structure with a d-spacing of 6.6 Å appeared, which can be indexed as (110) of the SnO ₂ crystal.

In the IZTO film annealed at 700 °C, SnO ₂ , Bixbyite solid solution In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4) and spinel solid solution Zn _2-x Sn _1-x In _2x O ₄ (0≤x Based on the three-phase identification of ≤0.45), their mole fractions were estimated to be 0.20, 0.20 and 0.60, respectively, using the lever rule principle of the sub-solid ternary phase diagram. The average grain size in the vertical direction for the crystalline IZTO film was calculated from full-width-at-half-maximum (FWHM) using Scherrer's formula (D = kλ/βcosθ), and the average grain size in the vertical direction (average grain size) is shown in Table 2 below.

700 degree heat treatment time (h) 19 nm thick IZTO 50 nm thick IZTO One [Production Example 4]
11.9 nm [Production Example 9]
18.2 nm 4 [Production Example 12]
10.1 nm [Production Example 14]
16.8 nm

7 shows the transfer characteristics of TFTs according to TFT Preparation Examples 4 and 6 to 14 .

In addition, Table 3 below summarizes the electrical characteristics of TFTs according to TFT Preparation Examples 4 and 6 to 14.

IZTO
thickness heat treatment
time μFE
(cm ² V ^-1 s ^-1 ) SS
(Vdecade ^-1 ) V _TH
(V) I _ON/OFF NT, max
(cm ^-3 eV ^-1 ) Preparation 6 5 nm 1 h 16.6 0.50 0.3 9.75 × 10 ⁷ 3.7 × 10 ¹⁸ Preparation 10 5 nm 4 h 15.8 0.53 0.1 9.34 × 10 ⁷ 3.9 × 10 ¹⁸ Preparation 7 10 nm 1 h 24.2 0.59 1.0 4.00 × 10 ⁸ 2.2 × 10 ¹⁸ Preparation 11 10 nm 4 h 22.4 0.55 0.6 4.04 × 10 ⁸ 2.0 × 10 ¹⁸ Preparation 4 19 nm 1 h 39.7 0.26 -0.2 9.70 × 10 ⁸ 5.0 × 10 ¹⁷ Preparation 12 19 nm 4 h 39.7 0.27 -0.7 9.32 × 10 ⁸ 5.2 × 10 ¹⁷ Preparation 8 30 nm 1 h 39.7 0.46 -1.3 9.24 × 10 ⁸ 5.6 × 10 ¹⁷ Preparation 13 30 nm 4 h 39.9 0.42 -2.1 9.43 × 10 ⁹ 5.1 × 10 ¹⁷ Preparation 9 50 nm 1 h 34.9 0.97 -4.0 9.75 × 10 ⁸ 7.1 × 10 ¹⁷ Preparation 14 50 nm 4 h 36.5 0.97 -4.2 9.86 × 10 ⁸ 7.1 × 10 ¹⁷

Referring to FIG. 7 and Table 3, it can be seen that the change in electrical performance according to the annealing time at each thickness is not large. It can be seen that the partially crystallized TFT having a 10 nm thick IZTO film (Preparation Examples 7 and 11) has somewhat improved electrical properties compared to TFTs having an amorphous 5 nm thick IZTO film (Preparation Examples 6 and 10). Among the polycrystalline IZTO films with percolated spherulites, the TFTs having an IZTO film with a thickness of 19 nm (Preparation Examples 4 and 12) showed a μFE value of about 39.7 cm ² V ^-1 s ^-1 . This is 2.4 times higher than that of a TFT having an a-IZTO film (TFT Preparation Example 6). In addition, in the TFT having an IZTO film having a thickness of 19 nm or more as a channel layer (Preparation Examples 4, 8-9, and 12-14), the high-speed bulk trap (N _T ) exhibits a value of less than 10 ¹⁸ , and thus 19- A TFT having an IZTO film having a thickness of 30 nm as a channel layer (Preparation Examples 4, 8, and 12-13) may exhibit an SS value of less than 0.5. In addition, a TFT having an IZTO film having a thickness of 19 nm or more as a channel layer shows an I _ON/OFF value of 9 × 10 ⁸ or more, which is an IZTO film having a thickness of 5 nm or a partially crystallized IZTO film having a thickness of 10 nm It is larger than TFT provided as a channel layer. This may mean that grain boundary defects do not significantly cause leakage current in the polycrystalline IZTO film compared to the polycrystalline Si film. This was understood because the band gap of the polycrystalline IZTO film was greater than 3 eV.

On the other hand, the NT value of the 30 nm and 50 nm thick _IZTO FETs is slightly higher than the NT value of the 19 nm thick _IZTO FET. I can understand. On the other hand, in the 19 nm thick IZTO, mainly 2D-shaped spherical phases were grown.

8 shows the transfer characteristics of TFTs according to TFT Preparation Examples 1, 4, 6 to 9 under a positive gate bias stress condition. A positive gate bias stress (PBS) was applied for the indicated time at a gate bias of V _TH + 20 V and a drain bias of 5.1 V.

Referring to Figure 8, TFT (a) according to Preparation Example 1 having an IZTO film of 19 nm thickness annealed at 350 ° C. for 1 hour, having an IZTO film of 5 nm thickness annealed at 700 ° C. for 1 hour Compared to the TFT (c) according to Preparation Example 7 having a TFT (b) according to Preparation Example 6, and a 10 nm thick IZTO film annealed at 700° C. for 1 hour, 19 nm thick annealed at 700° C. for 1 hour TFT according to Preparation Example 4 having an IZTO film of (d), a TFT according to Preparation Example 8 having a 30 nm thick IZTO film annealed at 700° C. for 1 hour (e), and at 700° C. for 1 hour It can be seen that the TFT (f) according to Preparation Example 9 having an annealed 50 nm-thick IZTO film has little V _TH change even with a positive gate bias stress. It was understood that this excellent PBS stability was due to the crystallization effect.

9 shows the transfer characteristics of TFTs according to TFT Manufacturing Examples 1, 4, 6 to 9 under a negative gate bias stress condition. A negative gate bias stress (NBS) was applied for the indicated time at a gate bias of V _TH - 20 V and a drain bias of 5.1 V.

Referring to FIG. 9, TFT (a) according to Preparation Example 1 having an IZTO film of 19 nm thickness annealed at 350 ° C. for 1 hour (a), an IZTO film of 5 nm thickness annealed at 700 ° C. for 1 hour Compared to the TFT (c) according to Preparation Example 7 having a TFT (b) according to Preparation Example 6, and a 10 nm thick IZTO film annealed at 700° C. for 1 hour, 19 nm thick annealed at 700° C. for 1 hour TFT according to Preparation Example 4 having an IZTO film of (d), a TFT according to Preparation Example 8 having a 30 nm thick IZTO film annealed at 700° C. for 1 hour (e), and at 700° C. for 1 hour It can be seen that the TFT (f) according to Preparation Example 9 having an annealed 50 nm-thick IZTO film has little V _TH change even under negative gate bias stress. It was understood that this excellent NBS stability was due to the crystallization effect.

On the other hand, due to crystallization at 700 °C, the optical bandgap (EG) increased from 2.84 eV (a-IZTO film) to 3.22 eV, meaning that the ECBM or EVBM was changed by 0.35 eV.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes are made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims (22)

gate electrode;
a crystalline IZTO channel layer overlapping the upper or lower portions of the gate electrode;
a gate insulating film disposed between the gate electrode and the IZTO channel layer; and
Including source and drain electrodes respectively connected to both ends of the IZTO channel layer,
The IZTO channel layer is a thin film transistor having all three crystal phases of bixbite, spinel, and SnO ₂ . delete According to claim 1,
The IZTO channel layer is a thin film transistor having 2D-shaped spherulitic crystallites. 4. The method of claim 3,
The crystal grains are thin film transistors having a percolation shape. delete According to claim 1,
The bixbite crystal phase is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4),
The spinel crystal phase is Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45) thin film transistor. 7. The method of claim 6,
The IZTO channel layer is In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45), and SnO ₂ Each of 0.15 to A thin film transistor containing a molar ratio of 0.25, 0.55 to 0.65, and 0.15 to 0.25. According to claim 1,
The IZTO channel layer is a thin film transistor having a thickness of more than 10nm. According to claim 1,
The IZTO channel layer is a thin film transistor having a thickness of 17 to 35nm. forming an amorphous IZTO layer on a substrate;
Heat treatment of the amorphous IZTO layer at a heat treatment temperature of 680° C. to 800° C. to convert the amorphous IZTO layer into a crystalline IZTO layer having all three crystalline phases of bixbite, spinel, and SnO ₂ A crystalline IZTO manufacturing method comprising the steps of: . delete 11. The method of claim 10,
The heat treatment is a crystalline IZTO manufacturing method in which the amorphous IZTO layer is exposed to the atmosphere, oxygen, or vacuum atmosphere. 11. The method of claim 10,
The crystalline IZTO layer is a crystalline IZTO manufacturing method having a form in which 2D spherulitic crystallites are percolated. 11. The method of claim 10,
The crystalline IZTO layer is the bixbite crystal phase of In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), the spinel crystal phase of Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45) ), and SnO ₂ A method for producing crystalline IZTO containing 0.15 to 0.25, 0.55 to 0.65, and 0.15 to 0.25 molar ratio, respectively. 11. The method of claim 10,
The crystalline IZTO layer is a crystalline IZTO manufacturing method having a thickness of 17 to 35nm. a gate electrode on the substrate; a channel layer overlapping an upper portion or a lower portion of the gate electrode; a gate insulating layer disposed between the gate electrode and the channel layer; And in forming a thin film transistor comprising source and drain electrodes respectively connected to both ends of the channel layer,
The channel layer is a crystalline IZTO layer,
The crystalline IZTO layer is
forming an amorphous IZTO layer; and
The amorphous IZTO layer is heat treated at a heat treatment temperature of 650° C. to 800° C. to transform the amorphous IZTO layer into a crystalline IZTO layer having all three crystal phases of bixbite, spinel, and SnO ₂ A thin film formed including a crystallization step Transistor manufacturing method. delete 17. The method of claim 16,
The crystalline IZTO layer is a thin film transistor manufacturing method having a form in which 2D spherulitic crystallites are percolated. 17. The method of claim 16,
The crystalline IZTO layer is the bixbite crystal phase of In _2-2x Zn _x Sn _x O ₃ (0≤x≤0.4), the spinel crystal phase of Zn _2-x Sn _1-x In _2x O ₄ (0≤x≤0.45) ), and SnO ₂ A thin film transistor manufacturing method containing 0.15 to 0.25, 0.55 to 0.65, and 0.15 to 0.25, respectively, in molar ratios. 17. The method of claim 16,
The crystalline IZTO layer is a thin film transistor manufacturing method having a thickness of 17 to 35 nm.
gate electrode;
a crystalline IZTO channel layer overlapping the upper or lower portions of the gate electrode;
a gate insulating film disposed between the gate electrode and the IZTO channel layer; and
Including source and drain electrodes respectively connected to both ends of the IZTO channel layer,
The IZTO channel layer is a thin film transistor having a crystal phase of In _2-2x Zn _x Sn _x O ₃ (0<x≤0.4) and/or Zn _2-x Sn _1-x In _2x O ₄ (0<x≤0.45). . 22. The method of claim 21,
The IZTO channel layer is a thin film transistor having a form in which 2D-shaped spherulitic crystallites are percolated.

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