TWI689096B - Metal oxide crystalline structure, and display panel circuit structure and thin film transistor having the same - Google Patents

Abstract

A metal oxide crystalline structure, a display panel circuit structure and a thin film transistor having the metal oxide crystalline structure are provided. The metal oxide crystalline structure includes indium (In), tin (Sn), gallium (Ga), and oxygen (O); wherein an atomic ratio of In: Sn: Ga: O is 2: 1: 1: 6, and the metal oxide crystalline structure has a crystalline unit cell of parallelepiped.

Description

Metal oxide crystal structure and circuit structure of display panel having the metal oxide crystal structure Thin film transistor

The invention generally relates to a metal oxide crystal structure and a circuit structure and a thin film transistor of a display panel having the metal oxide crystal structure. Specifically, the invention relates to a quaternary compound crystal unit and can be used as a metal oxide semiconductor The metal oxide crystal structure of the layer and the circuit structure and thin film transistor of the display panel having the metal oxide crystal structure.

Display panels generally use thin film transistors as pixel switching elements or current driving elements, so that pixels can be independently controlled to achieve the display effect. Thin-film transistors for display panels usually use a silicon-based active layer with low carrier mobility, which makes the operation speed lower and unstable. Furthermore, thin film transistors with silicon-based active layers are not suitable for the manufacture of large-size panels.

Furthermore, display panels generally use glass or plastic materials as substrates. Therefore, due to the melting point of the substrates used, high-temperature processes cannot be used in the manufacture of display panels, which greatly limits the selection and manufacture of active layer materials for thin-film transistors.

Therefore, it is one of the important issues to develop materials suitable for active layers of thin film transistors of display panels.

One object of the present invention is to provide a metal oxide structure having crystal units with optimized atomic structure geometry, which can be used as a metal oxide semiconductor layer suitable for thin film transistors.

In one embodiment, the present invention provides a metal oxide crystal structure, which includes indium, tin, gallium and oxygen atoms, wherein the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6, and the metal oxide The crystal structure has a crystal unit that is a diamond-shaped hexahedron.

Another object of the present invention is to provide a thin film transistor. The metal oxide semiconductor layer formed by a metal oxide crystal structure is used as an active layer of the thin film transistor, which can provide a high carrier mobility and is suitable for a display panel with a narrow frame. And sensor applications.

In another embodiment, the present invention provides a thin film transistor including a gate layer, a gate insulating layer, a metal oxide semiconductor layer and a source/drain layer, wherein the gate insulating layer is located on the gate layer; metal The oxide semiconductor layer is located on the gate insulating layer. The metal oxide semiconductor layer has a metal oxide crystal structure. The metal oxide crystal structure includes indium, tin, gallium, and oxygen atoms, and the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6, the metal oxide crystal structure has a crystalline unit of rhombic hexahedron; the source/drain layer is located on the metal oxide semiconductor layer.

In yet another embodiment, the present invention provides a thin film transistor including a metal oxide semiconductor layer, a source/drain doped layer, a gate insulating layer, a gate layer, and a source/drain layer, wherein the metal is oxidized The semiconductor layer has a metal oxide crystal structure, the metal oxide crystal structure includes indium, tin, gallium and oxygen atoms, and the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6, the metal oxide crystal structure The crystal unit is a diamond-shaped hexahedron; the source/drain doped layer is located on the metal oxide semiconductor layer; the gate insulating layer is located on the source/drain doped layer and is partially connected to the metal oxide semiconductor layer; the source The /drain layer is located on the gate insulating layer and is electrically connected to the source/drain doped layer.

In another embodiment, the present invention provides a thin film transistor including a first gate layer, a first gate insulating layer, a metal oxide semiconductor layer, a source/drain doped layer, and a second gate insulating layer , A second gate layer and a source/drain layer, wherein the first gate insulating layer is located on the first gate layer; the metal oxide semiconductor layer is located on the first gate insulating layer, and the metal oxide semiconductor layer has metal An oxide crystal structure. The metal oxide crystal structure includes indium, tin, gallium, and oxygen atoms, and the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6. The metal oxide crystal structure has a crystal unit of diamond Hexahedron; the source/drain doped layer is located on the metal oxide semiconductor layer; the second gate insulating layer is located on the source/drain doped layer and is partially connected to the metal oxide semiconductor layer corresponding to the first gate layer The second gate layer is located on the second gate insulating layer and corresponds to the first gate layer; the source/drain layer passes through the second gate insulating layer and is electrically connected to the source/drain doped layer.

In yet another embodiment, the present invention provides a circuit structure of a display panel, which includes a substrate and a plurality of thin film transistors, the substrate has a plurality of regions; the plurality of thin film transistors are respectively disposed in the plurality of regions, and the plurality of thin film transistors Each has a metal oxide semiconductor layer, and the metal oxide semiconductor layer is selected from a crystalline indium gallium zinc oxide semiconductor layer, a crystalline indium tin gallium oxide semiconductor layer, and a combination thereof, wherein indium in the crystalline indium tin gallium oxide semiconductor layer: The atomic ratio of tin:gallium:oxygen is 2:1:1:6, and the crystalline indium tin gallium oxide semiconductor layer has a crystal unit of rhombic hexahedron.

In one embodiment, the metal oxide crystal structure includes a plurality of crystalline units with a rhombic shape stacked up.

In one embodiment, the metal oxide crystal structure includes a plurality of crystalline units arranged in a rhombic shape.

In one embodiment, the lengths a, b, and c of the three sides of the rhombic hexahedron are 6.00 ±10% Å, 6.71±10% Å, 3.48±10% Å, and the three included angles α, β, γ of the three edges are 89.9964±10% degrees, 89.9986±10% degrees, 72.6328±10% degrees, respectively.

In one embodiment, the plurality of thin film transistors include at least one of bottom gate transistors, top gate transistors, and double gate transistors.

In one embodiment, the thin film transistor of the present invention further includes a crystalline indium gallium zinc oxide semiconductor layer, wherein the crystalline indium gallium zinc oxide semiconductor layer is located between the gate insulating layer and the source/drain layer.

In one embodiment, the crystalline indium gallium zinc oxide semiconductor layer is located between the metal oxide semiconductor layer and the gate insulating layer.

Compared with the conventional technology, the metal oxide crystal structure of the present invention has a crystalline unit with an atomic structure geometry optimization viewpoint, has high stability and high carrier mobility, is suitable for thin-film transistors of display panels, and is suitable for narrow-frame display panels And can be matched with other metal oxide layers. It should be used in circuits in different areas of the display panel to use the characteristics of different metal oxides to optimize the function of each device, such as reducing power consumption and increasing the ability to block moisture. .

1‧‧‧Metal oxide crystal structure

10, 10’, 10” ‧‧‧ thin film transistor

12‧‧‧ substrate

14‧‧‧Amorphous metal oxide layer

16, 16’‧‧‧ heat transfer layer

20‧‧‧Double gate transistor

30‧‧‧Display circuit structure

31‧‧‧ Gate drive array area

32‧‧‧ Peripheral circuit area

33‧‧‧Pixel area

100‧‧‧ substrate

110‧‧‧Gate layer

115‧‧‧crystalline indium gallium zinc oxide semiconductor layer

120‧‧‧Gate insulation

130‧‧‧Metal oxide semiconductor layer

140‧‧‧ source/drain layer

142‧‧‧Source

144‧‧‧ Jiji

150‧‧‧Amorphous silicon layer

152‧‧‧Doped source region

154‧‧‧ Drain doped region

162‧‧‧Silicon oxide layer

164‧‧‧Amorphous silicon layer

170‧‧‧Insulation

210‧‧‧First gate layer

220‧‧‧Second gate layer

230‧‧‧ First gate insulating layer

232‧‧‧Lower gate insulating layer

234‧‧‧Upper gate insulating layer

240‧‧‧Second gate insulating layer

300a~300c‧‧‧thin film transistor

310‧‧‧Gate

320‧‧‧Gate insulation

332‧‧‧crystalline indium tin gallium oxide semiconductor layer

334‧‧‧crystalline indium gallium zinc oxide semiconductor layer

350‧‧‧ source/drain doped layer

360‧‧‧Inert layer

FIG. 1A is a schematic diagram of a metal oxide crystal structure according to an embodiment of the invention.

FIG. 1B is a schematic diagram of a diamond hexahedron of the metal oxide crystal structure of FIG. 1A.

2A and 2B are schematic diagrams showing different embodiments of forming the metal oxide crystal structure of the present invention.

3A to 3C respectively show crystalline metal oxide layer after the heat treatment of different chemical composition schematic energy, wherein the heat treatment energy 3A to 3C were ^{160mJ / cm 2, 200mJ / cm} 2 and 240mJ / cm ^2.

4A and 4B show XRD and SAED diagrams of the amorphous indium tin gallium oxide semiconductor layer, respectively.

5A and 5B respectively show XRD and SAED diagrams of the crystalline indium tin gallium oxide semiconductor layer of the present invention.

6 is an EDX diagram of the crystalline indium tin gallium oxide semiconductor layer of the present invention.

7 shows a cross-sectional HRTEM image of the crystalline indium tin gallium oxide semiconductor layer of the present invention.

FIG. 8 shows a top-view HRTEM image of the crystalline indium tin gallium oxide semiconductor layer of the present invention.

9A and 9B show a schematic side view and a schematic top view of the crystalline indium tin gallium oxide structure of the present invention.

10A and 10B are schematic diagrams of thin film transistors of various embodiments of the present invention.

11 is a schematic diagram of a thin film transistor according to another embodiment of the invention.

12 is a schematic diagram of a thin film transistor according to another embodiment of the invention.

13 is a schematic diagram of a circuit structure of a display panel according to an embodiment of the invention.

The invention provides a metal oxide crystal structure and a circuit structure and a thin film transistor of a display panel having the metal oxide crystal structure. The metal oxide semiconductor layer formed by the metal oxide crystal structure serves as an active layer of the thin film transistor , Can provide high mobility, suitable for narrow border display panel and sensor applications. Hereinafter, the details of the metal oxide crystal structure, the circuit structure of the display panel having the metal oxide crystal structure and the thin film transistor according to the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1A is a schematic diagram of a metal oxide crystal structure according to an embodiment of the invention. As shown in FIG. 1A, the metal oxide crystal structure 1 includes indium (In), tin (Sn), gallium (Ga), and oxygen (O) atoms, where the atomic ratio of indium: tin: gallium: oxygen is 2: 1: 1:6. The metal oxide crystal structure 1 has a crystal unit cell (rhombic hexahedron). That is, the crystal unit of the metal oxide crystal structure 1 is an indium tin gallium oxide (In ₂ SnGaO ₆ , ITGO) quaternary compound containing two indium atoms, one tin atom, one gallium atom, and six oxygen atoms, and It has a rhombic hexahedral structure. FIG. 1B is a schematic diagram of a diamond hexahedron of the metal oxide crystal structure of FIG. 1A. As shown in FIG. 1B, the lengths of the triangular edges a, b, and c of the rhombic hexahedron are preferably about 6.00±10% Å, 6.71±10% Å, and 3.48±10% Å, respectively. The angles α, β, and γ are preferably about 89.9964±10% degrees, 89.9986±10% degrees, 72.6328±10% degrees, where γ is the angle between edges a and b; β is the angle between edges a and c ; Α is the angle between edges b and c.

2A and 2B are schematic diagrams showing different embodiments of forming the metal oxide crystal structure of the present invention. As shown in FIG. 2A, in one embodiment, an amorphous metal oxide layer 14 is first formed on the substrate 12. The amorphous metal oxide layer 14 can be formed on the substrate 12 by methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, and the like. The substrate 12 may be, for example, a glass substrate, a plastic substrate, a quartz substrate, etc., but it is not limited thereto. Next, a heat transfer layer 16 is formed on the amorphous metal oxide layer 14, and then heat treatment is performed so that the amorphous metal oxide layer 14 is converted into a crystalline metal oxide layer. In this embodiment, the metal oxide layer 14 is preferably an indium tin gallium oxide semiconductor layer. For example, a target material of indium tin gallium oxide is selected, and an amorphous indium tin gallium oxide semiconductor layer (ie, an amorphous metal oxide layer 14) is formed on the substrate 12 by physical vapor deposition. Next, for example, a silicon oxide layer 162 and an amorphous silicon layer 164 are formed on the amorphous indium tin gallium oxide semiconductor layer as the heat transfer layer 16. Then, the amorphous silicon layer 164 and silicon oxide are heat-treated by excimer laser annealing (ELA) A substrate in which the layer 162 and the amorphous indium tin gallium oxide semiconductor layer (ie, the amorphous metal oxide layer 14) are stacked so that the amorphous indium tin gallium oxide semiconductor layer has sufficient heat to be converted into crystalline indium tin gallium An oxide semiconductor layer (ie, a crystalline metal oxide layer).

As shown in FIG. 2B, in another embodiment, another heat transfer layer 16' may be formed between the amorphous metal oxide layer 14 and the substrate 12, so that the amorphous metal oxide layer 14 has both above and below The heat transfer layers 16, 16' can enhance the heat transfer during heat treatment. For example, before forming the amorphous indium tin gallium oxide semiconductor layer of FIG. 2A, a silicon oxide layer may be formed on the substrate 12 as a heat transfer layer 16' under the amorphous indium tin gallium oxide semiconductor layer. Next, similar to the embodiment of FIG. 2A, an amorphous indium tin gallium oxide semiconductor layer, a silicon oxide layer 162, and an amorphous silicon layer 164 are sequentially formed on the heat transfer layer 16' (i.e., the silicon oxide layer) on the substrate 12. Then, the amorphous silicon layer 164, the silicon oxide layer 162, the amorphous indium tin gallium oxide semiconductor layer (ie, the amorphous metal oxide layer 14) and the silicon oxide layer (ie The heat transfer layer 16') is stacked on the substrate 12 so that the amorphous indium tin gallium oxide semiconductor layer has sufficient heat to be converted into a crystalline indium tin gallium oxide semiconductor layer.

It should be noted here that the amorphous metal oxide layer 14 is heat-treated to form a crystalline metal oxide layer in the manner described in FIG. 2A or FIG. 2B. The process temperature can be controlled at a lower temperature (preferably the substrate 12 (Below the melting point, for example, below several hundred degrees Celsius), so that the amorphous metal oxide layer 14 has sufficient heat to be converted into a crystalline metal oxide layer and will not peel off from the substrate 12 due to overheating, while also ensuring that, for example, a glass substrate or plastic The substrate 12 having a lower melting point, such as a substrate, is not damaged due to overheating.

3A to 3C respectively show crystalline metal oxide layer after the heat treatment of different chemical composition schematic energy, wherein the heat treatment energy 3A to 3C were ^{160mJ / cm 2, 200mJ / cm} 2 and 240mJ / cm ^2. As shown in FIGS. 3A to 3C, after the amorphous metal oxide layer 14 is converted into a crystalline metal oxide layer using the method of FIG. 2B, even under different heat treatment conditions, the chemical composition of the metal oxide layer after crystallization is substantially insignificant change.

4A and 4B respectively show X-ray diffraction analysis (X-ray diffraction (XRD) and selected area electron diffraction analysis (SAED) diagrams of the amorphous indium tin gallium oxide semiconductor layer. 5A and 5B respectively show XRD and SAED diagrams of the crystalline indium tin gallium oxide semiconductor layer of the present invention. It can be seen from the comparison between FIGS. 4A and 4B and FIGS. 5A and 5B that the crystalline indium tin gallium oxide semiconductor layer has a more obvious characteristic distribution than the amorphous indium tin gallium oxide semiconductor layer.

6 is a diagram of energy dispersive X-ray spectroscopy (EDX) of the crystalline indium tin gallium oxide semiconductor layer of the present invention. According to EDX analysis, the atomic ratio of crystalline indium tin gallium oxide (ITGO) is about In:Sn:Ga:O=2:1:1:6.

Next, the first principle calculation is used to predict, establish, and find the atomic arrangement and cross-sectional characteristics of the surface of the indium tin gallium oxide to confirm that the crystal unit of the indium tin gallium oxide has a geometrically optimized atomic structure. For example, the PWSCF component in Quantum Espresso software is used to find the optimal stability of the crystal structure of In-Sn-Ga (indium tin gallium) oxide semiconductor, where the atomic ratio of In:Sn:Ga:O is 2:1 : 1:6. PWSCF is a first-principle electronic structure calculation program that describes the potential energy potential of electrons and atoms based on density functional theory (DFT), plane wave basis sets and pseudopotentials approximation methods. The calculation parameter setting of PWSCF chooses the Perdew-Burke-Emzerhof (PBE) exchange-dependent energy functional of general gradient approximation (GGA). The cut-off energy is set to 680eV, and an 11x11x11 K-point grid is used. The convergence conditions for relaxation of molecular structure optimization require each atom The force is less than 0.5meV/A. Fig. 1A shows a crystalline unit of an indium tin gallium oxide semiconductor obtained by computational relaxation optimization.

Furthermore, the calculation is performed using an enlarged cell lattice containing 80 atoms (2x1x4), and the first-principle calculation parameter setting also uses generalized gradient approximation (GGA) PBE exchange-related energy functionals with the cell lattice. The cut-off energy is set to 680 eV and the convergence conditions optimized for molecular structure relaxation require that the force per atom is less than 0.5 meV/A and use a 1x3x1 K-dot grid.

7 shows a cross-sectional high-resolution transmission electron micrograph (HRTEM) image of the crystalline indium tin gallium oxide semiconductor layer of the present invention. As shown in FIG. 7, the lattice spacing (d-spacing) is about 2.97 nm/10 layers and 2.74 nm/10 layers (ie, 2.97 Å and 2.74 Å), which is consistent with the calculated cross-sectional results.

FIG. 8 shows a top-view HRTEM image of the crystalline indium tin gallium oxide semiconductor layer of the present invention. As shown in Figure 8, the lattice spacing is about 2.53nm/10 layers (ie 2.53Å), which is in agreement with the calculated cross-sectional results.

9A and 9B show a schematic side view and a schematic top view of the crystalline indium tin gallium oxide structure of the present invention. As shown in FIGS. 9A and 9B, the first principle calculation and the material structure analysis of the various crystalline indium tin gallium oxides above can confirm the indium: tin: gallium: oxygen of the indium tin gallium oxide crystal structure of the present invention The atomic ratio is 2:1:1:6, and the indium tin gallium oxide crystal structure has a rhombohedral crystalline unit, and the lengths of the three edges a, b, and c of the rhombic hexahedron are about 6.00±10, respectively. % Å, 6.71±10% Å, 3.48±10% Å, and the three included angles α, β, γ of the three edges are about 89.9964±10% degrees, 89.9986±10% degrees, 72.6328±10% degrees, respectively. Furthermore, the crystal unit of the metal oxide (ie, indium tin gallium oxide) crystal structure is a rhombic hexahedron, and a plurality of crystal units are stacked in a rhombic shape and arranged in a rhombic shape.

The crystalline metal oxide structure of the present invention can be applied to thin film transistor devices. Please refer to FIG. 10A, which is a schematic diagram of a thin film transistor according to an embodiment of the present invention. As shown in FIG. 10A, the thin film transistor 10 has a bottom gate transistor structure, which includes a gate layer 110, a gate insulating layer 120, a metal oxide semiconductor layer 130, and a source/drain layer 140. The gate layer 110 is located on the substrate 100. The gate insulating layer 120 is located on the gate layer 110. The metal oxide semiconductor layer 130 is located on the gate insulating layer 120. The source/drain layer 140 is located on the metal oxide semiconductor layer 130. In this embodiment, the metal oxide semiconductor layer 130 has a metal oxide crystal structure. Similar to the embodiment shown in FIG. 1A above, in this embodiment, the metal oxide crystal structure includes indium, tin, gallium, and oxygen atoms, wherein the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6 , And the crystal structure of the metal oxide has a crystal unit of rhombic hexahedron. In other words, in this embodiment, the metal oxide semiconductor layer 130 is preferably an indium tin gallium oxide semiconductor layer having the indium tin gallium oxide crystal structure shown in the embodiment of FIG. 1A.

Specifically, the thin film transistor 10 is fabricated on the substrate 100, and the substrate 100 may be a transparent substrate such as glass, polymer, quartz, or the like. The gate layer 110 is preferably a metal layer, such as tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), or alloys thereof. The gate insulating layer 120 may directly cover the gate layer 110, and the gate insulating layer 120 may include silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto. The metal oxide semiconductor layer 130 may be formed on the gate insulating layer 120 by, for example, the method described in FIG. 2A or FIG. 2B. In this embodiment, the metal oxide semiconductor layer 130 is a crystalline indium tin gallium oxide semiconductor layer containing indium, tin, gallium, and oxygen atoms as an active layer of the thin film transistor. As shown in the embodiment of FIG. 1A above, the atomic ratio of indium:tin:gallium:oxygen in the crystalline indium tin gallium oxide semiconductor layer is 2:1:1:6, and it is indium with a crystalline unit of rhombic hexahedron Tin gallium oxide crystal structure. The lengths of the three sides a, b, and c of the rhombohedron are 6.00±10% Å, 6.71±10% Å, 3.48±10% Å, and the three included angles α, β, γ of the three edges are 89.9964±10% degrees, 89.9986±10% degrees, 72.6328±10% degrees, respectively. The metal oxide (eg, indium tin gallium oxide) crystal structure includes a plurality of crystalline unit rhombic stacked upward, and the plurality of crystalline units are arranged in a rhomboid. The source and drain layers 140 include a source electrode 142 and a drain electrode 144, and may be composed of metallic materials or non-metallic conductive materials. In an embodiment, the metal material includes, for example, tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), or alloys thereof, but not limited thereto. In another embodiment, the non-metallic conductive material includes, for example, indium tin oxide, but not limited thereto. In one embodiment, the thin film transistor 10 of the present invention may further include an amorphous silicon layer 150, wherein the amorphous silicon layer 150 is located on the metal oxide semiconductor layer 130 to serve as a doped region of the source electrode 142 and the drain electrode 144, For example, n+ or p+ doped amorphous silicon source doped region 152 and drain doped region 154.

Please refer to FIG. 10B, which is a schematic diagram of a thin film transistor according to another embodiment of the present invention. As shown in FIG. 10B, the difference between the thin film transistor 10' of the present invention and the embodiment of FIG. 10A is that it further includes a crystalline indium gallium zinc oxide (IGZO) oxide semiconductor layer 115, wherein the crystalline indium gallium zinc oxide semiconductor layer 115 is located at the gate Between the insulating layer 120 and the source/drain layer 140. Specifically, the crystalline indium gallium zinc oxide semiconductor layer 115 is located between the metal oxide semiconductor layer 130 (for example, the crystalline indium tin gallium oxide semiconductor layer) and the gate insulating layer 120, so that the thin film transistor 10' has crystalline indium gallium The active layer of the double layer structure of the zinc oxide semiconductor layer 115 and the crystalline indium tin gallium oxide semiconductor layer (for example, 130) utilizes the characteristics of different metal oxides to achieve the optimization of the function of each device. For example, the crystalline indium tin gallium oxide semiconductor layer has a high carrier mobility (μ), and the crystalline indium gallium zinc oxide semiconductor layer 115 has a low off current (I _off ) to help reduce power consumption. Furthermore, the active layer design of the double-layer structure can increase the barrier ability of the thin film transistor 10' against moisture, which is beneficial to improve reliability.

It should be noted here that depending on the actual application, the indium gallium zinc oxide semiconductor layer The gallium oxide semiconductor layer can be crystallized by the same heat treatment process to simplify the manufacturing process and reduce the manufacturing cost. For example, after depositing the amorphous indium tin gallium oxide semiconductor layer, before performing the heat treatment process of crystallization, an amorphous indium gallium zinc oxide semiconductor layer may be formed on the amorphous indium tin gallium oxide semiconductor layer. Next, the amorphous indium gallium zinc oxide semiconductor layer and the amorphous indium tin gallium oxide semiconductor layer are simultaneously heat-treated in the manner as shown in FIG. 2A or FIG. 2B to form a crystalline indium gallium zinc oxide semiconductor layer and a crystalline indium tin gallium semiconductor layer, respectively The oxide semiconductor layer, but not limited to this.

Furthermore, please refer to FIG. 11, which is a schematic diagram of a thin film transistor according to another embodiment of the present invention. As shown in FIG. 11, the crystalline metal oxide semiconductor layer having the metal oxide crystal structure of the present invention can also be applied to top gate transistors. Specifically, in this embodiment, the top gate transistor 10" includes a substrate 100, an insulating layer 170, a metal oxide semiconductor layer 130, an amorphous silicon layer 150, a gate insulating layer 120, a gate layer 110 and a source Electrode/drain layer 140. Specifically, in this embodiment, the insulating layer 170 is located on the substrate 100. The metal oxide semiconductor layer 130 is located on the insulating layer 170 as an active layer, and the metal oxide semiconductor layer 130 is preferred It is an indium tin gallium oxide semiconductor layer with an indium tin gallium oxide crystal structure as shown in the embodiment of FIG. 1A. The amorphous silicon layer 150 is located on the metal oxide semiconductor layer 130 as a source/drain doped layer, and The amorphous silicon layer 150 includes a source doped region 152 and a drain doped region 154. The gate insulating layer 120 is located on the amorphous silicon layer 150 and is partially connected to the metal oxide semiconductor layer 130 corresponding to the gate layer 110. The gate layer 110 Located on the gate insulating layer 120 and corresponding to the metal oxide semiconductor layer 130. The source/drain layer 140 includes a source 142 and a drain 144, and is electrically connected to the source doped region 152 and the drain through the gate insulating layer 120, respectively极平面区154.

It should be noted here that the material and structure details of the substrate 100, the metal oxide semiconductor layer 130, the amorphous silicon layer 150, and the source/drain layer 140 can refer to the relevant description of FIG. 10A, and the gate The layer 110 may include metallic or non-metallic conductive materials, such as tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo) or alloys thereof, indium tin oxide, or the like. The gate insulating layer 120 may be selected from one or more layers with a dielectric layer having a suitable dielectric constant, such as but not limited to: silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, the insulating layer 170 can also be selected from one or more layers with a dielectric layer having a suitable dielectric constant, such as but not limited to: silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the top gate transistor 10" uses an indium tin gallium oxide layer with a high carrier mobility as an active layer, which is suitable for a gate drive array (GOA) circuit to be oxidized by indium tin gallium The high carrier mobility of the object improves the performance of the transistor and is more suitable for narrow frame design.

In addition, please refer to FIG. 12, which is a schematic diagram of a thin film transistor according to another embodiment of the present invention. As shown in FIG. 12, the crystalline metal oxide semiconductor layer having the metal oxide crystal structure of the present invention can also be applied to a double gate transistor. Specifically, in this embodiment, the dual gate transistor 20 includes a substrate 100, a first gate layer 210, a second gate layer 220, a first gate insulating layer 230, a second gate insulating layer 240, The metal oxide semiconductor layer 130, the amorphous silicon layer 150, and the source/drain layer 140. Specifically, in this embodiment, the first gate layer 210 is located on the substrate 100. The first gate insulating layer 230 is located on the first gate layer 210, and the first gate insulating layer 230 may be a double-layer gate insulating layer structure including a lower gate insulating layer 232 and an upper gate insulating layer 234. The metal oxide semiconductor layer 130 is located on the first gate insulating layer 230 as an active layer, and the metal oxide semiconductor layer 130 is preferably indium tin gallium oxide having the indium tin gallium oxide crystal structure shown in the embodiment of FIG. 1A物电子层。 Material semiconductor layer. The amorphous silicon layer 150 is located on the metal oxide semiconductor layer 130 as a source/drain doped layer, and the amorphous silicon layer 150 includes a source doped region 152 and a drain doped region 154. The second gate insulating layer 240 is located on the amorphous silicon layer 150 and is partially connected to the metal oxide semiconductor layer 130 corresponding to the first gate layer 210. The second gate layer 220 is located on the second gate insulating layer 240 and corresponds to the first gate layer 210. The source/drain layer 140 includes a source 142 and a drain 144, and is electrically connected to the source doped region 152 and the drain doped region 154 through the second gate insulating layer 240, respectively.

It should be noted here that the material and structure details of the substrate 100, the metal oxide semiconductor layer 130, the amorphous silicon layer 150, and the source/drain layer 140 can refer to the relevant description of FIG. 10A, and the first gate layer 210 and the first The second gate layer 220 may include metallic or non-metallic conductive materials, such as tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo) or alloys thereof, or indium tin oxide. The lower gate insulating layer 232, the upper gate insulating layer 234, and the second gate insulating layer 240 under the first gate insulating layer 230 may be selected from dielectric layers with suitable dielectric constants, such as but not limited to: silicon oxide , Silicon nitride or silicon oxynitride. Furthermore, the second gate insulating layer 240 can also serve as an inert layer to protect the underlying layers (eg, the first gate layer 210, the first gate insulating layer 230, the metal oxide semiconductor layer 130, and the amorphous silicon layer 150 Wait). In this embodiment, the dual gate transistor 20 uses an indium tin gallium oxide layer with a high carrier mobility as an active layer, which is suitable for a gate drive array (GOA) circuit to enhance a display device (such as organic light emission) The control of the threshold voltage and on current of the diode display (OLED).

Furthermore, the metal oxide crystal structure of the present invention can be used in conjunction with other suitable metal oxide semiconductor layers to take advantage of the characteristics of different metal oxides to optimize the function of each device, such as reducing power consumption and increasing the barrier to moisture Ability etc. Please refer to FIG. 13, which is a schematic diagram of a circuit structure of a display panel according to an embodiment of the invention. As shown in FIG. 13, the circuit structure 30 of the display panel includes a substrate 100 and a plurality of thin film transistors 300a, 300b, and 300c. The substrate 100 has a plurality of regions (for example, 31, 32, and 33), and the plurality of thin film transistors 300a, 300b, and 300c are respectively disposed in the plurality of regions. Specifically, the plurality of regions of the substrate 100 may include, for example, the gate driving array region 31, the peripheral circuit region 32, the pixel region 33, and the like. The thin film transistors 300a, 300b, and 300c are respectively disposed in the gate driving array area 31, the peripheral circuit area 32, and the pixel area 33. Thin film The crystals 300a, 300b, and 300c include a gate layer 310, a gate insulating layer 320, at least one metal oxide semiconductor layer (eg, 332, 334), a source/drain doped layer 350, and an inert layer 360.

It should be noted here that the gate layer 310, the gate insulating layer 320, and the source/drain doped layer 350 are doped with the gate layer 110, the gate insulating layer 120 or 230, and the source/drain doped in the previous embodiment. The similar structure and function of the impurity layer (such as the amorphous silicon layer 150) will not be repeated here. The inert layer 360 covers the source/drain doped layer 350, and preferably includes an insulating material to protect the transistor. In addition, although the source/drain layer is not shown in this embodiment, similar to the embodiment of FIG. 12, the source/drain layer can be electrically connected to the source/drain doped layer 350 through the inert layer 360.

In this embodiment, the plurality of thin film transistors 300a, 300b, and 300c each have at least one metal oxide semiconductor layer (for example, 332, 334), and the metal oxide semiconductor layer is preferably selected from a crystalline indium gallium zinc oxide semiconductor layer , A crystalline indium tin gallium oxide semiconductor layer and a combination thereof, in which the atomic ratio of indium: tin: gallium: oxygen in the crystalline indium tin gallium oxide semiconductor layer is 2:1:1:6, and the crystalline indium tin gallium oxide semiconductor The layer has crystalline units that are rhombohedral. The lengths of the three edges a, b, and c of the rhombic hexahedron are 6.00±10% Å, 6.71±10% Å, and 3.48±10% Å, and the three included angles α, β, and γ of the three edges are respectively 89.9964±10% degree, 89.9986±10% degree, 72.6328±10% degree. In other words, at least one thin film transistor (eg, 300a, 300c) of the plurality of thin film transistors 300a, 300b, 300c preferably includes a crystalline indium gallium zinc oxide semiconductor layer having an indium tin gallium oxide crystal structure as shown in FIG. 1A .

For example, the thin film transistor 300a located in the gate driving array region 31 preferably has a crystalline indium tin gallium oxide semiconductor layer 332 as an active layer to improve the transistor performance by the high carrier mobility of indium tin gallium oxide , More suitable for narrow border design. The thin film transistor 300b located in the peripheral circuit area 32 preferably has a crystalline indium gallium zinc oxide semiconductor layer 334 as an active layer, so as to effectively reduce power consumption by the low off current characteristic of indium gallium zinc oxide. Furthermore, the thin film transistor 300c located in the pixel region 33 is preferably similar to the embodiment of FIG. 10B and is an active two-layer structure having a crystalline indium tin gallium oxide semiconductor layer 332 and a crystalline indium gallium zinc oxide semiconductor layer 334 In order to achieve high carrier mobility (μ) and low off current (I _off ), it is beneficial to improve the performance of transistors, reduce power consumption and increase the ability to block moisture to improve reliability.

It should be noted here that at least one metal oxide semiconductor layer (such as single-layer indium-gallium-zinc oxide or indium-tin-gallium oxide, or double-layer indium-gallium-zinc oxide and indium in the plurality of thin film transistors 300a, 300b, 300c Tin gallium oxide), one or two mask photolithography processes can be used to form the desired pattern of amorphous indium gallium zinc oxide semiconductor layer and amorphous indium tin gallium oxide semiconductor layer, and then the same heat treatment process (such as 2A or 2B) to form a single-layer or double-layer structure of a crystalline indium gallium zinc oxide semiconductor layer and a crystalline indium tin gallium oxide semiconductor layer.

In addition, in the embodiment of FIG. 13, the plurality of thin film transistors 300a, 300b, and 300c are described by taking the structure of the bottom gate transistor as an example, but it is not limited to this. In other embodiments, the plurality of thin film transistors 300a, 300b, and 300c may have a structure similar to the top gate transistor of FIG. 11 or the double gate transistor of FIG. In other words, the circuit structure 30 of the display panel may include a plurality of thin film transistors 300a, 300b, and 300c composed of at least one of a bottom gate transistor, a top gate transistor, and a double gate transistor.

The present invention has been described by the above-mentioned embodiments, however, the above-mentioned embodiments are for illustrative purposes only and not for limitation. Those skilled in the art should know that the embodiments specifically described herein may have other modifications of the illustrated embodiments without departing from the spirit of the present invention. Therefore, the scope of the present invention also covers such modifications and is only limited by the scope of the attached patent application.

1‧‧‧Metal oxide crystal structure

Claims (17)

A metal oxide crystal structure includes indium, tin, gallium and oxygen atoms, wherein: the atomic ratio of indium:tin:gallium:oxygen is 2:1:1:6, and the metal oxide crystal structure has a crystal unit as Rhombus hexahedron. The metal oxide crystal structure according to claim 1, wherein the metal oxide crystal structure includes a plurality of the crystal units with a rhombic shape stacked upward. The metal oxide crystal structure according to claim 1, wherein the metal oxide crystal structure comprises a plurality of rhombic arrangements of the crystal units. The metal oxide crystal structure according to any one of claims 1 to 3, wherein the lengths of the triangular edges a, b, and c of the rhombic hexahedron are 6.00±10% Å, 6.71±10% Å, 3.48 ±10% Å, and the three angles α, β, and γ of the three edges are 89.9964±10% degrees, 89.9986±10% degrees, and 72.6328±10% degrees, respectively. A thin film transistor, including: a gate layer; a gate insulating layer on the gate layer; a metal oxide semiconductor layer on the gate insulating layer, the metal oxide semiconductor layer has a metal oxide Crystal structure, wherein the metal oxide crystal structure includes indium, tin, gallium and oxygen atoms, and the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6, the metal oxide crystal structure has a crystal The unit is a diamond-shaped hexahedron; and a source/drain layer is located on the metal oxide semiconductor layer. A thin film transistor, including: a metal oxide semiconductor layer, the metal oxide semiconductor layer has a metal oxide crystal Structure, wherein the metal oxide crystal structure includes indium, tin, gallium and oxygen atoms, and the atomic ratio of indium:tin:gallium:oxygen is 2:1:1:6, the metal oxide crystal structure has a crystal unit as Diamond hexahedron; a source/drain doped layer on the metal oxide semiconductor layer; a gate insulating layer on the source/drain doped layer and partially connected to the metal oxide semiconductor layer A gate layer on the gate insulating layer corresponding to the metal oxide semiconductor layer; and a source/drain layer on the gate insulating layer and electrically connected to the source/drain doped layer. A thin film transistor includes: a first gate layer; a first gate insulating layer on the first gate layer; a metal oxide semiconductor layer on the first gate insulating layer, the metal The oxide semiconductor layer has a metal oxide crystal structure, wherein the metal oxide crystal structure includes indium, tin, gallium, and oxygen atoms, and the atomic ratio of indium: tin: gallium: oxygen is 2:1:1:6. The metal oxide crystal structure has a crystal unit as a diamond-shaped hexahedron; a source/drain doped layer on the metal oxide semiconductor layer; and a second gate insulating layer on the source/drain doped The metal oxide semiconductor layer is partially connected to the impurity layer and corresponds to the first gate layer; a second gate layer is located on the second gate insulating layer and corresponds to the first gate layer; and a source/drain The electrode layer is electrically connected to the source/drain doped layer through the second gate insulating layer. The thin film transistor according to any one of claims 5 to 7, wherein the metal oxide crystal structure includes a plurality of the crystalline unit rhombic stacked upward. The thin film transistor according to any one of claims 5 to 7, wherein the metal oxide crystal structure includes a plurality of rhombic arrangements of the crystal units. The thin film transistor according to any one of claims 5 to 7, wherein the lengths of the triangular edges a, b, and c of the rhombohedral hexahedron are 6.00±10% Å, 6.71±10% Å, and 3.48±10, respectively. % Å, and the three included angles α, β, and γ of the three edges are 89.9964±10% degrees, 89.9986±10% degrees, and 72.6328±10% degrees, respectively. The thin film transistor according to any one of claims 5 to 7, further comprising a crystalline indium gallium zinc oxide semiconductor layer, wherein the crystalline indium gallium zinc oxide semiconductor layer is located on the gate insulating layer and the source/drain Between polar layers. The thin film transistor according to claim 10, wherein the crystalline indium gallium zinc oxide semiconductor layer is located between the metal oxide semiconductor layer and the gate insulating layer. A circuit structure of a display panel includes: a substrate having a plurality of regions; and a plurality of thin-film transistors respectively disposed in the plurality of regions, and each of the plurality of thin-film transistors has a metal oxide semiconductor layer, and the The metal oxide semiconductor layer is selected from a crystalline indium gallium zinc oxide semiconductor layer, a crystalline indium tin gallium oxide semiconductor layer and combinations thereof, wherein the crystalline indium tin gallium oxide semiconductor layer indium: tin: gallium: oxygen The atomic ratio is 2:1:1:6, and the crystalline indium tin gallium oxide semiconductor layer has a crystal unit which is a rhombic hexahedron. The circuit structure of the display panel according to claim 13, wherein the crystalline indium tin gallium oxide semiconductor layer includes a plurality of crystalline unit rhombic stacked up. The circuit structure of the display panel according to claim 13, wherein the crystalline indium tin gallium oxide semiconductor The bulk layer includes a plurality of crystalline units arranged in a rhombic shape. The circuit structure of the display panel according to any one of claims 13 to 15, wherein the lengths of the triangular edges a, b, and c of the rhombic hexahedron are 6.00±10% Å, 6.71±10% Å, 3.48 ±10% Å, and the three angles α, β, and γ of the three edges are 89.9964±10% degrees, 89.9986±10% degrees, and 72.6328±10% degrees, respectively. The circuit structure of the display panel according to claim 13, wherein the plurality of thin film transistors include at least one of a bottom gate transistor, a top gate transistor, and a double gate transistor.

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