JP5946624B2 - Oxide semiconductor film and semiconductor device - Google Patents

Description

The present invention relates to an oxide semiconductor film and a semiconductor device including the oxide semiconductor film.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor is disclosed (see Patent Document 1).

JP 2006-165528 A

An oxide semiconductor (hereinafter referred to as IGZO) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) that can be used for an active layer of a transistor has a wider band gap than a silicon semiconductor. It has characteristics. However, since characteristics of IGZO change due to oxygen deficiency, improvement to an oxide semiconductor film that does not release oxygen is required. Further, although IGZO has a wider band gap than silicon, it is required to have a wider band gap in order to improve the breakdown voltage of the oxide semiconductor film and to suppress light degradation.

Thus, according to one embodiment of the present invention, an oxide semiconductor that can stabilize a bond of oxygen in an oxide semiconductor film and have a larger band gap than IGZO can be obtained by making the bond energy of a crystal structure larger than that of IGZO. Another object is to provide a film and a semiconductor device including the oxide semiconductor film.

One embodiment of the present invention is an oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen. In the crystal structure, lanthanum has a structure in which oxygen is 6-coordinated and indium has a structure in which oxygen is 5-coordinated. By using lanthanum in the crystal structure of the oxide semiconductor film, the oxide semiconductor film has a band gap larger than that of the oxide semiconductor film having a crystal structure containing indium, gallium, zinc, and oxygen, and the bond energy of the crystal structure is increased. It can be.

One embodiment of the present invention is an oxide semiconductor film including a crystal of the general formula In _x La _(2-x) Zn _y O _{3 + y} (x is a number greater than or equal to 1 and less than 2, y is a number greater than or equal to 1 and less than 6). .

One embodiment of the present invention has a crystal structure in which an indium oxide layer, a lanthanum oxide layer, and a zinc oxide layer are arranged in layers, and the general formula of the crystal structure is In _x La _(2-x) Zn _y O _{3 + y} (x Is an oxide semiconductor film having a number of 1 or more and less than 2, and y is a number of 1 or more and less than 6.

In one embodiment of the present invention, the lanthanum oxide layer has a structure in which oxygen atoms are six-coordinated, and the indium oxide layer is an oxide semiconductor film having a structure in which indium atoms are five-coordinated. preferable.

In one embodiment of the present invention, the oxide semiconductor film includes an oxide semiconductor film, a gate insulating film, a source electrode, a drain electrode, and a gate electrode. The oxide semiconductor film has the general formula In _x La _(2-x) Zn _y O _{3 + y} ( x is a number of 1 or more and less than 2, and y is a number of 1 or more and less than 6).

In one embodiment of the present invention, an oxide semiconductor film includes a gate insulating film, a source electrode, a drain electrode, and a gate electrode. The oxide semiconductor film includes an indium oxide layer, a lanthanum oxide layer, and a zinc oxide layer arranged in layers. A semiconductor having a general crystal structure, and the general formula of the crystal structure is In _x La _(2-x) Zn _y O _{3 + y} (where x is a number from 1 to less than 2, y is a number from 1 to less than 6) Device.

In one embodiment of the present invention, the semiconductor device in which the lanthanum oxide layer has a structure in which oxygen atoms are six-coordinated to lanthanum atoms and the indium oxide layer has a structure in which oxygen atoms are five-coordinated to indium atoms is preferable.

According to one embodiment of the present invention, an oxide semiconductor film having a band gap larger than that of IGZO and a larger bond energy of a crystal structure can be obtained. In addition, by providing the oxide semiconductor film, the dielectric breakdown voltage is excellent, the deterioration when irradiated with light is reduced, and the electrical characteristics such as the threshold voltage hardly change even when used for a long time. A highly reliable semiconductor device can be provided.

FIG. 10 is a model diagram illustrating a crystal structure of an oxide semiconductor. FIG. 6 is a model diagram illustrating a bonding state of atoms in an oxide semiconductor. FIG. 10 is a model diagram illustrating a crystal structure of an oxide semiconductor. FIG. 10 is a model diagram illustrating a crystal structure of an oxide semiconductor. FIG. 10 is a model diagram illustrating a crystal structure of an oxide semiconductor. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 4A and 4B are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 10A and 10B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device.

Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings.

Note that the size, the layer thickness, or the region of each structure illustrated in the drawings and the like in the embodiments and examples is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

Note that the terms first, second, third to Nth (N is a natural number of 2 or more) used in this specification are given to avoid confusion between components, and are limited numerically. It is not a thing.

(Embodiment 1)
In this embodiment, an example of a crystal structure included in the oxide semiconductor film will be described in detail.

FIGS. 1A and 1B illustrate model diagrams of a unit cell having a crystal structure including indium, lanthanum, zinc, and oxygen included in an oxide semiconductor film.

The model diagrams for the unit cell of the crystal structure shown in FIGS. 1 (A) and 1 (B) are obtained by optimizing the structure by first-principles calculation using the plane wave-pseudopotential method based on the density functional theory. is there. As shown in FIGS. 1A and 1B, the unit cell of the crystal structure can take a hexagonal layered crystal structure.

Note that a model diagram of a unit cell including indium, lanthanum, zinc, and oxygen illustrated in FIG. 1A is represented by the general formula In _x La _(2-x) Zn _y O _{3 + y} (x is a number of 1 or more and less than 2, When y is a number of 1 or more and less than 6, the composition of the crystal structure represents the crystal structure at x = 1 and y = 1. In this case, the composition ratio of indium: lanthanum: zinc is 1: 1: 1 [atomic percentage], which can be represented by the general formula InLaZnO ₄ . Note that InLaZnO ₄ can form an oxide semiconductor film by a sputtering method using an oxide target having a composition ratio of 1: 1: 1 [atomic percentage] or a composition ratio in the vicinity thereof. Note that in the general formula In _x La _(2-x) Zn _y O _{3 + y} , x may be a number greater than 0 and less than 2, but by increasing the proportion of indium rather than lanthanum, the field-effect mobility is increased. Since it can be enlarged, it is preferable.

In the above general formula, the lower limit is 1 and the upper limit is 2 for the variable x that determines the composition ratio of indium and lanthanum. This is derived as a composition ratio capable of maintaining a crystal structure in which the indium oxide layer, the lanthanum oxide layer, and the zinc oxide layer form a layer like the crystal structure of this embodiment. For example, if the variable x is smaller than 1, indium is less than that of lanthanum, which makes it difficult to maintain the crystal structure. Further, if the variable x is 2 or more, the lantern disappears and the desired effect cannot be obtained. Therefore, in the general formula In _x La _(2-x) Zn _y O _{3 + y} , x is 1 or more and less than 2.

In the above general formula, the lower limit is 1 and the upper limit is 6 for the variable y that determines the composition ratio of zinc oxide. This is derived as a composition ratio capable of maintaining a crystal structure in which the indium oxide layer, the lanthanum oxide layer, and the zinc oxide layer form a layer like the crystal structure of this embodiment. For example, if the variable y is smaller than 1, zinc is less than indium and lanthanum, and thus it is difficult to maintain the crystal structure. Moreover, if the variable y is 6 or more, since zinc is increased as compared with indium and lanthanum, zinc oxide is likely to precipitate alone. Therefore, in the general formula In _x La _(2-x) Zn _y O _{3 + y} , y is 1 or more and less than 6.

Note that in this embodiment, in this embodiment, indium, lanthanum, zinc, and oxygen are shown as combinations of elements included in the oxide semiconductor film; however, indium can be replaced with other elements. . In that case, the above-described general formula can be expressed as M _x La _(2-x) Zn _y O _{3 + y} . In the above general formula, M is an element that is trivalent and has an ion radius smaller than that of lanthanum. For example, aluminum, scandium, yttrium, cerium, neodymium, promethium, gadolinium, europium, lutetium, or the like may be used. .

FIG. 1A is a model diagram of a unit cell having indium, lanthanum, zinc, and oxygen when the horizontal direction is the a-axis, the depth direction is the b-axis, and the vertical direction is the c-axis. As shown in FIG. 1A, the unit lattice of a crystal structure can take a layered crystal structure. The basic skeleton of the crystal structure is the same as that of IGZO.

In the model diagram of the unit cell shown in FIG. 1A, a crystal structure in which an indium oxide layer (In—O layer), a lanthanum oxide layer (La—O layer), and a zinc oxide layer (Zn—O layer) are arranged in layers. Have The crystal structure is an optimized crystal structure having indium, lanthanum, zinc, and oxygen, derived by first-principles calculation.

1A can be said to be a structure in which an indium oxide layer and a zinc oxide layer are inserted between lanthanum oxide layers. On the other hand, the crystal structure of the homologous phase which is a crystal structure of IGZO is a structure in which a gallium oxide layer and a zinc oxide layer are inserted between indium oxide layers.

In FIG. 1B, the model diagram of the unit cell shown in FIG. 1A is shown as a model diagram of the unit cell when observed from the c-axis direction. As shown in FIG. 1B, it can be seen that atoms such as indium, lanthanum, zinc, and oxygen in the model diagram of the crystal structure are arranged in the c-axis direction.

Note that, in the structure of this embodiment mode, as shown in FIG. 1B, the metal atoms are layered or the metal atoms and oxygen atoms are viewed in a direction perpendicular to the c-axis perpendicular to the ab plane of the unit cell. The configuration may be a layered arrangement, or the c-axis may be inclined with respect to the ab plane. When the c-axis has an inclination with respect to the ab plane, the inclination of the c-axis with respect to the ab plane is preferably in the range of 85 ° to 95 °.

Next, in FIGS. 2A and 2B, model diagrams in the crystal structure focusing on lanthanum atoms and indium atoms in the model diagram of the unit cell having indium, lanthanum, zinc, and oxygen shown in FIG. Show.

FIG. 2A is a model diagram in the crystal structure extracted and focused on the indium atoms and the oxygen atoms around the indium atoms in the model diagram of the unit cell shown in FIG. FIG. 2B is a model diagram in the crystal structure extracted by paying attention to the lanthanum atom and the oxygen atoms around the lanthanum atom in the model diagram of the unit cell shown in FIG.

In the model diagram in the crystal structure focusing on the indium atom shown in FIG. 2A, the indium atom has five oxygen atoms coordinated. In the model diagram in the crystal structure focusing on the lanthanum atom shown in FIG. 2B, the oxygen atom is six-coordinated to the lanthanum atom. Although not particularly illustrated, the zinc atom has a structure in which oxygen atoms are tetracoordinated.

In other words, the crystal structure of the model diagram of the unit cell shown in FIG. 1A is that an indium oxide layer in which oxygen atoms are pentacoordinated and a tetracoordinate of oxygen atoms in a lanthanum oxide layer in which oxygen atoms are six coordinated. This structure has a zinc oxide layer. On the other hand, the crystal structure of the homologous phase, which is the crystal structure of IGZO, is that a gallium oxide layer in which oxygen atoms are pentacoordinated and a zinc oxide layer in which oxygen atoms are tetracoordinated between indium oxide layers in which oxygen atoms are six coordinated. It is the structure which has.

The bond distance between the five-coordinate metal and oxygen shown in FIG. 2A can be estimated as 0209 nm, 0.213 nm, and 0.224 nm depending on the type of atoms adjacent to the oxygen atom. 2B can be estimated to be 0242 nm and 0.253 nm although it depends on the type of atoms adjacent to the oxygen atom. That is, the bond distance between the hexacoordinate metal and oxygen is larger than the bond distance between the pentacoordinate metal and oxygen. This is because the bond between the metal and oxygen is weakened by the increase in the coordination number of the oxygen atom to the metal atom.

In the case where metal atoms having different coordination numbers are present in the crystal structure as in the configuration of the present embodiment, the bond energy of the crystal structure is obtained by setting the metal having a large ionic radius to a position having a large coordination number. Can be increased more.

Focusing on the indium atoms and lanthanum atoms of the metal atoms in this embodiment, the lanthanum atoms have a larger ionic radius than the indium atoms. Accordingly, as shown in FIGS. 1A, 2A, and 2B, a structure in which oxygen atoms are six-coordinated to lanthanum atoms and a structure in which oxygen atoms are five-coordinated to indium atoms is used. Thus, the bond energy of the crystal structure can be increased.

On the other hand, the crystal structure of the homologous phase, which is the crystal structure of IGZO, is focused on indium atoms, which are six-coordinate metal atoms, and gallium atoms, which are five-coordinate metal atoms. Atoms have a smaller ionic radius than indium atoms. Accordingly, as shown in FIGS. 1A, 2A, and 2B, a structure in which oxygen atoms are six-coordinated to lanthanum atoms and a structure in which oxygen atoms are five-coordinated to indium atoms is used. Thus, the bond energy of the crystal structure can be increased as compared with the crystal structure of the homologous phase which is the crystal structure of IGZO.

Lanthanum atoms have a smaller electronegativity than indium atoms, and the absolute value of the electronegativity can be increased with the bonded oxygen. Therefore, by adopting a structure in which an oxygen atom is six-coordinated with respect to a lanthanum atom, a bond between metal and oxygen by Coulomb force can be strengthened as compared with a six-coordinate indium atom in the crystal structure of IGZO. . Indium atoms have a smaller electronegativity than gallium atoms, and can increase the absolute value of the electronegativity with the bound oxygen. Therefore, by adopting a structure in which an oxygen atom is pentacoordinated with respect to an indium atom, a metal-oxygen bond by Coulomb force can be strengthened as compared with a pentacoordinate gallium atom in the crystal structure of IGZO. . A semiconductor device such as a transistor including the oxide semiconductor film described in this embodiment is in an off state by strengthening the bond between metal and oxygen and suppressing the generation of carriers such as charges due to desorption of oxygen. Leakage current, that is, off-current can be reduced.

In the model diagram of the unit cell of the crystal structure shown in FIG. 1A, the structure is optimized by first-principles calculation using a plane wave-pseudopotential method based on the density functional theory, and the state density is calculated. Comparing the calculated band gap with the band gap obtained by calculating the density of states using the same method for the crystal structure of IGZO, a model for the unit cell of the crystal structure shown in FIG. The band gap obtained from the figure can be estimated larger than the band gap obtained from the crystal structure of IGZO.

Note that in the crystal structure including indium, lanthanum, zinc, and oxygen illustrated in FIG. 1A, the repetition by the unit cell 301 extends over the entire oxide semiconductor film as illustrated in FIG. It may be. Alternatively, a structure in which part of the oxide semiconductor film becomes an amorphous region and a mixed region with a region having a crystal structure is formed may be employed.

1 to 3, the composition of the crystal structure is represented by the general formula In _x La _(2-x) Zn _y O _{3 + y} (x is a number from 1 to 2 and y is a number from 1 to 6). The crystal structure at x = 1 and y = 1 has been shown as an example, but other composition ratios may be used. For example, the unit lattice of the crystal structure when x = 1.5 and y = 1 is shown in FIGS. 4A and 4B in the same manner as FIGS. In this case, the composition ratio of indium: lanthanum: zinc is 3: 1: 2 [atomic percentage], which can be expressed by the general formula In _1.5 La _0.5 ZnO ₄ .

The model diagrams for the unit cell of the crystal structure shown in FIGS. 4A and 4B are the structures optimized by the first-principles calculation using the plane wave-pseudopotential method based on the density functional theory. is there. As shown in FIGS. 4A and 4B, the unit lattice of the crystal structure can take a hexagonal layered crystal structure.

FIG. 4B shows the model diagram of the unit cell shown in FIG. 4A when the unit cell model is observed from the c-axis direction. As shown in FIG. 4B, it can be seen that atoms such as indium, lanthanum, zinc, and oxygen in the model diagram of the crystal structure are arranged in the c-axis direction. Note that as in FIG. 1B, the c-axis may have an inclination.

In the model diagram of the unit cell shown in FIG. 4A, an indium oxide layer, a lanthanum oxide layer, and a zinc oxide layer that are formed in layers as viewed from the direction perpendicular to the c-axis are mixed and formed in layers. It will be. The crystal structure is an optimized crystal structure having indium, lanthanum, zinc, and oxygen, derived by first-principles calculation.

In the model diagram of the unit cell shown in FIG. 4A, a layer in which lanthanum oxide and indium oxide are mixed (LaO—InO layer) and a layer in which indium oxide and zinc oxide are mixed (InO—ZnO layer) are stacked. The resulting crystal structure. In a layer in which lanthanum oxide and indium oxide are mixed (LaO—InO layer), the metal atom has a structure in which oxygen atoms are six-coordinated.

Accordingly, in the oxide semiconductor film having the crystal structure illustrated in FIG. 4A, as in FIG. 1A, a lanthanum atom which is a metal atom having a large ion radius is located at a position where the coordination number of oxygen atoms is large. By doing so, the bond energy of the crystal structure can be increased.

Focusing on the indium atoms and lanthanum atoms of the metal atoms in this embodiment, the lanthanum atoms have a larger ionic radius than the indium atoms. Therefore, as shown in FIG. 4A, a structure in which oxygen atoms are six-coordinated to lanthanum atoms and indium atoms, and a structure in which oxygen atoms are five-coordinated to indium atoms, Similarly, the bond energy of the crystal structure can be increased.

Note that in the crystal structure including indium, lanthanum, zinc, and oxygen illustrated in FIG. 4A, the repetition of the unit lattice 501 extends over the entire oxide semiconductor film as illustrated in FIG. It may be. Alternatively, a structure in which part of the oxide semiconductor film becomes an amorphous region and a mixed region with a region having a crystal structure is formed may be employed.

As described above, in the structure of this embodiment, the oxide semiconductor film having a crystal structure including lanthanum is used, and the lanthanum is in a position where oxygen is six-coordinated. An oxide semiconductor film with a wide gap can be obtained.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

6A and 6B are a plan view and a cross-sectional view of a transistor 420 as an example of a semiconductor device. 6A is a plan view of the transistor 420, and FIG. 6B is a cross-sectional view taken along line X1-Y1 in FIG. 6A. Note that in FIG. 6A, some components of the transistor 420 (eg, the insulating film 407) are omitted in order to avoid complexity.

A transistor 420 illustrated in FIGS. 6A and 6B includes a base insulating film 436, a source electrode 405a, a drain electrode 405b, and a source on one side surface in a channel length direction over a substrate 400 having an insulating surface. An oxide semiconductor film 403 in contact with the electrode and in contact with the drain electrode on the other side surface in the channel length direction; a gate insulating film 402 in contact with the top surfaces of the oxide semiconductor film 403, the source electrode 405a, and the drain electrode 405b; A gate electrode 401 provided over the oxide semiconductor film 403, a side wall 412a in contact with one of the side surfaces in the channel length direction of the gate electrode 401, and a side wall 412b in contact with the other side surface in the channel length direction of the gate electrode 401. And comprising.

In the transistor 420, at least part of the sidewall 412 a is provided over the source electrode 405 a with the gate insulating film 402 interposed therebetween. Further, at least a part of the side wall 412b is provided over the drain electrode 405b with the gate insulating film 402 interposed therebetween. The sidewall 412a and the sidewall 412b include a conductive material. Therefore, since the sidewall 412a and the sidewall 412b can function as part of the gate electrode 401, a region overlapping with the source electrode 405a or the drain electrode 405b with the gate insulating film 402 interposed therebetween is substantially a Lov region. It can be.

6 includes as constituent elements an insulating film 407 provided over the sidewall 412a, the sidewall 412b, and the gate electrode 401, and a wiring layer 435a and a wiring layer 435b provided over the insulating film 407. Also good. The wiring layer 435a is electrically connected to the source electrode 405a through an opening provided in the insulating film 407 and the gate insulating film 402, and the wiring layer 435b is an opening provided in the insulating film 407 and the gate insulating film 402. Is electrically connected to the drain electrode 405b.

In the case where the transistor 420 is not provided with a sidewall containing a conductive material, precise alignment between the thin oxide semiconductor film and the thin gate electrode is required to form the Lov region. The required accuracy increases with miniaturization. However, since the transistor 420 described in this embodiment includes the sidewall 412a and the sidewall 412b containing a conductive material on the side surface in the channel length direction of the gate electrode 401, the sidewall 412a and the sidewall 412b and the source electrode 405a or the drain A region where the electrode 405b overlaps can also substantially function as a Lov region. Therefore, the degree of freedom of alignment in forming the gate electrode 401 can be improved, and the transistor 420 with high yield and suppressed reduction in on-state current can be provided.

The oxide semiconductor film 403 has the general formula In _x La _(2-x) Zn _y O _{3 + y} (where x is a number greater than or equal to 1 and less than 2, y is a number greater than or equal to 1 and less than 6) described in Embodiment 1. An oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen can be represented. By including the oxide semiconductor film, a semiconductor device that has higher breakdown voltage than IGZO due to a large band gap and reduced deterioration when irradiated with light can be obtained. Further, by increasing the bond energy of the crystal structure, electrical characteristics such as a threshold voltage hardly change even during long-term use, and a highly reliable semiconductor device can be obtained.

FIGS. 7A and 7B are a plan view and a cross-sectional view of a transistor 422 having a structure different from that of the transistor 420 illustrated in FIGS. 6A and 6B. FIG. 7A is a plan view of the transistor 422, and FIG. 7B is a cross-sectional view taken along line X2-Y2 in FIG. Note that in FIG. 7A, some components (eg, the insulating film 407) of the transistor 422 are omitted in order to avoid complexity.

A difference between the transistor 422 illustrated in FIGS. 7A and 7B and the transistor 420 illustrated in FIGS. 6A and 6B is the shape of the side surface of the oxide semiconductor film 403. In the transistor 422 illustrated in FIGS. 4A and 4B, the oxide semiconductor film 403 has a tapered shape on a side surface in contact with the source electrode 405a or the drain electrode 405b. When the side surface of the oxide semiconductor film 403 is tapered, a conductive film to be the source electrode 405a and the drain electrode 405b can be formed with high coverage.

Hereinafter, an example of a manufacturing process of the transistor of this embodiment will be described with reference to FIGS. Note that a manufacturing process of the transistor 422 is described below as an example.

First, the base insulating film 436 is formed over the substrate 400 having an insulating surface.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance high enough to withstand a later heat treatment step. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a plastic substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

The base insulating film 436 is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, a gallium oxide film, or a mixed material thereof. It can be a single layer or a laminated structure selected. Note that the base insulating film 436 is preferably formed as a single layer or a stacked structure including an oxide insulating film so that the oxide insulating film is in contact with the oxide semiconductor film 403 to be formed later. Note that the base insulating film 436 is not necessarily provided.

When the base insulating film 436 has a region containing oxygen exceeding the stoichiometric composition ratio (hereinafter also referred to as an oxygen-excess region), an oxide semiconductor formed later by the excess oxygen contained in the base insulating film 436 This is preferable because oxygen vacancies in the film 403 can be filled. In the case where the base insulating film 436 has a stacked structure, it is preferable that at least a layer in contact with the oxide semiconductor film 403 have an oxygen-excess region. In order to provide the oxygen-excess region in the base insulating film 436, for example, the base insulating film 436 may be formed in an oxygen atmosphere. Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be injected into the base insulating film 436 after deposition to form an oxygen-excess region. As an oxygen implantation method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Next, an oxide semiconductor film 413 is formed over the base insulating film 436 (see FIG. 8A). The thickness of the oxide semiconductor film 413 is, for example, 3 nm to 30 nm, preferably 5 nm to 20 nm. The oxide semiconductor film 413 can be expressed by a general formula, In _x La _(2-x) Zn _y O _{3 + y} (x is a number greater than or equal to 1 and less than 2, y is a number greater than or equal to 1 and less than 6,) indium, lanthanum, A film is formed using a sputtering target having a composition ratio of an oxide semiconductor having a crystal structure containing zinc and oxygen. The substrate temperature during film formation is from room temperature to 450 ° C.

As a method for forming the oxide semiconductor film 413, a sputtering method is used. The oxide semiconductor film 413 is formed using a sputtering apparatus that performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target, ie, a so-called CP sputtering apparatus (Column Plasma Sputtering system). May be.

When the oxide semiconductor film 413 is formed, the concentration of hydrogen contained in the oxide semiconductor film 413 is preferably reduced as much as possible. In order to reduce the hydrogen concentration, for example, when film formation is performed using a sputtering method, impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed as an atmospheric gas supplied into the processing chamber of the sputtering apparatus. A high-purity rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate.

In addition, the hydrogen concentration in the formed oxide semiconductor film 413 can be reduced by introducing a sputtering gas from which hydrogen and moisture have been removed while removing residual moisture in the deposition chamber. . In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. The film formation chamber evacuated using a cryopump has a high exhaust capability such as a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as hydrogen molecules and water (H ₂ O). The concentration of impurities contained in the oxide semiconductor film 413 formed in the film chamber can be reduced.

In addition, forming the oxide semiconductor film 413 with the substrate 400 held at a high temperature is also effective in reducing the concentration of impurities that can be contained in the oxide semiconductor film 413. The temperature for heating the substrate 400 may be 150 ° C. or higher and 450 ° C. or lower.

As the oxide semiconductor used for the oxide semiconductor film 413, the oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen described in Embodiment 1 is used. Therefore, since the band gap is large, the semiconductor device can have a higher breakdown voltage than IGZO and can have a reduced deterioration when irradiated with light. Further, by increasing the bond energy of the crystal structure, electrical characteristics such as a threshold voltage hardly change even during long-term use, and a highly reliable semiconductor device can be obtained.

The sputtering gas used for forming the oxide semiconductor film 413 is preferably a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed.

Prior to the formation of the oxide semiconductor film 413, planarization treatment may be performed on the deposition surface of the oxide semiconductor film 413. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, a powdery substance (also referred to as particles or dust) attached to the deposition surface of the oxide semiconductor film 413 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case of performing the combination, the order of steps is not particularly limited, and may be set as appropriate in accordance with the uneven state of the oxide semiconductor film 413.

The oxide semiconductor film 413 is preferably subjected to heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) included in the oxide semiconductor film 413. The heat treatment temperature is set to be 300 ° C. or higher and 700 ° C. or lower or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere.

By this heat treatment, hydrogen which is an n-type impurity can be removed from the oxide semiconductor. For example, the concentration of hydrogen contained in the oxide semiconductor film 413 after dehydration or dehydrogenation treatment can be 5 × 10 ¹⁹ / cm ³ or less, preferably 5 × 10 ¹⁸ / cm ³ or less.

Note that heat treatment for dehydration or dehydrogenation may be performed at any timing in the manufacturing process of the transistor 422 as long as it is performed after the oxide semiconductor film 413 is formed. However, in the case where an aluminum oxide film is used as the gate insulating film 402 or the insulating film 407, it is preferably performed before the aluminum oxide film is formed. Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatment.

Note that in the case where the base insulating film 436 containing oxygen is provided as the base insulating film 436, if heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor film 413 is processed into an island shape, the base insulating film 436 is formed. It is preferable because oxygen contained therein can be prevented from being released by heat treatment.

In the heat treatment, it is preferable that water or hydrogen is not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

Further, after the oxide semiconductor film 413 is heated by heat treatment, a high-purity oxygen gas, a high-purity oxygen dinitride gas, or ultra-dry air (in the same furnace while maintaining the heating temperature or gradually cooling from the heating temperature ( The moisture content when measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter is 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less). May be. It is preferable that water, hydrogen, or the like be not contained in the oxygen gas or the oxygen dinitride gas. Alternatively, the purity of the oxygen gas or oxygen dinitride gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or oxygen dinitride gas is 1 ppm or less, preferably 0.1 ppm or less). It is preferable to do. By supplying oxygen, which is a main component material of the oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or oxygen dinitride gas, the oxide The semiconductor film 413 can be highly purified and electrically i-type (intrinsic).

Alternatively, oxygen (at least including any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor film that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. Good.

By introducing oxygen into the oxide semiconductor film that has been subjected to dehydration or dehydrogenation treatment and supplying oxygen into the film, the oxide semiconductor film is highly purified and electrically i-type (intrinsic). can do. A transistor including an oxide semiconductor film which is highly purified and electrically i-type (intrinsic) is electrically stable because variation in electrical characteristics is suppressed.

In the step of introducing oxygen, when oxygen is introduced into the oxide semiconductor film, the oxygen may be introduced directly into the oxide semiconductor film or through other films such as the gate insulating film 402 and the insulating film 407 which are formed later. Alternatively, the oxide semiconductor film 403 may be introduced. In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used. However, oxygen is directly introduced into the exposed oxide semiconductor film 413. In addition to the above method, plasma treatment or the like can also be used.

The introduction of oxygen into the oxide semiconductor film is not particularly limited as long as it is performed after dehydration or dehydrogenation treatment. Further, oxygen may be introduced into the oxide semiconductor film subjected to the dehydration or dehydrogenation treatment a plurality of times.

Next, the oxide semiconductor film 413 is processed by a photolithography process, so that the island-shaped oxide semiconductor film 403 is formed. Here, a mask used for processing the island-shaped oxide semiconductor film 403 is preferably a mask having a finer pattern by performing slimming treatment on a mask formed by a photolithography method or the like.

As the slimming treatment, for example, an ashing treatment using radical oxygen (oxygen radical) or the like can be applied. However, the slimming process need not be limited to the ashing process as long as the mask formed by a photolithography method or the like can be processed into a finer pattern. In addition, since the channel length (L) of the transistor is determined by the mask formed by the slimming process, a process with good controllability can be applied as the slimming process.

As a result of the slimming treatment, a mask formed by a photolithography method or the like can be miniaturized to a line width of less than the resolution limit of the exposure apparatus, preferably ½ or less, more preferably １ ／ or less. . For example, the line width can be 30 nm to 2000 nm, preferably 50 nm to 350 nm. Thereby, further miniaturization of the transistor can be achieved.

Next, a conductive film 415 to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the island-shaped oxide semiconductor film 403 (see FIG. 8B).

The conductive film 415 is formed using a material that can withstand heat treatment performed later. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing the above-described element as a component Etc. can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is formed on one or both of the lower side or upper side of the metal film such as Al or Cu. It is good also as a structure which laminated | stacked. Alternatively, the conductive film 415 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

Next, polishing (cutting or grinding) is performed on the conductive film 415, and part of the conductive film 415 is removed so that the oxide semiconductor film 403 is exposed. By the polishing treatment, the conductive film 415 in a region overlapping with the oxide semiconductor film 403 is removed, so that a conductive film 415a having an opening in the region is formed (see FIG. 8C). As a polishing (cutting or grinding) method, a chemical mechanical polishing (CMP) process can be suitably used. In this embodiment, the conductive film 415 in a region overlapping with the oxide semiconductor film 403 is removed by CMP treatment.

The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform primary polishing at a low polishing rate after performing primary polishing at a high polishing rate. By combining polishing with different polishing rates in this manner, the planarity of the surfaces of the source electrode 405a, the drain electrode 405b, and the oxide semiconductor film 403 can be further improved.

Note that in this embodiment, CMP treatment is used to remove the conductive film 405 in a region overlapping with the oxide semiconductor film 403; however, other polishing (grinding or cutting) treatment may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where polishing treatment is combined with etching treatment, plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 415.

Note that in this embodiment, the upper end portion of the conductive film 415 a substantially matches the upper end portion of the oxide semiconductor film 403. Note that the shape of the conductive film 415a (or the source electrode 405a and the drain electrode 405b formed by processing the conductive film 415a) differs depending on conditions of polishing treatment for removing the conductive film 415. For example, the oxide semiconductor film 403 may recede in the film thickness direction from the surface.

Next, the conductive film 415a is processed by a photolithography step, so that a source electrode 405a and a drain electrode 405b (including a wiring formed using the same layer) are formed (see FIG. 8D).

Note that in this embodiment, the conductive film 415 is formed, and the conductive film 415 in a region overlapping with the oxide semiconductor film 403 is removed by polishing treatment, and then selectively etched to be the source electrode 405a and the drain electrode. Although the method of processing to 405b is shown, the embodiment of the present invention is not limited to this. After the deposited conductive film 415 is selectively etched and processed, the conductive film 415 in a region overlapping with the oxide semiconductor film 403 is removed by polishing, so that the source electrode 405a and the drain electrode 405b are formed. May be. Note that in the case where the etching process is performed before the polishing process, the conductive film 415 in a region overlapping with the oxide semiconductor film 403 is not removed by the etching process.

In the method for manufacturing the transistor described in this embodiment, etching is performed using a resist mask in the step of removing the conductive film 415 in a region overlapping with the oxide semiconductor film 403 when the source electrode 405a and the drain electrode 405b are formed. Since no treatment is used, precise processing can be performed accurately even when the width of the source electrode 405a and the drain electrode 405b in the channel length direction is miniaturized. Thus, in the manufacturing process of the semiconductor device, the transistor 420 having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

In addition, by removing the conductive film 415 in a region overlapping with the oxide semiconductor film 403, the oxide semiconductor film 403 and the source electrode 405a or the drain electrode 405b can be formed on a side surface in the channel length direction of the oxide semiconductor film 403. It becomes possible to make the structure which touches. Since the oxide semiconductor film 403 has a small thickness of 3 nm to 30 nm, preferably 5 nm to 20 nm, the contact area with the source electrode 405a or the drain electrode 405b is reduced by contacting the source electrode 405a or the drain electrode 405b on the side surface. The contact resistance at the contact interface can be increased. Therefore, even when the channel length (L) of the transistor 422 is shortened, the electric field between the source electrode 405a and the drain electrode 405b can be relaxed, and a short channel effect such as variation in threshold voltage can be suppressed.

Next, the gate insulating film 402 is formed over the oxide semiconductor film 403, the source electrode 405a, and the drain electrode 405b.

The gate insulating film 402 has a thickness of greater than or equal to 1 nm and less than or equal to 20 nm and can be formed as appropriate using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like. Alternatively, the gate insulating film 402 may be formed using a sputtering apparatus that performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target, a so-called CP sputtering apparatus.

Note that as the gate insulating film 402 is thicker, the short channel effect becomes more prominent, and the threshold voltage tends to easily shift to the negative side. However, in the method for manufacturing the transistor of this embodiment, the top surfaces of the source electrode 405a, the drain electrode 405b, and the oxide semiconductor film 403 are planarized by a polishing process, so that the thin gate insulating film 402 is covered. It can be formed with good properties.

As a material of the gate insulating film 402, silicon oxide, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, silicon nitride oxide, or the like can be used. The gate insulating film 402 preferably contains oxygen in a portion in contact with the oxide semiconductor film 403. In particular, the gate insulating film 402 preferably includes oxygen in the film (in the bulk) at least in an amount exceeding the stoichiometric composition ratio. For example, when a silicon oxide film is used as the gate insulating film 402, , SiO _{2 + α} (where α> 0). In this embodiment, a silicon oxide film with SiO _{2 + α} (α> 0) is used as the gate insulating film 402. By using this silicon oxide film as the gate insulating film 402, oxygen can be supplied to the oxide semiconductor film 403, whereby characteristics can be improved. Further, the gate insulating film 402 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage with the gate insulating film 402.

As materials for the gate insulating film 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0, The gate leakage current can be reduced by using a high-k material such as y> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), or lanthanum oxide. Further, the gate insulating film 402 may have a single-layer structure or a stacked structure.

Next, the gate electrode 401 is formed over the island-shaped oxide semiconductor film 403 with the gate insulating film 402 interposed therebetween (see FIG. 9A). The gate electrode 401 can be formed by a plasma CVD method, a sputtering method, or the like. The material of the gate electrode 401 is a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as a component (nitriding) A titanium film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode 401. The gate electrode 401 may have a single-layer structure or a stacked structure.

The material of the gate electrode 401 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc A conductive material such as oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

As one layer of the gate electrode 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, specifically, an IGZO film containing nitrogen, an In—Sn—O film containing nitrogen, or an In— A Ga—O film, an In—Zn—O film containing nitrogen, an Sn—O film containing nitrogen, an In—O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more, and when used as a gate electrode, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

Note that the gate electrode 401 can be formed by processing a conductive film (not illustrated) provided over the gate insulating film 402 using a mask. Here, the mask used for processing is preferably a mask having a finer pattern by performing slimming treatment on a mask formed by a photolithography method or the like.

Next, a film including a conductive material is formed over the gate electrode 401 and the gate insulating film 402, and the film including the conductive material is etched to form sidewalls 412a and 412b (see FIG. 9B). .

The sidewall 412a and the sidewall 412b are only required to have conductivity, and can be formed by processing a metal film such as tungsten or titanium or a silicon film containing an impurity element such as phosphorus or boron, for example. . Alternatively, after a polycrystalline silicon film is formed over the gate electrode 401 and the gate insulating film 402 and a sidewall in contact with the gate electrode 401 is formed by etching, an impurity element such as phosphorus or boron is introduced into the sidewall by doping. Alternatively, the sidewall 412a and the sidewall 412b having conductivity may be formed by performing heat treatment for activation.

Next, an insulating film 407 is formed over the gate insulating film 402, the gate electrode 401, the side wall 412a, and the side wall 412b.

The insulating film 407 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like. As the insulating film 407, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be typically used.

As the insulating film 407, an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride film (eg, an aluminum nitride film) can be used.

The insulating film 407 may be a single layer or a stacked layer. For example, a stacked layer of a silicon oxide film and an aluminum oxide film can be used. An aluminum oxide film has a high blocking effect (blocking effect) of preventing both hydrogen and moisture impurities and oxygen from passing through the film, and impurities such as hydrogen and moisture that cause fluctuations during and after the manufacturing process. It is preferable because it functions as a protective film for preventing entry of oxygen into the oxide semiconductor film 403 and release of oxygen, which is a main component material of the oxide semiconductor, from the oxide semiconductor film 403.

The insulating film 407 is preferably formed using a method by which an impurity such as water or hydrogen is not mixed into the insulating film 407 as appropriate, such as a sputtering method.

As in the formation of the oxide semiconductor film 403, in order to remove moisture remaining in the deposition chamber of the insulating film 407, an adsorption-type vacuum pump (such as a cryopump) is preferably used. The concentration of impurities contained in the insulating film 407 formed in the deposition chamber evacuated using a cryopump can be reduced. Further, as an evacuation unit for removing moisture remaining in the deposition chamber of the insulating film 407, a turbo molecular pump provided with a cold trap may be used.

In this embodiment, a stacked structure of an aluminum oxide film and a silicon oxide film is used as the insulating film 407 from the side in contact with the gate electrode 401. Note that when the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 420. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray reflectance measurement (XRR: X-Ray Reflection).

Next, an opening reaching the source electrode 405a or the drain electrode 405b is formed in the insulating film 407 and the gate insulating film 402, and a wiring layer 435a and a wiring layer 435b are formed in the openings (see FIG. 6C). Various circuits can be formed by connecting the wiring layer 435a and the wiring layer 435b to other transistors and elements.

The wiring layer 435a and the wiring layer 435b can be formed using a material and a method similar to those of the gate electrode 401, the source electrode 405a, or the drain electrode 405b. For example, aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten A metal film containing an element selected from the above, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing the above-described element as a component can be used. Further, a refractory metal film such as titanium, molybdenum, or tungsten or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) on one or both of the lower side or upper side of a metal film such as aluminum or copper It is good also as a structure which laminated | stacked. Further, the conductive film used for the wiring layer 435a and the wiring layer 435b may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (In ₂ O ₃ —ZnO). Alternatively, a material in which silicon oxide is included in these metal oxide materials can be used.

For example, as the wiring layer 435a and the wiring layer 435b, a single layer of a molybdenum film, a stack of a tantalum nitride film and a copper film, a stack of a tantalum nitride film and a tungsten film, or the like can be used.

Through the above process, the transistor 422 of this embodiment is formed.

Note that the length of the island-shaped oxide semiconductor film 403 in the channel length direction is longer than the length of the gate electrode 401 in the channel length direction, so that the degree of freedom of alignment is further improved in order to form the gate electrode 401. Can be made. In this case, an impurity region may be provided in the oxide semiconductor film 403 in order to reduce the channel length of the transistor.

For example, the transistor 424 illustrated in FIGS. 10A and 10B and the transistor 426 illustrated in FIGS. 11A and 11B are oxidized using the gate electrode 401 as a mask after the gate electrode 401 is formed. In this example, impurities are introduced into the physical semiconductor film 403 to form the impurity regions 403a and 403b in a self-aligning manner.

The transistor 424 has a structure similar to that of the transistor 420, and the oxide semiconductor film 403 included in the transistor 424 is sandwiched between a pair of impurity regions containing impurities (an impurity region 403a and an impurity region 403b) and a pair of impurity regions. The transistor 420 is different from the transistor 420 in that the channel formation region 403c is provided. A transistor 426 illustrated in FIGS. 11A and 11B has a structure similar to that of the transistor 422, and the oxide semiconductor film 403 included in the transistor 426 includes a pair of impurity regions (impurities) containing a dopant. The transistor 422 is different from the transistor 422 in that it includes a region 403a and an impurity region 403b) and a channel formation region 403c sandwiched between a pair of impurity regions. 10A is a plan view of the transistor 424, and FIG. 10B is a cross-sectional view taken along line X3-Y3 in FIG. 10A. FIG. 11A is a plan view of the transistor 426, and FIG. 11B is a cross-sectional view taken along line X4-Y4 in FIG. 11A.

The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

With the oxide semiconductor film including a pair of impurity regions with the channel formation region 403c interposed in the channel length direction, the transistors 424 and 426 have high on-characteristics (eg, on-state current and field-effect mobility), high-speed operation, A transistor capable of high-speed response can be obtained.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

(Embodiment 3)
In this embodiment, an example of a semiconductor device using the transistor described in this specification, capable of holding stored data even when power is not supplied, and having no limit on the number of writing times will be described with reference to drawings. To do.

FIG. 12 illustrates an example of a structure of a semiconductor device. 12A is a cross-sectional view of the semiconductor device, FIG. 12B is a plan view of the semiconductor device, and FIG. 12C is a circuit diagram of the semiconductor device. Here, FIG. 12A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG.

The semiconductor device illustrated in FIGS. 12A and 12B includes a transistor 160 using a first semiconductor material in a lower portion, a second semiconductor material in an upper portion, and in this embodiment mode, this embodiment mode. The transistor 162 including the oxide semiconductor film having a crystal structure including indium, lanthanum, zinc, and oxygen, which is described in Embodiment 1, is provided. The transistor 162 is an example to which the structure of the transistor 420 described in Embodiment 2 is applied.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition to using the transistor as described in Embodiment 2 using an oxide semiconductor to hold information as the transistor 162, a specific structure of the semiconductor device such as a material used in the semiconductor device and a structure of the semiconductor device Need not be limited to those shown here.

A transistor 160 in FIG. 12A includes a channel formation region 116 provided in a substrate 100 containing a semiconductor material (eg, silicon), an impurity region 120 provided so as to sandwich the channel formation region 116, and an impurity region. The metal compound region 124 in contact with 120, the gate insulating film 108 provided on the channel formation region 116, and the gate electrode 110 provided on the gate insulating film 108 are included. Note that in the drawing, the source electrode and the drain electrode may not be explicitly provided, but for convenience, the state may be referred to as a transistor. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed. That is, in this specification, the term “source electrode” can include a source region.

An element isolation insulating film 106 is provided over the substrate 100 so as to surround the transistor 160, and an insulating film 128 and an insulating film 130 are provided so as to cover the transistor 160. Note that in the transistor 160, a sidewall insulating film (sidewall insulating film) may be provided on a side surface of the gate electrode 110 so that the impurity region 120 includes regions having different impurity concentrations.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. In this embodiment, two insulating films are formed so as to cover the transistor 160. However, the insulating film may be a single layer or a stack of three or more layers. As a process before the formation of the transistor 162 and the capacitor 164, the insulating film formed over the transistor 160 is subjected to CMP to form the planarized insulating film 128 and the insulating film 130, and at the same time, the upper surface of the gate electrode 110 is formed. Expose.

The insulating film 128 and the insulating film 130 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like. An inorganic insulating film can be used. The insulating film 128 and the insulating film 130 can be formed by a plasma CVD method, a sputtering method, or the like.

Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case of using an organic material, the insulating film 128 and the insulating film 130 may be formed by a wet method such as a spin coating method or a printing method.

Note that in this embodiment, a silicon nitride film is used as the insulating film, and a silicon oxide film is used as the insulating film 130.

Planarization treatment is preferably performed on the formation region of the oxide semiconductor film 144 on the surface of the insulating film 130. In this embodiment, the oxide semiconductor film 144 is formed over the insulating film 130 that is sufficiently planarized by polishing treatment (eg, CMP treatment) (preferably the average surface roughness of the surface of the insulating film 130 is 0.15 nm or less). .

A transistor 162 illustrated in FIG. 12A is a transistor in which an oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen is used for an oxide semiconductor film having a channel formation region. Here, it is preferable that the oxide semiconductor film 144 included in the transistor 162 be highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

The transistor 162 includes an oxide semiconductor film 144 in contact with the electrode layer 142a or the electrode layer 142b on the side surface in the channel length direction. Accordingly, the resistance of the region where the oxide semiconductor film 144 is in contact with the electrode layer 142a or the electrode layer 142b can be increased, so that the electric field between the source and the drain can be reduced. Therefore, the short channel effect accompanying the reduction in transistor size can be suppressed.

In addition, the transistor 162 includes sidewalls 137a and 137b containing a conductive material on the side surface in the channel length direction of the gate electrode 148, so that the sidewalls 137a and 137b containing the conductive material are interposed in the electrode layer through the gate insulating film 146. Since the transistor overlaps with the electrode layer 142a or the electrode layer 142b, the transistor can substantially have a Lov region, and a decrease in on-state current of the transistor 162 can be suppressed.

Over the transistor 162, an interlayer insulating film 135 and an insulating film 150 are provided as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating film 150. When the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

In addition, a conductive layer 153 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the gate insulating film 146 provided therebetween, and the electrode layer 142a, the gate insulating film 146, and the conductive layer 153 provide capacitance. Element 164 is configured. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 164 and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

In this embodiment, the conductive layer 153 can be formed in the same manufacturing process as the gate electrode 148 of the transistor 162. Note that in the step of forming the sidewall 137a and the sidewall 137b on the side surface of the gate electrode 148, a sidewall may be provided on the side surface of the conductive layer as well.

Over the insulating film 150, a transistor 162 and a wiring 156 for connecting another transistor are provided. The wiring 156 is electrically connected to the electrode layer 142b through an electrode layer 136 formed in an opening formed in the insulating film 150, the interlayer insulating film 135, the gate insulating film 146, and the like.

12A and 12B, the transistor 160 and the transistor 162 are provided so that at least part of them overlap with each other, and the source region or the drain region of the transistor 160 and the oxide semiconductor film 144 are formed. It is preferable that a part is provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided so as to overlap with at least part of the gate electrode 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Note that the electrical connection between the electrode layer 142b and the wiring 156 may be performed by directly contacting the electrode layer 142b and the wiring 156 without providing the electrode layer 136. Moreover, a plurality of intervening electrode layers may be provided.

Next, an example of a circuit configuration corresponding to FIGS. 12A and 12B is illustrated in FIG.

In FIG. 12C, the first wiring (1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the transistor 160 are electrically connected. It is connected. In addition, the third wiring (3rd Line) and one of the source electrode and the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected to each other. It is connected to the. The gate electrode of the transistor 160 and one of the source electrode and the drain electrode of the transistor 162 are electrically connected to the other electrode of the capacitor 164, and the fifth wiring (5th Line) and the electrode of the capacitor 164 The other of these is electrically connected.

In the semiconductor device illustrated in FIG. 9C, data can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 160 and the capacitor 164. That is, predetermined charge is given to the gate electrode of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the charge given to the gate electrode of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the first wiring is changed according to the amount of charge held in the gate electrode of the transistor 160. The two wirings have different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high level charge is applied to the gate electrode of the transistor 160 is a low level charge applied to the gate electrode of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned “off” regardless of the state of the gate electrode, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively, a} potential at which the transistor 160 is turned on regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, a transistor with an extremely low off-state current in which an oxide semiconductor film having a crystal structure including indium, lanthanum, zinc, and oxygen is used for the oxide semiconductor film having a channel formation region. Thus, it is possible to retain the stored contents for an extremely long time. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

(Embodiment 4)
In this embodiment, a semiconductor device which uses the transistor described in Embodiment 2 and can hold stored data even when power is not supplied and has no limit on the number of writing operations is described in Embodiment 3. A structure different from the illustrated structure will be described with reference to FIGS.

FIG. 13A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 13B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 13A is described, and then the semiconductor device illustrated in FIG. 13B is described below.

In the semiconductor device illustrated in FIG. 13A, the bit line BL and the source or drain electrode of the transistor 162 are electrically connected, the word line WL and the gate electrode of the transistor 162 are electrically connected, and the transistor 162 The source electrode or the drain electrode of the capacitor and the first terminal of the capacitor 254 are electrically connected.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG. 13A is described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

The transistor 162 including an oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen for the oxide semiconductor film having a channel formation region has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. It can be seen that (= CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the bit line BL when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 13A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 13B is described.

A semiconductor device illustrated in FIG. 13B includes memory cell arrays 251a and 251b each including a plurality of memory cells 250 illustrated in FIG. 13A as a memory circuit in an upper portion, and memory cell arrays (memory cell arrays 251a and 251b) in a lower portion. The peripheral circuit 253 necessary for operating the device is operated. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 13B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (memory cell arrays 251a and 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

Note that the semiconductor device illustrated in FIG. 13B illustrates a structure in which two memory cell arrays 251 (a memory cell array 251a and a memory cell array 251b) are stacked; however, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of the memory cell 250 illustrated in FIG. 13A is described with reference to FIGS.

FIG. 14 shows an example of the configuration of the memory cell 250. 14A shows a cross-sectional view of the memory cell 250, and FIG. 14B shows a plan view of the memory cell 250. Here, FIG. 14A corresponds to a cross section taken along lines F1-F2 and G1-G2 in FIG.

The transistor 162 illustrated in FIGS. 14A and 14B can have the same structure as the structure described in Embodiment 2.

A conductive layer 262 is provided in a region overlapping with the electrode layer 142 a of the transistor 162 with the gate insulating film 146 provided therebetween, and the capacitor 254 includes the electrode layer 142 a, the gate insulating film 146, and the conductive layer 262. Is configured. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 functions as the other electrode of the capacitor 254.

Over the transistor 162 and the capacitor 254, an interlayer insulating film 135 and an insulating film 256 are provided as a single layer or a stacked layer. A memory cell 250 and a wiring 260 for connecting the adjacent memory cells 250 are provided on the insulating film 256. The wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 through an opening formed in the insulating film 256, the interlayer insulating film 135, the gate insulating film 146, and the like. However, the wiring 260 and the electrode layer 142b may be directly connected. Note that the wiring 260 corresponds to the bit line BL in the circuit diagram of FIG.

14A and 14B, the electrode layer 142b of the transistor 162 can also function as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

By adopting the planar layout shown in FIG. 14A, the area occupied by the semiconductor device can be reduced, so that high integration can be achieved.

As described above, a plurality of memory cells formed in multiple layers is formed using a transistor in which an oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen is used for an oxide semiconductor film having a channel formation region. ing. Transistors using an oxide semiconductor film having a crystal structure containing indium, lanthanum, zinc, and oxygen for the oxide semiconductor film having a channel formation region have low off-state current. Is possible. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

In this manner, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high speed operation), and an oxide semiconductor film including a channel formation region with indium, lanthanum, zinc, and A semiconductor having unprecedented characteristics by being integrally provided with a memory circuit using a transistor (a transistor with a sufficiently small off-state current in a broad sense) using an oxide semiconductor film having a crystal structure containing oxygen An apparatus can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

(Embodiment 5)
In this embodiment, an example in which the semiconductor device described in any of Embodiments 3 and 4 is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS. .

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In an ordinary SRAM, as shown in FIG. 15A, one memory cell includes six transistors 801 to 806, which are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 form an inverter and can be driven at high speed. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is normally 100 to 150 F ² . For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 15B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. The memory cell area of a DRAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 16 shows a block diagram of a portable device. 16 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. A sensor 919, an audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 909. In general, the memory circuit 912 is configured by SRAM or DRAM, and by adopting the semiconductor device described in Embodiment 3 or 4 in this portion, writing and reading of information is performed at high speed and long-term storage is performed. Holding is possible, and power consumption can be sufficiently reduced.

FIG. 17 illustrates an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 17 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit reads a signal line from image data (input image data), a memory 952, and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and is stored in the display 957 via the switch 955 and the display controller 956. The stored image data B is sent and displayed. This reading is continued until new image data is stored in the memory 952 next time.

As described above, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 952 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in Embodiment 3 or 4 for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently high. Can be reduced.

FIG. 18 is a block diagram of an electronic book. 18 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in Embodiment 3 or 4 can be used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 has a function of temporarily holding the contents of a book. An example of a function is when a user uses a highlight function. When a user is reading an electronic book, the user may want to mark a specific part. This marking function is called a highlight function, and is to show the difference from the surroundings by changing the display color, underlining, making the character thicker, or changing the font of the character. This is a function for storing and holding information on a location designated by the user. When this information is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by using the semiconductor device described in Embodiment 3 or 4, information writing and reading can be performed at high speed, long-term storage can be performed, and power consumption is sufficient. Can be reduced.

As described above, the portable device described in this embodiment includes the semiconductor device according to Embodiment 3 or Embodiment 4. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

In this example, by using the lanthanum atom in one embodiment of the present invention described in Embodiment Mode 1, it was calculated by the first principle calculation that the binding energy was increased as compared with the binding energy of the crystal structure of IGZO. .

The bond energy (E _binding ) is calculated from the following equation (1), where the bond energy is the sum of the dissociation energies of all bonds in the crystal structure.

E _binding = ΣE (atom) −E (total) (1)

In formula (1), E (atom) represents the energy of each atom present in the crystal structure, and E (total) represents the energy of the crystal. That is, from the formula (1), the larger the binding energy, the more stable the crystal structure. By stabilizing the crystal structure, the bond between metal and oxygen can be strengthened, and desorption of oxygen can be suppressed.

CASTEP, which is a density functional method program, was used for the calculation. The plane wave basis pseudopotential method was used as the density functional method, and GGA-PBE was used as the functional. The cut-off energy was 380 eV. The number of grids at k points was 9 × 9 × 3.

As the crystal structure used for calculating the binding energy, a unit cell structure of symmetry R-3 (international number: 148) was used in the crystal structure of IGZO (InGaZnO ₄ : model name, InGaZO). In the crystal structure having indium, lanthanum, zinc, and oxygen, the position of the gallium atom in the crystal structure of the IGZO in the crystal structure in which the lanthanum atom is a five-coordinate position of the oxygen atom (InLaZnO ₄ : model name, InLaZO). The one in which the atom in was replaced with a lanthanum atom was used. In the crystal structure having indium, lanthanum, zinc, and oxygen, the crystal structure in which the lanthanum atom has a six-coordinate position of the lanthanum atom (InLaZnO ₄ : model name, LaInZO), the position of the indium atom in the crystal structure of IGZO An atom in which the atom was replaced with a lanthanum atom and the atom at the position of the gallium atom was replaced with an indium atom was used.

Table 1 below shows the values of the respective binding energies E _binding .

From the values in Table 1, it was found that by replacing the gallium atom in the crystal structure of IGZO with a lanthanum atom, the binding energy can be increased and the crystal structure can be stabilized. The crystal structure of the model name LaInZO, which has a crystal structure in which the lanthanum atom is in the 6-coordinate position, and the crystal structure of model name InLaZO, in which the lanthanum atom is the crystal structure in which the oxygen atom is in the 5-coordinate position. It was found that the bond energy is larger than that of the crystal structure and the crystal structure can be stabilized.

In this example, structure optimization was performed by first-principles calculation using a plane wave-pseudopotential method based on density functional theory, and the energy state density was calculated for the optimized crystal structure.

First-principles calculation software CASTEP was used as the calculation program. The functional used was GGA-PBE, and the pseudopotential used Ultrasoft. The cut-off energy was 380 eV, the number of k points was 4 × 4 × 1 for structure optimization, and 5 × 5 × 3 for state density calculation.

The crystal structure used for the optimization of the crystal structure is the IGZO crystal structure (InGaZnO ₄ : model name, InGaZO), and the unit cell of symmetry R-3 (international number: 148) is arranged in the a-axis direction and the b-axis direction, respectively. A doubled crystal structure was used. In the crystal structure having indium, lanthanum, zinc, and oxygen, the position of the gallium atom in the crystal structure of the IGZO in the crystal structure in which the lanthanum atom is a five-coordinate position of the oxygen atom (InLaZnO ₄ : model name, InLaZO). The one in which the atom in was replaced with a lanthanum atom was used. In the crystal structure having indium, lanthanum, zinc, and oxygen, the crystal structure in which the lanthanum atom has a six-coordinate position of the lanthanum atom (InLaZnO ₄ : model name, LaInZO), the position of the indium atom in the crystal structure of IGZO An atom in which the atom was replaced with a lanthanum atom and the atom at the position of the gallium atom was replaced with an indium atom was used.

It can be seen that any of the optimized structures has a band gap and thus has an insulator or semiconductor density of states. Therefore, the band gap was calculated from the density of states. Table 2 below shows the respective band gap values.

In the density functional method, the band gap tends to be estimated to be small, and the actual band gap of the IGZO crystal is about 3.2 eV, which is larger than the band gap shown in Table 2.

From the values in Table 2, it was found that the band gap could be increased by replacing gallium atoms in the crystal structure of IGZO with lanthanum atoms. The crystal structure of model name LaInZO, which has a crystal structure in which the lanthanum atom has a six-coordinate position, is the crystal structure of model name InLaZO, which has a crystal structure in which the lanthanum atom has a five-coordinate position. It was found that the band gap can be increased.

This example can be implemented in combination with any of the structures described in the other embodiments as appropriate.

301 Unit lattice 501 Unit lattice 100 Substrate 106 Element isolation insulating film 108 Gate insulating film 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound region 128 Insulating film 130 Insulating film 135 Interlayer insulating film 136 Electrode layer 137a Side wall 137b Side wall 142a Electrode Layer 142b electrode layer 144 oxide semiconductor film 146 gate insulating film 148 gate electrode 150 insulating film 153 conductive layer 156 wiring 160 transistor 162 transistor 164 capacitor element 250 memory cell 251 memory cell array 251a memory cell array 251b memory cell array 253 peripheral circuit 254 capacitor element 256 Insulating film 260 Wiring 262 Conductive layer 400 Substrate 401 Gate electrode 402 Gate insulating film 403 Oxide semiconductor film 403a Impurity region 403b Impurity region 403c channel formation region 405 conductive film 405a source electrode 405b drain electrode 407 insulating film 412a side wall 412b side wall 413 oxide semiconductor film 415 conductive film 415a conductive film 420 transistor 422 transistor 424 transistor 426 transistor 435a wiring layer 435b wiring layer 436 base insulating film 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X decoder 808 Y decoder 811 Transistor 812 Storage capacitor 813 X decoder 814 Y decoder 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply circuit 906 Application processor 907 CPU
908 DSP
909 Interface 910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash memory 1005 Audio circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller

Claims (6)

An oxide semiconductor film including a crystal of the general formula In _x La _(2-x) Zn _y O _{3 + y} (x is a number greater than or equal to 1 and less than 2, y is a number greater than or equal to 1 and less than 6.) Indium oxide layer, the crystal structure of lanthanum oxide layer and zinc oxide layer is arranged in a layered possess,
An oxide semiconductor film in which a general formula of the crystal structure is In _x La _(2-x) Zn _y O _{3 + y} (x is a number of 1 to less than 2, y is a number of 1 to less than 6) . In claim 2,
The lanthanum oxide layer has a structure in which a lanthanum atom has six coordinated oxygen atoms,
The indium oxide layer is an oxide semiconductor film having a structure in which indium atoms are coordinated with five oxygen atoms. An oxide semiconductor film, a gate insulating film, a source electrode, a drain electrode, and a gate electrode;
The oxide semiconductor film includes a crystal having a general formula of In _x La _(2-x) Zn _y O _{3 + y} (where x is a number greater than or equal to 1 and less than 2, y is a number greater than or equal to 1 and less than 6) . An oxide semiconductor film, a gate insulating film, a source electrode, a drain electrode, and a gate electrode;
The oxide semiconductor film, an indium layer oxide, the crystal structure of lanthanum oxide layer and zinc oxide layer is arranged in a layered possess,
The general formula of the crystal structure is a semiconductor device in which In _x La _(2-x) Zn _y O _{3 + y} (x is a number from 1 to less than 2, y is a number from 1 to less than 6) . In claim 5,
The lanthanum oxide layer has a structure in which a lanthanum atom has six coordinated oxygen atoms,
The indium oxide layer is a semiconductor device having a structure in which indium atoms are coordinated by five oxygen atoms.