JP6049479B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a transistor using a semiconductor layer made of an amorphous oxide (In—Ga—Zn—O-based amorphous oxide) containing indium (In), gallium (Ga), and zinc (Zn) is disclosed (patent) Reference 1).

JP 2011-181801 A

In the oxide semiconductor, oxygen vacancies serve as donors and generate electrons which are carriers in the oxide semiconductor. If there are many oxygen vacancies in the oxide semiconductor including the channel formation region of the transistor, electrons are generated in the channel formation region, which causes the threshold voltage of the transistor to fluctuate in the negative direction.

An object is to provide a semiconductor device including a transistor including an oxide semiconductor film with stable electrical characteristics and high reliability.

Further, miniaturization of a transistor is indispensable in order to achieve high-speed operation of the transistor, low power consumption of the transistor, high integration, and the like.

In order to realize a higher-performance semiconductor device, the on-characteristics of a miniaturized transistor (for example, on-current and field-effect mobility) are improved to realize a high-speed response and high-speed driving of the semiconductor device and its manufacture An object is to provide a method.

An oxide semiconductor film, a gate insulating film, and a gate electrode layer are sequentially stacked, and side wall insulation including a first sidewall insulating layer, a second sidewall insulating layer, and a third sidewall insulating layer on a side surface of the gate electrode layer. In the semiconductor device including the transistor provided with the layer, the first sidewall insulating layer is in contact with part of the top surface of the gate insulating film and the side surface of the gate electrode layer, and the second sidewall insulating layer is the top surface of the oxide semiconductor film. , A side surface of the gate insulating film, and a side surface of the first side wall insulating layer, and a third side wall insulating layer is in contact with a side surface of the second side wall insulating layer. The first sidewall insulating layer and the third sidewall insulating layer are oxide insulating films, and the second sidewall insulating layer is an insulating film containing a metal element having a lower oxygen permeability than the first sidewall insulating layer (typically It is preferable that the first sidewall insulating layer has an oxygen excess region.

The oxygen excess region included in the first sidewall insulating layer can be formed by performing oxygen doping treatment (oxygen introduction treatment) on the first sidewall insulating layer and / or the oxide insulating film before etching. In the first sidewall insulating layer and / or the oxide insulating film before etching by the oxygen doping treatment, at least one or more stoichiometric amounts of the first sidewall insulating layer or / and the oxide insulating film before etching. It is possible to provide an oxygen-excess region where oxygen exceeding the theoretical composition is present. In addition, oxygen can be supplied to the first sidewall insulating layer and / or the gate insulating film and the oxide semiconductor film provided under the oxide insulating film before etching by the oxygen doping treatment.

The first sidewall insulating layer that is excessively filled with oxygen and contains excess oxygen in a region adjacent to the oxide semiconductor film and the gate insulating film can release oxygen from the gate insulating film and the oxide semiconductor film. And functions as an effective oxygen supply layer to the oxide semiconductor film and the gate insulating film.

Excess oxygen stored in the region adjacent to the oxide semiconductor film and the gate insulating film in the first sidewall insulating layer can be efficiently supplied to the gate insulating film and the oxide semiconductor film. Therefore, in the semiconductor device, generation of parasitic channels can be suppressed, and oxygen vacancies in the oxide semiconductor film and the interface can be compensated. Further, heat treatment can be performed after the oxygen doping treatment to supply oxygen from the oxygen-excess region to the oxide semiconductor film and the gate insulating film.

The second sidewall insulating layer provided in contact with part of the top surface of the oxide semiconductor film, the side surface of the gate insulating film, and the side surface of the first sidewall insulating layer is a metal element having a lower oxygen permeability than the first sidewall insulating layer. An insulating film containing silicon (typically an aluminum oxide film or a film containing an aluminum oxide film) is used.

By using an insulating film containing a metal element with low oxygen permeability as the second sidewall insulating layer, release of oxygen from the first sidewall insulating layer can be prevented.

The aluminum oxide film can be suitably used as an insulating film containing a metal element with low oxygen permeability. The aluminum oxide film has a high blocking effect (blocking effect) that prevents both hydrogen, moisture and other impurities, and oxygen from passing through the film. Therefore, when an aluminum oxide film is provided as the second sidewall insulating layer, impurities such as hydrogen and moisture, which cause variations in electrical characteristics, are mixed into the oxide semiconductor film and the sidewall insulating layer during and after the manufacturing process. , And a barrier film that prevents emission from the oxide semiconductor film and the first sidewall insulating layer.

An insulating film containing a metal element with low oxygen permeability (typically an aluminum oxide film) that can be used for the second sidewall insulating layer is a thin film (typically 10 nm or less, preferably 5 nm or less). ) High effect as the above barrier film. Since the second side wall insulating layer is provided on the first side wall insulating layer that covers the stepped portion formed between the gate insulating film and the gate electrode layer so as to be flattened, the second side wall insulating layer should be formed with good coverage even for a thin film. Can do. The second sidewall insulating layer is formed by etching using the third sidewall insulating layer laminated thereon as a mask. When the second sidewall insulating layer is a thin film, the etching process is easy, and the yield and productivity are improved.

The third side wall insulating layer functions as a mask when the second side wall insulating layer is formed, and the side wall insulating layer formed by stacking three side wall insulating layers can be used as the side wall insulating layer. Thickness and shape can be adjusted.

One embodiment of the structure of the invention disclosed in this specification includes an oxide semiconductor film including a channel formation region provided over the oxide insulating film, a gate insulating film over the oxide semiconductor film, and over the gate insulating film A first sidewall insulating layer covering a gate electrode layer, a part of an upper surface of the gate insulating film, and a side surface of the gate electrode layer; a part of an upper surface of the oxide semiconductor film; a side surface of the gate insulating film; A second sidewall insulating layer covering a side surface of the sidewall insulating layer; a third sidewall insulating layer covering a side surface of the second sidewall insulating layer; and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film The first sidewall insulating layer and the third sidewall insulating layer are oxide insulating films, and the second sidewall insulating layer contains a metal element having a lower oxygen permeability than the first sidewall insulating layer. A semiconductor device which is an insulating film.

Another embodiment of the structure of the invention disclosed in this specification includes an oxide semiconductor film including a channel formation region provided over an oxide insulating film, a gate insulating film over the oxide semiconductor film, and a gate insulating film A gate electrode layer; an insulating film on the gate electrode layer; a part of an upper surface of the gate insulating film; a side surface of the gate electrode layer; and a first sidewall insulating layer covering the side surface of the insulating film; A second side wall insulating layer covering a part of the upper surface of the gate insulating film, a side surface of the gate insulating film, and a side surface of the first side wall insulating layer; a third side wall insulating layer covering the side surface of the second side wall insulating layer; A source electrode layer and a drain electrode layer electrically connected to the physical semiconductor film, wherein the first sidewall insulating layer and the third sidewall insulating layer are oxide insulating films, and the second sidewall insulating layer and the insulating layer The semiconductor is an insulating film containing a metal element having a lower oxygen permeability than that of the first sidewall insulating layer It is the location.

When an insulating film containing a metal element with low oxygen permeability (typically an aluminum oxide film) is provided as an insulating film over the gate electrode layer, a channel formation region of the oxide semiconductor film, the gate insulating film, the gate electrode layer, and The first sidewall insulating layer is covered with the second sidewall insulating layer and the insulating film, that is, the oxide semiconductor film channel formation region, the gate insulating film, the gate electrode layer, and the first sidewall insulating layer are formed. The insulating film containing a metal element with low oxygen permeability that functions as a barrier film (typically an aluminum oxide film) can be used.

Another embodiment of the present invention is a semiconductor device in which the first sidewall insulating layer includes an oxygen-excess region in the above structure.

In the above structure, an oxide insulating film including an oxygen-excess region is provided over the gate electrode layer, and the insulating film containing a metal element having low oxygen permeability (typically an aluminum oxide film) is formed over the oxide insulating film. ), The oxide insulating film provided between the gate electrode layer and an insulating film containing a metal element with low oxygen permeability (typically an aluminum oxide film) is formed as an oxide semiconductor film and a gate. The insulating film and the first sidewall insulating layer can function as an oxygen supply source. In this case, the top and side surfaces of the gate electrode layer can be covered with an oxide insulating film serving as an oxygen supply source.

Another embodiment of the present invention is a semiconductor device in which the source electrode layer and the drain electrode layer are in contact with the oxide semiconductor film and the third sidewall insulating layer in the above structure.

In another embodiment of the structure of the invention disclosed in this specification, a first oxide insulating film is formed, an oxide semiconductor film is formed over the first oxide insulating film, and the oxide semiconductor film is formed over the oxide semiconductor film. An insulating film is formed, a gate electrode layer overlapping with the oxide semiconductor film is formed over the insulating film, an impurity element is introduced into the oxide semiconductor film using the gate electrode layer as a mask, and a second electrode is formed over the insulating film and the gate electrode layer. The first oxide insulating film is formed, the second oxide insulating film is etched to form a first sidewall insulating layer that covers the side surface of the gate electrode layer, and the gate electrode layer and the first sidewall insulating layer are used as a mask. An insulating film is etched to form a gate insulating film, and an oxide semiconductor film, a gate insulating film, and an insulating film containing a metal element having lower oxygen permeability than the first sidewall insulating layer are formed over the first sidewall insulating layer. And forming a third oxide insulating film over the insulating film containing the metal element. The third oxide insulating film is etched to form a third sidewall insulating layer that covers the side surface of the gate electrode layer through the insulating film containing the metal element, and the gate electrode layer and the third sidewall insulating layer are masked As a method for manufacturing a semiconductor device, a second sidewall insulating layer is formed by etching an insulating film containing a metal element, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film are formed.

As the second sidewall insulating layer, a metal film (typically an aluminum film) is formed, and a metal oxide film (typically an aluminum oxide film) formed by performing oxygen doping treatment on the metal film is used. it can. Oxygen can also be supplied to the first sidewall insulating layer provided under the metal film by the oxygen doping treatment.

“Oxygen doping” means adding oxygen (including at least one of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions) to the bulk. Say. The term “bulk” is used for the purpose of clarifying that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. Further, “oxygen doping” includes “oxygen plasma doping” in which oxygen in plasma form is added to a bulk.

A gas containing oxygen can be used for the oxygen doping treatment. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen doping treatment, a gas containing oxygen may contain a rare gas.

Depending on processing conditions, oxygen doping treatment can be performed not only for a film directly exposed to the oxygen doping treatment but also for a film provided under the film.

In the above structure, the second oxide insulating film and the third oxide insulating film can be formed by a deposition method using a deposition gas. For example, it can be formed by a chemical vapor deposition (CVD) method.

In addition, hydrogen or moisture is released to the first oxide insulating film, the oxide semiconductor film, the gate insulating film, the second oxide insulating film, and the third oxide insulating film which are base layers included in the semiconductor device Heat treatment (dehydration or dehydrogenation treatment) may be performed.

In addition, a dopant (impurity element) is introduced into the oxide semiconductor film in a self-aligning manner using the gate electrode layer as a mask, and the resistance is lower than that of the channel formation region with the channel formation region interposed between the oxide semiconductor film and the dopant (impurity element) Can be formed. The dopant is an impurity that changes the conductivity of the oxide semiconductor film. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

With an oxide semiconductor film including a low-resistance region with a channel formation region sandwiched in the channel length direction, the transistor has high on-state characteristics (eg, on-state current and field-effect mobility), and can operate at high speed and with high speed. It becomes.

One embodiment of the present invention relates to a semiconductor device including a transistor or a circuit including the transistor. For example, the invention relates to a semiconductor device including a transistor or a circuit including a transistor in which a channel formation region is formed using an oxide semiconductor. For example, power devices mounted on LSIs, CPUs, power supply circuits, semiconductor integrated circuits including memories, thyristors, converters, image sensors, etc., light-emitting displays having electro-optical devices and light-emitting elements typified by liquid crystal display panels The present invention relates to an electronic device equipped with a device as a component.

In a semiconductor device including a transistor including an oxide semiconductor film, stable electrical characteristics can be imparted and high reliability can be achieved.

A structure and a manufacturing method for realizing high-speed response and high-speed driving of a semiconductor device including a transistor including an oxide semiconductor film can be provided.

4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. 4A and 4B are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 10A and 10B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. In addition, the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor film is described as an example of a semiconductor device.

The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type having two gate electrode layers arranged above and below the channel formation region with a gate insulating film interposed therebetween may be used.

A transistor 440a illustrated in FIGS. 1A to 1C is an example of a top-gate transistor. 1A is a plan view of the transistor 440a, FIG. 1B is a cross-sectional view taken along line XY of FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. It is sectional drawing in V1-W1. Note that in FIG. 1A and FIG. 1C, some components of the transistor 440a are not illustrated in order to avoid complexity.

As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, a semiconductor device including the transistor 440a includes a channel formation region 409, a low-concentration region on a substrate 400 having an insulating surface provided with an oxide insulating film 436. Oxide semiconductor film 403 including resistance regions 404a and 404b, source electrode layer 405a, drain electrode layer 405b, gate insulating film 402, gate electrode layer 401, first sidewall insulating layers 411a and 411b, and second sidewall insulating layer 412a 412b, third sidewall insulating layers 414a and 414b, an insulating film 413, and an interlayer insulating film 415.

In addition, as illustrated in FIG. 1C which is a cross-sectional view in the channel width direction, a side end portion of the oxide semiconductor film 403 is covered with a gate insulating film 402, and an oxygen supply layer is formed over the gate insulating film 402. A first sidewall insulating layer 411 is provided. Further, side surfaces (side ends) of the oxide semiconductor film 403, the gate insulating film 402, and the first sidewall insulating layer 411 are covered with a second sidewall insulating layer 412 that functions as a barrier film that prevents oxygen release. The side surface of the second sidewall insulating layer 412 is covered with a third sidewall insulating layer 414.

Further, a side end portion of the oxide semiconductor film 403 in the channel width direction may be covered with an oxide insulating film serving as an oxygen supply source. 12A and 12B illustrate a structure in which an oxide insulating film 418 serving as an oxygen supply source is provided. 12A is a plan view of the transistor 440a, and FIG. 1B is a cross-sectional view taken along line V2-W2 in FIG.

As illustrated in FIGS. 12A and 12B, at least a side end portion of the oxide semiconductor film 403 in the channel width direction is covered with an oxide insulating film 418. The oxide insulating film 418 can be formed using a material and a method similar to those of the first sidewall insulating layer 411 and the oxide insulating film 436, and is preferably an oxygen-excess film. As the oxide insulating film 418, for example, a silicon oxide film by a sputtering method with a thickness of about 100 nm or a film in which oxygen is introduced into a silicon nitride film by a CVD method may be used.

Accordingly, release of oxygen can be prevented at the side end portion of the oxide semiconductor film 403 and oxygen vacancies can be compensated by supply of oxygen. Therefore, the generation of parasitic channels can be suppressed.

The sidewall insulating layers provided on the side surfaces of the gate electrode layer 401 of the transistor 440a are formed by sequentially stacking first sidewall insulating layers 411a and 411b, second sidewall insulating layers 412a and 412b, and third sidewall insulating layers 414a and 414b. It is the laminated structure made.

The first sidewall insulating layers 411a and 411b are in contact with part of the top surface of the gate insulating film 402 and the side surface of the gate electrode layer 401, and the second sidewall insulating layers 412a and 412b are part of the top surface of the oxide semiconductor film 403. The side surfaces of the gate insulating film 402 are in contact with the side surfaces of the first sidewall insulating layers 411a and 411b, and the third sidewall insulating layers 414a and 414b are in contact with the side surfaces of the second sidewall insulating layers 412a and 412b.

The first sidewall insulating layers 411a and 411b are preferably formed using an oxide insulating film having an oxygen-excess region.

The first sidewall insulating layers 411a and 411b which are excessively filled with oxygen and contain excess oxygen in a region adjacent to the oxide semiconductor film 403 and the gate insulating film 402 are formed of the gate insulating film 402 and the oxide semiconductor film 403. Oxygen is prevented from desorption from the oxide semiconductor film 403 and functions as an effective oxygen supply layer to the oxide semiconductor film 403 and the gate insulating film 402.

Excess oxygen stored in the first sidewall insulating layers 411a and 411b in a region adjacent to the oxide semiconductor film 403 and the gate insulating film 402 is efficiently supplied to the gate insulating film 402 and the oxide semiconductor film 403. Can do. Therefore, in the semiconductor device, generation of parasitic channels can be suppressed, and oxygen vacancies in the oxide semiconductor film 403 and the interface can be compensated. Further, heat treatment can be performed after the oxygen doping treatment, so that oxygen can be supplied from the oxygen-excess region to the oxide semiconductor film 403 and the gate insulating film 402.

The second sidewall insulating layers 412a and 412b provided in contact with part of the top surface of the oxide semiconductor film 403, the side surfaces of the gate insulating film 402, and the side surfaces of the first sidewall insulating layers 411a and 411b are the first sidewall insulating layers. An insulating film (typically, an aluminum oxide film or a film including an aluminum oxide film) containing a metal element that has lower oxygen permeability than 411a and 411b is used.

By using an insulating film containing a metal element having low oxygen permeability as the second sidewall insulating layers 412a and 412b, release of oxygen from the first sidewall insulating layers 411a and 411b can be prevented.

The aluminum oxide film can be suitably used as an insulating film containing a metal element with low oxygen permeability. The aluminum oxide film has a high blocking effect (blocking effect) that prevents both hydrogen, moisture and other impurities, and oxygen from passing through the film. Therefore, when the aluminum oxide film is provided as the second sidewall insulating layers 412a and 412b, the oxide semiconductor film 403 of impurities such as hydrogen and moisture, which cause variation in electrical characteristics during and after the manufacturing process, and the first Can be functioned as a barrier film for preventing entry into the sidewall insulating layers 411a and 411b and emission from the oxide semiconductor film 403 and the first sidewall insulating layers 411a and 411b.

An insulating film (typically, an aluminum oxide film) containing a metal element having lower oxygen permeability than the first sidewall insulating layers 411a and 411b that can be used for the second sidewall insulating layers 412a and 412b is a thin film. (Typically 10 nm or less, preferably 5 nm or less), the above barrier film is highly effective. The second sidewall insulating layers 412a and 412b are thin films because they are provided over the first sidewall insulating layers 411a and 411b so as to flatten the stepped portions formed between the gate insulating film 402 and the gate electrode layer 401. However, it can be formed with good coverage. Therefore, since the second sidewall insulating layers 412a and 412b can be thinned, processing is facilitated and productivity is improved.

An oxide insulating film can be used for the third sidewall insulating layers 414a and 414b. The third sidewall insulating layers 414a and 414b function as a mask when the second sidewall insulating layers 412a and 412b are formed, and the sidewall insulating layers of the transistor 440a formed by stacking three sidewall insulating layers are used as the sidewalls. The film thickness and shape can be adjusted to such an extent that they can function as an insulating layer.

The transistor 440 a includes an insulating film 413 over the gate electrode layer 401. In addition to functioning as a mask when the gate electrode layer 401 is formed, the insulating film 413 uses a film having a high barrier property (for example, an insulating film containing a metal element having lower oxygen permeability than the first sidewall insulating layers 411a and 411b). Thus, the transistor 440a can function as a protective film.

For example, when an insulating film containing a metal element with low oxygen permeability (typically an aluminum oxide film or a film including an aluminum oxide film) is provided as the insulating film 413 over the gate electrode layer 401, the oxide semiconductor film 403 The channel formation region 409, the gate insulating film 402, the gate electrode layer 401, and the first sidewall insulating layers 411a and 411b are covered with the second sidewall insulating layers 412a and 412b and the insulating film 413, that is, an oxide The channel formation region 409, the gate insulating film 402, the gate electrode layer 401, and the first sidewall insulating layers 411a and 411b of the semiconductor film 403 are formed using an insulating film containing a metal element with low oxygen permeability that functions as a barrier film (typically Can be covered with an aluminum oxide film or a film containing an aluminum oxide film.

Note that a dopant is introduced into the oxide semiconductor film 403 in a self-aligning manner using the gate electrode layer 401 as a mask, and the oxide semiconductor film 403 has a resistance lower than that of the channel formation region 409 with the channel formation region 409 interposed therebetween. Resistive regions 404a and 404b are formed. The dopant is an impurity (impurity element) that changes the conductivity of the oxide semiconductor film 403. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

By including the oxide semiconductor film 403 including the low-resistance regions 404a and 404b with the channel formation region 409 sandwiched in the channel length direction, the transistor 440a has high on-state characteristics (eg, on-state current and field-effect mobility) and high speed. Operation and high-speed response are possible.

An oxide semiconductor used for the oxide semiconductor film 403 contains at least indium (In). In particular, it is preferable to contain In and zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides In—Zn oxide, In—Mg oxide, In—Ga oxide, ternary metal In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La -Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm- Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, four In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, and In-Sn-Al-Zn-based oxides that are oxides of the base metal In-Sn-Hf-Zn-based oxides and In-Hf-Al-Zn-based oxides can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

However, the oxide semiconductor containing indium is not limited thereto, and an oxide semiconductor having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, and the like). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: The composition of the oxide of C (A + B + C = 1) is in the vicinity, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ r ² Satisfying. For example, r may be 0.05. The same applies to other oxides.

For example, the oxide semiconductor film 403 may include a non-single crystal. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous part. The amorphous part has a higher density of defect states than microcrystals and CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

For example, the oxide semiconductor film may include a CAAC-OS. For example, the CAAC-OS is c-axis oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

The oxide semiconductor film may include microcrystal, for example. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Alternatively, the microcrystalline oxide semiconductor film includes an oxide semiconductor having a crystal-amorphous mixed phase structure with a crystal part of 1 nm to less than 10 nm, for example.

For example, the oxide semiconductor film may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous and has no crystal part.

Note that the oxide semiconductor film may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

Note that the oxide semiconductor film may include a single crystal, for example.

The oxide semiconductor film preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

The CAAC-OS film is not completely amorphous. The CAAC-OS film includes, for example, an oxide semiconductor with a crystal-amorphous mixed phase structure including a crystal part and an amorphous part. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film and the boundary between the crystal part and the crystal part are not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. When viewed from the direction, the metal atoms are arranged in a triangular shape or a hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, the directions may be different from each other. The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Ra is an arithmetic mean roughness defined in JIS B 0601: 2001 (ISO4287: 1997) extended to three dimensions so that it can be applied to curved surfaces. It can be expressed as “average value of absolute values” and is defined by the following equation.

Here, the designated surface is a surface that is a target of roughness measurement, and has coordinates (x ₁ , y ₁ , f (x ₁ , y ₁ )), (x ₁ , y ₂ , f (x ₁ , y). ₂ )), (x ₂ , y ₁ , f (x ₂ , y ₁ )), (x ₂ , y ₂ , f (x ₂ , y ₂ )) A rectangular area obtained by projecting the surface onto the xy plane is represented by S ₀ , and the height of the reference surface (average height of the designated surface) is represented by Z ₀ . Ra can be measured with an atomic force microscope (AFM).

The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm), and a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method. Etc. can be used as appropriate. Alternatively, the oxide semiconductor film 403 may be formed using a sputtering apparatus which performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target.

For example, the CAAC-OS film is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target is cleaved from the ab plane, and may be separated as flat or pellet-like sputtering particles having a plane parallel to the ab plane. is there. In this case, the flat-plate-like sputtered particle reaches the substrate while maintaining a crystalline state, whereby a CAAC-OS film can be formed.

In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) existing in the deposition chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature at the time of film formation, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-Ga-Zn- which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder in a predetermined number of moles, and after heat treatment at a temperature of 1000 ° C. to 1500 ° C. An O compound target is used. X, Y and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3 or 3: 1: 2. Note that the type of powder and the mol number ratio to be mixed may be changed as appropriate depending on the sputtering target to be manufactured.

The oxide semiconductor film 403 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor film 403 is formed as a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and metal oxides having different compositions are formed on the first oxide semiconductor layer and the second oxide semiconductor layer. You may use thing. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, both the first oxide semiconductor layer and the second oxide semiconductor layer may be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be the same, and the compositions of the elements may be different. For example, the atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 2: 1: 3. It is good.

At this time, the In and Ga contents in the oxide semiconductor layer on the side close to the gate electrode (channel side) of the first oxide semiconductor layer and the second oxide semiconductor layer may be In> Ga. The content ratio of In and Ga in the oxide semiconductor layer far from the gate electrode (back channel side) is preferably In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor layer and the second oxide semiconductor layer. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, internal stress and external stress of the oxide semiconductor film 403 are relieved, The variation in characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, an oxide semiconductor having crystallinity such as CAAC-OS is preferably used for the oxide semiconductor layer on the channel side.

Alternatively, the oxide semiconductor film 403 may have a stacked structure of three or more layers, and a structure in which an amorphous oxide semiconductor layer is sandwiched between a plurality of crystalline oxide semiconductor layers. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the oxide semiconductor film 403 has a stacked structure of a plurality of layers can be used in appropriate combination.

2A to 2F illustrate an example of a method for manufacturing a semiconductor device including the transistor 440a.

First, the oxide insulating film 436 is formed over the substrate 400 having an insulating surface.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance enough to withstand heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device having flexibility, the transistor 440a including the oxide semiconductor film 403 may be directly formed over a flexible substrate, or the transistor including the oxide semiconductor film 403 over another manufacturing substrate. 440a may be manufactured and then peeled off and transferred to the flexible substrate. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor 440a including the oxide semiconductor film.

The oxide insulating film 436 can be formed by a plasma CVD method, a sputtering method, or the like using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material thereof. .

The oxide insulating film 436 may be a single layer or a stacked layer. For example, a silicon oxide film, an In—Hf—Zn-based oxide film, and an oxide semiconductor film 403 may be sequentially stacked over the substrate 400, or a silicon oxide film, In: Zr: Zn = 1: An In—Zr—Zn-based oxide film and an oxide semiconductor film 403 with an atomic ratio of 1: 1 may be stacked in this order, or a silicon oxide film, In: Gd: Zn = 1: 1: over the substrate 400. Alternatively, an In—Gd—Zn-based oxide film and an oxide semiconductor film 403 with an atomic ratio of 1 may be stacked in this order.

In this embodiment, a silicon oxide film formed by a sputtering method is used as the oxide insulating film 436.

Further, a nitride insulating film may be provided between the oxide insulating film 436 and the substrate 400. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or a mixed material thereof by a plasma CVD method, a sputtering method, or the like.

Since the oxide insulating film 436 is in contact with the oxide semiconductor film 403, it is preferable that oxygen in the film (in the bulk) be present in an amount exceeding at least the stoichiometric composition. For example, in the case where a silicon oxide film is used as the oxide insulating film 436, SiO _{2 + α} (where α> 0) is set. By using such an oxide insulating film 436, oxygen can be supplied to the oxide semiconductor film 403, which can improve characteristics. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled.

For example, by providing the oxide insulating film 436 containing a large amount (excessive) of oxygen which is an oxygen supply source in contact with the oxide semiconductor film 403, oxygen is supplied from the oxide insulating film 436 to the oxide semiconductor film 403. can do. Oxygen may be supplied to the oxide semiconductor film 403 by performing heat treatment with at least part of the oxide semiconductor film 403 and the oxide insulating film 436 being in contact with each other.

Planarization treatment may be performed on a region where the oxide semiconductor film 403 is in contact with the oxide insulating film 436. The planarization treatment is not particularly limited, and polishing treatment (for example, chemical mechanical polishing (CMP)), dry etching treatment, or plasma treatment can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. By performing reverse sputtering, powdery substances (also referred to as particles or dust) attached to the surface of the oxide insulating film 436 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate depending on the unevenness state of the surface of the oxide insulating film 436.

For example, the surface of the silicon oxide film used as the oxide insulating film 436 is polished by a chemical mechanical polishing method (polishing conditions: polyurethane-based polishing cloth, silica-based slurry, slurry temperature room temperature, polishing pressure 0.001 MPa, The number of rotations during polishing (table / spindle) is 60 rpm / 56 rpm and the polishing time is 0.5 minutes, and the average surface roughness (Ra) on the silicon oxide film surface may be about 0.15 nm.

Next, the oxide semiconductor film 403 is formed over the oxide insulating film 436.

In the formation process of the oxide semiconductor film 403, in order to prevent hydrogen or water from being contained in the oxide semiconductor film 403 as much as possible, as a pretreatment for forming the oxide semiconductor film 403, a preheating chamber of a sputtering apparatus is used. The substrate over which the oxide insulating film 436 is formed is preferably preheated, and impurities such as hydrogen and moisture adsorbed on the substrate and the oxide insulating film 436 are released and exhausted. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber.

Further, hydrogen (including water and hydroxyl groups) is removed from the oxide insulating film 436 so that impurities such as hydrogen (including water and hydroxyl groups) are reduced and oxygen is excessive. Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping treatment for dehydration or dehydrogenation may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be performed repeatedly.

The oxide semiconductor film 403 is preferably in a supersaturated state with more oxygen than the stoichiometric composition immediately after the formation. For example, in the case where the oxide semiconductor film 403 is formed by a sputtering method, the film formation is preferably performed under a condition where the proportion of oxygen in the film formation gas is large, particularly in an oxygen atmosphere (oxygen gas 100%). Preferably it is done. When the film is formed in a condition where the proportion of oxygen in the film forming gas is large, particularly in an atmosphere containing 100% oxygen gas, the release of Zn from the film can be suppressed even when the film forming temperature is set to 300 ° C. or higher.

In addition, since sufficient oxygen is supplied so that oxygen is in a supersaturated state, the insulating film in contact with the oxide semiconductor film 403 (a plurality of insulating films provided so as to surround the oxide semiconductor film 403) contains excess oxygen. An insulating film is preferable.

Note that in this embodiment, as a target for forming the oxide semiconductor film 403 by a sputtering method, an oxide target of In: Ga: Zn = 3: 1: 2 [atomic percentage] is used as a composition. An In—Ga—Zn-based oxide film (IGZO film) is formed.

The relative density (filling rate) of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target having a high relative density, the formed oxide semiconductor film can be a dense film.

As a sputtering gas used for forming the oxide semiconductor film 403, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

The substrate is held in a film formation chamber held in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the deposition chamber is removed, and the oxide semiconductor film 403 is formed over the substrate 400 using the above target. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the oxide semiconductor film 403 formed in the chamber can be reduced.

The oxide insulating film 436 and the oxide semiconductor film 403 are preferably formed successively without being released to the atmosphere. When the oxide insulating film 436 and the oxide semiconductor film 403 are formed successively without being exposed to the air, adsorption of impurities such as hydrogen and moisture to the surface of the oxide insulating film 436 can be prevented.

The oxide semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography process.

Further, a resist mask for forming the island-shaped oxide semiconductor film 403 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

Note that the etching of the oxide semiconductor film may be dry etching or wet etching, or both of them may be used. For example, as an etchant used for wet etching of the oxide semiconductor film, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Moreover, ITO-07N (manufactured by Kanto Chemical Co., Inc.) may be used. Alternatively, etching may be performed by dry etching using an ICP (Inductively Coupled Plasma) etching method. For example, an IGZO film is etched by ICP etching (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), power supply power 450 W, bias power 100 W, pressure 1.9 Pa) and processed into an island shape. Can do.

The oxide semiconductor film 403 is preferably highly purified so as not to contain impurities such as copper, aluminum, and chlorine. In the manufacturing process of the transistor 440a, it is preferable to select as appropriate a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor film 403. It is preferable to remove impurities on the surface of the oxide semiconductor film 403 by exposure to dilute hydrofluoric acid or the like or plasma treatment (N ₂ O plasma treatment or the like). Specifically, the copper concentration of the oxide semiconductor film 403 is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. The aluminum concentration of the oxide semiconductor film 403 is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration of the oxide semiconductor film 403 is 2 × 10 ¹⁸ atoms / cm ³ or less.

The oxide semiconductor film 403 may be subjected to heat treatment for removing excess hydrogen (including water and a hydroxyl group) (dehydration or dehydrogenation). The temperature of the heat treatment is 300 ° C. or higher and 700 ° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere. For example, a substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and the oxide semiconductor film 403 is subjected to heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then the substrate is taken out of the inert gas.

Note that in the heat treatment, it is preferable that water, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

In addition, after heating the oxide semiconductor film 403 by heat treatment, a dew point of high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) method) is supplied to the same furnace. The amount of water when measured using a meter may be 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or the dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or nitrous oxide introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide is 1 ppm or less, preferably 0.1 ppm or less. ) Is preferable. Oxygen is supplied by supplying oxygen, which is a main component material of the oxide semiconductor, which has been reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas. The physical semiconductor film 403 can be highly purified and electrically i-type (intrinsic).

Note that the timing for performing the heat treatment for dehydration or dehydrogenation may be after the formation of the film-shaped oxide semiconductor film or after the formation of the island-shaped oxide semiconductor film 403.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatments.

When heat treatment for dehydration or dehydrogenation is performed in a state where the film-shaped oxide semiconductor film covers the oxide insulating film 436 before being processed into an island shape as the oxide semiconductor film 403, an oxide is formed. This is preferable because oxygen contained in the insulating film 436 can be prevented from being released by heat treatment.

In the oxide semiconductor film, oxygen vacancies exist at locations where oxygen is released, and donor levels that cause fluctuations in electrical characteristics of the transistor are generated due to the oxygen vacancies. In particular, oxygen, which is a main component material of the oxide semiconductor, may be simultaneously desorbed and reduced by dehydration or dehydrogenation treatment.

Therefore, oxygen is preferably supplied to the oxide semiconductor film 403 when dehydration or dehydrogenation treatment is performed. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled.

Therefore, dehydration or dehydrogenation treatment is preferably performed before the step of introducing oxygen into the oxide semiconductor film 403.

In addition, by providing an oxide insulating film containing a large amount (excessive) of oxygen which serves as an oxygen supply source in contact with the oxide semiconductor film 403, oxygen is supplied from the oxide insulating film to the oxide semiconductor film 403. Can do. In the above structure, oxygen treatment of the oxide semiconductor film is performed by performing heat treatment in a state where at least part of the oxide semiconductor film 403 and the oxide insulating film subjected to heat treatment as dehydration or dehydrogenation treatment are in contact with each other. Supply may be performed.

In addition, any of oxygen (at least oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions) is added to the oxide semiconductor film 403 subjected to dehydration or dehydrogenation treatment. Oxygen doping treatment may be performed to introduce oxygen into the film. The oxygen dope includes “oxygen plasma dope” in which oxygen in plasma is added to a bulk.

A gas containing oxygen can be used for the oxygen doping treatment. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, a rare gas may be used in the oxygen doping process.

Doped oxygen (oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions) is ion implantation, ion doping, plasma immersion ion implantation, plasma treatment. Etc. can be used. A gas cluster ion beam may be used for the ion implantation method. The oxygen doping treatment may be performed on the entire surface at once, or may be performed by moving (scanning) using a linear ion beam or the like.

In the oxygen doping treatment, for example, when oxygen ions are implanted by an ion implantation method, the dose may be set to 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

The oxide semiconductor film 403 is preferably highly purified by sufficiently removing impurities such as hydrogen or by being supplied with sufficient oxygen to be in a supersaturated state. . Specifically, the hydrogen concentration of the oxide semiconductor film 403 is 5 × 10 ¹⁹ atoms / cm ³ or lower, preferably 5 × 10 ¹⁸ atoms / cm ³ or lower, more preferably 5 × 10 ¹⁷ atoms / cm ³ or lower. . Note that the hydrogen concentration in the oxide semiconductor film 403 is measured by secondary ion mass spectrometry (SIMS).

In addition, the insulating film in contact with the oxide semiconductor film 403 (the oxide insulating film 436, the gate insulating film 402, and the insulating film 407 (see the transistors 440b to 440e in FIG. 4)) can sufficiently remove impurities such as hydrogen. preferable. Specifically, the hydrogen concentration of the insulating film in contact with the oxide semiconductor film 403 is preferably less than 7.2 × 10 ²⁰ atoms / cm ³ .

Hydrogen or moisture is removed from the oxide semiconductor, purified so as not to contain impurities as much as possible, and supplied with oxygen to fill oxygen vacancies, thereby providing an I-type (intrinsic) oxide semiconductor or an I-type (intrinsic) ) Can be an oxide semiconductor close to the limit. By doing so, the Fermi level (Ef) of the oxide semiconductor can be brought to the same level as the intrinsic Fermi level (Ei). Therefore, when the oxide semiconductor film is used for a transistor, variation in threshold voltage Vth of the transistor due to oxygen vacancies and threshold voltage shift ΔVth can be reduced.

Next, an insulating film 442 which covers the oxide semiconductor film 403 is formed.

Note that the planarization treatment may be performed on the surface of the oxide semiconductor film 403 in order to improve the coverage with the insulating film 442. In particular, when a thin insulating film is used as the insulating film 442, the surface of the oxide semiconductor film 403 is preferably flat.

The thickness of the insulating film 442 is 1 nm to 20 nm, and a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. Alternatively, the insulating film 442 may be formed using a sputtering apparatus which performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target.

As a material of the insulating film 442, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. The insulating film 442 preferably contains oxygen in a portion in contact with the oxide semiconductor film 403. In particular, the insulating film 442 preferably has oxygen in the film (in the bulk) in an amount exceeding at least the stoichiometric composition. For example, when a silicon oxide film is used as the insulating film 442, SiO _{2 + α} (Where α> 0). In this embodiment, as the insulating film 442, a silicon oxide film with SiO _{2 + α} (α> 0) is used. By using this silicon oxide film as the insulating film 442, oxygen can be supplied to the oxide semiconductor film 403, whereby characteristics can be improved. Further, the insulating film 442 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage of the insulating film 442.

Further, as the material of the insulating film 442, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0, y) > 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), and high-k materials such as lanthanum oxide can be used to reduce gate leakage current. Further, the insulating film 442 may have a single-layer structure or a stacked structure.

Further, in order to reduce impurities such as hydrogen (including water and hydroxyl groups) and to be in an oxygen-excess state in the insulating film 442, hydrogen (including water and hydroxyl groups) is removed from the insulating film 442 (dehydration or dehydration). Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping treatment may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be performed repeatedly.

In this embodiment, oxygen plasma treatment using a microwave is performed on the insulating film 442 while heating at 200 ° C. to 400 ° C. By this treatment, the insulating film 442 has a high density, and the insulating film 442 can be subjected to dehydration or dehydrogenation treatment and oxygen doping treatment.

Next, a stack of a conductive film and an insulating film is formed over the insulating film 442, and the conductive film and the insulating film are etched to form a stack of the gate electrode layer 401 and the insulating film 413. The conductive film can be etched using the insulating film 413 as a mask to form the gate electrode layer 401.

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

The material of the gate electrode layer 401 is indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, oxide A conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Further, as one layer of the gate electrode layer 401 in contact with the insulating film 442, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, In—Ga—O film containing nitrogen, In—Zn—O film containing nitrogen, Sn—O film containing nitrogen, In—O film containing nitrogen, metal nitride film (InN, SnN, etc.) Can be used. These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor is made positive. Thus, a so-called normally-off switching element can be realized.

The insulating film 413 is typically an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film. Can be used. The insulating film 413 can be formed by a plasma CVD method, a sputtering method, or the like.

As the insulating film 413, a metal oxide film (typically an aluminum oxide film) formed by forming a metal film (typically an aluminum film) and performing oxygen doping treatment on the metal film can be used. In this embodiment, as the insulating film 413, an aluminum oxide film formed by forming an aluminum film and performing oxygen doping treatment on the aluminum film is used.

Next, dopant is introduced into the oxide semiconductor film 403 using the gate electrode layer 401 and the insulating film 413 as masks, so that low-resistance regions 404a and 404b are formed (see FIG. 2A).

The dopant is an impurity element that changes the conductivity of the oxide semiconductor film 403. As dopants, group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), tungsten (W), molybdenum (Mo), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), gallium (Ga), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) One or more selected from either can be used.

The dopant can be introduced into the oxide semiconductor film 403 through another film (eg, the insulating film 442) by an implantation method. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of a dopant, or a fluoride or chloride ion.

The dopant introduction step may be controlled by appropriately setting the implantation conditions such as the acceleration voltage and the dose, and the thickness of the film to be passed. In this embodiment, phosphorus ions are implanted by an ion implantation method using phosphorus as a dopant. Note that the dose amount of the dopant may be 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

The concentration of the dopant in the low resistance region is preferably 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²² / cm ³ or less.

When introducing the dopant, the substrate 400 may be heated.

Note that the treatment for introducing the dopant into the oxide semiconductor film 403 may be performed a plurality of times, and a plurality of types of dopant may be used.

Further, a heat treatment may be performed after the dopant introduction treatment. As heating conditions, it is preferable that the temperature is 300 ° C. or higher and 700 ° C. or lower, preferably 300 ° C. or higher and 450 ° C. or lower for 1 hour in an oxygen atmosphere. Further, the heat treatment may be performed under a nitrogen atmosphere, reduced pressure, or air (ultra-dry air).

In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The phosphorus (P) ion implantation conditions are an acceleration voltage of 30 kV and a dose of 1.0 × 10 ¹⁵ ions / cm ² .

In the case where the oxide semiconductor film 403 is a CAAC-OS film, the oxide semiconductor film 403 may be partially amorphized by introduction of a dopant.

Thus, the oxide semiconductor film 403 provided with the low resistance regions 404a and 404b with the channel formation region 409 interposed therebetween is formed.

Next, first sidewall insulating layers 411a and 411b are formed, and the insulating film 442 is etched using the first sidewall insulating layers 411a and 411b, the insulating film 413, and the gate electrode layer 401 as a mask to form the gate insulating film 402. (See FIG. 2B).

The first sidewall insulating layers 411a and 411b can be formed by forming an insulating film 444 and etching (anisotropic etching) the insulating film 444 as shown in FIG.

The first sidewall insulating layers 411a and 411b preferably have an oxygen excess region.

The oxygen excess region included in the first sidewall insulating layers 411a and 411b is formed by performing oxygen doping treatment (oxygen introduction treatment) on the first sidewall insulating layers 411a and 411b and / or the insulating film 444 before etching. can do. FIG. 3A shows an example in which the insulating film 444 is doped with oxygen 431a to provide an oxygen-excess region. FIG. 3B shows an example in which the first sidewall insulating layers 411a and 411b are doped with oxygen 431b to provide an oxygen-excess region. The oxygen doping treatment may be performed in one state of the insulating film 444 before etching and the first sidewall insulating layers 411a and 411b after etching, or both of the states may be performed.

In the first sidewall insulating layers 411a, 411b, and / or the insulating film 444 before etching, at least one or more places in the first sidewall insulating layers 411a, 411b, and / or the insulating film before etching by oxygen doping treatment. An oxygen-excess region can be provided in which there is more than 444 stoichiometric oxygen. In the oxygen doping treatment, oxygen may also be supplied to the first sidewall insulating layers 411a and 411b and / or the gate insulating film 402 and the oxide semiconductor film 403 provided under the insulating film 444 before etching. it can.

The first sidewall insulating layers 411a and 411b (insulating film 444) are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, and a silicon nitride oxide film. An inorganic insulating film such as an aluminum nitride oxide film can be used and may be a single layer or a stacked layer. The first sidewall insulating layers 411a and 411b (the insulating film 444) can be formed using a plasma CVD method, a sputtering method, or a CVD method using a deposition gas. As the CVD method, an LPCVD method, a plasma CVD method, or the like can be used. As another method, a coating film or the like can also be used.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method is used as the first sidewall insulating layers 411a and 411b (insulating film 444).

Over the oxide semiconductor film 403, the gate insulating film 402, the gate electrode layer 401, the first sidewall insulating layers 411a and 411b, and the insulating film 413, the oxygen permeability is lower than that of the first sidewall insulating layers 411a and 411b and the dense structure An insulating film 443 is provided as an insulating film containing a highly metal element (typically, an aluminum oxide film) (see FIG. 2C).

The insulating film 443 may be a single layer or a stacked layer, but includes an insulating film containing a metal element having oxygen permeability lower than that of the first sidewall insulating layers 411a and 411b.

When an aluminum oxide film having a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more) is used as the insulating film containing a metal element with low oxygen permeability, a stable electrical property can be obtained in the transistor 440a. It is more preferable because it can impart a desired characteristic. In addition, the insulating film containing a metal element having low oxygen permeability preferably includes oxygen in the film (in the bulk) in an amount exceeding the stoichiometric composition. For example, when an aluminum oxide film is used, AlO _x (where x> 1.5) may be set.

An aluminum oxide film that can be used as the insulating film 443 has a high blocking effect (blocking effect) that prevents both an impurity such as hydrogen and moisture and oxygen from passing through the film.

Therefore, the insulating film 443 is mixed into the oxide semiconductor film 403 and the first sidewall insulating layers 411a and 411b with impurities such as hydrogen and moisture, which cause electric characteristics to change during and after the manufacturing process, and It functions as a protective film for preventing release of oxygen from the oxide semiconductor film 403 and the first sidewall insulating layers 411a and 411b.

The insulating film 443 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like. Alternatively, a metal oxide film obtained by performing oxidation treatment on a metal film may be used as the insulating film 443. As illustrated in FIG. 3C, a metal film 446 is formed over the oxide semiconductor film 403, the gate insulating film 402, the gate electrode layer 401, the first sidewall insulating layers 411a and 411b, and the insulating film 413. As shown in FIG. 3D, the metal film 446 is oxidized by doping oxygen 431c, so that the insulating film 443 that is an oxide insulating film can be formed.

In this embodiment, as the insulating film 443, an aluminum oxide film obtained by performing oxygen doping treatment on an aluminum film is used.

The oxygen 431a, 431b, and 431c contain at least any of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions.

For the introduction of oxygen 431a, 431b, and 431c, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used. A gas cluster ion beam may be used as the ion implantation method. In addition, the introduction of oxygen 431a, 431b, and 431c may be performed on the entire surface of the substrate 400 at a time, or, for example, a linear ion beam may be used. In the case of using a linear ion beam, oxygen 431a, 431b, and 431c can be introduced to the entire surface of the film by relatively moving (scanning) the substrate or the ion beam.

As a supply gas of the oxygen 431a, 431b, and 431c, a gas containing O may be used. For example, O ₂ gas, N ₂ O gas, CO ₂ gas, CO gas, NO ₂ gas, or the like can be used. Note that a rare gas (eg, Ar) may be included in the oxygen supply gas.

The oxygen content in the treatment film after the oxygen doping treatment is preferably set to a level exceeding the stoichiometric composition of the treatment film. Note that the region containing oxygen in excess of the stoichiometric composition may be present in part of the treatment film. Note that the depth of oxygen implantation may be appropriately controlled depending on the implantation conditions.

Next, third sidewall insulating layers 414a and 414b are formed over the insulating film 443 (see FIG. 2D).

The third sidewall insulating layers 414a and 414b can be formed by forming an insulating film and etching the insulating film (anisotropic etching). The third sidewall insulating layers 414a and 414b may be formed using a material and a method similar to those of the first sidewall insulating layers 411a and 411b.

The thickness and shape of the third sidewall insulating layers 414a and 414b can be adjusted to such an extent that the sidewall insulating layer formed by stacking the three sidewall insulating layers can function as the sidewall insulating layer.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method is used as the third sidewall insulating layers 414a and 414b.

Next, the insulating film 443 is etched using the third sidewall insulating layers 414a and 414b as masks to form second sidewall insulating layers 412a and 412b (see FIG. 2E).

Even if the aluminum oxide film that can be used for the second sidewall insulating layers 412a and 412b is a thin film (typically 10 nm or less, preferably 5 nm or less), the above-described barrier film is highly effective. Since the second side wall insulating layers 412a and 412b are formed by etching using the third side wall insulating layers 414a and 414b stacked thereon as a mask, the second side wall insulating layers 412a and 412b are thin films. The etching process is easy, and the yield and productivity are improved. Therefore, as described in this embodiment, it is preferable to use an aluminum oxide film with high barrier properties as the second sidewall insulating layers 412a and 412b even if they are thin films.

After the second sidewall insulating layers 412a and 412b are formed, heat treatment may be performed at a temperature of 300 ° C. to 500 ° C. (eg, 400 to 450 ° C.). By the heat treatment, oxygen contained in the oxygen-excess regions of the first sidewall insulating layers 411a and 411b is diffused into the end portion of the oxide semiconductor film 403 in the channel width direction and enters from the end portion of the oxide semiconductor film 403. be able to. Further, the oxygen can be diffused into the gate insulating film 402 so that the interface between the oxide semiconductor film 403 and the gate insulating film 402 can be modified. Further, since the first sidewall insulating layers 411a and 411b are provided very close to the channel formation region 409 of the oxide semiconductor film 403, the oxygen in the first sidewall insulating layers 411a and 411b 409 can also be supplied. Therefore, oxygen contained in the first sidewall insulating layers 411a and 411b can be supplied to the oxide semiconductor film 403 and the gate insulating film 402 so that oxygen vacancies can be compensated.

An interlayer insulating film 415 is formed over the insulating film 413 and the third sidewall insulating layers 414a and 414b. The interlayer insulating film 415 can be formed using a material and a method similar to those of the third sidewall insulating layers 414a and 414b. In this embodiment, the interlayer insulating film 415 is formed to a thickness that can planarize unevenness caused by the transistor 440a. As the interlayer insulating film 415, a silicon oxynitride film formed by a CVD method or a silicon oxide film formed by a sputtering method can be used.

Further, a planarization insulating film may be formed in order to reduce surface unevenness due to the transistor. As the planarization insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed using these materials.

An opening reaching the oxide semiconductor film 403 is formed in the interlayer insulating film 415, and a source electrode layer 405a and a drain electrode layer 405b are formed in the opening. Various circuits can be formed by using the source electrode layer 405a and the drain electrode layer 405b to be connected to another transistor or element.

As a conductive film used for the source electrode layer 405a and the drain electrode layer 405b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above-described element is used as a component. A metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. The conductive film used for the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ ), and indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

For example, as the source electrode layer 405a and the drain electrode layer 405b, a single layer of a molybdenum film, a stack of a tantalum nitride film and a copper film, a stack of a tantalum nitride film and a tungsten film, or the like can be used.

Through the above steps, a semiconductor device including the transistor 440a of this embodiment can be manufactured (see FIG. 2F).

4A to 4D illustrate transistors 440b, 440c, 440d, and 440e with other structures.

As illustrated in the transistor 440b, an oxide insulating film 416 including an oxygen-excess region is provided over the gate electrode layer 401, and oxygen permeability is higher than that of the first sidewall insulating layers 411a and 411b over the oxide insulating film 416. A structure may be employed in which an insulating film 413 including a low-dense and dense metal element (typically, an aluminum oxide film) is included. With this structure, the oxide insulating film 416 provided between the gate electrode layer 401 and the insulating film 413 is transferred to the oxide semiconductor film 403, the gate insulating film 402, and the first sidewall insulating layers 411a and 411b. It can function as an oxygen supply source. In this case, the top and side surfaces of the gate electrode layer 401 can be covered with an oxide insulating film serving as an oxygen supply source.

A barrier film (protective film) for preventing release of oxygen may be provided over the transistor.

In the transistors 440c to 440e, the insulating film 407 is provided as a barrier film. As the barrier film, a film including an aluminum oxide film can be preferably used. Further, a stacked film in which a titanium oxide film, a nickel oxide film, a molybdenum oxide film, or a tungsten oxide film is stacked may be provided below or on the aluminum oxide film as the barrier film.

Note that when the aluminum oxide film used as the insulating film 407 functioning as a barrier film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), the transistor 440a has stable electrical characteristics. Is preferable. Such a high-density aluminum oxide film can be preferably used as the second sidewall insulating layers 412a and 412b and the insulating film 413.

The transistors 440c to 440e are covered with an insulating film 407 functioning as a barrier film for preventing oxygen release over the transistors 440c to 440e, so that release of oxygen from the transistors 440c to 440e (at least the oxide semiconductor film 403) is prevented. In addition, oxygen deficiency can be compensated by supplying oxygen. Therefore, generation of a parasitic channel can be suppressed.

In addition to the aluminum oxide film, the insulating film 407 can be typically an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film. Alternatively, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride film (eg, an aluminum nitride film) can be used.

In the transistors 440d and 440e, the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the exposed upper surface of the oxide semiconductor film 403 and the third sidewall insulating layers 414a and 414b. Therefore, the distance between the gate electrode layer 401 and the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the oxide semiconductor film 403 is determined by the sidewall insulating layers (first sidewall insulating layers 411a, 411b, The width of the second sidewall insulating layers 412a and 412b and the third sidewall insulating layers 414a and 414b) is the width in the channel length direction, so that further miniaturization can be achieved and the manufacturing process can be controlled more uniformly.

In this manner, the distance between the gate electrode layer 401 and the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the oxide semiconductor film 403 can be shortened; The resistance between the region where the electrode layer 405b and the oxide semiconductor film 403 are in contact (contact region) and the gate electrode layer 401 is reduced, so that the on-state characteristics of the transistors 440d and 440e can be improved.

4C, the insulating film 407 includes an interlayer insulating film 415, a source electrode layer 405a, a drain electrode layer 405b, sidewall insulating layers (second sidewall insulating layers 412a and 412b, and a third sidewall insulating layer). 414a, 414b) and the insulating film 413.

In the manufacturing process, the transistor 440d includes a gate electrode layer 401, an insulating film 413, and sidewall insulating layers (first sidewall insulating layers 411a and 411b, second sidewall insulating layers 412a and 412b, and a third sidewall insulating layer 414a; 414b) The conductive film provided over 414b) is removed by cutting (grinding or polishing), and the conductive film is divided to form the source electrode layer 405a and the drain electrode layer 405b. As a cutting (grinding or polishing) method, a chemical mechanical polishing (CMP) method can be suitably used.

In the manufacturing process, the transistor 440e includes a gate electrode layer 401, an insulating film 413, and sidewall insulating layers (first sidewall insulating layers 411a and 411b, second sidewall insulating layers 412a and 412b, and a third sidewall insulating layer 414a; 414b) is an example in which a source electrode layer 405a and a drain electrode layer 405b are formed by etching a conductive film provided over 414b while gradually retreating a resist mask using a photolithography process. The transistor 440e is an example in which the insulating film 413 is not provided over the gate electrode layer 401. In the transistor 440e, the gate electrode layer 401 and the insulating film 407 are in contact with each other.

As described above, in a semiconductor device including the transistors 440a to 440e including an oxide semiconductor film, stable electrical characteristics can be given and high reliability can be achieved.

A structure and a manufacturing method for realizing high-speed response and high-speed driving of a semiconductor device including a transistor including an oxide semiconductor film can be provided.

(Embodiment 2)
In this embodiment, an example of a semiconductor device using the transistor described in this specification, capable of holding stored data even when power is not supplied, and having no limit on the number of writing times will be described with reference to drawings. To do.

FIG. 5 illustrates an example of a structure of a semiconductor device. 5A is a cross-sectional view of the semiconductor device, FIG. 5B is a plan view of the semiconductor device, and FIG. 5C is a circuit diagram of the semiconductor device. Here, FIG. 5A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG.

The semiconductor device illustrated in FIGS. 5A and 5B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. . The transistor 162 is an example having a structure similar to that of the transistor 440d described in Embodiment 1.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition to using the transistor as described in Embodiment 1 using an oxide semiconductor to hold information for the transistor 162, a specific structure of the semiconductor device such as a material used for the semiconductor device and a structure of the semiconductor device Need not be limited to those shown here.

A transistor 160 in FIG. 5A includes a channel formation region 116 provided in a substrate 100 containing a semiconductor material (eg, silicon), an impurity region 120 provided so as to sandwich the channel formation region 116, and an impurity region. It has an intermetallic compound region 124 in contact with 120, a gate insulating film 108 provided on the channel formation region 116, and a gate electrode 110 provided on the gate insulating film 108. Note that in the drawing, the source electrode and the drain electrode may not be explicitly provided, but for convenience, the state may be referred to as a transistor. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed. That is, in this specification, the term “source electrode” can include a source region.

An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are provided so as to cover the transistor 160. Note that in the transistor 160, a sidewall insulating layer (sidewall insulating layer) may be provided on a side surface of the gate electrode 110, so that the impurity region 120 includes regions having different impurity concentrations.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. Two insulating films are formed so as to cover the transistor 160. As a process before the formation of the transistor 162 and the capacitor 164, the insulating film 2 is subjected to CMP to form the planarized insulating layer 128 and the insulating layer 130, and the upper surface of the gate electrode 110 is exposed at the same time.

The insulating layer 128 and the insulating layer 130 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like. An inorganic insulating film can be used. The insulating layer 128 and the insulating layer 130 can be formed by a plasma CVD method, a sputtering method, or the like.

Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case of using an organic material, the insulating layer 128 and the insulating layer 130 may be formed by a wet method such as a spin coating method or a printing method.

Note that in this embodiment, a silicon nitride film is used as the insulating film, and a silicon oxide film is used as the insulating layer 130.

Planarization treatment is preferably performed on the oxide semiconductor film 144 formation region over the surface of the insulating layer 130. In this embodiment, the oxide semiconductor film 144 is formed over the insulating layer 130 which is sufficiently planarized by polishing treatment (eg, CMP treatment) (preferably the average surface roughness of the surface of the insulating layer 130 is 0.15 nm or less). .

A transistor 162 illustrated in FIG. 5A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, it is preferable that the oxide semiconductor film 144 included in the transistor 162 be highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

In the manufacturing process, the transistor 162 is formed over the gate electrode 148 and the sidewall insulating layers (first sidewall insulating layers 136a and 136b, second sidewall insulating layers 137a and 137b, and third sidewall insulating layers 138a and 138b). The electrode layers 142a and 142b functioning as a source electrode layer and a drain electrode layer are formed using a step of removing the provided conductive film by a chemical mechanical polishing process. The electrode layers 142a and 142b are in contact with the side surfaces of the third sidewall insulating layers 138a and 138b and the oxide semiconductor film 144.

The first sidewall insulating layers 136a and 136b are preferably formed using an oxide insulating film having an oxygen-excess region.

The first sidewall insulating layers 136a and 136b which are excessively filled with oxygen and contain excess oxygen in a region adjacent to the oxide semiconductor film 144 and the gate insulating film 146 are formed of the gate insulating film 146 and the oxide semiconductor film 144. Oxygen is prevented from desorption from the oxide semiconductor film 144 and functions as an effective oxygen supply layer to the oxide semiconductor film 144 and the gate insulating film 146.

Excess oxygen stored in the first sidewall insulating layers 136a and 136b in a region adjacent to the oxide semiconductor film 144 and the gate insulating film 146 is efficiently supplied to the gate insulating film 146 and the oxide semiconductor film 144. Can do. Therefore, in the semiconductor device, generation of parasitic channels can be suppressed, and oxygen vacancies in the oxide semiconductor film 144 and the interface can be compensated. Further, heat treatment can be performed after the oxygen doping treatment, so that oxygen can be supplied from the oxygen-excess region to the oxide semiconductor film 144 and the gate insulating film 146.

The second sidewall insulating layers 137a and 137b provided in contact with part of the upper surface of the oxide semiconductor film 144, the side surfaces of the gate insulating film 146, and the side surfaces of the first sidewall insulating layers 136a and 136b are the first sidewall insulating layers. A film including an insulating film (typically an aluminum oxide film or an aluminum oxide film) containing a metal element whose oxygen permeability is lower than those of 136a and 136b is used. By using an insulating film containing a metal element with low oxygen permeability as the second sidewall insulating layers 137a and 137b, release of oxygen from the first sidewall insulating layers 136a and 136b can be prevented.

Furthermore, the aluminum oxide film has a high blocking effect (blocking effect) that prevents both hydrogen, moisture and other impurities, and oxygen from passing through the film. Therefore, when the aluminum oxide film is provided as the second sidewall insulating layers 137a and 137b, the oxide semiconductor film 144 of the impurity such as hydrogen or moisture, which becomes a variation factor of electric characteristics during and after the manufacturing process, and the first It is possible to function as a barrier film that prevents entry into the sidewall insulating layers 136a and 136b and emission from the oxide semiconductor film 144 and the first sidewall insulating layers 136a and 136b.

Even if the aluminum oxide film that can be used for the second sidewall insulating layers 137a and 137b is a thin film (typically 10 nm or less, preferably 5 nm or less), the above-described barrier film is highly effective. The second side wall insulating layers 137a and 137b are thin films because they are provided over the first side wall insulating layers 136a and 136b so as to flatten the step portions generated by the gate insulating film 146 and the gate electrode 148. Can also be formed with good coverage. Therefore, since the second sidewall insulating layers 137a and 137b can be thinned, processing becomes easy and productivity is improved.

An oxide insulating film can be used for the third sidewall insulating layers 138a and 138b. The third sidewall insulating layers 138a and 138b function as a mask when the second sidewall insulating layers 137a and 137b are formed, and the sidewall insulating layers of the transistor 162 formed by stacking the three sidewall insulating layers are used as the sidewalls. The film thickness and shape can be adjusted to such an extent that they can function as an insulating layer.

In addition, since the transistor 162 can shorten the distance between the gate electrode 148 and a region (contact region) where the oxide semiconductor film 144 is in contact with the electrode layers 142a and 142b functioning as a source electrode layer or a drain electrode layer, The region where the electrode layers 142a and 142b are in contact with the oxide semiconductor film 144 (contact region) and the resistance between the gate electrode 148 are reduced, so that the on-state characteristics of the transistor 162 can be improved.

In the step of removing the conductive film over the gate electrode 148 in the step of forming the electrode layers 142a and 142b, an etching step using a resist mask is not used, so that precise processing can be performed accurately. Thus, in a manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

Over the transistor 162, an interlayer insulating film 135 and an insulating film 150 are provided as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating film 150. When the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

In addition, a conductive layer 153 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the interlayer insulating film 135 and the insulating film 150 interposed therebetween. The electrode layer 142a, the interlayer insulating film 135, and the insulating film 150 are provided. The conductive element 153 includes the capacitor 164. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 164 and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

An insulating film 152 is provided over the transistor 162 and the capacitor 164. A transistor 162 and a wiring 156 for connecting another transistor are provided over the insulating film 152. Although not illustrated in FIG. 5A, the wiring 156 is electrically connected to the electrode layer 142b through an electrode formed in an opening formed in the insulating film 150, the insulating film 152, the gate insulating film 146, and the like. The Here, the electrode is preferably provided so as to overlap with at least part of the oxide semiconductor film 144 of the transistor 162.

5A and 5B, the transistor 160 and the transistor 162 are provided so that at least part of them overlaps with each other. The source region or the drain region of the transistor 160 and the oxide semiconductor film 144 are provided. It is preferable that a part is provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided so as to overlap with at least part of the gate electrode 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Note that the electrode layer 142b and the wiring 156 may be electrically connected to each other by bringing the electrode layer 142b and the wiring 156 into direct contact with each other, or an electrode is provided on an insulating film between the electrode layer 142b and the wiring 156. You may go through. A plurality of electrodes may be interposed therebetween.

Next, an example of a circuit configuration corresponding to FIGS. 5A and 5B is illustrated in FIG.

In FIG. 5C, the first wiring (1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the transistor 160 are electrically connected. It is connected. In addition, the third wiring (3rd Line) and one of the source electrode and the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected to each other. It is connected to the. The gate electrode of the transistor 160 and one of the source electrode and the drain electrode of the transistor 162 are electrically connected to the other electrode of the capacitor 164, and the fifth wiring (5th Line) and the electrode of the capacitor 164 The other of these is electrically connected.

In the semiconductor device illustrated in FIG. 5C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 160 and the capacitor 164. That is, predetermined charge is given to the gate electrode of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the charge given to the gate electrode of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the first wiring is changed according to the amount of charge held in the gate electrode of the transistor 160. The two wirings have different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high level charge is applied to the gate electrode of the transistor 160 is a low level charge applied to the gate electrode of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned “off” regardless of the state of the gate electrode, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively, a} potential at which the transistor 160 is turned on regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, it is possible to provide a semiconductor device which is miniaturized and highly integrated and has stable and high electrical characteristics, and a method for manufacturing the semiconductor device.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, a semiconductor device which uses the transistor described in Embodiment 1 or 2 and can hold stored data even when power is not supplied and has no limit on the number of writing operations. A structure different from the structure shown in Embodiment Mode 2 will be described with reference to FIGS.

6A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 6B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 6A will be described, and then the semiconductor device illustrated in FIG. 6B will be described below.

In the semiconductor device illustrated in FIG. 6A, the bit line BL and the source electrode or the drain electrode of the transistor 162 are electrically connected, and the word line WL and the gate electrode of the transistor 162 are electrically connected. The source electrode or the drain electrode of the capacitor and the first terminal of the capacitor 254 are electrically connected.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG. 6A is described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

The transistor 162 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB * VB0 + C * V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. It can be seen that (= CB * VB0 + C * V1) / (CB + C)) is higher than the potential of the bit line BL when the potential V0 is held (= CB * VB0 + C * V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 6A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 6B is described.

The semiconductor device illustrated in FIG. 6B includes memory cell arrays 251a and 251b each including a plurality of memory cells 250 illustrated in FIG. 6A as memory circuits in the upper portion, and the memory cell arrays 251 (memory cell arrays 251a and 251b) in the lower portion. 251 b) has a peripheral circuit 253 necessary for operating. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 6B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (memory cell arrays 251a and 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

Note that although the semiconductor device illustrated in FIG. 6B illustrates a structure in which two memory cell arrays 251 (a memory cell array 251a and a memory cell array 251b) are stacked, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of the memory cell 250 illustrated in FIG. 6A will be described with reference to FIGS.

FIG. 7 shows an example of the configuration of the memory cell 250. 7A is a cross-sectional view of the memory cell 250, and FIG. 7B is a plan view of the memory cell 250. Here, FIG. 7A corresponds to a cross section taken along lines F1-F2 and G1-G2 in FIG.

The transistor 162 illustrated in FIGS. 7A and 7B can have a structure similar to that described in Embodiment 1 or 2.

An insulating film 256 is provided as a single layer or a stacked layer over the transistor 162 provided over the insulating layer 130. In addition, a conductive layer 262 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the insulating film 256 interposed therebetween. The electrode layer 142a, the interlayer insulating film 135, the insulating film 256, and the conductive layer 262 are provided. Thus, a capacitor element 254 is formed. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 functions as the other electrode of the capacitor 254.

An insulating film 258 is provided over the transistor 162 and the capacitor 254. A memory cell 250 and a wiring 260 for connecting the adjacent memory cell 250 are provided over the insulating film 258. Although not illustrated, the wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 through an opening formed in the insulating film 256, the insulating film 258, and the like. However, another conductive layer may be provided in the opening, and the wiring 260 and the electrode layer 142b may be electrically connected through the other conductive layer. Note that the wiring 260 corresponds to the bit line BL in the circuit diagram of FIG.

7A and 7B, the electrode layer 142b of the transistor 162 can also function as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

By adopting the planar layout shown in FIG. 7A, the occupation area of the semiconductor device can be reduced, so that high integration can be achieved.

As described above, the plurality of memory cells formed in multiple layers in the upper portion are formed using transistors including an oxide semiconductor. Since a transistor including an oxide semiconductor has a small off-state current, stored data can be held for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

As described above, it is possible to provide a semiconductor device which is miniaturized and highly integrated and has stable and high electrical characteristics, and a method for manufacturing the semiconductor device.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS.

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In a normal SRAM, as shown in FIG. 8A, one memory cell is composed of six transistors 801 to 806, which are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 form an inverter and can be driven at high speed. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is normally 100 to 150 F ² . For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 8B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. The memory cell area of a DRAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 9 shows a block diagram of a portable device. 9 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. A sensor 919, an audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 909. In general, the memory circuit 912 includes an SRAM or a DRAM. By adopting the semiconductor device described in the above embodiment for this portion, information can be written and read at high speed, and long-term storage can be performed. In addition, power consumption can be sufficiently reduced.

FIG. 10 shows an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 10 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit reads a signal line from image data (input image data), a memory 952, and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and is stored in the display 957 via the switch 955 and the display controller 956. The stored image data B is sent and displayed. This reading is continued until new image data is stored in the memory 952 next time.

As described above, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 952 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently reduced. it can.

FIG. 11 is a block diagram of an electronic book. 11 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 has a function of temporarily holding the contents of a book. An example of a function is when a user uses a highlight function. When a user is reading an electronic book, the user may want to mark a specific part. This marking function is called a highlight function, and is to show the difference from the surroundings by changing the display color, underlining, making the character thicker, or changing the font of the character. This is a function for storing and holding information on a location designated by the user. When this information is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the above embodiment, writing and reading of information can be performed at high speed, long-term storage can be performed, and power consumption can be sufficiently reduced. Can do.

As described above, the portable device described in this embodiment includes the semiconductor device according to any of the above embodiments. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Claims (2)

An oxide semiconductor film including a channel formation region provided over the oxide insulating film;
A gate insulating film on the oxide semiconductor film;
A gate electrode layer on the gate insulating film;
A first sidewall insulating layer covering a part of the upper surface of the gate insulating film and a side surface of the gate electrode layer;
A second sidewall insulating layer covering a part of the upper surface of the oxide semiconductor film, a side surface of the gate insulating film, and a side surface of the first sidewall insulating layer;
A third sidewall insulating layer covering a side surface of the second sidewall insulating layer;
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film;
The first sidewall insulating layer and the third sidewall insulating layer are oxide insulating films,
The semiconductor device according to claim 1, wherein the second sidewall insulating layer is an insulating film containing a metal element having a lower oxygen permeability than the first sidewall insulating layer. An oxide semiconductor film including a channel formation region provided over the oxide insulating film;
A gate insulating film on the oxide semiconductor film;
A gate electrode layer on the gate insulating film;
An insulating film on the gate electrode layer;
A first sidewall insulating layer covering a part of the upper surface of the gate insulating film, a side surface of the gate electrode layer, and a side surface of the insulating film;
A second sidewall insulating layer covering a part of the upper surface of the oxide semiconductor film, a side surface of the gate insulating film, and a side surface of the first sidewall insulating layer;
A third sidewall insulating layer covering a side surface of the second sidewall insulating layer;
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film;
The first sidewall insulating layer and the third sidewall insulating layer are oxide insulating films,
The semiconductor device, wherein the second sidewall insulating layer and the insulating film are insulating films containing a metal element having lower oxygen permeability than the first sidewall insulating layer.