JP6088852B2 - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device).

In order to be applied to various electronic devices, high-speed operation of transistors, low power consumption of transistors, high integration, and the like are required and widely developed (see Patent Document 1).

JP 2004-39690 A

Further, miniaturization of a transistor is indispensable in order to achieve high-speed operation of the transistor, low power consumption of the transistor, high integration, and the like.

In order to realize a higher-performance semiconductor device, the on-characteristics of a miniaturized transistor (for example, on-current and field-effect mobility) are improved to realize a high-speed response and high-speed driving of the semiconductor device and its manufacture An object is to provide a method.

In addition, there is a concern that the yield in the manufacturing process may decrease with the miniaturization of the transistor.

An object is to provide a transistor with high electrical characteristics even in a minute structure with high yield.

Another object is to achieve high performance, high reliability, and high production in a semiconductor device including the transistor.

In a semiconductor device including a transistor in which a semiconductor film, a gate insulating film, and a gate electrode layer provided with a sidewall insulating layer on a side surface are sequentially stacked, the source electrode layer and the drain electrode layer are in contact with the semiconductor film and the sidewall insulating layer. Provided. In the manufacturing process of the semiconductor device, a conductive film and an oxide insulating film are stacked so as to cover the semiconductor film, the sidewall insulating layer, and the gate electrode layer, and the oxide insulating film is subjected to a first polishing process using an alkaline slurry. Is cut (ground, polished), and the conductive film is cut (ground, polished) by the second polishing process using acidic slurry, thereby removing a part of the gate electrode layer and the conductive film on the gate electrode layer. Thus, a source electrode layer and a drain electrode layer are formed. As a cutting (grinding or polishing) method, a chemical mechanical polishing (CMP) method is used.

In the step of dividing the conductive film on the gate electrode layer using the CMP method to form the source electrode layer and the drain electrode layer, an alkaline slurry in which the removal treatment proceeds more effectively on the oxide insulating film was used. A first polishing process and a second polishing process using an acidic slurry, in which the removal process proceeds more effectively on the metal film, are performed. In addition to the polishing process by the CMP method, an alkaline slurry and an acidic slurry are used for an oxide insulating film used for an interlayer insulating film and a sidewall insulating layer, and a metal film used for a gate electrode layer, a source electrode layer, and a drain electrode layer. Use different selection ratios. In the manufacturing process, in addition to the polishing process by the CMP method, more precise processing can be performed with good control by using the slurry having a different selection ratio to the processed object.

For the stack of the conductive film and the oxide insulating film provided over the gate electrode layer, first, the oxide insulating film is selectively removed by a first polishing process and provided over the gate electrode layer. The formed conductive layer is exposed. Since the second polishing process to be performed next is performed using an acidic slurry that effectively removes the metal film, the sidewall insulating layer is difficult to be removed, and part of the gate electrode layer is selectively removed. The conductive film can be removed.

Therefore, the height of the gate electrode layer, the source electrode layer, and the drain electrode layer (the height from the substrate) can be lower than the height of the upper surface of the sidewall insulating layer. With this structure, the gate electrode layer, the source electrode layer, and the drain electrode layer can be more reliably insulated from each other using the sidewall insulating layer, so that the gate electrode layer, the source electrode layer, and the drain electrode layer are in contact with each other. It is possible to reduce defects such as short circuits.

Thus, in a manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

A dopant (impurity element) is introduced into the semiconductor film in a self-aligned manner using the gate electrode layer as a mask, and the resistance of the semiconductor film is lower than that of the channel formation region with the channel formation region interposed therebetween. Form. The dopant is an impurity that changes the conductivity of the semiconductor film. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

By having a semiconductor film including a low-resistance region with a channel formation region sandwiched in the channel length direction, the transistor has high on-characteristics (eg, on-state current and field-effect mobility), and can operate at high speed and respond quickly. .

In one embodiment of the structure disclosed in this specification, a semiconductor film, a gate insulating film, and a gate electrode layer are sequentially stacked, and a sidewall insulating layer that covers a side surface of the gate electrode layer is formed. A conductive film is formed over the insulating film, the gate electrode layer, and the sidewall insulating layer, an oxide insulating film is formed over the conductive film, and an oxide over the gate electrode layer is formed by a first polishing process using an alkaline slurry. The insulating film is removed until the conductive film is exposed, and part of the gate electrode layer and the conductive film on the gate electrode layer are removed by a second polishing process using an acidic slurry, so that the conductive film is divided and the source is separated. This is a method for manufacturing a semiconductor device in which an electrode layer and a drain electrode layer are formed.

In one embodiment of the structure of the invention disclosed in this specification, an oxide semiconductor film, a gate insulating film, and a gate electrode layer are sequentially stacked, and a sidewall insulating layer that covers a side surface of the gate electrode layer is formed. A conductive film is formed over the gate insulating film, the gate electrode layer, and the sidewall insulating layer, an oxide insulating film is formed over the conductive film, and the first polishing treatment using an alkaline slurry is performed on the gate electrode layer. The oxide insulating film is removed until the conductive film is exposed, and part of the gate electrode layer and the conductive film on the gate electrode layer are removed by a second polishing process using an acidic slurry, so that the conductive film is divided. A method for manufacturing a semiconductor device in which a source electrode layer and a drain electrode layer are formed.

In the above structure, one embodiment of the structure of the invention disclosed in this specification is a semiconductor device in which a dopant is selectively introduced into an oxide semiconductor film using a gate electrode layer as a mask to form a low-resistance region in the oxide semiconductor film This is a manufacturing method.

One embodiment of a structure of the invention disclosed in this specification includes a semiconductor film including a channel formation region, a gate insulating film over the semiconductor film, a gate electrode layer over the gate insulating film, and a sidewall that covers a side surface of the gate electrode layer Insulating layer, semiconductor film, source electrode layer and drain electrode layer in contact with side surface of gate insulating film and side surface of sidewall insulating layer, oxide insulating film on source electrode layer and drain electrode layer, gate electrode layer, source electrode The gate electrode layer, the source electrode layer, and the drain electrode layer have a height higher than that of the sidewall insulating layer and the oxide insulating film. It is a low semiconductor device.

One embodiment of the structure of the invention disclosed in this specification includes an oxide semiconductor film including a channel formation region, a gate insulating film over the oxide semiconductor film, a gate electrode layer over the gate insulating film, and a gate electrode layer A sidewall insulating layer covering the side surface, an oxide semiconductor film, a source electrode layer and a drain electrode layer in contact with the side surface of the gate insulating film and the side surface of the sidewall insulating layer, and an oxide insulating film on the source electrode layer and the drain electrode layer; The gate electrode layer, the source electrode layer, and the drain electrode layer are in contact with each other and an interlayer insulating film is provided over the oxide insulating film, and the height of the upper surface of the gate electrode layer, the source electrode layer, and the drain electrode layer is a sidewall insulating layer And a semiconductor device lower than an oxide insulating film.

In the above structure, one embodiment of the structure of the invention disclosed in this specification is a semiconductor device in which an aluminum oxide film is used for a sidewall insulating layer and an oxide insulating film.

In the above structure, one embodiment of the structure of the invention disclosed in this specification is a semiconductor device in which the top surfaces of the source electrode layer and the drain electrode layer are lower than the top surface of the gate electrode layer.

One embodiment of the present invention relates to a semiconductor device including a transistor or a circuit including the transistor. For example, the invention relates to a semiconductor device including a transistor or a circuit including a transistor in which a channel formation region is formed using an oxide semiconductor. For example, power devices mounted on LSIs, CPUs, power supply circuits, semiconductor integrated circuits including memories, thyristors, converters, image sensors, etc., light-emitting displays having electro-optical devices and light-emitting elements typified by liquid crystal display panels The present invention relates to an electronic device equipped with a device as a component.

A transistor having high electrical characteristics even with a fine structure can be provided with high yield.

In a semiconductor device including the transistor, high performance, high reliability, and high production can be achieved.

4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. 4A and 4B are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 8A and 8B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. The figure which shows the structure of an Example transistor. The figure which shows the cross-sectional STEM image of an Example transistor. The figure which shows the electrical property of an Example transistor and a comparative example transistor. The figure which shows the electrical property of an Example transistor and a comparative example transistor. The figure which shows the electrical property of an Example transistor and a comparative example transistor.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. In addition, the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor film is described as an example of a semiconductor device.

The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type having two gate electrode layers disposed above and below the channel region with a gate insulating film interposed therebetween may be used.

A transistor 440a illustrated in FIGS. 1A and 1B is an example of a top-gate transistor. 1A is a plan view, and a cross section cut along a single-dot chain line X-Y in FIG. 1A corresponds to FIG.

As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, a semiconductor device including a transistor 440a includes a channel formation region 409, a low resistance region over a substrate 400 having an insulating surface provided with an insulating film 436. Semiconductor film 403 including 404a and 404b, source electrode layer 405a, drain electrode layer 405b, gate insulating film 402, gate electrode layer 401, sidewall insulating layers 412a and 412b provided on side surfaces of gate electrode layer 401, and source electrode layer 405a And the oxide insulating film 415 provided over the drain electrode layer 405b.

In the transistor 440a, the conductive film over the gate electrode layer 401 is divided using a CMP method, and the oxide insulating film is more effectively removed in the step of forming the source electrode layer 405a and the drain electrode layer 405b. A first polishing process using the proceeding alkaline slurry and a second polishing process using the acidic slurry in which the removal process effectively proceeds on the metal film are performed. In addition to polishing by a CMP method, an oxide insulating film used for the oxide insulating film 415 and the sidewall insulating layers 412a and 412b, and a metal film used for the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b In contrast, the different selectivity ratios of the alkaline slurry and the acidic slurry are utilized. In the manufacturing process, in addition to the polishing process by the CMP method, more precise processing can be performed with good control by using the slurry having a different selection ratio to the processed object.

For the stack of the conductive film and the oxide insulating film provided over the gate electrode layer 401, first, the oxide insulating film is selectively removed by a first polishing process, and the gate electrode layer 401 is formed. The conductive layer provided on is exposed. Since the second polishing process to be performed next is performed using an acidic slurry that effectively removes the metal film, the sidewall insulating layers 412a and 412b are difficult to remove, and the gate electrode layer 401 is selectively removed. Part and the conductive film can be removed.

The oxide insulating film 415 is provided so as to planarize unevenness due to the transistor 440a, and the height of the top surface is substantially the same as that of the sidewall insulating layers 412a and 412b. The heights of the top surfaces of the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b are lower than the heights of the top surfaces of the oxide insulating film 415 and the sidewall insulating layers 412a and 412b. In this embodiment, the height of the top surfaces of the source electrode layer 405a and the drain electrode layer 405b is lower than that of the gate electrode layer 401. Note that the height here is the height from the upper surface of the substrate 400.

With this structure, the gate electrode layer 401 and the source electrode layer 405a and the drain electrode layer 405b can be more reliably insulated from each other by using the sidewall insulating layers 412a and 412b. In addition, defects such as a short circuit due to contact with the drain electrode layer 405b can be reduced.

Note that a dopant is introduced into the semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask, and the resistance of the semiconductor film 403 is lower than that of the channel formation region 409 with the channel formation region 409 interposed therebetween. 404b is formed. The dopant is an impurity that changes the conductivity of the semiconductor film 403. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

By including the semiconductor film 403 including the low-resistance regions 404a and 404b with the channel formation region 409 sandwiched in the channel length direction, the transistor 440a has high on-characteristics (eg, on-current and field-effect mobility), high-speed operation, High-speed response is possible.

For the semiconductor film 403, an oxide semiconductor, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used. In addition, an organic semiconductor material or the like may be used.

2A to 2C and FIGS. 3A to 3D illustrate an example of a method for manufacturing a semiconductor device including the transistor 440a.

First, the insulating film 436 is formed over the substrate 400 having an insulating surface.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance enough to withstand heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a flexible semiconductor device, the transistor 440a including the semiconductor film 403 may be directly formed over a flexible substrate, or the transistor 440a including the semiconductor film 403 may be manufactured over another manufacturing substrate. Then, it may be peeled off and transferred to the flexible substrate. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor 440a including the oxide semiconductor film.

The insulating film 436 can be formed using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material thereof by a plasma CVD method, a sputtering method, or the like.

The insulating film 436 may be a single layer or a stacked layer.

In this embodiment, a silicon oxide film formed by a sputtering method is used as the insulating film 436.

Further, a nitride insulating film may be provided between the insulating film 436 and the substrate 400. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or a mixed material thereof by a plasma CVD method, a sputtering method, or the like.

Next, a semiconductor film 403 is formed over the insulating film 436, and an insulating film 442 covering the semiconductor film 403 is formed.

Note that the above planarization treatment may be performed on the surface of the semiconductor film 403 in order to improve the coverage with the insulating film 442. In particular, when a thin insulating film is used as the insulating film 442, the surface of the semiconductor film 403 is preferably flat.

The thickness of the insulating film 442 is, for example, 1 nm to 20 nm, and a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. Alternatively, the insulating film 442 may be formed using a sputtering apparatus which performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target.

As a material of the insulating film 442, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. The insulating film 442 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage of the insulating film.

Further, as the material of the insulating film 442, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0, y) > 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), and high-k materials such as lanthanum oxide can be used to reduce gate leakage current. Further, the insulating film 442 may have a single-layer structure or a stacked structure.

Next, a conductive film is formed over the insulating film 442, and the conductive film is etched to form the gate electrode layer 449 (see FIG. 2A).

The gate electrode layer 449 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode layer 449. The gate electrode layer 449 may have a single-layer structure or a stacked structure.

The material of the gate electrode layer 449 is indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, oxide A conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Next, a dopant is introduced into the semiconductor film 403 using the gate electrode layer 449 as a mask to form low-resistance regions 404a and 404b.

The dopant is an impurity that changes the conductivity of the semiconductor film 403. As the dopant, group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium One or more selected from (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used.

The dopant can be introduced into the semiconductor film 403 through another film (for example, an insulating film for forming the gate insulating film 402 and the sidewall insulating layers 411a and 411b) by an implantation method. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of a dopant, or a fluoride or chloride ion.

The dopant introduction step may be controlled by appropriately setting the implantation conditions such as the acceleration voltage and the dose, and the thickness of the film to be passed. In this embodiment, phosphorus ions are implanted by an ion implantation method using phosphorus as a dopant. Note that the dose amount of the dopant may be 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

The concentration of the dopant in the low resistance region is preferably 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²² / cm ³ or less.

When introducing the dopant, the substrate 400 may be heated.

Note that the treatment for introducing a dopant into the semiconductor film 403 may be performed a plurality of times, and a plurality of types of dopant may be used.

Further, a heat treatment may be performed after the dopant introduction treatment. As heating conditions, it is preferable that the temperature is 300 ° C. or higher and 700 ° C. or lower, preferably 300 ° C. or higher and 450 ° C. or lower for 1 hour in an oxygen atmosphere. Further, the heat treatment may be performed under a nitrogen atmosphere, reduced pressure, or air (ultra-dry air).

Therefore, the semiconductor film 403 provided with the low resistance regions 404a and 404b with the channel formation region 409 interposed therebetween is formed.

Next, an insulating film is formed over the gate electrode layer 449, and the insulating film is etched to form sidewall insulating layers 411a and 411b. Further, with the gate electrode layer 449 and the sidewall insulating layers 411a and 411b as masks, the insulating film is etched to form the gate insulating film 402 (see FIG. 2B).

As the sidewall insulating layers 411a and 411b, a single layer or a stacked layer of an oxide insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film can be used. The sidewall insulating layers 411a and 411b can be formed by a plasma CVD method, a sputtering method, or the like. In this embodiment, a silicon oxynitride film formed by a CVD method is used.

Next, a conductive film to be a source electrode layer and a drain electrode layer (including a wiring formed using the same layer) is formed over the semiconductor film 403, the gate insulating film 402, the gate electrode layer 449, and the sidewall insulating layers 411a and 411b. Form.

The conductive film is formed using a material that can withstand heat treatment performed later. As the conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or metal nitriding containing the above-described element as a component A material film (titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. The conductive film used for the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ ), and indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

A resist mask is formed over the conductive film by a photolithography process and is selectively etched to form an island-shaped conductive film 445, and then the resist mask is removed. Note that in the etching step, the conductive film 445 over the gate electrode layer 449 is not removed.

When a 30-nm-thick tungsten film is used as the conductive film, the conductive film is etched by, for example, dry etching ((etching condition: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm : 55 sccm, power source power 3000 W, bias power 140 W, pressure 0.67 Pa) to form an island-shaped tungsten film.

An oxide insulating film 446 which serves as an interlayer insulating film is stacked over the island-shaped conductive film 445 (see FIG. 2C).

The oxide insulating film 446 can be formed using a material and a method similar to those of the sidewall insulating layers 411a and 411b. Since the oxide insulating film 446 functions as an interlayer insulating film, the oxide insulating film 446 is formed to have a thickness with which the unevenness generated by the transistor 440a can be planarized.

Next, first polishing treatment is performed on the oxide insulating film 446 and the conductive film 445 by a chemical mechanical polishing method using an alkaline slurry, and part of the oxide insulating film 446 is removed so that the conductive film 445 is exposed. The oxide insulating film 446 is selectively removed by the first polishing process using an alkaline slurry in which the removal process proceeds more selectively with respect to the oxide insulating film 446, and the oxide insulating film 446 is provided over the gate electrode layer 449. The conductive film 445 can be exposed.

In the CMP process used for the polishing process, if the uneven shape or material of the processed object is different, the progress of the polishing process easily varies depending on the region. When variations occur in the processing region, an excessively processed region or an insufficiently processed region occurs in the surface, leading to poor characteristics or variations in the semiconductor device. As in this embodiment, since the treatment for removing the oxide insulating film 446 and the conductive film 445 is not performed at the time of the first polishing treatment, the treatment region can be controlled more accurately and in-plane variation can be suppressed. be able to.

Through the first polishing treatment, the oxide insulating film 446 is processed into the oxide insulating film 447 (see FIG. 3A).

Next, a second polishing process is performed on the conductive film 445 by a chemical mechanical polishing method using an acidic slurry, and a part of the gate electrode layer 449 and the conductive film 445 over the gate electrode layer 449 are removed. 401, a source electrode layer 405a and a drain electrode layer 405b are formed. Since the second polishing process is performed using an acidic slurry in which the removal process proceeds more selectively with respect to the metal film, the oxide insulating film 447 and the sidewall insulating layers 411a and 411b are not easily removed, and more selectively. A part of the gate electrode layer 401 and the conductive film 445 can be removed.

Note that by the second polishing treatment, the oxide insulating film 447 and the sidewall insulating layers 411a and 411b are also removed, whereby the oxide insulating film 415 and the sidewall insulating layers 412a and 412b can be obtained. That is, it is possible to selectively remove the convex portions by polishing treatment, and further selectively remove the film that is easily removed from the slurry while polishing the entire surface.

Note that in this embodiment, the source electrode layer 405a and the drain electrode layer 405b are provided so as to be in contact with the side surfaces of the sidewall insulating layers 412a and 412b provided on the side surfaces of the gate electrode layer 401. The side surface of 412b is covered to a position slightly lower than the upper end portion.

Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 3B).

In the transistor 440a, the height of the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b (the height from the substrate 400) can be lower than the height of the top surfaces of the sidewall insulating layers 412a and 412b. With this structure, the gate electrode layer 401 and the source electrode layer 405a and the drain electrode layer 405b can be more reliably insulated from each other by using the sidewall insulating layers 412a and 412b. In addition, defects such as a short circuit due to contact with the drain electrode layer 405b can be reduced.

Therefore, in the manufacturing process of the semiconductor device, the transistor 440a having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

The source electrode layer 405a and the drain electrode layer 405b are provided in contact with the exposed upper surface of the semiconductor film 403 and the sidewall insulating layer 412a or the sidewall insulating layer 412b. Therefore, the distance between the gate electrode layer 401 and the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the semiconductor film 403 is the width in the channel length direction of the sidewall insulating layers 412a and 412b, which is finer. In addition to achieving this, control can be performed with more variation in the manufacturing process.

In this manner, the distance between the gate electrode layer 401 and the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the semiconductor film 403 can be shortened, so the source electrode layer 405a or the drain electrode layer The resistance between the region where 405b and the semiconductor film 403 are in contact (contact region) and the gate electrode layer 401 is reduced, so that the on-state characteristics of the transistor 440a can be improved.

The structure in which the gate electrode layer 401 is exposed as in the transistor 440a can be used in an integrated circuit in which another wiring or a semiconductor element is stacked over the transistor 440a.

An interlayer insulating film may be provided over the transistor 440a. 4A, an insulating film 407 and an insulating film 416 functioning as an interlayer insulating film are stacked over the transistor 440a, and openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 407 and the insulating film 416. An example is shown in which the wiring layers 435a and 435b are formed in the openings. Various circuits can be formed by connecting the wiring layers 435a and 435b to other transistors and elements.

As the interlayer insulating film, a highly dense inorganic insulating film (for example, an aluminum oxide film) serving as a protective insulating film or a planarization film that can planarize unevenness can be provided. For example, an aluminum oxide film can be used as the insulating film 407 and a silicon oxynitride film can be used as the insulating film 416.

The wiring layer 435a and the wiring layer 435b can be formed using a material and a method similar to those of the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b, for example, Al, Cr, Cu, Ta, Ti, A metal film containing an element selected from Mo and W, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing the above-described element as a component can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. Further, the conductive film used for the wiring layer 435a and the wiring layer 435b may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ ), and indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

For example, as the wiring layers 435a and 435b, a single layer of a molybdenum film, a stack of a tantalum nitride film and a copper film, a stack of a tantalum nitride film and a tungsten film, or the like can be used.

Further, a highly dense inorganic insulating film (typically an aluminum oxide film) which serves as a protective insulating film may be provided between the source electrode layer 405a and the drain electrode layer 405b and the oxide insulating film 415.

FIG. 4B illustrates an example of the transistor 440 b in which the insulating film 410 is provided between the source and drain electrode layers 405 a and 405 b and the oxide insulating film 415.

Further, the sidewall insulating layers 412a and 412b may have a stacked structure. FIG. 4C illustrates an example of the transistor 440c including the sidewall insulating layers 412a1 and 412a2 and the sidewall insulating layers 412b1 and 412b2 having a stacked structure. For example, a highly dense oxide insulating film (eg, an aluminum oxide film) is provided as the sidewall insulating layers 412a1 and 412b1, and an oxide insulating film (eg, a silicon oxynitride film) with good coverage is provided as the sidewall insulating layers 412a2 and 412b2. Can be used.

The insulating films 407 and 410 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like.

In addition to the aluminum oxide film, as the insulating films 407 and 410, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be used. Alternatively, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (eg, an aluminum nitride film) can be used.

In the semiconductor device, a planarization insulating film may be formed in order to reduce surface unevenness. As the planarization insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed using these materials.

As described above, in the semiconductor device, the transistors 440a, 440b, and 440c with high on-state characteristics that have a fine structure with little variation in shape and characteristics can be provided with high yield.

Therefore, it is possible to provide a semiconductor device that is miniaturized and has high electrical characteristics, and a method for manufacturing the semiconductor device.

(Embodiment 2)
An oxide semiconductor can be used as a semiconductor film used for a transistor included in the semiconductor device disclosed in this specification. In this embodiment, an example in which an oxide semiconductor film is used as the semiconductor film 403 included in the transistors 440a, 440b, and 440c described in Embodiment 1 is described.

An oxide semiconductor used for the semiconductor film preferably contains at least indium (In). In particular, it is preferable to contain In and zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides In—Zn oxide, In—Mg oxide, In—Ga oxide, ternary metal In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La -Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm- Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, four In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, and In-Sn-Al-Zn-based oxides that are oxides of the base metal In-Sn-Hf-Zn-based oxides and In-Hf-Al-Zn-based oxides can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

However, the oxide semiconductor containing indium is not limited thereto, and an oxide semiconductor having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, and the like). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: The composition of the oxide of C (A + B + C = 1) is in the vicinity, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ r ² Satisfying. For example, r may be 0.05. The same applies to other oxides.

The semiconductor film 403 may include a non-single crystal, for example. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous part. The amorphous part has a higher density of defect states than microcrystals and CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

For example, the oxide semiconductor film may include a CAAC-OS. For example, the CAAC-OS is c-axis oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

The oxide semiconductor film may include microcrystal, for example. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.

For example, the oxide semiconductor film may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous and has no crystal part.

Note that the oxide semiconductor film may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

Note that the oxide semiconductor film may include a single crystal, for example.

The oxide semiconductor film preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

In most cases, a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the crystal part and the crystal part included in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. When viewed from the direction, the metal atoms are arranged in a triangular shape or a hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. Further, when an impurity is added to the CAAC-OS film, the crystallinity of a crystal part in the impurity-added region may be decreased.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, the directions may be different from each other. The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Ra is an arithmetic mean roughness defined in JIS B 0601: 2001 (ISO4287: 1997) extended to three dimensions so that it can be applied to curved surfaces. It can be expressed as “average value of absolute values” and is defined by the following equation.

Here, the designated surface is a surface that is a target of roughness measurement, and has coordinates (x ₁ , y ₁ , f (x ₁ , y ₁ )), (x ₁ , y ₂ , f (x ₁ , y). ₂ )), (x ₂ , y ₁ , f (x ₂ , y ₁ )), (x ₂ , y ₂ , f (x ₂ , y ₂ )) A rectangular area obtained by projecting the surface onto the xy plane is represented by S ₀ , and the height of the reference surface (average height of the designated surface) is represented by Z ₀ . Ra can be measured with an atomic force microscope (AFM).

The thickness of the semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm), and a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method, or the like is used. It can be used as appropriate. Alternatively, the semiconductor film 403 may be formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

For example, the CAAC-OS film is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target is cleaved from the ab plane, and may be separated as flat or pellet-like sputtering particles having a plane parallel to the ab plane. is there. In this case, the flat-plate-like sputtered particle reaches the substrate while maintaining a crystalline state, whereby a CAAC-OS film can be formed.

In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) existing in the deposition chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature at the time of film formation, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-Ga-Zn- which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder in a predetermined number of moles, and after heat treatment at a temperature of 1000 ° C. to 1500 ° C. An O compound target is used. X, Y and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3 or 3: 1: 2. Note that the type of powder and the mol number ratio to be mixed may be changed as appropriate depending on the sputtering target to be manufactured.

The semiconductor film 403 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the semiconductor film 403 is a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and metal oxides having different compositions are formed on the first oxide semiconductor layer and the second oxide semiconductor layer. It may be used. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, both the first oxide semiconductor layer and the second oxide semiconductor layer may be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be the same, and the compositions of the elements may be different. For example, the atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 2: 1: 3. It is good.

At this time, the In and Ga contents in the oxide semiconductor layer on the side close to the gate electrode (channel side) of the first oxide semiconductor layer and the second oxide semiconductor layer may be In> Ga. The content ratio of In and Ga in the oxide semiconductor layer far from the gate electrode (back channel side) is preferably In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor layer and the second oxide semiconductor layer. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, internal stress of the semiconductor film 403 and external stress are reduced, so that the transistor The variation in characteristics can be reduced, and the reliability of the transistor can be further improved.

On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, an oxide semiconductor having crystallinity such as CAAC-OS is preferably used for the oxide semiconductor layer on the channel side.

Alternatively, the semiconductor film 403 may have a stacked structure of three or more layers, and a structure in which an amorphous oxide semiconductor layer is sandwiched between a plurality of crystalline oxide semiconductor layers. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the semiconductor film 403 has a stacked structure of a plurality of layers can be used in appropriate combination.

As the insulating film 436, a silicon oxide film, an In—Hf—Zn-based oxide film, and a semiconductor film 403 may be sequentially stacked over the substrate 400, or a silicon oxide film, In: Zr: Zn = An In—Zr—Zn-based oxide film having a 1: 1: 1 atomic ratio and a semiconductor film 403 may be stacked in this order, or a silicon oxide film, In: Gd: Zn = 1: 1: may be formed over the substrate 400. An In—Gd—Zn-based oxide film having an atomic ratio of 1 and the semiconductor film 403 may be stacked in this order.

Since the insulating film 436 is in contact with the semiconductor film 403, it is preferable that an amount of oxygen exceeding the stoichiometric ratio exists in the film (in the bulk). For example, when a silicon oxide film is used as the insulating film 436, SiO _{2 + α} (α> 0) is set. By using such an insulating film 436, oxygen can be supplied to the semiconductor film 403, and the characteristics can be improved. By supplying oxygen to the semiconductor film 403, oxygen vacancies in the film can be compensated.

For example, when the insulating film 436 containing a large amount (excessive) of oxygen serving as an oxygen supply source is provided in contact with the semiconductor film 403, oxygen can be supplied from the insulating film 436 to the semiconductor film 403. Oxygen may be supplied to the semiconductor film 403 by performing heat treatment with at least part of the semiconductor film 403 and the insulating film 436 being in contact with each other.

In the formation process of the semiconductor film 403, in order to prevent the semiconductor film 403 from containing hydrogen or water as much as possible, an insulating film 436 is formed in the preheating chamber of the sputtering apparatus as a pretreatment for the formation of the semiconductor film 403. It is preferable to preheat the substrate so that impurities such as hydrogen and moisture adsorbed on the substrate and the insulating film 436 are desorbed and exhausted. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber.

Planarization treatment may be performed on a region where the semiconductor film 403 is in contact with the insulating film 436. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the insulating film 436 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. Further, in the case of performing the combination, the order of steps is not particularly limited, and may be set as appropriate in accordance with the uneven state of the surface of the insulating film 436.

For example, the surface of the silicon oxide film used as the insulating film 436 is polished by a chemical mechanical polishing method (polishing conditions: polyurethane-based polishing cloth, silica-based slurry, slurry temperature at room temperature, polishing pressure 0.001 MPa, polishing time) The number of rotations (table / spindle) 60 rpm / 56 rpm, polishing time 0.5 minutes) is performed, and the average surface roughness (Ra) on the silicon oxide film surface may be about 0.15 nm.

Note that the semiconductor film 403 is formed under conditions such that a large amount of oxygen is contained during film formation (for example, film formation is performed by a sputtering method in an atmosphere containing 100% oxygen), and a large amount of oxygen is preferable (preferably The oxide semiconductor is preferably a film in which a region where the oxygen content is excessive with respect to the stoichiometric composition in the crystalline state is included.

Note that in this embodiment, as a target for forming the semiconductor film 403 by a sputtering method, an oxide target of In: Ga: Zn = 3: 1: 2 [atomic percentage] is used as a composition. A -Ga-Zn-based oxide film (IGZO film) is formed.

The relative density (filling rate) of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target having a high relative density, the formed oxide semiconductor film can be a dense film.

As the sputtering gas used for forming the semiconductor film 403, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

The substrate is held in a film formation chamber held in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the deposition chamber is removed, and the semiconductor film 403 is formed over the substrate 400 using the target. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the semiconductor film 403 formed in the chamber can be reduced.

The insulating film 436 and the semiconductor film 403 are preferably formed continuously without being released to the atmosphere. When the insulating film 436 and the semiconductor film 403 are formed successively without being exposed to the atmosphere, impurities such as hydrogen and moisture can be prevented from being adsorbed on the surface of the insulating film 436.

The semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography process.

Further, a resist mask for forming the island-shaped semiconductor film 403 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

Note that the etching of the oxide semiconductor film may be dry etching or wet etching, or both of them may be used. For example, as an etchant used for wet etching of the oxide semiconductor film, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Alternatively, etching may be performed by dry etching using an ICP (Inductively Coupled Plasma) etching method. For example, an IGZO film is etched by ICP etching (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), power supply power 450 W, bias power 100 W, pressure 1.9 Pa) and processed into an island shape. Can do.

Further, the semiconductor film 403 may be subjected to heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group). The temperature of the heat treatment is 300 ° C. or higher and 700 ° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere. For example, a substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and the semiconductor film 403 is subjected to heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then the substrate is taken out of the inert gas.

Note that in the heat treatment, it is preferable that water, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

In addition, after heating the semiconductor film 403 by heat treatment, a high-purity oxygen gas, a high-purity dinitrogen monoxide gas, or an ultra-dry air (CRDS (cavity ring-down laser spectroscopy) type dew point meter) is installed in the same furnace. The water content when measured by using may be 20 ppm (air at dew point conversion of −55 ° C.) or less, preferably 1 ppm or less, more preferably 10 ppb or less. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or the dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or nitrous oxide introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide is 1 ppm or less, preferably 0.1 ppm or less. ) Is preferable. By supplying oxygen, which is a main component material of the oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas, the semiconductor The film 403 can be highly purified and can be electrically i-type (intrinsic).

Note that the timing for performing the heat treatment for dehydration or dehydrogenation may be after the formation of the film-shaped oxide semiconductor film or after the formation of the island-shaped semiconductor film 403.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatments.

Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. .

In addition, oxygen that is a main component material of the oxide semiconductor may be desorbed and reduced at the same time by the dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen vacancies exist at locations where oxygen is released, and donor levels that cause fluctuations in electrical characteristics of the transistor are generated due to the oxygen vacancies.

By introducing oxygen into the semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment and supplying oxygen into the film, the semiconductor film 403 is highly purified and electrically converted into an I-type (intrinsic). Can do. A transistor including the highly purified semiconductor film 403 which is electrically i-type (intrinsic) is electrically stable because variation in electrical characteristics is suppressed.

As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

When introducing oxygen into the semiconductor film 403, the oxygen introduction step may be directly introduced into the semiconductor film 403 or may be introduced into the semiconductor film 403 through another film such as the gate insulating film 402 or the insulating film 407. May be. In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used. However, when oxygen is directly introduced into the exposed semiconductor film 403, Plasma treatment or the like can also be used.

The introduction of oxygen into the semiconductor film 403 is preferably performed after dehydration or dehydrogenation treatment, but is not particularly limited. In addition, oxygen may be introduced into the semiconductor film 403 subjected to the dehydration or dehydrogenation treatment a plurality of times.

As a material of the gate insulating film 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used.

In the case where an oxide semiconductor film is used as the semiconductor film 403, the gate insulating film 402 preferably contains oxygen in a portion in contact with the semiconductor film 403. In particular, the gate insulating film 402 preferably includes oxygen in the film (in the bulk) in an amount exceeding at least the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating film 402, SiO 2 _{2 + α} (where α> 0). In this embodiment, a silicon oxide film with SiO _{2 + α} (α> 0) is used as the gate insulating film 402. By using this silicon oxide film as the gate insulating film 402, oxygen can be supplied to the semiconductor film 403, and the characteristics can be improved. Further, the gate insulating film 402 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage with the gate insulating film 402.

Further, as one layer of the gate electrode layer 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen or an In—Sn—O film containing nitrogen is used. In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, In-O films containing nitrogen, metal nitride films (InN, SnN, etc.) ) Can be used. These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

In the case where an oxide semiconductor film is used as the semiconductor film 403, the insulating films 407 and 410 provided over the semiconductor film 403 are preferably films including an aluminum oxide film. The aluminum oxide film has a high blocking effect (blocking effect) that prevents both hydrogen, moisture and other impurities, and oxygen from passing through the film.

Therefore, the aluminum oxide film is a main component of an oxide semiconductor, and the entry of impurities such as hydrogen and moisture into the semiconductor film 403, which cause variation in a transistor including the oxide semiconductor film, during and after the manufacturing process. It functions as a protective film for preventing release of oxygen as a component material from the semiconductor film 403.

The insulating films 407 and 410 are preferably formed by appropriately using a method (preferably a sputtering method) in which impurities such as water and hydrogen are not mixed into the insulating films 407 and 410.

As in the formation of the oxide semiconductor film, an adsorption-type vacuum pump (such as a cryopump) is preferably used to remove residual moisture in the deposition chambers of the insulating films 407 and 410. The concentration of impurities contained in the insulating films 407 and 410 formed in the film formation chamber evacuated using a cryopump can be reduced. In addition, as an exhaust unit for removing moisture remaining in the deposition chambers of the insulating films 407 and 410, a turbo molecular pump provided with a cold trap may be used.

As a sputtering gas used for forming the insulating films 407 and 410, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

As described above, an oxide semiconductor film can be preferably used as the semiconductor film of the transistors 440a, 440b, and 440c disclosed in this specification.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a semiconductor device using the transistor described in this specification, capable of holding stored data even when power is not supplied, and having no limit on the number of writing times will be described with reference to drawings. To do.

FIG. 5 illustrates an example of a structure of a semiconductor device. 5A is a cross-sectional view of the semiconductor device, FIG. 5B is a plan view of the semiconductor device, and FIG. 5C is a circuit diagram of the semiconductor device. Here, FIG. 5A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG.

The semiconductor device illustrated in FIGS. 5A and 5B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. . As an example of the transistor 162, a transistor in which the structure of the transistor 440a described in Embodiment 1 is used and the oxide semiconductor film described in Embodiment 2 is used for the semiconductor film 144 is described.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition to the transistor 162 that uses an oxide semiconductor to hold information as described in Embodiment 1, a specific structure of a semiconductor device such as a material used for the semiconductor device and a structure of the semiconductor device is described here. It is not necessary to limit to what is shown by.

A transistor 160 in FIG. 5A includes a channel formation region 116 provided in a substrate 185 containing a semiconductor material (eg, silicon), an impurity region 120 provided so as to sandwich the channel formation region 116, and an impurity region. It has an intermetallic compound region 124 in contact with 120, a gate insulating film 108 provided on the channel formation region 116, and a gate electrode 110 provided on the gate insulating film 108. Note that in the drawing, the source electrode and the drain electrode may not be explicitly provided, but for convenience, the state may be referred to as a transistor. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed. That is, in this specification, the term “source electrode” can include a source region.

An element isolation insulating layer 106 is provided over the substrate 185 so as to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are provided so as to cover the transistor 160. Note that in the transistor 160, a sidewall insulating layer (sidewall insulating layer) may be provided on a side surface of the gate electrode 110, so that the impurity region 120 includes regions having different impurity concentrations.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. Two insulating films are formed so as to cover the transistor 160. As a process before the formation of the transistor 162 and the capacitor 164, the insulating film 2 is subjected to CMP to form the planarized insulating layer 128 and the insulating layer 130, and the upper surface of the gate electrode 110 is exposed at the same time.

The insulating layer 128 and the insulating layer 130 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like. An inorganic insulating film can be used. The insulating layer 128 and the insulating layer 130 can be formed by a plasma CVD method, a sputtering method, or the like.

Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case of using an organic material, the insulating layer 128 and the insulating layer 130 may be formed by a wet method such as a spin coating method or a printing method.

Note that in this embodiment, a silicon nitride film is used as the insulating film, and a silicon oxide film is used as the insulating layer 130.

Planarization treatment is preferably performed on the formation region of the semiconductor film 144 on the surface of the insulating layer 130. In this embodiment, the semiconductor film 144 is formed over the insulating layer 130 that is sufficiently planarized by polishing treatment (for example, CMP treatment) (preferably the average surface roughness of the surface of the insulating layer 130 is 0.15 nm or less).

A transistor 162 illustrated in FIG. 5A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the semiconductor film 144 included in the transistor 162 is preferably highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

Since the off-state current of the transistor 162 including an oxide semiconductor film is small, stored data can be retained for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

In the transistor 162, the oxide insulating film 135 and the sidewall insulating layer are separated in the step of forming the electrode layers 142a and 142b functioning as the source electrode layer and the drain electrode layer by dividing the conductive film over the gate electrode 148 using a CMP method. A first polishing process using an alkaline slurry in which the removal treatment proceeds more effectively on the oxide insulating film used for 136a and 136b, and an acidic slurry in which the removal treatment effectively proceeds on the metal film. The second polishing process used is performed. In addition to the polishing process by the CMP method, an alkaline slurry is applied to the oxide insulating film 135 and the oxide insulating film used for the sidewall insulating layers 136a and 136b and the metal film used for the gate electrode 148 and the electrode layers 142a and 142b. And different selectivity ratios of acidic slurries. In the manufacturing process, in addition to the polishing process by the CMP method, more precise processing can be performed with good control by using the slurry having a different selection ratio to the processed object.

For the stack of the conductive film and the oxide insulating film provided over the gate electrode 148, first, the oxide insulating film is selectively removed by a first polishing process, and then provided over the gate electrode 148. The formed conductive layer is exposed. Since the second polishing process to be performed next is performed using an acidic slurry that effectively removes the metal film, the sidewall insulating layers 136a and 136b are difficult to remove, and the gate electrode 148 is selectively removed. And the conductive film can be removed. Therefore, the height of the gate electrode 148 and the electrode layers 142a and 142b (the height from the substrate 185) can be made lower than the height of the top surfaces of the sidewall insulating layers 136a and 136b. With this structure, since the gate electrode 148 and the electrode layers 142a and 142b can be more reliably insulated by using the sidewall insulating layers 136a and 136b, the gate electrode 148 and the electrode layers 142a and 142b are in contact with each other. It is possible to reduce defects such as a short circuit due to. Thus, in a manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

Therefore, since the transistor 162 can shorten the distance between the gate electrode 148 and the region (contact region) where the electrode layers 142a and 142b functioning as the source electrode layer or the drain electrode layer are in contact with the semiconductor film 144, the electrode layer The region (contact region) where 142a and 142b and the semiconductor film 144 are in contact with each other and the resistance between the gate electrodes 148 are reduced, so that the on-state characteristics of the transistor 162 can be improved.

Over the transistor 162, the oxide insulating film 135 and the insulating film 150 are provided as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating film 150. When the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

In addition, a conductive layer 153 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the oxide insulating film 135 and the insulating film 150 interposed therebetween, and the electrode layer 142a, the oxide insulating film 135, and the insulating layer are insulated. The capacitor 150 is formed by the film 150 and the conductive layer 153. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 164 and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

An insulating film 152 is provided over the transistor 162 and the capacitor 164. A transistor 162 and a wiring 156 for connecting another transistor are provided over the insulating film 152. Although not illustrated in FIG. 5A, the wiring 156 is electrically connected to the electrode layer 142b through an electrode formed in an opening formed in the insulating film 150, the insulating film 152, the gate insulating film 146, and the like. The Here, the electrode is preferably provided so as to overlap with at least part of the semiconductor film 144 of the transistor 162.

5A and 5B, the transistor 160 and the transistor 162 are provided so that at least part of them overlaps, and the source or drain region of the transistor 160 and part of the semiconductor film 144 are overlapped with each other. Are preferably provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided so as to overlap with at least part of the gate electrode 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Note that the electrode layer 142b and the wiring 156 may be electrically connected to each other by bringing the electrode layer 142b and the wiring 156 into direct contact with each other, or an electrode is provided on an insulating film between the electrode layer 142b and the wiring 156. You may go through. A plurality of electrodes may be interposed therebetween.

Next, an example of a circuit configuration corresponding to FIGS. 5A and 5B is illustrated in FIG.

In FIG. 5C, the first wiring (1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the transistor 160 are electrically connected. It is connected. In addition, the third wiring (3rd Line) and one of the source electrode and the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected to each other. It is connected to the. The gate electrode of the transistor 160 and one of the source electrode and the drain electrode of the transistor 162 are electrically connected to the other electrode of the capacitor 164, and the fifth wiring (5th Line) and the electrode of the capacitor 164 The other of these is electrically connected.

In the semiconductor device illustrated in FIG. 5C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 160 and the capacitor 164. That is, predetermined charge is given to the gate electrode of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the charge given to the gate electrode of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the first wiring is changed according to the amount of charge held in the gate electrode of the transistor 160. The two wirings have different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high level charge is applied to the gate electrode of the transistor 160 is a low level charge applied to the gate electrode of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned “off” regardless of the state of the gate electrode, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively, a} potential at which the transistor 160 is turned on regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a semiconductor device which uses any of the transistors described in any of Embodiments 1 to 3, can store stored contents even in a state where power is not supplied, and has no limit on the number of writing operations. A structure different from the structure shown in Embodiment Mode 2 will be described with reference to FIGS.

6A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 6B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 6A will be described, and then the semiconductor device illustrated in FIG. 6B will be described below.

In the semiconductor device illustrated in FIG. 6A, the bit line BL and the source electrode or the drain electrode of the transistor 162 are electrically connected, and the word line WL and the gate electrode of the transistor 162 are electrically connected. The source electrode or the drain electrode of the capacitor and the first terminal of the capacitor 254 are electrically connected.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG. 6A is described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

The transistor 162 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB * VB0 + C * V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. (= (CB * VB0 + C * V1) / (CB + C)) may be higher than the potential of the bit line BL when the potential V0 is held (= (CB * VB0 + C * V0) / (CB + C)). Recognize.

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 6A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 6B is described.

The semiconductor device illustrated in FIG. 6B includes memory cell arrays 251a and 251b each including a plurality of memory cells 250 illustrated in FIG. 6A as memory circuits in the upper portion, and the memory cell arrays 251 (memory cell arrays 251a and 251b) in the lower portion. 251 b) has a peripheral circuit 253 necessary for operating. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 6B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (memory cell arrays 251a and 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

Note that although the semiconductor device illustrated in FIG. 6B illustrates a structure in which two memory cell arrays 251 (a memory cell array 251a and a memory cell array 251b) are stacked, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of the memory cell 250 illustrated in FIG. 6A will be described with reference to FIGS.

FIG. 7 shows an example of the configuration of the memory cell 250. 7A is a cross-sectional view of the memory cell 250, and FIG. 7B is a plan view of the memory cell 250. Here, FIG. 7A corresponds to a cross section taken along lines F1-F2 and G1-G2 in FIG.

The transistor 162 illustrated in FIGS. 7A and 7B can have the same structure as the structure described in Embodiment 1 or 2.

An insulating film 256 is provided as a single layer or a stacked layer over the transistor 162 provided over the insulating layer 180. In addition, a conductive layer 262 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the insulating film 256 provided therebetween, and the electrode layer 142a, the oxide insulating film 135, the insulating film 256, and the conductive layer are provided. The capacitor 254 is configured by the H.262. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 functions as the other electrode of the capacitor 254.

An insulating film 258 is provided over the transistor 162 and the capacitor 254. A memory cell 250 and a wiring 260 for connecting the adjacent memory cell 250 are provided over the insulating film 258. Although not illustrated, the wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 through an opening formed in the insulating film 256, the insulating film 258, and the like. However, another conductive layer may be provided in the opening, and the wiring 260 and the electrode layer 142b may be electrically connected through the other conductive layer. Note that the wiring 260 corresponds to the bit line BL in the circuit diagram of FIG.

7A and 7B, the electrode layer 142b of the transistor 162 can also function as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

By adopting the planar layout shown in FIG. 7A, the occupation area of the semiconductor device can be reduced, so that high integration can be achieved.

As described above, in this embodiment, the plurality of memory cells formed in multiple layers in the upper portion are formed using transistors including an oxide semiconductor. Since a transistor including an oxide semiconductor has a small off-state current, stored data can be held for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS.

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In a normal SRAM, as shown in FIG. 8A, one memory cell is composed of six transistors 801 to 806, which are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 form an inverter and can be driven at high speed. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is normally 100 to 150 F ² . For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 8B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. The memory cell area of a DRAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 9 shows a block diagram of a portable device. 9 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. A sensor 919, an audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface 909 (IF909). In general, the memory circuit 912 includes an SRAM or a DRAM. By adopting the semiconductor device described in the above embodiment for this portion, information can be written and read at high speed, and long-term storage can be performed. In addition, power consumption can be sufficiently reduced.

FIG. 10 shows an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 10 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit reads a signal line from image data (input image data), a memory 952, and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and is stored in the display 957 via the switch 955 and the display controller 956. The stored image data B is sent and displayed. This reading is continued until new image data is stored in the memory 952 next time.

As described above, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 952 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently reduced. it can.

FIG. 11 is a block diagram of an electronic book. 11 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 has a function of temporarily holding the contents of a book. An example of a function is when a user uses a highlight function. When a user is reading an electronic book, the user may want to mark a specific part. This marking function is called a highlight function, and is to show the difference from the surroundings by changing the display color, underlining, making the character thicker, or changing the font of the character. This is a function for storing and holding information on a location designated by the user. When this information is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the above embodiment, writing and reading of information can be performed at high speed, long-term storage can be performed, and power consumption can be sufficiently reduced. Can do.

As described above, the portable device described in this embodiment includes the semiconductor device according to any of the above embodiments. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

In this example, a transistor which is one embodiment of the semiconductor device disclosed in this specification was manufactured, and cross-sectional observation and evaluation of electric characteristics were performed.

As a transistor, an example transistor having a structure similar to that of the transistor 340 illustrated in FIG. 12 was manufactured. A method for manufacturing an example transistor is described below.

A silicon oxide film having a thickness of 1000 nm was formed as the insulating film 336 on the silicon substrate 300 subjected to the plasma treatment with Ar (Ar flow rate 50 sccm, pressure 0.6 Pa, power supply power 200 W, 3 minutes) using the sputtering method ( Film forming conditions: oxygen (oxygen 50 sccm) atmosphere, pressure 0.4 Pa, power supply power (power output) 1.5 kW, distance between silicon substrate and target 60 mm, substrate temperature 100 ° C.

Next, the surface of the insulating film 336 is subjected to a polishing process (polishing pressure of 0.01 MPa, the number of rotations during polishing (table / spindle): 60 rpm / 56 rpm) by a chemical mechanical polishing (CMP) method. The average surface roughness (Ra) was about 0.2 nm.

An IGZO film with a thickness of 20 nm was formed over the insulating film 336 by a sputtering method using an oxide target of In: Ga: Zn = 3: 1: 2 [atomic ratio] as an oxide semiconductor film. The deposition conditions were argon and oxygen (argon: oxygen = 30 sccm: 15 sccm), pressure 0.4 Pa, power supply power 0.5 kW, and substrate temperature 200 ° C.

An oxide semiconductor film is etched by dry etching (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), ICP power supply power 450 W, bias power 100 W, pressure 1.9 Pa) to form an island-shaped semiconductor film 303 was formed.

Next, a 20 nm thick silicon oxynitride film serving as a gate insulating film was formed by a CVD method.

A tantalum nitride film with a film thickness of 30 nm is formed on the gate insulating film by sputtering (film formation conditions: argon and nitrogen (argon: nitrogen = 50 sccm: 10 sccm) atmosphere, pressure 0.6 Pa, power supply power 1 kW) and film thickness 200 nm. A stack of tungsten films (film formation conditions: argon (100 sccm) atmosphere, pressure 2.0 Pa, power supply power 4 kW) was formed.

A resist mask was formed on the tantalum nitride film and the tungsten film by photolithography. After the resist mask was formed by exposure, a slimming process was further performed by etching to reduce the length in the channel length direction to 210 nm.

The tantalum nitride film and the tungsten film are etched by dry etching ((first etching condition: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm: 55 sccm), ICP power supply power 3 kW, bias power 110 W, pressure 0) (Second etching condition: etching gas (Cl ₂ = 100 sccm), power source power 2 kW, bias power 50 W, pressure 0.67 Pa)) to form an island-shaped gate electrode layer 301.

Next, an aluminum oxide film (deposition condition: argon and oxygen (argon: oxygen = 25 sccm: 25 sccm) atmosphere) is formed on the gate electrode layer 301 as an insulating film by a sputtering method, a pressure of 0.4 Pa, a power supply power of 2.5 kW, The distance between the glass substrate and the target was 60 nm, and the substrate temperature was 250 nm.

A silicon oxynitride film having a thickness of 100 nm was formed as an insulating film over the aluminum oxide film by a CVD method.

Using the gate electrode layer 301 as a mask, the silicon oxynitride film, the aluminum oxide film, and the silicon oxynitride film are passed through, and phosphorus ions are implanted into the semiconductor film 303 by an ion implantation method, so that a channel formation region 309 and a low resistance region 304a are obtained. , 304b was formed. The phosphorus ion implantation conditions were an acceleration voltage of 110 kV and a dose of 4.0 × 10 ¹⁵ ions / cm ² .

The silicon oxynitride film is etched by dry etching (etching conditions: etching gas (CHF ₃ : He = 30 sccm: 120 sccm, power supply power 3 kW, bias power 200 W, pressure 2.0 Pa, lower electrode temperature −10 ° C.) to gate Side wall insulating layers 312a2 and 312b2 are formed to cover the side surfaces of the electrode layer 301. The aluminum oxide film and the gate insulating film are etched using the gate electrode layer 301 and the side wall insulating layers 312a2 and 312b2 as a mask to form side wall insulating layers 312a1, 312b1, and Then, the gate insulating film 302 was formed, and the etching conditions of the aluminum oxide film were as follows: etching gas BCl ₃ = 80 sccm, ICP power supply power 550 W, bias power 150 W, pressure 1.0 Pa, and lower electrode temperature 70 ° C.

On the semiconductor film 303, the gate insulating film 302, the gate electrode layer 301, and the sidewall insulating layers 312a1, 312a2, 312b1, and 312b2, a tungsten film with a thickness of 30 nm is formed by sputtering (film formation condition: argon (80 sccm) atmosphere, pressure 0 8 Pa, power supply power 1 kW, substrate temperature 200 ° C.).

Next, the tungsten film is etched by dry etching (etching conditions: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm: 55 sccm), power supply power 3 kW, bias power 110 W, pressure 0.67 Pa). An island-shaped tungsten film was formed.

Next, an aluminum oxide film (deposition conditions: argon and oxygen) is formed on the semiconductor film 303, the gate insulating film 302, the gate electrode layer 301, the sidewall insulating layers 312a1, 312a2, 312b1, 312b2, and the tungsten film as an insulating film by a sputtering method. Under an atmosphere of (argon: oxygen = 25 sccm: 25 sccm), a pressure of 0.4 Pa, a power supply power of 2.5 kW, a distance between the glass substrate and the target of 60 mm, and a substrate temperature of 250 ° C. was formed to a thickness of 70 nm.

Further, a silicon oxynitride film was formed at 460 nm over the aluminum oxide film by a CVD method.

Next, a first polishing process is performed on the silicon oxynitride film and the aluminum oxide film by a chemical mechanical polishing method (polishing conditions: hard polyurethane polishing cloth, alkaline slurry (NP8020 (manufactured by Nitta Haas Co.)), slurry temperature at room temperature The polishing (load) pressure is 0.08 MPa, the rotation speed during polishing (table / spindle) is 51 rpm / 50 rpm), the silicon oxynitride film and the aluminum oxide film on the gate electrode layer 301 are removed, and the tungsten film is exposed. It was. The first polishing treatment is performed using an alkaline slurry that effectively removes the oxide insulating film. The silicon oxynitride film and the aluminum oxide film were partly removed by the first polishing process to form insulating films 310 and 315.

Next, a second polishing process (polishing condition: hard polyurethane polishing cloth, acidic slurry (SSW2000 (manufactured by Cabot)) (135 ml) is added to the tungsten film by a chemical mechanical polishing method. (Diluted twice), slurry temperature at room temperature, polishing (load) pressure 0.01 MPa, polishing rotation speed (table / spindle) 39 rpm / 35 rpm), part of the gate electrode layer 301 and on the gate electrode layer 301 The tungsten film was removed. By the second polishing treatment, the tungsten film was divided to form the source electrode layer 305a and the drain electrode layer 305b.

An example transistor was manufactured through the above steps.

Example An aluminum oxide film (film formation conditions: argon and oxygen (argon: oxygen = 25 sccm: 25 sccm) atmosphere, pressure 0.4 Pa, power supply power 2.5 kW, glass substrate as an interlayer insulating film 307 on the transistor by sputtering. The distance between the target and the target was 60 nm, and the substrate temperature was 250 ° C., and a silicon oxynitride film was formed to 400 nm as an interlayer insulating film 317 on the aluminum oxide film by a CVD method. After the interlayer insulating film was formed, heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere.

Openings reaching the source electrode layer and the drain electrode layer were formed.

A titanium film with a film thickness of 50 nm is formed in the opening by sputtering (film formation condition: argon (20 sccm) atmosphere, pressure 0.1 Pa, power supply power 12 kW), and an aluminum film with a film thickness 100 nm (film formation condition: argon (50 sccm) atmosphere A titanium film having a thickness of 50 nm and a film thickness of 50 nm (deposition conditions: argon (20 sccm) atmosphere, pressure 0.1 Pa, power supply power 12 kW) was laminated.

Etching (etching condition: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), ICP power supply power 450 W, bias power 100 W, pressure 1.9 Pa) is performed on the stack of the titanium film, the aluminum film, and the titanium film. 335a and 335b were formed.

A polyimide film having a thickness of 1.5 μm was formed on the wiring layer, and heat treatment was performed in the atmosphere at 300 ° C. for 1 hour.

In this example, three types of transistors having a channel width (W) of 10 μm and channel lengths of 0.1 μm, 0.3 μm, and 10 μm were manufactured as the example transistors.

In addition to the steps shown below, a comparative transistor was also produced in the same manner as the example transistor. In the following, in the method for manufacturing the comparative transistor, steps different from those of the method for manufacturing the example transistor are described in detail.

In the comparative transistor, a film thickness is formed by a sputtering method using an oxide target of In: Ga: Zn = 3: 1: 2 [atomic ratio] as a semiconductor film over a silicon substrate provided with an insulating film. A 10 nm IGZO film was formed. Further, oxygen ions were implanted into the IGZO film by an ion implantation method. The oxygen ion implantation conditions were an acceleration voltage of 5 kV and a dose of 2.5 × 10 ¹⁵ ions / cm ² .

Using the gate electrode layer as a mask, a silicon oxynitride film serving as a gate insulating film was passed, and phosphorus ions were implanted into the semiconductor film by an ion implantation method, so that a semiconductor film including a channel formation region and a low resistance region was formed. The phosphorus ion implantation conditions were an acceleration voltage of 110 kV and a dose of 4.0 × 10 ¹⁵ ions / cm ² . After phosphorus ion implantation into the oxide semiconductor film, an aluminum oxide film was not provided over the gate electrode layer, and a silicon oxynitride film was formed to a thickness of 90 nm by a CVD method.

The silicon oxynitride film was etched by a dry etching method to form a sidewall insulating layer covering the side surface of the gate electrode layer. Using the gate electrode layer and the sidewall insulating layer as a mask, the silicon oxynitride film was etched to form a gate insulating film.

A tungsten film was formed over the semiconductor film, the gate insulating film, the gate electrode layer, and the sidewall insulating layer by a sputtering method, and the tungsten film was etched by a dry etching method to form an island-shaped tungsten film.

An aluminum oxide film was formed by a sputtering method over the semiconductor film, the gate insulating film, the gate electrode layer, the sidewall insulating layer b, and the tungsten film, and a silicon oxynitride film was formed over the aluminum oxide film by a CVD method.

Polishing silicon oxynitride film, aluminum oxide film and tungsten film by chemical mechanical polishing method (Polishing conditions: hard polyurethane polishing cloth, alkaline slurry (NP8020 (made by Nita Haas Co.)), slurry temperature at room temperature, polishing (Load) pressure 0.08 MPa, polishing rotation speed (table / spindle) 51 rpm / 50 rpm), and a silicon oxynitride film, an aluminum oxide film, and tungsten on the gate electrode layer 501 so that the gate electrode layer is exposed. The membrane was removed.

In the comparative transistor, the silicon oxynitride film and the aluminum oxide film were removed by one polishing process, and the tungsten film on the gate electrode layer was removed and divided to form a source electrode layer and a drain electrode layer. .

A comparative transistor was manufactured through the above steps.

A silicon oxynitride film having a thickness of 400 nm was formed as an interlayer insulating film over the transistor of the comparative example by a CVD method, and after the interlayer insulating film was formed, heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere.

Openings reaching the source electrode layer and the drain electrode layer were formed, and a titanium film, an aluminum film, and a titanium film were stacked in the openings, and etched to form a wiring layer. A polyimide film having a thickness of 1.5 μm was formed on the wiring layer, and heat treatment was performed in the atmosphere at 300 ° C. for 1 hour.

As comparative transistors, three types of transistors having a channel width (W) of 10 μm and channel lengths of 0.1 μm, 0.3 μm, and 10 μm were manufactured.

A cross section in the channel length direction of an example transistor (channel length: 0.1 μm) was cut out, and cross sections of the example transistor and the comparative example transistor were observed with a scanning transmission electron microscope (STEM). In this example, STEM used “Hitachi ultra-thin film evaluation apparatus HD-2300” (manufactured by Hitachi High-Technologies Corporation). FIG. 13 shows a cross-sectional STEM image of the example transistor.

In the example transistor, the oxide insulating film is more effectively removed in the step of forming the source electrode layer 305a and the drain electrode layer 305b by dividing the conductive film over the gate electrode layer 301 using a CMP method. The first polishing process using the alkaline slurry in which the progress is performed and the second polishing process using the acidic slurry in which the removal process is effectively performed on the metal film are performed. An alkaline slurry and an acidic slurry have an oxide insulating film used for the sidewall insulating layers 312a1, 312a2, 312b1, and 312b2 and a metal film used for the gate electrode layer 301, the source electrode layer 305a, and the drain electrode layer 305b. Utilize different selection ratios.

First, with respect to the stack of the conductive film and the oxide insulating film provided over the gate electrode layer 301, the oxide insulating film is selectively removed by a first polishing process, and then the gate electrode layer 301 is formed. The conductive layer provided on is exposed. Since the second polishing process to be performed next is performed using an acidic slurry that effectively removes the metal film, the side wall insulating layers 312a1, 312a2, 312b1, and 312b2 are difficult to remove, and the gate is selectively removed. Part of the electrode layer 301 and the conductive film can be removed. Therefore, as shown in FIG. 13, the height of the gate electrode layer 301, the source electrode layer 305a, and the drain electrode layer 305b (the height from the silicon substrate 300) is the upper surface of the sidewall insulating layers 312a1, 312a2, 312b1, and 312b2. It can be made lower than the height. With this structure, the gate electrode layer 301 can be more reliably insulated from the source electrode layer 305a and the drain electrode layer 305b by using the sidewall insulating layers 312a1, 312a2, 312b1, and 312b2. Defects such as a short circuit due to contact between the source electrode layer 305a and the drain electrode layer 305b can be reduced. Therefore, it is possible to manufacture fine transistor examples with high yield.

On the other hand, in the case of the comparative transistor in which the stack of the conductive film and the oxide insulating film provided on the gate electrode layer is removed by a single polishing process, the comparative transistor is a sidewall insulating layer when the conductive film is removed. Therefore, the upper portion of the gate electrode layer can be exposed. Such excessive removal of the sidewall insulating layer causes a short circuit between the gate electrode layer, the source electrode layer, and the drain electrode layer, and the yield and productivity are reduced. In addition, when a laminated structure with different materials is processed by a single polishing process, variations in the processing region are likely to occur within the substrate surface, particularly in the manufacturing process of a semiconductor device including a plurality of integrated microscopic transistors. It will greatly affect the form of defects.

Next, evaluation results of electrical characteristics of the example transistor and the comparative transistor are shown.

FIG. 14A shows an example transistor having a channel length of 0.1 μm, and FIG. 14B shows a drain voltage (Vd) of a comparative example transistor having a channel length of 0.1 μm of 1 V (thick line), 0.1 V ( The gate voltage (Vg) -drain current (Id) characteristics and field effect mobility in a thin line) are shown. The field effect mobility of an example transistor with a drain voltage (Vd) of 0.1 V and a channel length of 0.1 μm is 7.6 cm ² / Vs, and the field effect of a comparative example transistor with a channel length of 0.1 μm. The mobility was 1.0 cm ² / Vs.

FIG. 15A shows an example transistor having a channel length of 0.3 μm, and FIG. 15B shows a drain voltage (Vd) of a comparative example transistor having a channel length of 0.3 μm of 1 V (thick line) and 0.1 V ( The gate voltage (Vg) -drain current (Id) characteristics and field effect mobility in a thin line) are shown. The field effect mobility of the example transistor with a drain voltage (Vd) of 0.1 V and a channel length of 0.3 μm is 18.6 cm ² / Vs, and the field effect of the comparative transistor with a channel length of 0.3 μm. The mobility was 3.8 cm ² / Vs.

FIG. 16A shows an example transistor having a channel length of 10 μm, and FIG. 16B shows a gate of a comparative example transistor having a channel length of 10 μm with a drain voltage (Vd) of 1 V (thick line) and 0.1 V (thin line). The voltage (Vg) -drain current (Id) characteristics and field effect mobility are shown. The field effect mobility of the example transistor having a drain voltage (Vd) of 0.1 V and a channel length of 10 μm is 22.6 cm ² / Vs, and the field effect mobility of the comparative example transistor having a channel length of 10 μm is It was 4.0 cm ² / Vs.

Note that the measurement range of FIGS. 14 to 16 is a gate voltage of −4V to + 4V.

As compared with the comparative transistor, the transistor of the example showed good electrical characteristics as a switching element in all of the transistors in the measurement substrate with channel lengths of 0.1 μm, 0.3 μm, and 10 μm. On the other hand, many of the comparative example transistors cannot obtain electrical characteristics as a switching element, and the defect is particularly remarkable in a sample having a channel length of 10 μm.

The defect rate in the example transistor and the comparative transistor was calculated. The defect rate can be obtained from the characteristics of gate voltage (Vg) -drain current (Id) when the drain voltage (Vd) of the transistor in FIGS. The point at which no electrical characteristics were obtained as a switching element (threshold voltage was outside −4 V to +4 V and on / off characteristics were not obtained) at 13 points in the comparative transistor was calculated as a defective point.

In the comparative example transistor, the channel length of 0.1 μm was a high failure rate of 31%, the channel length of 0.3 μm was a failure rate of 38%, and the channel length of 10 μm was a high failure rate of 69%. The channel length of 0.1 μm is a considerably low numerical value of 8%, and when the channel length is 0.3 μm and the channel length is 10 μm, the defect rate is 0%.

Thus, in the transistor of the example, it was confirmed that defective electrical characteristics of the transistor were reduced in the plane, and a highly reliable semiconductor device could be manufactured with a high yield.

As described above, as shown in this embodiment, a transistor having high electrical characteristics can be provided with high yield even when the structure is minute. In a semiconductor device including the transistor, high performance, high reliability, and high production can be achieved.

Claims (10)

A semiconductor film, a gate insulating film, and a gate electrode layer are sequentially stacked,
Forming a sidewall insulating layer covering the side surface of the gate electrode layer;
Forming a conductive film on the semiconductor film, the gate insulating film, the gate electrode layer, and the sidewall insulating layer;
Forming an oxide insulating film on the conductive film;
By the first polishing process using an alkaline slurry, the oxide insulating film on the gate electrode layer is removed until the conductive film is exposed,
A part of the gate electrode layer and the conductive film on the gate electrode layer are removed and the conductive film is divided by a second polishing process using an acidic slurry to form a source electrode layer and a drain electrode layer. A method for manufacturing a semiconductor device. An oxide semiconductor film, a gate insulating film, and a gate electrode layer are sequentially stacked,
Forming a sidewall insulating layer covering the side surface of the gate electrode layer;
Forming a conductive film on the semiconductor film, the gate insulating film, the gate electrode layer, and the sidewall insulating layer;
Forming an oxide insulating film on the conductive film;
By the first polishing process using an alkaline slurry, the oxide insulating film on the gate electrode layer is removed until the conductive film is exposed,
A part of the gate electrode layer and the conductive film on the gate electrode layer are removed and the conductive film is divided by a second polishing process using an acidic slurry to form a source electrode layer and a drain electrode layer. A method for manufacturing a semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a dopant is selectively introduced into the oxide semiconductor film using the gate electrode layer as a mask to form a low resistance region in the oxide semiconductor film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a chemical mechanical polishing method is used as the first polishing process and the second polishing process. 5. A semiconductor film including a channel formation region;
A gate insulating film on the semiconductor film;
A gate electrode layer on the gate insulating film;
A sidewall insulating layer covering a side surface of the gate electrode layer;
A source electrode layer and a drain electrode layer in contact with the semiconductor film, the side surface of the gate insulating film and the side surface of the sidewall insulating layer;
An oxide insulating film on the source electrode layer and the drain electrode layer;
The gate electrode layer, the source electrode layer, and the drain electrode layer are in contact with each other, and an interlayer insulating film is provided on the oxide insulating film,
The semiconductor device according to claim 1, wherein heights of upper surfaces of the gate electrode layer, the source electrode layer, and the drain electrode layer are lower than those of the sidewall insulating layer and the oxide insulating film. An oxide semiconductor film including a channel formation region;
A gate insulating film on the oxide semiconductor film;
A gate electrode layer on the gate insulating film;
A sidewall insulating layer covering a side surface of the gate electrode layer;
A source electrode layer and a drain electrode layer in contact with the side surfaces of the oxide semiconductor film, the side surface of the gate insulating film and the side wall insulating layer;
An oxide insulating film on the source electrode layer and the drain electrode layer;
The gate electrode layer, the source electrode layer, and the drain electrode layer are in contact with each other, and an interlayer insulating film is provided on the oxide insulating film,
The semiconductor device according to claim 1, wherein heights of upper surfaces of the gate electrode layer, the source electrode layer, and the drain electrode layer are lower than those of the sidewall insulating layer and the oxide insulating film.   7. The semiconductor device according to claim 6, wherein the sidewall insulating layer includes an aluminum oxide film.   8. The semiconductor device according to claim 6, wherein the oxide insulating film includes an aluminum oxide film.   9. The semiconductor device according to claim 5, wherein heights of upper surfaces of the source electrode layer and the drain electrode layer are lower than heights of the upper surface of the gate electrode layer.   10. The semiconductor device according to claim 5, wherein the semiconductor film includes a low-resistance region containing a dopant adjacent to the channel formation region.