JP5888929B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required. Various metal oxides exist and are used in various applications.

Some metal oxides exhibit semiconductor properties. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors that use such metal oxides that exhibit semiconductor characteristics as a channel formation region are already known. (Patent Document 1 and Patent Document 2).

Patent Document 3 describes that zinc oxide, magnesium zinc oxide, and cadmium zinc oxide are used as semiconductors.

JP 2007-123861 A JP 2007-96055 A US Pat. No. 6,727,522

An object of one embodiment of the present invention is to provide a material suitable for semiconductor use such as a transistor or a diode. Specifically, an object is to provide a manufacturing method for forming an oxide semiconductor film with high crystallinity and a material obtained by the manufacturing method.

Another object is to provide a semiconductor device capable of mass production of a highly reliable semiconductor device using a large substrate such as mother glass or a plastic substrate, and a manufacturing method thereof.

One embodiment of the present invention disclosed in this specification has a composition of A _1-X Zr _X Zn _Y O _Z (where A is indium (In), aluminum (Al), magnesium (Mg), neodymium (Nd), An oxide semiconductor layer represented by cerium (Ce), lanthanum (La), or hafnium (Hf), where X = 0.001 to 0.5, Y is 0.5 or more, and Z is 0.5 or more) The semiconductor device includes a gate insulating layer in contact with the oxide semiconductor layer and a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

By including zirconium which is one of Group 4 elements in the composition of the oxide semiconductor layer, a material that can be easily crystallized can be obtained.

In addition, since the oxide semiconductor material containing zirconium can be easily crystallized, an oxide semiconductor layer with high crystallinity can be formed over a large substrate such as mother glass or a plastic substrate. it can. An oxide semiconductor film with high crystallinity is formed by performing heat treatment after the formation of the oxide semiconductor layer using the oxide semiconductor material containing zirconium and further improving crystallinity.

Specifically, an oxide semiconductor material containing at least indium and zinc contains zirconium which is one of group 4 elements. An energy gap of an oxide semiconductor material film in which zirconium is included in an oxide semiconductor material containing at least indium and zinc (hereinafter also referred to as an InZrZnO _X film (where X> 0)) has indium, gallium, and IGZO films. It becomes larger than the oxide semiconductor material film containing zinc (about 3.2 eV). Zirconium is a group 4 element, and is a stable material in which one bond captures oxygen and easily fixes oxygen.

In the present specification, the term “energy gap” is used in the same meaning as “band gap” and “forbidden bandwidth”. As the band gap value, a value obtained by measuring with a single film ellipso of the material is used. In this specification, the value of the ionization potential is a value obtained by adding the band gap and the electron affinity. Note that the electron affinity represents an energy difference between a vacuum level and a conduction band of an oxide semiconductor.

In the case of using a thin film of an oxide semiconductor material containing zirconium, an oxide semiconductor film having a crystal structure can be formed immediately after film formation. Therefore, the heat treatment after the formation of the oxide semiconductor film can be omitted, which can be said to be a process suitable for mass production. Note that an oxide semiconductor film having a crystal structure includes a crystal part, and the c-axis direction of the crystal part is perpendicular to the formation surface of the oxide semiconductor film or perpendicular to the surface of the oxide semiconductor film. One of the features is the direction.

Another embodiment of the present invention is an oxide semiconductor layer containing indium, zirconium, and zinc, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween A semiconductor device having a layer.

In the above structure, the zirconium content in the oxide semiconductor layer is less than or equal to the indium content. In addition, the zirconium content in the oxide semiconductor layer is equal to or less than the zinc content.

Specifically, when an oxide semiconductor material containing zirconium is formed by a sputtering method, the atomic ratio is preferably In: Zr: Zn = 1: 1: 1, 4: 1: 4, 3: 2. An oxide target of 2: 4, 2: 1: 3, 5: 1: 3, or 4: 2: 3 is used.

Further, tin may be contained in an oxide semiconductor material containing indium, zinc, and zirconium. Another structure of the present invention is an oxide containing indium, zirconium, zinc, and tin. The semiconductor device includes a physical semiconductor layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

By including zirconium in the oxide semiconductor layer of the transistor, crystallinity can be improved. By increasing the crystallinity of the oxide semiconductor layer, a transistor with further improved electrical characteristics (such as field-effect mobility and threshold value) can be obtained. In addition, the off-state current of the transistor can be extremely small.

In addition, a highly reliable semiconductor device can be mass-produced using a large substrate such as mother glass.

(A) is an energy band diagram of an InZrZnO _X film, and (B) is an energy band diagram of an IGZO film. (A) is a graph showing the XRD result of the InZrZnO _X film, and (B) is a graph showing the XRD result of the InCeZnO _X film. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of one embodiment of a semiconductor device. 4A and 4B are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 10A and 10B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. Cross-sectional TEM photograph (magnified 2 million times) of InZrZnO _X film immediately after film formation. The cross-sectional TEM photograph (2 million times) of the InZrZnO _X film | membrane after heat processing of 650 degreeC. A cross-sectional TEM photograph (4 million times) of an InZrZnO _X film immediately after film formation. The cross-sectional TEM photograph (8 million times) of the InZrZnO _X film | membrane after heat processing of 650 degreeC.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device is described below.

A transistor is manufactured over an insulating surface, and a film (InZrZnO _X film) containing zirconium in an oxide semiconductor material containing at least indium and zinc is used as an oxide semiconductor layer serving as a channel formation region of the transistor.

The structure of the transistor may be a top gate structure having a gate electrode layer over a gate insulating layer over an oxide semiconductor layer, or a bottom having an oxide semiconductor layer over a gate electrode layer through a gate insulating layer. It may be a gate structure.

Note that the transistor is not particularly limited to a single gate structure in which one channel formation region is formed, and may be, for example, a double gate structure in which two channel formation regions are formed or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type having two gate electrode layers arranged above and below the channel formation region with a gate insulating layer interposed therebetween may be used.

The InZrZnO _X film has an atomic ratio of In: Zr: Zn = 1: 1: 1, 4: 1: 4, 3: 2: 4, 2: 1: 3, 5: 1: 3, or 4: 2: It forms by sputtering method using the oxide target shown by 3. FIG.

In this embodiment, an InZrZnO _X film formed using a target having an atomic ratio of In: Zr: Zn = 1: 1: 1 is used.

A sample in which an InZrZnO _X film having a thickness of 100 nm was actually formed on a glass substrate was prepared, the ionization potential of the sample was measured, and an energy band diagram was calculated based on the result. The value of the ionization potential is a value obtained by adding the band gap and the electron affinity, and the band gap value is obtained by measuring with a single film ellipso of the material. As shown in FIG. 1A, an energy band diagram of IGZO is shown in FIG. 1B as a comparative example.

In addition, Table 1 shows the results of calculating a plurality of samples in which InZrZnO _X films having different film formation conditions are formed, preparing samples having different heat treatment conditions, and calculating the respective energy gaps (Eg).

Sample 1 was formed by sputtering using a sputtering apparatus under a substrate temperature of room temperature and a mixed atmosphere of oxygen and argon (oxygen 33%). Sample 2 is formed by depositing the substrate at room temperature and in an oxygen atmosphere (oxygen 100%). Sample 3 is a film formed at a substrate temperature of 200 ° C. under a mixed atmosphere of oxygen and argon (oxygen 33%). Sample 4 is formed by forming a film at a substrate temperature of 200 ° C. under an oxygen atmosphere (oxygen 100%). Sample 5 is a film formed at a substrate temperature of 300 ° C. under a mixed atmosphere of oxygen and argon (oxygen 33%). Sample 6 is a film formed at a substrate temperature of 300 ° C. under an oxygen atmosphere (oxygen 100%).

In addition, a sputtering apparatus having a DC power supply device was used for film formation of all the samples, a pressure of 0.4 Pa, a power supply power of 200 W, and a distance between the substrate and the target (T-S distance) was 130 mm.

In addition, the heat treatment after the film formation was performed without heat treatment, 450 ° C. heat treatment, and 650 ° C. heat treatment. The heating at 450 ° C. was performed in a nitrogen atmosphere until the temperature was raised to 450 ° C. and held for 1 hour, and then the gas was changed to an oxygen atmosphere and held for 1 hour, and then the temperature was lowered to room temperature. Further, the heating at 650 ° C. was performed in a nitrogen atmosphere until the temperature was raised to 650 ° C. and held for 1 hour, and then the gas was changed to an oxygen atmosphere and held for 1 hour, and then the temperature was lowered to room temperature.

From Table 1, it can be read that the band gap of the InZrZnO _X film is 3.4 eV or more and 3.7 eV or less.

In addition, FIG. 2A shows the result of XRD (X-Ray-Diffraction) analysis performed on Sample 2, Sample 4, and Sample 6 that were formed in an oxygen atmosphere (oxygen 100%). As a comparative example, a target having an atomic ratio of In: Ce: Zn = 1: 1: 1 is used, and an InCeZnO _X film (where X> 0) is formed in an oxygen atmosphere (oxygen 100%). The result of XRD analysis of the performed sample is shown in FIG.

The InZrZnO _X film has higher crystallinity than the InCeZnO _X film, and it can be confirmed from XRD analysis that there is a crystalline portion even when the substrate temperature is room temperature. From this, it can be said that an InZrZnO _X film having high crystallinity can be formed on a plastic film having a heat resistant temperature of about 100 ° C. Note that Zr is a Group 4 element, and an InTiZnO _X film in which Ti of the same Group 4 element is replaced with Zr remains in an amorphous structure even when heated at 650 ° C. Therefore, it can be said that Zr, which is easy to crystallize an oxide semiconductor when included in an oxide semiconductor, has an unexpected effect, in particular, an effect that a film having a crystal structure can be obtained even at room temperature.

Further, FIGS. 16, 17, 18, and 19 show TEM photographs of cross sections of samples provided with InZrZnO _X films. FIG. 16 is a photograph of the cross section of the InZrZnO _X film immediately after film formation observed at 2 million times, and FIG. 17 is a photograph of the cross section of the InZrZnO _X film after heating at 650 ° C. at 2 million times. 18 is a photograph obtained by observing the cross section of the InZrZnO _X film immediately after film formation at 4 million times, and FIG. 19 is a photograph obtained by observing the cross section of the InZrZnO _X film after heating at 650 ° C. at 8 million times.

Further, from the XRD analysis and the cross-sectional TEM photograph, it can be said that the InZrZnO _X film is in a CAAC state or a polycrystalline state immediately after the film formation. Since the InZrZnO _X film can form an oxide semiconductor film having a crystal structure immediately after film formation, heat treatment for crystallization can be omitted after the oxide semiconductor film is formed. Therefore, a process suitable for mass production can be achieved using a large substrate such as mother glass or a plastic substrate. The plastic substrate can be manufactured as a roll film by reducing the thickness of the substrate to manufacture a semiconductor device on the film by a roll-to-roll method.

Here, CAAC (C Axis Aligned Crystal) is a triangular or hexagonal atomic arrangement in which the c-axis is oriented in a direction perpendicular to the formation surface or surface of the oxide semiconductor film and viewed from the direction perpendicular to the ab plane. And a crystal and amorphous mixed phase structure in which metal atoms are layered or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. In this mixed phase structure, the CAACs may have different a-axis and b-axis directions.

A CAAC oxide semiconductor (CAAC-OS) film is neither completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure. Although the size of a crystal is estimated to be several nanometers to several tens of nanometers, in an observation with a transmission electron microscope (TEM), a boundary between an amorphous material included in a CAAC-OS film and a CAAC is not always clear. is not. In addition, a crystal grain boundary (also referred to as a grain boundary) is not confirmed in the CAAC-OS film. Since the CAAC-OS film does not have a crystal grain boundary, the electron mobility due to the crystal grain boundary is unlikely to decrease.

Note that in the CAAC-OS film, the distribution of crystal regions in the film is not necessarily uniform. For example, in the case where crystal growth is performed from the surface side of the CAAC-OS film, the crystal ratio is high in the vicinity of the CAAC-OS film surface, and the amorphous ratio is high in the vicinity of the formation surface. .

Since the c-axis of the crystal part in the CAAC faces a direction perpendicular to the formation surface or surface of the CAAC-OS film, the c-axis depends on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface). The direction of facing may be different. Note that the c-axis direction of the crystal part in the CAAC is substantially perpendicular to the formation surface or the surface when the CAAC-OS film is formed.

With the use of the CAAC-OS film, change in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is reduced; thus, a highly reliable transistor can be obtained.

In addition, by adding zirconium to the oxide semiconductor layer of the transistor to increase crystallinity, a transistor with further improved electrical characteristics (such as field-effect mobility and threshold value) can be obtained. In addition, the off-state current of the transistor can be extremely small.

The composition is _{A 1-X Zr X Zn Y} O Z ( however, A is In, Al, Mg, Nd, Ce, La, or at Hf, X = 0.001 to 0.5, Y is 0. 5 or more, Z is 0.5 or more) The oxide semiconductor film obtained by a sputtering method using a target represented by the above formula has high crystallinity due to zirconium contained therein, and forms a CAAC-OS film in contact with the plastic film. It can also be formed immediately after the film. Further, a transistor can be manufactured by a roll-to-roll method using the CAAC-OS film.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

FIGS. 3A and 3B are a plan view and a cross-sectional view of a transistor 420 as an example of a semiconductor device. 3A is a plan view of the transistor 420, and FIG. 3B is a cross-sectional view taken along line X1-Y1 in FIG. Note that in FIG. 3A, some components (eg, the insulating layer 407) are not illustrated in order to avoid complexity.

A transistor 420 illustrated in FIGS. 3A and 3B includes a base insulating layer 436, a source electrode layer 405a, a drain electrode layer 405b, and one side surface in a channel length direction over a substrate 400 having an insulating surface. An oxide semiconductor layer 403 that is in contact with the source electrode layer and in contact with the drain electrode layer on the other side surface in the channel length direction, and a gate insulating layer 402 that is in contact with the top surfaces of the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b. A gate electrode layer 401 provided over the oxide semiconductor layer 403 with the gate insulating layer 402 interposed therebetween, a sidewall layer 412a in contact with one of the side surfaces of the gate electrode layer 401 in the channel length direction, and a channel of the gate electrode layer 401 And a side wall layer 412b in contact with the other of the side surfaces in the longitudinal direction.

In the transistor 420, at least part of the sidewall layer 412 a is provided over the source electrode layer 405 a with the gate insulating layer 402 interposed therebetween. Further, at least a part of the sidewall layer 412b is provided over the drain electrode layer 405b with the gate insulating layer 402 interposed therebetween. The sidewall layer 412a and the sidewall layer 412b contain a conductive material. Therefore, since the sidewall layer 412a and the sidewall layer 412b can function as part of the gate electrode layer 401, a region overlapping with the source electrode layer 405a or the drain electrode layer 405b with the gate insulating layer 402 interposed therebetween is formed. It can be substantially the Lov region.

3 includes an insulating layer 406 and an insulating layer 407 provided over the sidewall layer 412a, the sidewall layer 412b, and the gate electrode layer 401, and a wiring layer 435a and a wiring layer provided over the insulating layer 407. 435b may be included in the component. The wiring layer 435a is electrically connected to the source electrode layer 405a through openings provided in the insulating layer 406, the insulating layer 407, and the gate insulating layer 402, and the wiring layer 435b includes the insulating layer 406, the insulating layer 407, and It is electrically connected to the drain electrode layer 405b through an opening provided in the gate insulating layer 402.

In the case where the transistor 420 is not provided with a sidewall layer containing a conductive material, precise alignment between the thin oxide semiconductor layer and the thin gate electrode layer is required to form the Lov region. With the miniaturization of transistors, the required accuracy becomes higher. However, since the transistor 420 described in this embodiment includes the sidewall layer 412a and the sidewall layer 412b containing a conductive material on the side surface in the channel length direction of the gate electrode layer 401, the sidewall layer 412a and the sidewall layer 412b; A region where the source electrode layer 405a or the drain electrode layer 405b overlaps can also function as a Lov region. Therefore, the degree of alignment freedom in forming the gate electrode layer 401 can be improved, and the transistor 420 with high yield and suppressed reduction in on-state current can be provided.

The oxide semiconductor layer 403 is the InZrZnO _X film described in Embodiment 1 and is a CAAC-OS film having a crystal part immediately after deposition even when the substrate temperature is room temperature.

FIGS. 4A and 4B are a plan view and a cross-sectional view of a transistor 422 having a structure different from that of the transistor 420 illustrated in FIGS. 3A and 3B. 4A is a plan view of the transistor 422, and FIG. 4B is a cross-sectional view taken along line X2-Y2 in FIG. 4A. Note that in FIG. 4A, some components (eg, the insulating layer 407) of the transistor 422 are omitted in order to avoid complexity.

A difference between the transistor 422 illustrated in FIGS. 4A and 4B and the transistor 420 illustrated in FIGS. 3A and 3B is the shape of the side surface of the oxide semiconductor layer 403. In the transistor 422 illustrated in FIGS. 4A and 4B, the oxide semiconductor layer 403 has a tapered shape on a side surface in contact with the source electrode layer 405a or the drain electrode layer 405b. When the side surface of the oxide semiconductor layer 403 is tapered, the conductive film to be the source electrode layer 405a and the drain electrode layer 405b can be formed with high coverage.

Hereinafter, an example of a manufacturing process of the transistor of this embodiment will be described with reference to FIGS. Note that a manufacturing process of the transistor 422 is described below as an example.

First, the base insulating layer 436 is formed over the substrate 400 having an insulating surface.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance high enough to withstand a later heat treatment step. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a plastic substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate such as a plastic substrate as the substrate 400. With the use of the deposition method described in Embodiment 1, an oxide semiconductor film having a crystal structure can be formed immediately after deposition even when the substrate temperature during deposition is room temperature. The transistor 422 including the oxide semiconductor layer 403 can be formed directly, so that a flexible semiconductor device can be realized.

The base insulating layer 436 is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, a gallium oxide film, or a mixed material thereof. It can be a single layer or a laminated structure selected. Note that the base insulating layer 436 is preferably formed as a single layer or a stacked structure including an oxide insulating film so that the oxide insulating film is in contact with the oxide semiconductor layer 403 to be formed later. Note that the base insulating layer 436 is not necessarily provided.

When the base insulating layer 436 has a region containing oxygen exceeding the stoichiometric composition ratio (hereinafter also referred to as an oxygen-excess region), an oxide semiconductor formed later by excess oxygen contained in the base insulating layer 436 This is preferable because oxygen vacancies in the layer 403 can be filled. In the case where the base insulating layer 436 has a stacked structure, it is preferable that at least a layer in contact with the oxide semiconductor layer 403 have an oxygen-excess region. In order to provide the oxygen-excess region in the base insulating layer 436, for example, the base insulating layer 436 may be formed in an oxygen atmosphere. Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be injected into the base insulating layer 436 after deposition to form an oxygen-excess region. As an oxygen implantation method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Next, an oxide semiconductor layer 413 is formed over the base insulating layer 436 (see FIG. 5A). The thickness of the oxide semiconductor layer 413 is, for example, 3 nm to 30 nm, preferably 5 nm to 20 nm. As the oxide semiconductor layer 413, an InZrZnO _X film is used and is formed under the film formation conditions described in Embodiment 1. The substrate temperature during film formation is from room temperature to 450 ° C. The InZrZnO _X film is a CAAC-OS film immediately after deposition when the substrate temperature is between room temperature and 450 ° C.

The oxide semiconductor layer 413 is a crystalline oxide semiconductor immediately after deposition because an InZrZnO _X film is used. In order to further increase the crystallinity, the temperature of the heat treatment performed immediately after film formation is 250 ° C. or higher and 700 ° C. or lower, preferably 400 ° C. or higher, more preferably 500 ° C. or higher, and further preferably 550 ° C. or higher. Note that the heat treatment can also serve as another heat treatment in the manufacturing process.

As a method for forming the oxide semiconductor layer 413, the sputtering method described in Embodiment 1 is used. In addition, the oxide semiconductor layer 413 is formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target, that is, a so-called CP sputtering apparatus (Column Plasma Sputtering system). May be.

When the oxide semiconductor layer 413 is formed, it is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor layer 413 as much as possible. In order to reduce the hydrogen concentration, for example, when film formation is performed using a sputtering method, impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed as an atmospheric gas supplied into the processing chamber of the sputtering apparatus. A high-purity rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate.

In addition, the hydrogen concentration of the formed oxide semiconductor layer 413 can be reduced by introducing a sputtering gas from which hydrogen and moisture are removed while removing residual moisture in the deposition chamber. . In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. The film formation chamber evacuated using a cryopump has a high exhaust capability such as a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as hydrogen molecules and water (H ₂ O). The concentration of impurities contained in the oxide semiconductor layer 413 formed in the film chamber can be reduced.

In addition, forming the oxide semiconductor layer 413 with the substrate 400 kept at a high temperature is also effective in reducing the concentration of impurities that can be contained in the oxide semiconductor layer 413. The temperature for heating the substrate 400 may be 150 ° C. or higher and 450 ° C. or lower.

An oxide semiconductor used for the oxide semiconductor layer 413 includes at least indium (In), zinc (Zn), and zirconium (Zr). In addition, it is preferable to include tin (Sn) as a stabilizer for reducing variation in electric characteristics of the transistor including the oxide semiconductor.

The sputtering gas used for forming the oxide semiconductor layer 413 is preferably a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed.

Prior to the formation of the oxide semiconductor layer 413, planarization treatment may be performed on the deposition surface of the oxide semiconductor layer 413. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, a powdery substance (also referred to as particles or dust) attached to the deposition surface of the oxide semiconductor layer 413 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate depending on the uneven state of the oxide semiconductor layer 413.

The oxide semiconductor layer 413 is preferably subjected to heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) included in the oxide semiconductor layer 413. The heat treatment temperature is set to be 300 ° C. or higher and 700 ° C. or lower or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere.

By this heat treatment, hydrogen which is an n-type impurity can be removed from the oxide semiconductor. For example, the concentration of hydrogen contained in the oxide semiconductor layer 413 after dehydration or dehydrogenation treatment can be 5 × 10 ¹⁹ / cm ³ or less, preferably 5 × 10 ¹⁸ / cm ³ or less.

Note that heat treatment for dehydration or dehydrogenation may be performed at any timing in the manufacturing process of the transistor 422 as long as it is performed after the oxide semiconductor layer 413 is formed. However, in the case where an aluminum oxide film is used as the gate insulating layer 402 or the insulating layer 406, it is preferably performed before the aluminum oxide film is formed. Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatment.

Note that in the case where the base insulating layer 436 containing oxygen is provided as the base insulating layer 436, if heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor layer 413 is processed into an island shape, the base insulating layer 436 is formed. It is preferable because oxygen contained therein can be prevented from being released by heat treatment.

In the heat treatment, it is preferable that water or hydrogen is not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

In addition, after heating the oxide semiconductor layer 413 by heat treatment, a high-purity oxygen gas, a high-purity oxygen dinitride gas, or ultra-dry air ( The moisture content when measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter is 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less). May be. It is preferable that water, hydrogen, or the like be not contained in the oxygen gas or the oxygen dinitride gas. Alternatively, the purity of the oxygen gas or oxygen dinitride gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or oxygen dinitride gas is 1 ppm or less, preferably 0.1 ppm or less). It is preferable to do. By supplying oxygen, which is a main component material of the oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or oxygen dinitride gas, the oxide The semiconductor layer 413 can be highly purified and electrically i-type (intrinsic).

Alternatively, oxygen (at least including any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. Good.

By introducing oxygen into the oxide semiconductor layer subjected to dehydration or dehydrogenation treatment and supplying oxygen into the film, the oxide semiconductor layer is highly purified and electrically i-type (intrinsic). can do. A transistor including an oxide semiconductor layer which is highly purified and electrically i-type (intrinsic) has a suppressed variation in electrical characteristics and is electrically stable.

In the step of introducing oxygen, when oxygen is introduced into the oxide semiconductor layer, the oxygen may be introduced directly into the oxide semiconductor layer or through other films such as a gate insulating layer 402 and an insulating layer 406 which are formed later. The oxide semiconductor layer 403 may be introduced. In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used. However, oxygen is directly introduced into the exposed oxide semiconductor layer 413. In addition to the above method, plasma treatment or the like can also be used.

The timing of oxygen introduction into the oxide semiconductor layer is not particularly limited as long as it is after the formation of the oxide semiconductor layer. In addition, oxygen may be introduced into the oxide semiconductor layer a plurality of times.

Next, the oxide semiconductor layer 413 is processed by a photolithography process, so that the island-shaped oxide semiconductor layer 403 is formed. Here, a mask used for processing the island-shaped oxide semiconductor layer 403 is preferably a mask having a finer pattern by performing slimming treatment on a mask formed by a photolithography method or the like.

As the slimming treatment, for example, an ashing treatment using radical oxygen (oxygen radical) or the like can be applied. However, the slimming process need not be limited to the ashing process as long as the mask formed by a photolithography method or the like can be processed into a finer pattern. In addition, since the channel length (L) of the transistor is determined by the mask formed by the slimming process, a process with good controllability can be applied as the slimming process.

As a result of the slimming treatment, a mask formed by a photolithography method or the like can be miniaturized to a line width of less than the resolution limit of the exposure apparatus, preferably ½ or less, more preferably １ ／ or less. . For example, the line width can be 30 nm to 2000 nm, preferably 50 nm to 350 nm. Thereby, further miniaturization of the transistor can be achieved.

Next, a conductive film 415 to be a source electrode layer and a drain electrode layer (including a wiring formed using the same layer) is formed over the island-shaped oxide semiconductor layer 403 (see FIG. 5B). .

The conductive film 415 is formed using a material that can withstand heat treatment performed later. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing the above-described element as a component Etc. can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is formed on one or both of the lower side or upper side of the metal film such as Al or Cu. It is good also as a structure which laminated | stacked. Alternatively, the conductive film 415 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

Next, polishing (cutting or grinding) is performed on the conductive film 415, and part of the conductive film 415 is removed so that the oxide semiconductor layer 403 is exposed. By the polishing treatment, the conductive film 415 in a region overlapping with the oxide semiconductor layer 403 is removed, so that a conductive film 415a having an opening in the region is formed (see FIG. 5C). As a polishing (cutting or grinding) method, a chemical mechanical polishing (CMP) process can be suitably used. In this embodiment, the conductive film 415 in a region overlapping with the oxide semiconductor layer 403 is removed by CMP treatment.

The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform primary polishing at a low polishing rate after performing primary polishing at a high polishing rate. In this manner, by combining polishing with different polishing rates, planarity of the surfaces of the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor layer 403 can be further improved.

Note that in this embodiment, CMP treatment is used to remove the conductive film 405 in a region overlapping with the oxide semiconductor layer 403; however, other polishing (grinding or cutting) treatment may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where polishing treatment is combined with etching treatment, plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 415.

Note that in this embodiment, the upper end portion of the conductive film 415 a substantially matches the upper end portion of the oxide semiconductor layer 403. Note that the shape of the conductive film 415a (or the source electrode layer 405a and the drain electrode layer 405b formed by processing the conductive film 415a) differs depending on conditions of polishing treatment for removing the conductive film 415. For example, the oxide semiconductor layer 403 may have a shape that recedes from the surface in the film thickness direction.

Next, the conductive film 415a is processed by a photolithography step, so that a source electrode layer 405a and a drain electrode layer 405b (including a wiring formed using the same layer) are formed (see FIG. 5D).

Note that in this embodiment, the conductive film 415 is formed, and the conductive film 415 in the region overlapping with the oxide semiconductor layer 403 is removed by polishing treatment, and then selectively etched to be the source electrode layer 405a and the drain. Although the method of processing into the electrode layer 405b has been shown, the embodiment of the present invention is not limited to this. After the deposited conductive film 415 is selectively etched and processed, the conductive film 415 in a region overlapping with the oxide semiconductor layer 403 is removed by polishing, so that the source electrode layer 405a and the drain electrode layer 405b are removed. May be formed. However, in the case where the etching process is performed prior to the polishing process, the conductive film 415 in the region overlapping with the oxide semiconductor layer 403 is not removed by the etching process.

In the method for manufacturing the transistor described in this embodiment, a resist mask is used in the step of removing the conductive film 415 in a region overlapping with the oxide semiconductor layer 403 when the source electrode layer 405a and the drain electrode layer 405b are formed. Therefore, precise processing can be performed accurately even when the width of the source electrode layer 405a and the drain electrode layer 405b in the channel length direction is miniaturized. Thus, in the manufacturing process of the semiconductor device, the transistor 420 having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

Further, by removing the conductive film 415 in a region overlapping with the oxide semiconductor layer 403, the oxide semiconductor layer 403 and the source electrode layer 405a or the drain electrode layer 405b can be formed in the channel length direction of the oxide semiconductor layer 403. It becomes possible to make it the structure which touches in a side surface. Since the thickness of the oxide semiconductor layer 403 is as small as 3 nm to 30 nm, preferably 5 nm to 20 nm, the oxide semiconductor layer 403 is in contact with the source electrode layer 405a or the drain electrode layer 405b on its side surface, so that the oxide semiconductor layer 403 can be connected to the source electrode layer 405a or the drain electrode layer 405b. The contact area can be reduced, and the contact resistance at the contact interface can be increased. Therefore, even when the channel length (L) of the transistor 422 is shortened, the electric field between the source electrode layer 405a and the drain electrode layer 405b can be reduced, and a short channel effect such as variation in threshold voltage can be suppressed. .

Next, the gate insulating layer 402 is formed over the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b.

The gate insulating layer 402 has a thickness of 1 nm to 20 nm and can be formed using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate. Alternatively, the gate insulating layer 402 may be formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target, a so-called CP sputtering apparatus.

Note that as the gate insulating layer 402 is thicker, the short channel effect becomes more prominent, and the threshold voltage tends to easily shift to the negative side. However, in the method for manufacturing the transistor of this embodiment, the top surfaces of the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor layer 403 are planarized by polishing treatment; Can be formed with good coverage.

As a material of the gate insulating layer 402, silicon oxide, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, silicon nitride oxide, or the like can be used. The gate insulating layer 402 preferably contains oxygen in a portion in contact with the oxide semiconductor layer 403. In particular, the gate insulating layer 402 preferably includes oxygen in the film (in the bulk) at least in an amount exceeding the stoichiometric composition ratio. For example, when a silicon oxide film is used as the gate insulating layer 402, , SiO _{2 + α} (where α> 0). In this embodiment, a silicon oxide film with SiO _{2 + α} (where α> 0) is used as the gate insulating layer 402. By using this silicon oxide film as the gate insulating layer 402, oxygen can be supplied to the oxide semiconductor layer 403, whereby characteristics can be improved. Further, the gate insulating layer 402 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage of the gate insulating layer 402.

Further, as a material of the gate insulating layer 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0, The gate leakage current can be reduced by using a high-k material such as y> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), or lanthanum oxide. Further, the gate insulating layer 402 may have a single-layer structure or a stacked structure.

Next, the gate electrode layer 401 is formed over the island-shaped oxide semiconductor layer 403 with the gate insulating layer 402 interposed therebetween (see FIG. 6A). The gate electrode layer 401 can be formed by a plasma CVD method, a sputtering method, or the like. The material of the gate electrode layer 401 is a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above element as a component ( A titanium nitride film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

The material of the gate electrode layer 401 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium A conductive material such as zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Further, as one layer of the gate electrode layer 401 in contact with the gate insulating layer 402, a metal oxide containing nitrogen, specifically, an IGZO film containing nitrogen, an In—Sn—O film containing nitrogen, or In containing nitrogen. A -Ga-O film, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. . These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

Note that the gate electrode layer 401 can be formed by processing a conductive film (not illustrated) provided over the gate insulating layer 402 using a mask. Here, the mask used for processing is preferably a mask having a finer pattern by performing slimming treatment on a mask formed by a photolithography method or the like.

Next, a film containing a conductive material is formed over the gate electrode layer 401 and the gate insulating layer 402, and the film containing the conductive material is etched to form sidewall layers 412a and 412b (FIG. 6B). )reference).

The sidewall layer 412a and the sidewall layer 412b only have to be conductive, and are formed by processing a metal film such as tungsten or titanium, or a silicon film containing an impurity element such as phosphorus or boron, for example. Can do. Alternatively, after a polycrystalline silicon film is formed over the gate electrode layer 401 and the gate insulating layer 402 and a sidewall layer in contact with the gate electrode layer 401 is formed by etching, an impurity element such as phosphorus or boron is doped into the sidewall layer. After the introduction, the heat treatment for activation may be performed to form the sidewall layer 412a and the sidewall layer 412b having conductivity.

Next, the insulating layer 406 and the insulating layer 407 are formed over the gate insulating layer 402, the gate electrode layer 401, the sidewall layer 412a, and the sidewall layer 412b.

The insulating layer 406 or the insulating layer 407 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like. As the insulating layer 406 or the insulating layer 407, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be typically used.

As the insulating layer 406 or the insulating layer 407, an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, or a barium oxide film) or a metal nitride film (eg, an aluminum nitride film) is also used. be able to.

As the insulating layer 406 or the insulating layer 407, an aluminum oxide film is preferably provided. An aluminum oxide film has a high blocking effect (blocking effect) of preventing both hydrogen and moisture impurities and oxygen from passing through the film, and impurities such as hydrogen and moisture that cause fluctuations during and after the manufacturing process. It can be preferably applied because it functions as a protective film for preventing entry of oxygen into the oxide semiconductor layer 403 and release of oxygen, which is a main component material of the oxide semiconductor, from the oxide semiconductor layer 403.

The insulating layer 407 is preferably formed using a method by which an impurity such as water or hydrogen is not mixed into the insulating layer 407 as appropriate, such as a sputtering method.

In the same manner as in the formation of the oxide semiconductor layer 403, an adsorption-type vacuum pump (such as a cryopump) is preferably used in order to remove residual moisture in the deposition chamber of the insulating layer 406 or the insulating layer 407. The concentration of impurities contained in the insulating layer 406 or the insulating layer 407 formed in the deposition chamber evacuated using a cryopump can be reduced. Further, as an exhaustion unit for removing moisture remaining in the deposition chamber of the insulating layer 406 or the insulating layer 407, a turbo molecular pump provided with a cold trap may be used.

In this embodiment, an aluminum oxide film is formed as the insulating layer 406 from the side in contact with the gate electrode layer 401, and a silicon oxide film is used as the insulating layer 407. Note that when the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 420. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray reflectance measurement (XRR: X-Ray Reflection).

Note that in the case where an aluminum oxide film is formed as the insulating layer 406, heat treatment is preferably performed after the aluminum oxide film is formed. The aluminum oxide film has a function of preventing water (including hydrogen) from entering the oxide semiconductor layer and a function of preventing release of oxygen from the oxide semiconductor layer. Therefore, when the oxide semiconductor layer 403 and / or the insulating layer in contact with the oxide semiconductor layer 403 has an oxygen-excess region, heat treatment is performed in a state where the aluminum oxide film is provided, so that the oxide semiconductor layer in the oxide semiconductor layer (in the bulk) Alternatively, at an interface between the insulating layer and the oxide semiconductor layer, at least one region where oxygen exceeding the stoichiometric ratio of the film exists (also referred to as an oxygen-excess region) can be provided.

Next, openings reaching the source electrode layer 405a or the drain electrode layer 405b are formed in the insulating layer 407, the insulating layer 406, and the gate insulating layer 402, and a wiring layer 435a and a wiring layer 435b are formed in the openings (FIG. 6C). reference). Various circuits can be formed by connecting the wiring layer 435a and the wiring layer 435b to other transistors and elements.

The wiring layer 435a and the wiring layer 435b can be formed using a material and a method similar to those of the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b, for example, Al, Cr, Cu, Ta, Ti, A metal film containing an element selected from Mo and W, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing the above-described element as a component can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. Further, the conductive film used for the wiring layer 435a and the wiring layer 435b may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (In ₂ O ₃ —ZnO). Alternatively, a material in which silicon oxide is included in these metal oxide materials can be used.

For example, as the wiring layer 435a and the wiring layer 435b, a single layer of a molybdenum film, a stack of a tantalum nitride film and a copper film, a stack of a tantalum nitride film and a tungsten film, or the like can be used.

Through the above process, the transistor 422 of this embodiment is formed.

Note that by making the length of the island-shaped oxide semiconductor layer 403 in the channel length direction longer than the length of the gate electrode layer 401 in the channel length direction, the degree of freedom in alignment is increased in order to form the gate electrode layer 401. It can be improved further. In this case, an impurity region may be provided in the oxide semiconductor layer 403 in order to reduce the channel length of the transistor.

For example, in the transistor 424 illustrated in FIGS. 7A and 7B and the transistor 426 illustrated in FIGS. 8A and 8B, after the gate electrode layer 401 is formed, the gate electrode layer 401 is masked. In this example, impurities are introduced into the oxide semiconductor layer 403 to form the impurity regions 403a and 403b in a self-aligning manner.

The transistor 424 has a structure similar to that of the transistor 420, and the oxide semiconductor layer 403 included in the transistor 424 is sandwiched between a pair of impurity regions containing impurities (an impurity region 403a and an impurity region 403b) and a pair of impurity regions. The transistor 420 is different from the transistor 420 in that the channel formation region 403c is provided. A transistor 426 illustrated in FIGS. 8A and 8B has a structure similar to that of the transistor 422, and the oxide semiconductor layer 403 included in the transistor 426 includes a pair of impurity regions (impurities) containing a dopant. The transistor 422 is different from the transistor 422 in that it includes a region 403a and an impurity region 403b) and a channel formation region 403c sandwiched between a pair of impurity regions. Note that FIG. 7A is a plan view of the transistor 424, and FIG. 7B is a cross-sectional view taken along line X3-Y3 in FIG. 8A is a plan view of the transistor 426, and FIG. 8B is a cross-sectional view taken along line X4-Y4 in FIG. 8A.

The dopant is an impurity that changes the conductivity of the oxide semiconductor layer 403. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

With the oxide semiconductor layer including a pair of impurity regions with the channel formation region 403c interposed in the channel length direction, the transistors 424 and 426 have high on-characteristics (eg, on-state current and field-effect mobility), high-speed operation, A transistor capable of high-speed response can be obtained.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a semiconductor device using the transistor described in this specification, capable of holding stored data even when power is not supplied, and having no limit on the number of writing times will be described with reference to drawings. To do.

FIG. 9 illustrates an example of a structure of a semiconductor device. 9A is a cross-sectional view of the semiconductor device, FIG. 9B is a plan view of the semiconductor device, and FIG. 9C is a circuit diagram of the semiconductor device. Here, FIG. 9A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG. 9B.

The semiconductor device illustrated in FIGS. 9A and 9B includes a transistor 160 using a first semiconductor material in a lower portion, a second semiconductor material in an upper portion, and in this embodiment mode, this embodiment mode. The transistor 162 including the InZrZnO _X film described in Embodiment 1 is provided. The transistor 162 is an example to which the structure of the transistor 420 described in Embodiment 2 is applied.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition to using the transistor as described in Embodiment 2 using an oxide semiconductor to hold information as the transistor 162, a specific structure of the semiconductor device such as a material used in the semiconductor device and a structure of the semiconductor device Need not be limited to those shown here.

A transistor 160 in FIG. 9A includes a channel formation region 116 provided in a substrate 100 containing a semiconductor material (eg, silicon), an impurity region 120 provided so as to sandwich the channel formation region 116, and an impurity region. The gate electrode layer 110 includes a metal compound region 124 in contact with 120, a gate insulating layer 108 provided over the channel formation region 116, and a gate electrode layer 110 provided over the gate insulating layer 108. Note that in the drawing, the source electrode layer and the drain electrode layer may not be explicitly provided, but for convenience, the transistor may be referred to as a transistor including such a state. In this case, in order to describe a connection relation of the transistors, the source electrode layer and the drain electrode layer may be expressed including the source region and the drain region. That is, in this specification, the term “source electrode layer” can include a source region.

An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are provided so as to cover the transistor 160. Note that in the transistor 160, a sidewall insulating layer (sidewall insulating layer) may be provided on a side surface of the gate electrode layer 110 so that the impurity region 120 includes regions having different impurity concentrations.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. In this embodiment, two insulating films are formed so as to cover the transistor 160. However, the insulating film may be a single layer or a stack of three or more layers. As a process before the formation of the transistor 162 and the capacitor 164, the insulating film formed over the transistor 160 is subjected to CMP to form the planarized insulating layer 128 and the insulating layer 130, and at the same time, the top surface of the gate electrode layer 110. To expose.

The insulating layer 128 and the insulating layer 130 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like. An inorganic insulating film can be used. The insulating layer 128 and the insulating layer 130 can be formed by a plasma CVD method, a sputtering method, or the like.

Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case of using an organic material, the insulating layer 128 and the insulating layer 130 may be formed by a wet method such as a spin coating method or a printing method.

Note that in this embodiment, a silicon nitride film is used as the insulating film, and a silicon oxide film is used as the insulating layer 130.

Planarization treatment is preferably performed on the formation region of the oxide semiconductor layer 144 on the surface of the insulating layer 130. In this embodiment, the oxide semiconductor layer 144 is formed over the insulating layer 130 which is sufficiently planarized by polishing treatment (eg, CMP treatment) (preferably the average surface roughness of the surface of the insulating layer 130 is 0.15 nm or less). .

A transistor 162 illustrated in FIG. 9A is a transistor in which an InZrZnO _X film is used for an oxide semiconductor layer having a channel formation region. Here, the oxide semiconductor layer 144 included in the transistor 162 is preferably highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

The transistor 162 includes an oxide semiconductor layer 144 in contact with the electrode layer 142a or the electrode layer 142b on the side surface in the channel length direction. Therefore, the resistance of the region where the oxide semiconductor layer 144 is in contact with the electrode layer 142a or the electrode layer 142b can be increased, so that the electric field between the source and the drain can be reduced. Therefore, the short channel effect accompanying the reduction in transistor size can be suppressed.

In addition, the transistor 162 includes sidewall layers 137a and 137b including a conductive material on a side surface in the channel length direction of the gate electrode layer 148, so that the sidewall layers 137a and 137b including the conductive material are interposed through the gate insulating layer 146. Since the transistor overlaps with the electrode layer 142a or the electrode layer 142b, the transistor can substantially have a Lov region, and a decrease in on-state current of the transistor 162 can be suppressed.

Over the transistor 162, the insulating layer 132, the interlayer insulating film 135, and the insulating layer 150 are provided as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating layer 132 and the insulating layer 150. When the aluminum oxide film has a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

In addition, a conductive layer 153 is provided in a region overlapping with the electrode layer 142a of the transistor 162 with the gate insulating layer 146 provided therebetween, and the electrode layer 142a, the gate insulating layer 146, and the conductive layer 153 provide capacitance. Element 164 is configured. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 164 and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

In this embodiment, the conductive layer 153 can be formed in the same manufacturing process as the gate electrode layer 148 of the transistor 162. Note that in the step of forming the sidewall layer 137a and the sidewall layer 137b on the side surface of the gate electrode layer 148, a sidewall layer may be provided on the side surface of the conductive layer as well.

Over the insulating layer 150, the transistor 162 and a wiring 156 for connecting another transistor are provided. The wiring 156 is electrically connected to the electrode layer 142b through an electrode layer 136 formed in an opening formed in the insulating layer 150, the interlayer insulating film 135, the insulating layer 132, the gate insulating layer 146, and the like.

9A and 9B, the transistor 160 and the transistor 162 are provided so that at least part of them overlap with each other, and the source region or the drain region of the transistor 160 and the oxide semiconductor layer 144 are overlapped with each other. It is preferable that a part is provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided so as to overlap at least partly with the gate electrode layer 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Note that the electrical connection between the electrode layer 142b and the wiring 156 may be performed by directly contacting the electrode layer 142b and the wiring 156 without providing the electrode layer 136. Moreover, a plurality of intervening electrode layers may be provided.

Next, an example of a circuit configuration corresponding to FIGS. 9A and 9B is illustrated in FIG.

In FIG. 9C, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode layer of the transistor 160 are electrically connected. Connected. In addition, the third wiring (3rd Line) and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode layer of the transistor 162 are connected. Are electrically connected. One of a gate electrode layer of the transistor 160 and a source electrode layer or a drain electrode layer of the transistor 162 is electrically connected to the other electrode of the capacitor 164, and a fifth wiring (5th Line) and a capacitor The other of the 164 electrodes is electrically connected.

In the semiconductor device illustrated in FIG. 9C, by using the feature that the potential of the gate electrode layer of the transistor 160 can be held, information can be written, held, and read as follows.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, predetermined charge is supplied to the gate electrode layer of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off and the transistor 162 is turned off, whereby the charge given to the gate electrode layer of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode layer of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, according to the amount of charge held in the gate electrode layer of the transistor 160, The second wiring takes different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold value V _{th_H in the} case where a high-level charge is applied to the gate electrode layer of the transistor 160 is a low-level charge applied to the gate electrode layer of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L in the} case of Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode layer of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned off regardless of the state of the gate electrode layer, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively} , a potential that turns on the transistor 160 regardless of the state of the gate electrode layer, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current using an InZrZnO _X film for an oxide semiconductor layer having a channel formation region. is there. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a semiconductor device which uses the transistor described in Embodiment 2 and can hold stored data even when power is not supplied and has no limit on the number of writing operations is described in Embodiment 3. A structure different from the illustrated structure will be described with reference to FIGS.

FIG. 10A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 10B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 10A is described, and then the semiconductor device illustrated in FIG. 10B is described below.

In the semiconductor device illustrated in FIG. 10A, the bit line BL and the source or drain electrode layer of the transistor 162 are electrically connected, and the word line WL and the gate electrode layer of the transistor 162 are electrically connected. The source or drain electrode layer of the transistor 162 and the first terminal of the capacitor 254 are electrically connected.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

The transistor 162 using an InZrZnO _X film for an oxide semiconductor layer having a channel formation region has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. It can be seen that (= CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the bit line BL when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 10A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 10B is described.

The semiconductor device illustrated in FIG. 10B includes memory cell arrays 251a and 251b each including a plurality of memory cells 250 illustrated in FIG. 10A as memory circuits in the upper portion, and memory cell arrays (memory cell arrays 251a and 251b in the lower portion. The peripheral circuit 253 necessary for operating the device is operated. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 10B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (memory cell arrays 251a and 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

Note that in the semiconductor device illustrated in FIG. 10B, a structure in which two memory cell arrays 251 (a memory cell array 251a and a memory cell array 251b) are stacked is illustrated; however, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of the memory cell 250 illustrated in FIG. 10A will be described with reference to FIGS.

FIG. 11 shows an example of the configuration of the memory cell 250. FIG. 11A is a cross-sectional view of the memory cell 250, and FIG. 11B is a plan view of the memory cell 250. Here, FIG. 11A corresponds to a cross section taken along lines F1-F2 and G1-G2 in FIG.

The transistor 162 illustrated in FIGS. 11A and 11B can have the same structure as the structure described in Embodiment 2.

A conductive layer 262 is provided in a region overlapping with the electrode layer 142 a of the transistor 162 with the gate insulating layer 146 provided therebetween. The capacitor 254 includes the electrode layer 142 a, the gate insulating layer 146, and the conductive layer 262. Is configured. That is, the electrode layer 142 a of the transistor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 functions as the other electrode of the capacitor 254.

Over the transistor 162 and the capacitor 254, the insulating layer 132, the interlayer insulating film 135, and the insulating layer 256 are provided as a single layer or a stacked layer. On the insulating layer 256, a memory cell 250 and a wiring 260 for connecting the adjacent memory cell 250 are provided. The wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 through an opening formed in the insulating layer 256, the interlayer insulating film 135, the insulating layer 132, the gate insulating layer 146, and the like. However, the wiring 260 and the electrode layer 142b may be directly connected. Note that the wiring 260 corresponds to the bit line BL in the circuit diagram of FIG.

In FIGS. 11A and 11B, the electrode layer 142b of the transistor 162 can also function as a source electrode layer of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

By employing the planar layout shown in FIG. 11A, the area occupied by the semiconductor device can be reduced, so that high integration can be achieved.

As described above, the plurality of memory cells formed in multiple layers is formed using a transistor in which an InZrZnO _X film is used for an oxide semiconductor layer having a channel formation region. A transistor in which an InZrZnO _X film is used for an oxide semiconductor layer having a channel formation region has low off-state current; thus, by using this transistor, stored data can be held for a long time. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

In this manner, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and an InZrZnO _X film for an oxide semiconductor layer having a channel formation region are used. By integrally including a memory circuit using a transistor (a transistor with a sufficiently small off-state current in a broader sense), a semiconductor device having characteristics that have never existed can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example in which the semiconductor device described in any of Embodiments 3 and 4 is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS. .

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In a normal SRAM, as shown in FIG. 12A, one memory cell is composed of six transistors 801 to 806, which are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 form an inverter and can be driven at high speed. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is normally 100 to 150 F ² . For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 12B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. The memory cell area of a DRAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 13 shows a block diagram of a portable device. 13 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. A sensor 919, an audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 909. In general, the memory circuit 912 is configured by SRAM or DRAM, and by adopting the semiconductor device described in Embodiment 3 or 4 in this portion, writing and reading of information is performed at high speed and long-term storage is performed. Holding is possible, and power consumption can be sufficiently reduced.

FIG. 14 shows an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 14 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit reads a signal line from image data (input image data), a memory 952, and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and is stored in the display 957 via the switch 955 and the display controller 956. The stored image data B is sent and displayed. This reading is continued until new image data is stored in the memory 952 next time.

As described above, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 952 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in Embodiment 3 or 4 for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently high. Can be reduced.

FIG. 15 is a block diagram of an electronic book. 15 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in Embodiment 3 or 4 can be used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 has a function of temporarily holding the contents of a book. An example of a function is when a user uses a highlight function. When a user is reading an electronic book, the user may want to mark a specific part. This marking function is called a highlight function, and is to show the difference from the surroundings by changing the display color, underlining, making the character thicker, or changing the font of the character. This is a function for storing and holding information on a location designated by the user. When this information is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by using the semiconductor device described in Embodiment 3 or 4, information writing and reading can be performed at high speed, long-term storage can be performed, and power consumption is sufficient. Can be reduced.

As described above, the portable device described in this embodiment includes the semiconductor device according to Embodiment 3 or Embodiment 4. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

100 substrate 106 element isolation insulating layer 108 gate insulating layer 110 gate electrode layer 116 channel formation region 120 impurity region 124 metal compound region 128 insulating layer 130 insulating layer 132 insulating layer 135 interlayer insulating film 136 electrode layer 137a side wall layer 137b side wall layer 142a electrode Layer 142b electrode layer 144 oxide semiconductor layer 146 gate insulating layer 148 gate electrode layer 150 insulating layer 153 conductive layer 156 wiring 160 transistor 162 transistor 164 capacitor 250 memory cell 251 memory cell array 251a memory cell array 251b memory cell array 253 peripheral circuit 254 capacitor 256 Insulating layer 260 Wiring 262 Conductive layer 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 403a Impurity region 403b Impurity region 403 c channel formation region 405 conductive film 405a source electrode layer 405b drain electrode layer 406 insulating layer 407 insulating layer 412a sidewall layer 412b sidewall layer 413 oxide semiconductor layer 415 conductive film 415a conductive film 420 transistor 422 transistor 424 transistor 426 transistor 435a wiring layer 435b Wiring layer 436 Base insulating layer 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X decoder 808 Y decoder 811 Transistor 812 Storage capacitor 813 X decoder 814 Y decoder 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply Circuit 906 Application processor 907 CPU
908 DSP
909 Interface 910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash memory 1005 Audio circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller

Claims (2)

An oxide semiconductor layer containing indium, zirconium, and zinc;
A gate insulating layer in contact with the oxide semiconductor layer;
Have a said oxide semiconductor layer overlapping with the gate electrode layer through the gate insulating layer,
The semiconductor device, wherein the oxide semiconductor layer has a crystal oriented such that a c-axis is along a direction perpendicular to the surface. In claim 1,
The semiconductor device, wherein the oxide semiconductor layer has a crystal oriented so that the c-axis is perpendicular to the surface immediately after film formation.