KR102255584B1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a transistor having high electrical characteristics even in the case of a fine structure.
A transistor comprising a source electrode layer in contact with one side of the oxide semiconductor layer in the channel length direction and a drain electrode layer in contact with the other. In addition, a gate electrode layer is provided in a region overlapping the channel formation region through the gate insulating layer, and a portion of the gate electrode layer is in contact with the side surface of the gate electrode layer in a region overlapping the source electrode layer or the drain electrode layer through the gate insulating layer. By setting it as the structure which has a conductive layer functioning as a Lov region, maintaining a fine channel length. The conductive layer formed to be in contact with the side surface of the gate electrode layer is formed by forming a conductive film and an insulating layer covering the gate electrode layer, then processing the insulating layer to form a sidewall insulating layer, and processing the conductive film using the sidewall insulating layer as a mask. . Accordingly, a fine conductive layer can be formed in a self-aligning manner so as to contact the side surface of the gate electrode layer.

Description

A semiconductor device and a manufacturing method of a semiconductor device TECHNICAL FIELD [SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

In addition, in this specification and the like, the term "semiconductor device" refers to all devices that can function by using semiconductor properties, and all of the electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are semiconductor devices.

The technology of constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely applied to semiconductor electronic devices such as integrated circuits (ICs) and image display devices (referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for fabricating a transistor using zinc oxide or an In-Ga-Zn-based oxide as an oxide semiconductor and using a switching element of a pixel of a display device and the like is described in Patent Document 1 and Patent Document 2.

Japanese Published Patent Application No. 2007-123861 Japanese Published Patent Application No. 2007-96055

In order to achieve high-speed transistor operation, low power consumption, and high integration, miniaturization of transistors is essential.

In order to realize a high-speed response and high-speed driving of a semiconductor device, it is desirable to improve the on-state characteristics (for example, on-state current and field effect mobility) of a microscopic transistor. In order to suppress the decrease in the on-state current of the transistor, it is effective to provide a region in which the gate electrode layer overlaps the source electrode layer or the drain electrode layer (hereinafter, also referred to as the Lov region) through the gate insulating layer. Do.

However, in order to form the Lov region, precise alignment between an oxide semiconductor layer having a thin line width and a gate electrode layer having a thin line width is required, and as the transistor becomes finer, the required accuracy becomes higher. Therefore, there is a concern that the yield in the fabrication process may decrease as the transistor is miniaturized.

Accordingly, an object of one embodiment of the present invention is to provide a semiconductor device that achieves miniaturization while maintaining good characteristics.

Another object of one embodiment of the present invention is to provide a transistor having high electrical characteristics even in a fine structure with high yield.

In one embodiment of the present invention, in a transistor having an oxide semiconductor layer including a channel formation region and a pair of impurity regions through the channel formation region, a source electrode layer in contact with one side of a side surface of the oxide semiconductor layer in a channel length direction , To form a drain electrode layer in contact with the other side. In addition, the gate electrode layer has a gate electrode layer in a region overlapping the channel formation region through the gate insulating layer, and a gate electrode layer in a region overlapping the source electrode layer or the drain electrode layer through the gate insulating layer so as to contact the side surface of the gate electrode layer in the channel length direction. By having a configuration having a conductive layer that functions as a part of the electrode layer, a Lov region is formed while maintaining a fine channel length. The conductive layer formed in contact with the side surface of the gate electrode layer in the channel length direction is formed by forming a conductive film and an insulating layer covering the gate electrode layer, then processing the insulating layer to form a sidewall insulating layer, and processing the conductive film using the sidewall insulating layer as a mask. Is formed. Accordingly, a fine conductive layer can be formed in a self-aligning manner in contact with the side surface of the gate electrode layer. More specifically, it can be set as the following structure, for example.

One aspect of the present invention includes a source electrode layer and a drain electrode layer, a first impurity region, a second impurity region, and a channel formation region interposed between the first impurity region and the second impurity region, and the channel length of the first impurity region An oxide semiconductor layer in contact with the source electrode layer in the side of the direction and in contact with the drain electrode layer in the side of the channel length direction of the second impurity region, the gate insulating layer in contact with the upper surfaces of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate insulating layer. A gate electrode layer interposed therebetween, a gate electrode layer overlapping the channel formation region, a conductive layer in contact with the side surface of the gate electrode layer and at least partially overlapping the source electrode layer and the drain electrode layer through the gate insulating layer in the channel length direction, and the conductive layer facing the gate electrode layer A semiconductor device having a sidewall insulating layer formed on a side surface thereof, and the side end portion of the conductive layer coincides with the side end portion of the sidewall insulating layer.

In the above semiconductor device, the thickness of the gate insulating layer in the region overlapping the gate electrode layer may be larger than the thickness of the gate insulating layer in the region overlapping the conductive layer.

Further, in the above semiconductor device, the thickness of the gate insulating layer in the region overlapping the conductive layer may be thicker than the thickness of the gate insulating layer in the region not overlapping with the conductive layer and not overlapping with the gate electrode layer.

In another aspect of the present invention, a source electrode layer and a drain electrode layer are formed, an oxide semiconductor layer covering the source electrode layer and the drain electrode layer is formed, and the oxide semiconductor layer in the region overlapping the source electrode layer and the drain electrode layer is chemically mechanically connected. It is removed by magic to form an oxide semiconductor layer having an opening, and the oxide semiconductor layer having an opening is processed to form an island-shaped oxide semiconductor layer disposed between the source electrode layer and the drain electrode layer, and the oxide semiconductor layer, the source electrode layer, and the drain electrode layer A gate insulating layer is formed thereon, a gate electrode layer overlapping with the oxide semiconductor layer is formed through the gate insulating layer, impurities are introduced into the oxide semiconductor layer using the gate electrode layer as a mask, and self-aligned removal of the oxide semiconductor layer is performed. 1 impurity region and second impurity region are formed, a conductive film is formed on the gate insulating layer and the gate electrode layer, an insulating layer is formed on the conductive film, and the insulating layer is processed to insulate the sidewalls in contact with the side surfaces of the gate electrode layer through the conductive film. This is a method of manufacturing a semiconductor device in which a layer is formed and a conductive film is etched using the sidewall insulating layer as a mask to form a conductive layer in contact with the side surface of the gate electrode layer.

In another aspect of the present invention, an island-shaped oxide semiconductor layer is formed, a first conductive film covering the oxide semiconductor layer is formed, and the first conductive film overlapping the oxide semiconductor layer is removed by a chemical mechanical polishing method. A first conductive film having an opening is formed, a source electrode layer and a drain electrode layer are formed by processing the first conductive film having an opening, a gate insulating layer is formed on the oxide semiconductor layer, the source electrode layer and the drain electrode layer, and the gate insulating layer is interposed therebetween. Forming a gate electrode layer overlapping with the oxide semiconductor layer, introducing impurities into the oxide semiconductor layer using the gate electrode layer as a mask, forming a first impurity region and a second impurity region in self-alignment in the oxide semiconductor layer, and gate insulation A second conductive film is formed on the layer and the gate electrode layer, an insulating layer is formed on the second conductive film, the insulating layer is processed to form a sidewall insulating layer in contact with the side surface of the gate electrode layer through the second conductive film, and the sidewall insulating layer This is a method of manufacturing a semiconductor device in which a conductive layer in contact with a side surface of a gate electrode layer is formed by etching the second conductive film using as a mask.

In addition, in this specification and the like, "match" includes things that are substantially coincident. For example, it is assumed that the end surface of the layer A and the end surface of the layer B of the layered structure etched by using the same mask coincide.

Further, the oxide semiconductor has a state such as single crystal, polycrystalline (also referred to as polycrystal), or amorphous (also referred to as amorphous).

Since an amorphous oxide semiconductor can obtain a relatively flat surface, a transistor using this can reduce the interfacial scattering of carriers (electrons) during operation, and relatively easily obtain a relatively high field effect mobility. I can.

In addition, in the case of the oxide semiconductor having crystallinity, defects in the bulk can be further reduced, and when the flatness of the surface is increased, the transistor using the oxide semiconductor having the crystallinity has a field effect mobility higher than that of the transistor using the amorphous oxide semiconductor. You can get it. In order to increase the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface, and specifically, the average surface roughness (Ra) may be formed on a surface of 0.15 nm or less, preferably 0.1 nm or less.

In addition, Ra is a three-dimensional extension so that the arithmetic mean roughness defined in JIS B 0601:2001 (ISO4287:1997) can be applied to a curved surface, and'a value obtained by averaging the absolute value of the deviation from the reference surface to the specified surface. It can be expressed as', and is defined by the following equation.

[Equation 1]

Here, the designated surface refers to the surface to be subjected to roughness measurement, and coordinates [x ₁ , y ₁ , f(x ₁ , y ₁ )][x ₁ , y ₂ , f(x ₁ , y ₂ )][x ₂ , y ₁ , f(x ₂ , y ₁ )][x ₂ , y ₂ , f(x ₂ , y ₂ )] as a rectangular area connected by 4 points, and projecting the specified plane onto the xy plane The area of is S ₀ , and the height of the reference plane (the average height of the designated plane) is Z ₀ . Ra can be measured by an atomic force microscope (AFM).

In the semiconductor device of one embodiment of the present invention, after forming an impurity region in the oxide semiconductor layer in a self-alignment manner using the gate electrode layer as a mask, it contacts the side surface of the gate electrode layer in the channel length direction and overlaps the source electrode layer and the drain electrode layer. Forming a conductive layer. Accordingly, the Lov region can be formed while maintaining a fine channel length, thereby providing a transistor having a fine structure in which a decrease in on current is suppressed.

In addition, the conductive layer functioning as a part of the gate electrode layer is formed by self-aligning processing the insulating layer formed on the gate electrode layer through the conductive film into a sidewall insulating layer, and then etching the conductive film using the sidewall insulating layer as a mask. However, since an etching process using a resist mask is not used, precise processing can be performed accurately. Therefore, in the manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

Therefore, according to one embodiment of the present invention, it is possible to provide a semiconductor device that achieves miniaturization while maintaining good characteristics.

1A is a plan view showing an embodiment of a semiconductor device, and FIG. 1B is a cross-sectional view.
2A is a plan view showing an embodiment of a semiconductor device, and FIG. 2B is a cross-sectional view.
3A to 3D are diagrams showing an example of a method of manufacturing a semiconductor device.
4A to 4D are diagrams showing an example of a method of manufacturing a semiconductor device.
5A is a plan view showing an embodiment of a semiconductor device, and FIG. 5B is a cross-sectional view.
6A to 6D are diagrams showing an example of a method of manufacturing a semiconductor device.
7A to 7C are cross-sectional views illustrating an embodiment of a semiconductor device.
8A is a cross-sectional view showing an embodiment of a semiconductor device, FIG. 8B is a plan view, and FIG. 8C is a circuit diagram.
9A is a circuit diagram showing an embodiment of a semiconductor device, and FIG. 9B is a perspective view.
10A is a cross-sectional view illustrating an embodiment of a semiconductor device, and FIG. 10B is a plan view.
11A and 11B are circuit diagrams showing an embodiment of a semiconductor device.
12 is a block diagram showing an embodiment of a semiconductor device.
13 is a block diagram showing an embodiment of a semiconductor device.
14 is a block diagram showing an embodiment of a semiconductor device.
15 is a cross-sectional STEM photograph of an example sample.

An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that the form and detailed contents can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the following embodiments.

In addition, in the configuration of the present invention described below, the same reference numerals are used in common among different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted. In addition, in the case of indicating a portion having the same function, the hatch pattern is made the same, and there is a case where no reference numeral is given in particular.

In addition, in this specification and the like, ordinal numbers attached as first, second, etc. are used for convenience, and do not indicate a process order or a lamination order. In addition, in this specification and the like, it does not indicate a unique name as a matter for specifying the invention.

(Embodiment 1)

In this embodiment, a semiconductor device and an embodiment of a method for manufacturing a semiconductor device will be described with reference to FIGS. 1A to 4D.

1A and 1B are plan views and cross-sectional views of a transistor 420 as an example of a semiconductor device. 1A is a plan view of the transistor 420, and FIG. 1B is a cross-sectional view taken along X1-Y1 of FIG. 1A. In addition, in FIG. 1A, in order to avoid complication, some of the constituent elements of the transistor 420 (eg, the insulating layer 407, etc.) are omitted and illustrated.

The transistor 420 shown in FIGS. 1A and 1B includes a base insulating layer 436, a source electrode layer 405a and a drain electrode layer 405b, and an impurity region 403a on a substrate 400 having an insulating surface. The oxide semiconductor layer 403 including the impurity region 403b and the channel formation region 403c, and the gate insulating layer 402 in contact with the upper surfaces of the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b ), the gate electrode layer 401 overlapping the channel formation region 403c through the gate insulating layer 402, the conductive layer 411 in contact with the side surface of the gate electrode layer 401, and the conductive layer 411. It is configured to include a sidewall insulating layer 412 formed on the side opposite to the gate electrode layer 401.

The oxide semiconductor layer 403 contacts the source electrode layer 405a from the side surface of the impurity region 403a in the channel length direction, and contacts the drain electrode layer 405b from the side surface of the impurity region 403b in the channel length direction.

In addition, in the cross section of the transistor 420 in the channel length direction, at least a part of the conductive layer 411 is formed on the source electrode layer 405a and the drain electrode layer 405b through the gate insulating layer 402. Since the conductive layer 411 is formed in contact with the side surface of the gate electrode layer 401 and can function as a part of the gate electrode layer 401, the source electrode layer is formed through the gate insulating layer 402 in the cross section in the channel length direction. A region overlapping with 405a or the drain electrode layer 405b may be the Lov region.

Further, a sidewall insulating layer 412 is formed so as to contact a part of a side surface of the conductive layer 411 that faces the gate electrode layer 401. The conductive layer 411 is formed by processing a conductive film covering the gate electrode layer 401 in a manufacturing process using the sidewall insulating layer 412 as a mask. Accordingly, the side end portion of the conductive layer 411 coincides with the side end portion of the sidewall insulating layer 412.

In addition, if the length of the Lov region is long, there is a concern that the parasitic capacitance generated in the region may increase, but in this embodiment, a sidewall insulating layer formed in a self-aligning manner on the side surface of the gate electrode layer 401 via the conductive layer 411 ( 412) can control the length of the Lov area. Therefore, it is possible to precisely process a fine Lov area.

In addition, the transistor 420 shown in FIGS. 1A and 1B includes an insulating layer 406 and an insulating layer 407 formed on the sidewall insulating layer 412 and the gate electrode layer 401, and the insulating layer 407. The wiring layer 435a and the wiring layer 435b may be included as constituent elements. The wiring layer 435a is electrically connected to the source electrode layer 405a through openings provided in the insulating layer 406, the insulating layer 407, and the gate insulating layer 402, and the wiring layer 435b is the insulating layer 406, It is electrically connected to the drain electrode layer 405b through openings provided in the insulating layer 407 and the gate insulating layer 402.

The oxide semiconductor layer 403 includes an impurity region 403a and an impurity region 403b formed self-aligning by introducing a dopant using the gate electrode layer 401 as a mask. The region may function as a source region or a drain region of the transistor 420 and is a region having a lower resistance than the channel formation region 403c. By forming the impurity region 403a and the impurity region 403b, an electric field applied to the channel formation region 403c formed between the pair of impurity regions can be relaxed. In addition, by making each of the source electrode layer 405a and the drain electrode layer 405b in contact with the impurity region, the contact resistance between the oxide semiconductor layer 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. .

In addition, by making the length of the oxide semiconductor layer 403 in the channel length direction longer than that of the gate electrode layer 401 in the channel length direction, the degree of freedom of alignment for forming the gate electrode layer 401 can be further improved, and the oxide By forming an impurity region in the semiconductor layer 403, the channel length of the transistor 420 can be reduced. Therefore, a micronized transistor can be manufactured with good yield.

Dopants included in the impurity region 403a and the impurity region 403b are impurities that change the conductivity of the oxide semiconductor layer 403. As dopants, elements of Group 15 (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium ( One or more elements selected from He), neon (Ne), indium (In), titanium (Ti), and zinc (Zn) may be used. Further, as a method of introducing a dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

Further, the oxide semiconductor layer 403 is preferably a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

The CAAC-OS film is not completely single crystal, nor is it completely amorphous. The CAAC-OS film is an oxide semiconductor layer having a crystalline-amorphous mixed phase structure having a crystalline portion and an amorphous portion in an amorphous phase. In addition, the crystal part is often sized to fit in a cube whose one side is less than 100 nm. In addition, the boundary between the amorphous portion and the crystal portion included in the CAAC-OS film is not clear from observation by a transmission electron microscope (TEM). In addition, grain boundaries (also referred to as grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Accordingly, in the CAAC-OS film, the decrease in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film is aligned in a direction in which the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and has a triangular or hexagonal shape when viewed from a direction perpendicular to the ab plane. It has an atomic arrangement, and when viewed from a direction perpendicular to the c-axis, metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. Further, the directions of the a-axis and the b-axis may be different between different crystal parts. In the case of simply describing "vertical" in the present specification, the range of 85° or more and 95° or less is also included. In addition, in the case of simply describing "parallel", the range of -5° or more and 5° or less is also included.

In addition, the distribution of crystal parts in the CAAC-OS film may not be uniform. For example, in the case of crystal growth on the surface side of the oxide semiconductor film in the process of forming the CAAC-OS film, there may be a case where the ratio of the crystal portion occupied near the surface is higher than near the surface to be formed. In addition, there are cases where the crystal portion is amorphized in the impurity addition region by adding an impurity to the CAAC-OS film.

The c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the CAAC-OS film. Depending on the cross-sectional shape), they may face different directions. In addition, the c-axis direction of the crystal part is a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface when the CAAC-OS film is formed. A crystal portion is formed by forming a film or performing a crystallization treatment such as heat treatment after film formation.

Transistors using the CAAC-OS film have little variation in electrical characteristics due to irradiation with visible or ultraviolet light. Therefore, the transistor has high reliability.

2A and 2B are plan views and cross-sectional views of a transistor 422 as another example of the semiconductor device according to the present embodiment. 2A is a plan view of the transistor 422, and FIG. 2B is a cross-sectional view taken along X2-Y2 in FIG. 2A. In addition, in FIG. 2A, some of the constituent elements of the transistor 422 (for example, the insulating layer 407, etc.) are omitted to avoid complication.

2A and 2B, the transistor 422 shown in FIG. 1 is similar to the transistor 420 shown in FIG. 1, a base insulating layer 436, a source electrode layer 405a, and a drain electrode layer on the substrate 400 having an insulating surface. 405b, an oxide semiconductor layer 403 including an impurity region 403a, an impurity region 403b, and a channel formation region 403c, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b ), the gate insulating layer 402 in contact with the upper surface of the gate insulating layer 402, the gate electrode layer 401 overlapping the channel formation region 403c through the gate insulating layer 402, and a conductive layer in contact with the side surface of the gate electrode layer 401 ( 411 and a sidewall insulating layer 412 formed on a side surface of the conductive layer 411 opposite to the gate electrode layer 401.

The oxide semiconductor layer 403 included in the transistor 422 shown in FIGS. 2A and 2B is shown in FIGS. 1A and 1B in that it has a tapered shape on the side in contact with the source electrode layer 405a or the drain electrode layer 405b. It is different from the illustrated transistor 420. The taper angle of the oxide semiconductor layer 403 in the transistor 422 may be, for example, 20° or more and 50° or less. In addition, the "taper angle" here refers to the inclination angle formed by the side and bottom of the tapered layer when a layer having a tapered shape (here, the oxide semiconductor layer 403) is observed from a direction perpendicular to its cross-section. .

By making the side surface of the oxide semiconductor layer 403 into a tapered shape, the contact area with the source electrode layer 405a or the drain electrode layer 405b can be enlarged, so that the contact resistance can be further reduced.

In addition, when the oxide semiconductor layer 403 is an oxide semiconductor having crystallinity, the oxide semiconductor layer 403 has a tapered shape, so that oxygen vacancies due to the oxygen desorption from the side surface of the oxide semiconductor layer 403 are generated. By suppressing, it is possible to reduce the occurrence of leakage current in the transistor 422.

Hereinafter, an example of the manufacturing process of the transistor of this embodiment will be described with reference to FIGS. 3A to 4D. In addition, in the following, a method of manufacturing the transistor 422 will be described as an example.

First, a base insulating layer 436 is formed on a substrate 400 having an insulating surface.

There is no great limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand a later heat treatment process. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon or silicon carbide as a material, a compound semiconductor substrate made of silicon germanium, an SOI substrate, etc. may be applied. You may use it.

Further, a flexible substrate may be used as the substrate 400 to fabricate a semiconductor device. In order to manufacture a flexible semiconductor device, a transistor 422 including an oxide semiconductor layer 403 may be directly fabricated on a flexible substrate, or a transistor including an oxide semiconductor layer 403 on another fabricated substrate ( 422) may be fabricated, and then peeled off from the fabrication substrate and transferred to a flexible substrate. Further, in order to peel from the fabrication substrate and transfer to the flexible substrate, a release layer may be formed between the fabrication substrate and the transistor 422 including the oxide semiconductor layer.

The base insulating layer 436 is a single layer of a film containing silicon oxide, silicon nitride, silicon oxide nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxide nitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or a mixture of these materials. It can be structured or laminated. However, it is preferable that the underlying insulating layer 436 has a single-layer structure or a stacked structure including an oxide insulating film, and has a structure in which the oxide insulating film contacts the oxide semiconductor layer 403 to be formed later. Further, the underlying insulating layer 436 may not necessarily be formed.

If the underlying insulating layer 436 has an oxygen-containing region (hereinafter, also referred to as an oxygen-excessive region) exceeding the stoichiometric composition, the oxide semiconductor layer 403 to be formed later by the excess oxygen contained in the underlying insulating layer 436 ), it is preferable because it can preserve oxygen deficiencies. In the case where the underlying insulating layer 436 has a laminated structure, it is preferable to have an oxygen excess region at least in the layer in contact with the oxide semiconductor layer 403. In order to form an oxygen-excessive region in the underlying insulating layer 436, for example, the underlying insulating layer 436 may be formed in an oxygen atmosphere. Alternatively, oxygen (containing at least any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the formed underlying insulating layer 436 to form an oxygen-excessive region. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Next, an oxide semiconductor layer is formed on the underlying insulating layer 436 and processed into an island shape to form an oxide semiconductor layer 403 (see Fig. 3A). The thickness of the oxide semiconductor layer 403 is, for example, 3 nm to 30 nm, preferably 5 nm to 20 nm.

The oxide semiconductor layer may have a single-layer structure or a stacked structure. In addition, an amorphous structure may be sufficient or a crystalline structure may be sufficient as it. When the oxide semiconductor layer has an amorphous structure, a crystalline oxide semiconductor layer may be obtained by performing heat treatment on the oxide semiconductor layer in a subsequent fabrication step. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor layer is set to 250°C or higher and 700°C or lower, preferably 400°C or higher, more preferably 500°C or higher, and further preferably 550°C or higher. In addition, the said heat treatment may also serve as another heat treatment in a manufacturing process.

As a method for forming the oxide semiconductor layer, a sputtering method, a Molecular Beam Epitaxy (MBE) method, a chemical vapor deposition (CVD) method, a pulse laser deposition method, an atomic layer deposition (ALD) method, or the like can be appropriately used. Further, the oxide semiconductor layer may be formed by using a sputtering apparatus that forms a film while a plurality of substrate surfaces are fixed substantially perpendicular to the sputtering target surface.

When forming the oxide semiconductor layer, it is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor layer as much as possible. In order to reduce the hydrogen concentration, for example, in the case of forming by sputtering, as an atmospheric gas supplied into the deposition chamber of a sputtering device, a high-purity rare gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed (representative As an example, argon), oxygen, and a mixed gas of a rare gas and oxygen are appropriately used.

Further, the hydrogen concentration in the formed oxide semiconductor layer can be reduced by introducing hydrogen and a sputtering gas from which moisture has been removed to form a film while removing residual moisture in the film formation chamber. In order to remove residual moisture in the film formation chamber, it is preferable to use an adsorption type vacuum pump, for example, a cryo pump, an ion pump, or a titanium sublimation pump. Further, it may be a turbomolecular pump plus a cold trap. Since the film formation chamber exhausted by using a cryopump has high evacuation capacity of compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) _{, for example, hydrogen molecules and water (H 2 O),} The concentration of impurities included in the oxide semiconductor layer formed in the deposition chamber can be reduced.

In the case of forming the oxide semiconductor layer by sputtering, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. do. By using a metal oxide target having a high relative density, the formed oxide semiconductor layer can be formed into a dense film.

In addition, forming the oxide semiconductor layer while maintaining the substrate 400 at a high temperature is also effective in reducing the concentration of impurities that may be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150°C or more and 450°C or less, and preferably, the substrate temperature is 200°C or more and 350°C or less. Further, by heating the substrate to a high temperature during film formation, a crystalline oxide semiconductor layer can be formed.

The oxide semiconductor used for the oxide semiconductor layer 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain both In and Zn. In addition, as a stabilizer for reducing non-uniformity in electrical characteristics of a transistor using the oxide semiconductor, it is preferable to additionally have gallium (Ga) in addition to these. It is also preferred to have tin (Sn) as a stabilizer. In addition, it is preferable to have hafnium (Hf) as a stabilizer. In addition, it is preferable to have aluminum (Al) as a stabilizer. Further, it is preferable to have zirconium (Zr) as a stabilizer.

In addition, as other stabilizers, lanthanides, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may have any one or more.

For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg Oxide, In-Ga Oxide, In-Ga-Zn Oxide (also referred to as IZO), In-Al-Zn Oxide, In-Sn-Zn Oxide , Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In -Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy -Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, quaternary metal oxide Phosphorus In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide , In-Hf-Al-Zn-based oxide can be used.

In addition, here, for example, an In-Ga-Zn-based oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is irrelevant. Further, metal elements other than In, Ga, and Zn may be contained.

Further, as the oxide semiconductor, _{a material denoted by InMO 3} (ZnO) _m (m>0, and m is not an integer) may be used. In addition, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, _{a material represented by In 2} SnO ₅ (ZnO) _n (n>0, and n is an integer) may be used.

For example, the atomic ratio In:Ga:Zn=1:1:1(=1/3:1/3:1/3), In:Ga:Zn= 2:2:1(=2/5: 2/5:1/5), or In:Ga:Zn=3:1:2 (=1/2:1/6:1/3), In-Ga-Zn oxide or oxide having a composition near it Can be used. Alternatively, the atomic ratio is In:Sn:Zn=1:1:1(=1/3:1/3:1/3), In:Sn:Zn=2:1:3(=1/3:1/ 6:1/2) or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) In-Sn-Zn oxide or oxide having a composition near it good.

However, the present invention is not limited to the above, and a composition having an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold value, deviation, etc.). In addition, in order to obtain the necessary semiconductor properties, it is preferable that the carrier concentration or impurity concentration, the defect density, the atomic ratio of the metal element and oxygen, the distance between atoms, the density, and the like are appropriate.

For example, the In-Sn-Zn-based oxide can relatively easily obtain high mobility. However, even when an In-Ga-Zn-based oxide is used, the mobility can be increased by reducing the defect density in the bulk.

In addition, for example, the composition of the oxide in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c=1) is In:Ga:Zn=A:B: In the vicinity of the composition of the oxide of C(A+B+C=1), it means that a, b, and c satisfy ^{(aA) 2} +(bB) ² +(cC) ^{2 ?} r ^2. As r, it is good to set it as 0.05, for example. The same goes for other oxides.

In addition, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed as the sputtering gas used when forming the oxide semiconductor layer.

When a CAAC-OS film is applied as the oxide semiconductor layer 403, three methods are mentioned as a method of obtaining the CAAC-OS film. The first method is a method of forming an oxide semiconductor layer at a film forming temperature of 200°C or more and 450°C or less, and performing c-axis alignment substantially perpendicular to the surface. The second method is a method of forming an oxide semiconductor layer having a thin thickness and then performing a heat treatment at 200°C or higher and 700°C or lower to perform a c-axis orientation substantially perpendicular to the surface. The third method is a method of forming a first layer with a thin film thickness, then performing a heat treatment at 200°C or more and 700°C or less, and then forming a second layer and oriented in the c-axis substantially perpendicular to the surface.

Before forming the oxide semiconductor layer, a planarization treatment may be performed on the surface to be formed of the oxide semiconductor layer. Although it does not specifically limit as a planarization process, A polishing process (for example, a chemical mechanical polishing method), a dry etching process, and a plasma process can be used.

As the plasma treatment, for example, reverse sputtering in which plasma is generated by introducing argon gas can be performed. Reverse sputtering refers to a method of modifying the surface of a substrate by forming plasma in the vicinity of the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Further, instead of argon, nitrogen, helium, oxygen, or the like may be used. By performing reverse sputtering, powdery substances (also referred to as particles and garbage) adhering to the formation surface of the oxide semiconductor layer can be removed.

As the planarization treatment, a polishing treatment, a dry etching treatment, and a plasma treatment may be performed a plurality of times, or a combination thereof may be performed. In addition, when performing these combinations, the process order is not particularly limited, and may be appropriately set according to the uneven state of the formation surface of the oxide semiconductor layer.

In addition, it is preferable to heat the oxide semiconductor layer 403 to remove (dehydrate or dehydrogenate) excess hydrogen (including water or hydroxyl group) contained in the oxide semiconductor layer 403. The temperature of the heat treatment is set to be 300°C or more and 700°C or less, or less than the strain point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere or the like.

By this heat treatment, hydrogen, which is an impurity imparting n-type conductivity, can be removed from the oxide semiconductor. For example, the concentration of hydrogen contained in the oxide semiconductor layer 403 after dehydration or dehydrogenation treatment may be 5×10 ¹⁹ /cm ³ or less, preferably 5×10 ¹⁸ /cm ³ or less.

In addition, the heat treatment for dehydration or dehydrogenation may be performed at any timing in the manufacturing process of the transistor 422 as long as the oxide semiconductor layer is formed. In addition, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times, or may be combined with other heat treatments.

In the case of forming the underlying insulating layer 436 containing oxygen as the underlying insulating layer 436, heating treatment for dehydration or dehydrogenation is performed before the oxide semiconductor layer is processed into an island shape, the underlying insulating layer It is preferable because oxygen contained in (436) can be prevented from being released to the outside of the film due to heat treatment.

In the heat treatment, it is preferable that no water, hydrogen, or the like is contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) is preferable.

In addition, after heating the oxide semiconductor layer 403 by heat treatment, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air (CRDS ( Cavity ring-down laser spectroscopy) method as measured using a dew point meter, the moisture content may be 20 ppm (-55° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less air) may be introduced. . It is preferable that oxygen gas or dinitrogen monoxide gas does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm or less). It is preferable to do it. High purity of the oxide semiconductor layer 403 by supplying oxygen, which is the main component material of the reduced oxide semiconductor at the same time as a process of removing impurities by dehydration or dehydrogenation by the action of oxygen gas or dinitrogen monoxide gas. And i-type (intrinsic).

In addition, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer subjected to dehydration or dehydrogenation treatment to supply oxygen into the film.

By introducing oxygen into the oxide semiconductor layer subjected to dehydration or dehydrogenation and supplying oxygen into the film, the oxide semiconductor layer can be highly purified and i-type (intrinsic). A transistor having a highly purified and i-type (intrinsic) oxide semiconductor layer is electrically stable because fluctuations in electrical characteristics are suppressed.

In the process of introducing oxygen, when oxygen is introduced into the oxide semiconductor layer, it may be directly introduced into the oxide semiconductor layer, or it passes through another film such as the gate insulating layer 402 or the insulating layer 406 to be formed later. Oxygen may be introduced into the oxide semiconductor layer 403. In the case of introducing oxygen through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. may be used, but when oxygen is directly introduced into the exposed oxide semiconductor layer 403, in addition to the above method, Plasma treatment or the like can also be used.

The timing of introduction of oxygen into the oxide semiconductor layer is not particularly limited as long as it is after the oxide semiconductor layer is formed. In addition, oxygen may be introduced into the oxide semiconductor layer a plurality of times.

Next, a conductive film 405 serving as a source electrode layer and a drain electrode layer (including wiring formed in such a layer) is formed on the oxide semiconductor layer 403 (see Fig. 3B).

As the material of the conductive film 405, a material capable of withstanding heat treatment is used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-described elements (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. Can be used. In addition, a high melting point metal film such as Ti, Mo, W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the lower or upper side of a metal film such as Al and Cu. You may have one configuration. Alternatively, the conductive film 405 may be formed using a conductive metal oxide. Conductive metal oxides include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ -SnO ₂ , abbreviated as ITO), indium oxide zinc oxide ( In ₂ O ₃ -ZnO) or those in which silicon oxide is included in these metal oxide materials can be used.

Next, a polishing (cutting, grinding) treatment is performed on the conductive film 405 to remove a part of the conductive film 405 so that the oxide semiconductor layer 403 is exposed. By the polishing treatment, the conductive film 405 in a region overlapping with the oxide semiconductor layer 403 is removed, so that a conductive film having an opening is formed in the region. As a method of polishing (cutting, grinding), chemical mechanical polishing (CMP) treatment can be suitably used. In this embodiment, the conductive film 405 in the region overlapping with the oxide semiconductor layer 403 is removed by CMP treatment.

Further, the CMP treatment may be performed only once or may be performed a plurality of times. When performing the CMP treatment by dividing into a plurality of times, it is preferable to perform primary polishing at a high polishing rate and then finish polishing at a low polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surfaces of the conductive film 405 and the oxide semiconductor layer 403 can be further improved.

In the present embodiment, the CMP treatment is used to remove the conductive film 405 in the region overlapping with the oxide semiconductor layer 403, but other polishing (grinding, cutting) treatments may be used. Alternatively, a polishing treatment such as a CMP treatment may be combined with an etching (dry etching, wet etching) treatment or a plasma treatment. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering, etc.) may be performed to improve the flatness of the treated surface. In the case of performing a combination of etching treatment, plasma treatment, or the like as the polishing treatment, the process order is not particularly limited, and may be appropriately set according to the material of the conductive film 405, the film thickness, and the unevenness of the surface.

Next, the oxide semiconductor layer 403 is exposed and the conductive film 405 having an opening is selectively etched using a mask produced by a photolithography process, and the source electrode layer 405a and the drain electrode layer 405b are (Including the wiring formed of such a layer) is formed (see Fig. 3C).

In addition, in this embodiment, after the conductive film 405 is formed, the conductive film 405 in the region overlapping the oxide semiconductor layer 403 is removed by polishing treatment, the source electrode layer 405a and the source electrode layer 405a and the source electrode layer 405a are selectively etched. Although a method of processing the drain electrode layer 405b has been shown, the embodiment of the present invention is not limited to this. After the formation of the conductive film 405 is selectively etched, the conductive film 405 in the region overlapping with the oxide semiconductor layer 403 is removed by a polishing treatment to form the source electrode layer 405a and the drain electrode layer 405b. It may be formed.

In the method of manufacturing the transistor described in this embodiment, in the step of removing the conductive film 405 in the region overlapping with the oxide semiconductor layer 403 when forming the source electrode layer 405a and the drain electrode layer 405b. However, since the etching treatment using the resist mask is not performed, precise processing can be accurately performed even when the length of the oxide semiconductor layer 403 is reduced. Therefore, in the manufacturing process of a semiconductor device, the transistor 422 having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

In addition, in this embodiment, the upper end portions of the source electrode layer 405a and the drain electrode layer 405b substantially coincide with the upper end portions of the oxide semiconductor layer 403. However, the shapes of the source electrode layer 405a and the drain electrode layer 405b are different depending on the condition of the polishing treatment for removing a part of the conductive film 405. For example, the film thickness of the source electrode layer 405a and the drain electrode layer 405b may be smaller than the film thickness of the oxide semiconductor layer 403.

Next, a gate insulating layer 402 is formed over the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b.

The gate insulating layer 402 has a film thickness of 1 nm or more and 20 nm or less and can be formed by appropriately using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like. In addition, the gate insulating layer 402 may be formed using a sputtering apparatus that performs film formation while a plurality of substrate surfaces are provided substantially perpendicular to the sputtering target surface.

Further, as the thickness of the gate insulating layer 402 increases, the short channel effect becomes more pronounced, and the threshold voltage tends to fluctuate toward the negative side. However, in the method of manufacturing the transistor of the present embodiment, since the top surfaces of the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor layer 403 are planarized by the polishing treatment, the gate insulating layer having a thin thickness ( 402) can be formed with good coatability.

As the material of the gate insulating layer 402, silicon oxide, gallium oxide, aluminum oxide, silicon nitride, silicon oxide nitride, aluminum oxide nitride, silicon nitride oxide, or the like can be used. It is preferable that the gate insulating layer 402 contains oxygen at a portion in contact with the oxide semiconductor layer 403. In particular, it is preferable that the gate insulating layer 402 has an amount of oxygen exceeding at least a stoichiometric composition in the film (in the bulk). For example, when a silicon oxide film is used as the gate insulating layer 402, It is preferable to set it as SiO _2+α (however, α>0). In this embodiment, as the gate insulating layer 402 _{, a silicon oxide film of SiO 2+α} (however, α>0) is used. By using this silicon oxide film as the gate insulating layer 402, oxygen can be supplied to the oxide semiconductor layer 403 and the characteristics can be improved.

In addition, the gate leakage current can be reduced by using a high-k material such as hafnium oxide, yttrium oxide, hafnium silicate, nitrogen-added hafnium silicate, hafnium aluminate, and lanthanum oxide as the material of the gate insulating layer 402. . Further, the gate insulating layer 402 may have a single-layer structure or a stacked structure.

In addition, as with the underlying insulating layer 436, if the gate insulating layer 402 has an oxygen-excessive region, oxygen vacancies in the oxide semiconductor layer 403 can be preserved by excess oxygen contained in the gate insulating layer 402. It is desirable because it can. When the gate insulating layer 402 has a laminated structure, it is preferable to have an oxygen-excessive region at least in the layer in contact with the oxide semiconductor layer 403. In order to form an oxygen-excessive region in the gate insulating layer 402, for example, the gate insulating layer 402 may be formed in an oxygen atmosphere. Alternatively, oxygen (containing at least any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the formed gate insulating layer 402 to form an oxygen-excessive region. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

In addition, when oxygen is introduced into the gate insulating layer 402 after formation, oxygen may be simultaneously introduced into the oxide semiconductor layer 403 by the above oxygen introduction treatment. Further, it is preferable to perform heat treatment after introducing oxygen into the gate insulating layer 402. The temperature of the heat treatment can be, for example, 300°C or more and 450°C or less. In addition, the heat treatment can also serve as a dehydration treatment or a dehydrogenation treatment from the oxide semiconductor layer 403.

In addition, the timing of the oxygen introduction treatment to the gate insulating layer 402 is not particularly limited as long as the gate insulating layer 402 is formed. Further, a plurality of oxygen introduction methods may be used in combination. For example, after forming the gate insulating layer 402, oxygen may be introduced and heat treated by ion implantation and plasma treatment. Alternatively, after forming the gate insulating layer 402, oxygen may be introduced by plasma treatment, and after forming the insulating layer 406 in a subsequent step, oxygen may be introduced again by ion implantation and heat treatment may be performed, The order of performing the plasma treatment and the ion implantation treatment may be changed.

Next, a gate electrode layer 401 is formed on the island-shaped oxide semiconductor layer 403 via the gate insulating layer 402. The gate electrode layer 401 can be formed by plasma CVD or sputtering. In addition, the material used for the gate electrode layer 401 is a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described elements ( Titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Further, as the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single layer structure or a laminate structure.

In addition, the material of the gate electrode layer 401 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium. Conductive materials such as zinc oxide and indium tin oxide to which silicon oxide has been added can also be applied. Further, it is also possible to have a laminated structure of the conductive material and the metal material.

In addition, as one layer of the gate electrode layer 401 in contact with the gate insulating layer 402, a metal oxide containing nitrogen, specifically an In-Ga-Zn-O film containing nitrogen, or an In-Sn-O containing nitrogen. A film, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, a Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (InN, SnN, etc.) ) Can be used. These films have a work function of 5 eV (electron volt) or more, preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the transistor can be varied to the positive side, so-called normal-off switching The device can be realized.

Further, the gate electrode layer 401 may be formed by processing a conductive film (not shown) formed on the gate insulating layer 402 using a mask. Here, as for the mask used for processing, it is preferable to apply a slimming treatment to a mask formed by a photolithography method or the like to obtain a mask having a finer pattern.

As the slimming treatment, for example, an ashing treatment using radical oxygen (oxygen radical) or the like can be applied. However, the slimming treatment need not be limited to the ashing treatment as long as it is a treatment capable of processing a mask formed by a photolithography method or the like into a finer pattern. In addition, since the channel length L of the transistor is determined by the mask formed by the slimming treatment, the slimming treatment can be applied with a treatment having good controllability.

As a result of performing the slimming treatment, the mask formed by a photolithography method or the like can be made finer to a line width of less than or equal to the resolution limit of the exposure apparatus, preferably less than or equal to 1/2, more preferably less than or equal to 1/3. For example, the line width can be 30 nm or more and 2000 nm or less, preferably 50 nm or more and 350 nm or less. In this way, the transistor can be further refined.

Next, a dopant 431 is introduced into the oxide semiconductor layer 403 using the gate electrode layer 401 as a mask to form an impurity region 403a and an impurity region 403b. By introducing the dopant 431, an oxide semiconductor layer 403 in which a pair of impurity regions are formed is formed through the channel formation region 403c (see Fig. 3D).

As a method of introducing the dopant 431, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In this case, it is preferable to use a single ion of the dopant 431, a fluoride ion or a chloride ion.

The step of introducing the dopant 431 may be controlled by appropriately setting injection conditions such as an acceleration voltage and a dose, and the thickness of the film to be passed. In addition, the dose amount of the dopant 431 may be, for example, 1×10 ¹³ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less. Further, the concentration of the dopant 431 in the impurity region is preferably 5×10 ¹⁸ /cm ³ or more and 1×10 ²² /cm ³ or less.

When the dopant 431 is introduced, it may be performed while heating the substrate 400.

Further, the treatment of introducing the dopant 431 into the oxide semiconductor layer 403 may be performed several times, or a plurality of types of dopants may be used.

Further, after the dopant 431 is introduced, heat treatment may be performed. As heating conditions, it is preferable that the temperature is set to 300°C or more and 700°C or less, and preferably 300°C or more and 450°C or less, and performed in an oxygen atmosphere for 1 hour. Further, heat treatment may be performed under a nitrogen atmosphere, under reduced pressure, and in the atmosphere (super dry air).

When the oxide semiconductor layer 403 is used as a CAAC-OS film, a part of the oxide semiconductor layer 403 may become amorphous due to the introduction of the dopant 431. In this case, the crystallinity of the oxide semiconductor layer 403 can be restored by performing heat treatment after introducing the dopant 431.

3D, since the oxide semiconductor layer 403 has a tapered shape, a region overlapping with the source electrode layer 405a or the drain electrode layer 405b is included at the end. Depending on the conditions for introducing the dopant 431, it may be difficult to introduce the dopant 431 in the region. Therefore, when the impurity region 403a or the impurity region 403b has a dopant concentration distribution in the film thickness direction. There is.

Next, a conductive film 415 is formed over the gate electrode layer 401 and the gate insulating layer 402, and an insulating layer 416 is formed over the conductive film 415 (see Fig. 4A).

The conductive film 415 can be formed using the same material as the gate electrode layer 401, and is preferably formed using a sputtering method. In addition, the thickness of the conductive film 415 is preferably 10 nm or more and 50 nm or less, for example.

The insulating layer 416 can be formed using, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like, and is preferably formed by a CVD method.

In general, the sputtering method has lower step coverage (step coverage) compared to the CVD method. Therefore, when forming a conductive film having a thick thickness in contact with the gate electrode layer 401 and anisotropically etching the conductive film to form a conductive layer in contact with the sidewall of the gate electrode layer 401 in a self-aligning manner, a step portion (gate insulating layer) In some cases, a region with low density is formed at the boundary between the region in contact with the 402 and the region in contact with the gate electrode layer 401 ). If the conductive layer functioning as a part of the gate electrode layer includes a region having a low density, the region may cause a leakage current.

However, in this embodiment, after forming the thin conductive film 415 so as to cover the gate electrode layer 401, the insulating layer 416 in contact with the conductive film 415 is formed by a CVD method having good step coverage. To form. Accordingly, it is possible to cover the gate electrode layer 401 by the conductive film 415 having a good film quality.

In addition, in this embodiment, the gate electrode layer 401 has a tapered end portion, but the embodiment of the present invention is not limited thereto. However, since the gate electrode layer 401 has a tapered shape, the conductive film 415 is preferable because it becomes easy to ensure good step coverage.

Next, the insulating layer 416 is anisotropically etched to form the sidewall insulating layer 412 (see Fig. 4B).

Next, by etching the conductive film 415 using the sidewall insulating layer 412 as a mask, the conductive layer 411 is formed in contact with the side surface of the gate electrode layer 401 in the channel length direction (see Fig. 4C).

After that, an insulating layer 406 and an insulating layer 407 are formed on the gate insulating layer 402, the gate electrode layer 401, and the sidewall insulating layer 412. In addition, in this embodiment, an example in which a laminated structure of the insulating layer 406 and the insulating layer 407 is formed on the gate insulating layer 402, the gate electrode layer 401, and the sidewall insulating layer 412 is shown. , One embodiment of the present invention is not limited to this, and an insulating layer having a single layer structure may be formed. Alternatively, three or more insulating layers may be laminated.

The insulating layer 406 or the insulating layer 407 can be formed by a plasma CVD method, a sputtering method, or a vapor deposition method. In particular, it is preferable to form the insulating layer 406 or the insulating layer 407 by appropriately using a method such as a sputtering method in which impurities such as water and hydrogen are not mixed. As the insulating layer 406 or the insulating layer 407, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be used.

In addition, as the insulating layer 406 or the insulating layer 407, an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (for example, an aluminum nitride film ) Can also be used.

In addition, it is preferable to form an aluminum oxide film as the insulating layer 406 or the insulating layer 407. The aluminum oxide film has a high blocking effect (blocking effect) that does not allow the film to pass through both impurities such as hydrogen and moisture, and oxygen, and hydrogen, which is a factor of fluctuations in the operating characteristics of the transistor during and after the fabrication process, Since it functions as a protective film that prevents impurities such as moisture from being mixed into the oxide semiconductor layer 403 and oxygen, which is a main component material constituting the oxide semiconductor, is released from the oxide semiconductor layer 403, it can be preferably applied. .

Similar to the formation of the oxide semiconductor layer 403, in order to remove residual moisture in the film forming chamber forming the insulating layer 406 or the insulating layer 407, an adsorption type vacuum pump (such as a cryo pump) is used. It is desirable. The concentration of impurities contained in the insulating layer 406 or the insulating layer 407 formed in the film formation chamber exhausted by using the cryopump can be reduced. In addition, as an exhaust means for removing residual moisture in the film forming chamber in which the insulating layer 406 or the insulating layer 407 is formed, a cold trap may be applied to the turbo molecular pump.

In this embodiment, an aluminum oxide film is formed as the insulating layer 406 and a silicon oxide film is formed as the insulating layer 407. Further, by making the aluminum oxide film at a high density (film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), it is possible to impart stable electrical characteristics to the transistor 422. The film density can be measured by a Rutherford Backscattering Spectrometry (RBS) or an X-ray reflectance measurement (XRR).

Further, in the case of forming an aluminum oxide film as the insulating layer 406, it is preferable to perform heat treatment after forming the aluminum oxide film. The aluminum oxide film has a function of preventing water (including hydrogen) from entering the oxide semiconductor layer and a function of preventing oxygen from being desorbed from the oxide semiconductor layer. Therefore, when the oxide semiconductor layer 403 and/or the insulating layer in contact with it has an oxygen-excessive region, heat treatment is performed in a state in which an aluminum oxide film is formed, thereby forming the oxide semiconductor layer film (in the bulk) or the insulating layer and the oxide. At the interface of the semiconductor layer, at least one oxygen-excessive region can be formed.

Next, openings reaching the source electrode layer 405a or drain electrode layer 405b are formed in the insulating layer 407, the insulating layer 406, and the gate insulating layer 402, and the wiring layer 435a and the wiring layer ( 435b) is formed (see Fig. 4D). Various circuits can be formed by connecting the wiring layer 435a and the wiring layer 435b to other transistors or elements.

The wiring layer 435a and the wiring layer 435b can be formed using materials and methods such as the gate electrode layer 401, the conductive layer 411, the source electrode layer 405a, or the drain electrode layer 405b. For example, Al , Cr, Cu, Ta, Ti, Mo, W, a metal film containing an element selected from, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as a component can be used. . In addition, a high melting point metal film such as Ti, Mo, W or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the lower or upper side of a metal film such as Al, Cu, etc. It may be configured. Further, as the conductive film used for the wiring layer 435a and the wiring layer 435b, it may be formed of a conductive metal oxide. Conductive metal oxides include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (In ₂ O ₃ -ZnO), or these metals. What made the oxide material contain silicon oxide can be used.

For example, a single layer of a molybdenum film, a laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film may be used as the wiring layer 435a and the wiring layer 435b.

The transistor 422 of this embodiment is formed by the above-described process.

The transistor described in this embodiment includes an oxide semiconductor layer 403 including a pair of impurity regions and a channel formation region, and a source electrode layer 405a in contact with a side surface of the oxide semiconductor layer 403 in the channel length direction in the impurity region. And a drain electrode layer 405b. As a result, the contact resistance between the oxide semiconductor layer 403 and the source electrode layer 405a or the drain electrode layer 405b can be reduced, and the on characteristics (for example, on-current and field effect mobility) are high, and high-speed operation, high-speed operation. A transistor capable of responding can be used.

In addition, by introducing a dopant using the gate electrode layer 401 as a mask, the length of the island-shaped oxide semiconductor layer 403 in the channel length direction is maintained to the extent that the alignment accuracy of the gate electrode layer 401 is maintained. The length of (403c) can be reduced. Therefore, the micronized transistor 422 can be manufactured with good yield.

In addition, in the step of removing the oxide semiconductor layer 413 in the region overlapping with the source electrode layer 405a and the drain electrode layer 405b, since the etching treatment using a resist mask is not used, the source electrode layer 405a and the drain electrode layer 405a Even when the spacing between the electrode layers 405b is small, precise processing can be accurately performed. Therefore, in the manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

Further, in the semiconductor device of this embodiment, a conductive layer 411 is formed on the side surface of the gate electrode layer 401. As a result, since the conductive layer 411 overlaps the source electrode layer 405a and the drain electrode layer 405b via the gate insulating layer 402, a transistor having a Lov region can be obtained, thereby reducing the on-state current of the transistor. Can be suppressed.

In addition, in the manufacturing process, the conductive layer 411 is formed by processing the insulating layer 416 formed on the gate electrode layer 401 through the conductive film 415 into the sidewall insulating layer 412 in a self-aligning manner by anisotropic etching. Thereafter, it is formed by etching the conductive film 415 using the sidewall insulating layer 412 as a mask, and since an etching process using a resist mask is not used, precise processing can be accurately performed. Therefore, in the manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

As described above, in one embodiment of the disclosed invention, the problem associated with miniaturization can be solved, and as a result, the transistor size can be sufficiently reduced. By making the transistor size sufficiently small, the area occupied by the semiconductor device is reduced, and the number of acquisitions of the semiconductor device is increased. Therefore, the manufacturing cost per semiconductor device is suppressed. In addition, since the channel length is reduced, effects such as high-speed operation and low power consumption can be obtained. That is, by achieving miniaturization of a transistor using an oxide semiconductor according to one embodiment of the disclosed invention, various effects accompanying this can be obtained.

As described above, the configurations and methods described in this embodiment can be used in appropriate combination with the configurations and methods described in other embodiments.

(Embodiment 2)

In this embodiment, a configuration of a semiconductor device different from that of the first embodiment and a method of manufacturing the same according to one embodiment of the present invention will be described with reference to FIGS. 5A to 7C. In addition, the same parts as the above-described embodiment and parts and steps having the same functions can be performed in the same manner as in the above-described embodiment, and repetitive description is omitted. In addition, detailed description of the same location is omitted.

5A and 5B are plan views and cross-sectional views of a transistor 424 as an example of a semiconductor device. 5A is a plan view of the transistor 424, and FIG. 5B is a cross-sectional view taken along X3-Y3 in FIG. 5A. In addition, in FIG. 5A, some of the constituent elements of the transistor 424 (for example, the insulating layer 407, etc.) are omitted to avoid complication.

The transistor 424 shown in Figs. 5A and 5B is similar to the transistor 420 shown in Figs. 1A and 1B, a base insulating layer 436 and a source electrode layer 405a on a substrate 400 having an insulating surface. And an oxide semiconductor layer 403 including a drain electrode layer 405b, an impurity region 403a, an impurity region 403b, and a channel formation region 403c, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain. The gate insulating layer 402 in contact with the upper surface of the electrode layer 405b, the gate electrode layer 401 overlapping the channel formation region 403c through the gate insulating layer 402, and the side surface of the gate electrode layer 401 It comprises a conductive layer 411 and a sidewall insulating layer 412 formed on a side surface of the conductive layer 411 facing the gate electrode layer 401.

The source electrode layer 405a and the drain electrode layer 405b included in the transistor 424 shown in FIGS. 5A and 5B have a tapered shape on the side in contact with the oxide semiconductor layer 403 as shown in the first embodiment. It is different from the transistor. In the transistor 424, the taper angles of the source electrode layer 405a and the drain electrode layer 405b may be, for example, 20° or more and 50° or less.

By making the side surfaces of the source electrode layer 405a and the drain electrode layer 405b tapered, an oxide semiconductor layer serving as the oxide semiconductor layer 403 can be formed in a space between the source electrode layer 405a and the drain electrode layer 405b with good coverage. I can. Further, since the contact area between the oxide semiconductor layer 403 and the source electrode layer 405a and the drain electrode layer 405b can be enlarged, the contact resistance can be reduced.

In addition, since the source electrode layer 405a and the drain electrode layer 405b have a tapered shape, the oxide semiconductor layer 403 formed in contact with the source electrode layer 405a and the drain electrode layer 405b is reverse tapered in the side of the channel length direction. It becomes a configuration having a shape. Here, in the case where the oxide semiconductor layer 403 is an oxide semiconductor having crystallinity, the oxide semiconductor layer 403 has a tapered shape, and thus oxygen vacancies are generated due to the release of oxygen from the side surface of the oxide semiconductor layer 403. Is suppressed, and the leakage current of the transistor 424 can be reduced.

Further, since the oxide semiconductor layer 403 has an inverse taper shape, the length of the upper surface of the oxide semiconductor layer 403 in contact with the gate insulating layer 402 in the channel length direction can be increased. Accordingly, the degree of freedom of alignment when forming the gate electrode layer 401 on the oxide semiconductor layer 403 with the gate insulating layer 402 interposed therebetween can be improved. In addition, the electric field of the source electrode layer 405a and the drain electrode layer 405b can be effectively relaxed.

Hereinafter, an example of the manufacturing process of the transistor 424 of the present embodiment will be described with reference to FIGS. 6A to 6D.

First, a base insulating layer 436 is formed on a substrate 400 having an insulating surface, and a conductive film to be a source electrode layer and a drain electrode layer (including wiring formed of such a layer) is formed on the base insulating layer 436. After formation, this is processed to form a source electrode layer 405a and a drain electrode layer 405b (see Fig. 6A).

Next, an oxide semiconductor layer 413 is formed covering the source electrode layer 405a and the drain electrode layer 405b and in contact with the underlying insulating layer 436 (see Fig. 6B). The oxide semiconductor layer 413 can be formed in the same manner as the oxide semiconductor layer forming method described in the first embodiment.

Next, a polishing (cutting, grinding) treatment is performed on the oxide semiconductor layer 413 to remove a part of the oxide semiconductor layer 413 so that the source electrode layer 405a and the drain electrode layer 405b are exposed. By the polishing treatment, the oxide semiconductor layer 413 in a region overlapping the source electrode layer 405a and the drain electrode layer 405b is removed, and an opening is formed in the region. As a polishing method, CMP treatment can be suitably used. In this embodiment, the oxide semiconductor layer 413 in a region overlapping the source electrode layer 405a and the drain electrode layer 405b is removed by CMP treatment. Further, the CMP treatment may be performed only once or may be performed a plurality of times.

In this embodiment, although the CMP treatment is used as a method of removing the oxide semiconductor layer 413 in the region overlapping with the source electrode layer 405a and the drain electrode layer 405b, other polishing treatments may be used. Alternatively, a polishing treatment such as a CMP treatment may be combined with an etching (dry etching, wet etching) treatment or a plasma treatment.

Next, by selectively etching the channel width direction of the oxide semiconductor layer 413 from which the region overlapping the source electrode layer 405a and the drain electrode layer 405b has been removed using a mask prepared by a photolithography process, the source electrode layer An island-shaped oxide semiconductor layer 403 is formed in the region between 405a and the drain electrode layer 405b (see Fig. 6C).

In addition, in this embodiment, the oxide semiconductor layer 413 is formed, the oxide semiconductor layer 413 in the region overlapping the source electrode layer 405a and the drain electrode layer 405b is removed by polishing treatment, and then selectively etched. A method of processing and processing into the island-shaped oxide semiconductor layer 403 has been presented, but the embodiment of the present invention is not limited thereto. The oxide semiconductor layer 413 after formation is selectively etched and processed in the channel width direction, and then the oxide semiconductor layer 413 in the region overlapping the source electrode layer 405a and the drain electrode layer 405b is removed by polishing. Thus, by processing in the channel length direction, an island-shaped oxide semiconductor layer 403 may be formed.

In addition, in this embodiment, the upper end portions of the source electrode layer 405a and the drain electrode layer 405b substantially coincide with the upper end portions of the oxide semiconductor layer 403. However, the shape of the oxide semiconductor layer 403 may be different depending on the conditions of the polishing treatment of the oxide semiconductor layer 413. For example, the upper end of the oxide semiconductor layer 403 is the source electrode layer 405a or the drain electrode layer ( 405b) may be in contact with the side surface in the channel length direction.

After forming the island-shaped oxide semiconductor layer 403, the gate insulating layer 402, the gate electrode layer 401, the conductive layer 411, and sidewall insulation are similar to the process shown in FIGS. 3D to 4D of the first embodiment. A layer 412, an insulating layer 406, an insulating layer 407, a wiring layer 435a, and a wiring layer 435b are formed. By the above, the transistor 424 of this embodiment is formed (see Fig. 6D).

In the method of fabricating the transistor described in this embodiment, when forming the island-shaped oxide semiconductor layer 403, the oxide semiconductor layer 413 in the region overlapping the source electrode layer 405a and the drain electrode layer 405b is removed. In the process, since the etching treatment using a resist mask is not used for processing in the channel length direction, even when the length of the source electrode layer 405a and the drain electrode layer 405b in the channel length direction is reduced, precise processing is accurately performed. Can be done. Therefore, in the manufacturing process of a semiconductor device, the transistor 424 having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

In addition, in the above-described transistor 420, transistor 422, and transistor 424, the case where the sidewall insulating layer 412 is in contact with a part of the upper surface of the conductive layer 411 has been exemplified, but the embodiment of the present invention It is not limited to this. The size of the sidewall insulating layer 412 (length in the channel length direction or the film thickness of the sidewall insulating layer) can be appropriately set by controlling the etching process of the insulating layer 416.

For example, as in the transistor 426 shown in FIG. 7A, the height of the sidewall insulating layer 412 (distance from the surface of the substrate 400 to the top surface of the sidewall insulating layer 412) and the conductive layer The height of 411 (distance from the surface of the substrate 400 to the uppermost surface of the conductive layer 411) may be matched. Alternatively, as in the transistor 428 shown in FIG. 7B, the height of the sidewall insulating layer 412 (the distance from the surface of the substrate 400 to the uppermost surface of the sidewall insulating layer 412) is the height of the conductive layer 411 ( The shape may be lower than the distance from the surface of the substrate 400 to the uppermost surface of the conductive layer 411). In the transistor 428, the upper end of the sidewall insulating layer 412 is in contact with the side surface of the conductive layer 411. In addition, in the transistors 426 and 428 shown in Figs. 7A and 7B, except for the size of the sidewall insulating layer 412, the same configuration as the transistor 420 shown in Figs. 1A and 1B can be used. have.

Further, when patterning the gate electrode layer 401 and/or when etching the conductive film 415 using the sidewall insulating layer 412 as a mask, depending on the etching treatment conditions, the gate insulating layer 402 is Some may be etched.

For example, in the transistor 430 shown in FIG. 7C, the gate insulating layer 402 is formed by etching treatment for forming the gate electrode layer 401 and etching treatment for forming the conductive layer 411, respectively. This is an example in which the film thickness is reduced, and the film thickness of the gate insulating layer 402 in the region overlapping the gate electrode layer 401 in the transistor 430 is thicker than the film thickness in the region overlapping the conductive layer 411. Further, the film thickness of the gate insulating layer 402 in the region overlapping the conductive layer 411 is greater than the film thickness of the region not overlapping with the conductive layer 411 and not overlapping with the gate electrode layer 401.

In addition, the present embodiment is not limited to this, for example, a partial region of the gate insulating layer 402 by an etching treatment for forming the gate electrode layer 401 (a region that does not overlap with the gate electrode layer 401) The film thickness of the gate insulating layer 402 is decreased in some cases, and the film thickness of the gate insulating layer 402 is not decreased due to the etching treatment for forming the conductive layer 411.

In the transistor described in this embodiment, after forming an impurity region in the oxide semiconductor layer 403 in a self-aligning manner using the gate electrode layer 401 as a mask, the transistor is in contact with the side surface of the gate electrode layer 401, and is In the conductive layer 411 overlapping the source electrode layer 405a and the drain electrode layer 405b is formed. Accordingly, the Lov region can be formed while maintaining a fine channel length, thereby providing a transistor having a fine structure in which a decrease in on current is suppressed.

In addition, the conductive layer 411 functioning as a part of the gate electrode layer 401 is self-aligning with the insulating layer 416 formed on the gate electrode layer 401 with the conductive film 415 interposed therebetween. After processing, it is formed by etching the conductive film 415 using the sidewall insulating layer as a mask, and since an etching process using a resist mask is not used, precise processing can be accurately performed. Therefore, in the manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape or characteristic can be manufactured with good yield.

As described above, the configurations and methods described in this embodiment can be used in appropriate combination with the configurations and methods described in other embodiments.

(Embodiment 3)

In the present embodiment, an example of a semiconductor device in which the transistor described in the present specification is used and the memory contents can be maintained even in a state where no power is supplied, and the number of writes is not limited will be described with reference to the drawings.

8A to 8C are examples of the configuration of a semiconductor device. 8A is a cross-sectional view of the semiconductor device, FIG. 8B is a plan view of the semiconductor device, and FIG. 8C is a circuit diagram of the semiconductor device. Here, FIG. 8A corresponds to the cross section at C1-C2 and D1-D2 in FIG. 8B.

The semiconductor device shown in Figs. 8A and 8B has a transistor 160 using a first semiconductor material at the bottom, and a transistor 162 using a second semiconductor material at the top. As the transistor 162, the transistor of one embodiment of the present invention described in the first or second embodiment can be applied. In this embodiment, an example in which the structure of the transistor 420 described in Embodiment 1 is applied as the transistor 162 will be described.

Here, it is preferable that the first semiconductor material and the second semiconductor material be made of materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (silicon or the like), and the second semiconductor material can be an oxide semiconductor. Transistors using materials other than oxide semiconductors are easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can maintain charge over a long period of time due to its characteristics.

Incidentally, both of the transistors are described as n-channel transistors, but it goes without saying that a p-channel transistor can be used. In addition, in addition to the case of using as the transistor 162 a transistor as described in Embodiment 1 or Embodiment 2 in which an oxide semiconductor is used to retain information, semiconductor devices such as materials used in semiconductor devices and structures of semiconductor devices, etc. It is not necessary to limit the specific configuration of the to what is described here.

The transistor 160 shown in FIG. 8A includes a channel formation region 116 provided on a substrate 100 including a semiconductor material (eg, silicon, etc.), and an impurity region 120 provided to sandwich the channel formation region 116. ), an intermetallic compound region 124 in contact with the impurity region 120, a gate insulating layer 108 provided over the channel formation region 116, and a gate electrode layer 110 provided over the gate insulating layer 108. . In addition, although the source electrode layer and the drain electrode layer are not clearly shown in the drawings, for convenience, such a state is sometimes referred to as a transistor. In addition, in this case, in order to describe the connection relationship between the transistors, the source electrode layer or the drain electrode layer including the source region and the drain region may be expressed in some cases. That is, in the description of the source electrode layer in the present specification, the source region may be included.

A device isolation insulating layer 106 is formed on the substrate 100 to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are formed to cover the transistor 160. Further, in the transistor 160, a sidewall insulating layer (sidewall insulating layer) may be provided on the side surface of the gate electrode layer 110, and an impurity region 120 including regions having different impurity concentrations may be formed.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, by using the transistor as a read transistor, information can be read out at high speed. In this embodiment, two insulating films are formed so as to cover the transistor 160. However, the insulating film may have a single-layer structure or may be laminated with three or more layers. As a process before forming the transistor 162 and the capacitive element 164, a CMP process is performed on the insulating film formed on the transistor 160 to form the planarized insulating layer 128 and the insulating layer 130, and at the same time, the gate electrode layer Expose the top surface of (110).

The insulating layer 128 and the insulating layer 130 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxide nitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and an aluminum nitride oxide film. An inorganic insulating film such as a film can be used. The insulating layer 128 and the insulating layer 130 can be formed using a plasma CVD method, a sputtering method, or the like.

In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition, a low dielectric constant material (low-k material) or the like can be used in addition to the organic material. In the case of using an organic material, the insulating layer 128 and the insulating layer 130 may be formed by a wet method such as a spin coating method or a printing method.

In this embodiment, a silicon nitride film is used as the insulating layer 128 and a silicon oxide film is used as the insulating layer 130.

On the surface of the insulating layer 130, it is preferable to perform a planarization treatment on a region in which the oxide semiconductor layer 144 is formed. In this embodiment, the oxide semiconductor layer (preferably, the average surface roughness of the surface of the insulating layer 130 is 0.15 nm or less) is sufficiently flattened by a polishing treatment (e.g., CMP treatment) on the insulating layer 130. 144).

The transistor 162 shown in Fig. 8A is a transistor in which an oxide semiconductor is used in a channel formation region. Here, it is preferable that the oxide semiconductor layer 144 included in the transistor 162 is highly purified. By using the highly purified oxide semiconductor, the transistor 162 having very excellent off characteristics can be obtained.

Since the transistor 162 has a very small off current, it is possible to retain the memory contents for a long period by using this. That is, since the refresh operation is not necessary or the semiconductor memory device in which the frequency of the refresh operation is very small can be used, power consumption can be sufficiently reduced.

The transistor 162 includes an oxide semiconductor layer 144 including a pair of impurity regions and a channel formation region, and an electrode layer 142a and an electrode layer 142b in contact with a side surface of the oxide semiconductor layer 144 in the channel length direction in the impurity region. Has. Accordingly, the contact resistance between the oxide semiconductor layer 144 and the electrode layer 142a or the electrode layer 142b can be reduced, thereby improving the on-state current of the transistor 162.

In addition, the transistor 162 includes a conductive layer 137a and a conductive layer 137b on side surfaces of the gate electrode layer 148 in the channel length direction, so that the conductive layer 137a and the conductive layer 137b are gate insulating layers. Since it overlaps with the electrode layer 142a or the electrode layer 142b via 146, a transistor having a Lov region can be used, and a decrease in the on-state current of the transistor 162 can be suppressed.

Further, the conductive layer 137a and the conductive layer 137b are formed by using the sidewall insulating layer 138a and the sidewall insulating layer 138b as masks, respectively. Since the conductive layer 137a and the conductive layer 137b are thin enough that coverage defects by sputtering do not become a problem, in the transistor 162, due to the conductive layer 137a and the conductive layer 137b. The occurrence of leakage current can be suppressed.

On the transistor 162, an insulating layer 132, an insulating layer 135, and an insulating layer 150 are formed as a single layer or a stack. In this embodiment, an aluminum oxide film is used as the insulating layer 132 and the insulating layer 150. When the aluminum oxide film has a high density (film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), stable electrical characteristics can be provided to the transistor 162.

In addition, a conductive layer 153 is formed in a region overlapping with the electrode layer 142a of the transistor 162 through the gate insulating layer 146, the electrode layer 142a, the gate insulating layer 146, and the conductive layer. The capacitive element 164 is composed of the layer 153. That is, the electrode layer 142a of the transistor 162 functions as one electrode of the capacitor element 164, and the conductive layer 153 functions as the other electrode of the capacitor element 164. In addition, when the capacitor is not required, the capacitor 164 may be configured not to be formed. Further, the capacitor 164 may be formed separately above the transistor 162.

In this embodiment, the conductive layer 153 can be formed by the same manufacturing process as the gate electrode layer 148 of the transistor 162. In the process of forming the conductive layer 137a, the conductive layer 137b, the sidewall insulating layer 138a, and the sidewall insulating layer 138b on the side surface of the gate electrode layer 148, the same applies to the side surface of the conductive layer 153 A conductive layer or a sidewall insulating layer may be formed.

A wiring 156 for connecting the transistor 162 and other transistors is formed on the insulating layer 150. The wiring 156 is electrically connected to the electrode layer 142b through an electrode layer 136 formed in an opening formed in the insulating layer 150, the insulating layer 135, the insulating layer 132, and the gate insulating layer 146.

8A and 8B, the transistor 160 and the transistor 162 are formed to overlap at least a portion, and the source region or the drain region of the transistor 160 and a portion of the oxide semiconductor layer 144 are formed to overlap each other. It is desirable. In addition, the transistor 162 and the capacitor 164 are formed to overlap at least a portion of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is formed by overlapping at least a portion of the gate electrode layer 110 of the transistor 160. By employing such a planar layout, since the area occupied by the semiconductor device can be reduced, high integration can be achieved.

Further, the electrode layer 142b and the wiring 156 may be electrically connected by directly contacting the electrode layer 142b and the wiring 156 without forming the electrode layer 136. Further, a plurality of conductive layers may be interposed therebetween.

In addition, an example of the circuit configuration corresponding to Figs. 8A and 8B is shown in Fig. 8C.

In FIG. 8C, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode layer of the transistor 160 are electrically connected. In addition, the third wiring (3rd Line) and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected. . In addition, the other of the gate electrode layer of the transistor 160 and the source electrode layer and the drain electrode layer of the transistor 162 is electrically connected to one electrode of the capacitor element 164, and the fifth wiring (5th Line) and the capacitor element ( The other electrode of 164) is electrically connected.

In the semiconductor device shown in Fig. 8C, by taking advantage of the feature that the potential of the gate electrode layer of the transistor 160 can be maintained, information can be recorded, retained, and read as follows.

The recording and maintenance of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. Thereby, the potential of the third wiring is supplied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is provided to the gate electrode layer of the transistor 160 (write). Here, it is assumed that one of the charges providing the other two potential levels (hereinafter referred to as a low level charge and a high level charge) is provided. Thereafter, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the electric charge provided to the gate electrode layer of the transistor 160 is held (maintained).

Since the off current of the transistor 162 is very small, the charge of the gate electrode layer of the transistor 160 is maintained over a long period of time.

Next, reading of information will be described. When a predetermined potential (positive potential) is provided to the first wiring and an appropriate potential (read potential) is provided to the fifth wiring, the second wiring is reduced according to the amount of charge held in the gate electrode layer of the transistor 160. The potential is different. In general, when the transistor 160 is of an n-channel type, the estimated threshold value V _{th_H} when a high level charge is provided to the gate electrode layer of the transistor 160 is a low level charge at the gate electrode layer of the transistor 160. This is because it is lower than _{the estimated threshold Vth_L} in the case where it is provided.

Here, the estimated threshold voltage refers to the potential of the fifth wiring required to turn the transistor 160 into the "on state". Therefore, by setting the potential of the fifth wiring to the potential V _{0 between V th_H} and V _{th_L} , the charge provided to the gate electrode layer of the transistor 160 can be discriminated. For example, in the case where high-level electric charges are provided during recording, when the potential of the fifth wiring becomes V ₀ (> V _{th_H} ), the transistor 160 is in the "on state". When a low-level charge is provided, even when the potential of the fifth wiring becomes V ₀ (<V _{th_L} ), the transistor 160 is in the "off state". Accordingly, information held by the potential of the second wiring can be read.

In addition, in the case of arranging and using memory cells in an array shape, it is necessary to be able to read only information of a desired memory cell. In the case where information is not read in this way, a potential at which the transistor 160 becomes "off state", that is, a potential _{lower than Vth_H} , may be provided to the fifth wiring regardless of the state of the gate electrode layer. Alternatively, a potential at which the transistor 160 becomes "on state", that is, a potential _{greater than Vth_L} may be provided to the fifth wiring regardless of the state of the gate electrode layer.

In the semiconductor device described in the present embodiment, the memory contents can be retained for a very long time by applying a transistor with an extremely small off-current using an oxide semiconductor to the channel formation region. That is, it is not necessary to perform the refresh operation, or since the frequency of the refresh operation can be made extremely low, power consumption can be sufficiently reduced. Further, even when no electric power is supplied (however, it is preferable that the potential be fixed), the contents of the memory can be maintained over a long period of time.

Further, in the semiconductor device described in the present embodiment, a high voltage is not required for recording information, and there is no problem of deterioration of the element. For example, as in a conventional nonvolatile memory, since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, there is no problem of deterioration of the gate insulating layer. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of times rewritable, which is a problem in the conventional nonvolatile memory, and reliability is drastically improved. Further, since information is recorded by switching the on-state and off-state of the transistor, high-speed operation can be easily realized.

As described above, it is possible to provide a semiconductor device that realizes miniaturization and high integration, and is provided with high electrical properties, and a method of manufacturing the semiconductor device.

As described above, the configurations and methods described in this embodiment can be used in appropriate combination with the configurations and methods described in other embodiments.

(Embodiment 4)

In this embodiment, the memory contents can be retained even when the transistor described in the first embodiment or the second embodiment is used and no power is supplied, and the configuration described in the third embodiment of the semiconductor device having no limitation on the number of writes and Different configurations will be described with reference to Figs. 9A to 10B.

9A is a diagram showing an example of a circuit configuration of a semiconductor device, and FIG. 9B is a conceptual diagram showing an example of a semiconductor device. First, the semiconductor device shown in Fig. 9A will be described, and then the semiconductor device shown in Fig. 9B will be described below.

In the semiconductor device shown in FIG. 9A, the bit line BL and the source electrode layer or the drain electrode layer of the transistor 162 are electrically connected, the word line WL and the gate electrode layer of the transistor 162 are electrically connected, and the transistor 162 The source electrode layer or the drain electrode layer of) and the first terminal of the capacitor 254 are electrically connected.

Next, a case where information is recorded and information is retained in the semiconductor device (memory cell 250) shown in Fig. 9A will be described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. Thereby, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (write). Thereafter, the potential of the word line WL is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off to maintain the potential of the first terminal of the capacitor element 254 (hold).

The transistor 162 using the oxide semiconductor has a feature that the off current is very small. Accordingly, by turning the transistor 162 off, the potential of the first terminal of the capacitor element 254 (or the charge accumulated in the capacitor element 254) can be maintained over a very long period of time.

Next, reading of information will be described. When the transistor 162 is turned on, the floating state bit line BL and the capacitor element 254 conduct, and charges are redistributed between the bit line BL and the capacitor element 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor element 254 (or the electric charge accumulated in the capacitor element 254).

For example, the potential of the first terminal of the capacitive element 254 is V, the capacity of the capacitive element 254 is C, the capacitance component of the bit line BL (hereinafter, also referred to as bit line capacity) is CB, and the charge is redistributed. If the potential of the bit line BL before the conversion is set to VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V)/(CB+C). Therefore, if the potential of the first terminal of the capacitor 254 as the state of the memory cell 250 has two states of V1 and V0 (V1>V0), the potential of the bit line BL when the potential V1 is maintained ( =(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the bit line BL when the potential V0 is maintained (=(CB×VB0+C×V0)/(CB+C)). I can see that.

Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read.

As described above, since the semiconductor device shown in FIG. 9A has a characteristic that the off current of the transistor 162 is very small, the charge accumulated in the capacitor element 254 can be maintained over a long period of time. That is, it is not necessary to perform the refresh operation, or since the frequency of the refresh operation can be made extremely low, power consumption can be sufficiently reduced. In addition, even when there is no power supply, the stored contents can be maintained over a long period of time.

Next, the semiconductor device shown in Fig. 9B will be described.

The semiconductor device shown in FIG. 9B has a memory cell array 251a and a memory cell array 251b having a plurality of memory cells 250 shown in FIG. 9A as a memory circuit at the top, and a memory cell array 251 at the bottom. ) (Memory cell array 251a and memory cell array 251b). Further, the peripheral circuit 253 is electrically connected to the memory cell array 251.

By setting it as the structure shown in FIG. 9B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (memory cell array 251a and memory cell array 251b), thereby achieving miniaturization of the semiconductor device. I can.

It is more preferable that the transistor formed in the peripheral circuit 253 use a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenic can be used, and it is preferable to use a single crystal semiconductor. In addition, an organic semiconductor material or the like may be used. Transistors using such semiconductor materials are capable of sufficient high-speed operation. Accordingly, various circuits (logical circuits, driving circuits, etc.) requiring high-speed operation can be suitably realized by the transistor.

In addition, in the semiconductor device shown in Fig. 9B, the configuration in which two memory cell arrays 251 (memory cell array 251a and memory cell array 251b) are stacked is illustrated, but the number of memory cell arrays to be stacked is this. It is not limited to Three or more memory cell arrays may be stacked.

Next, a specific configuration of the memory cell 250 shown in Fig. 9A will be described with reference to Figs. 10A and 10B.

10A and 10B are examples of the configuration of the memory cell 250. A cross-sectional view of the memory cell 250 is shown in FIG. 10A and a plan view of the memory cell 250 is shown in FIG. 10B. Here, FIG. 10A corresponds to the cross section in F1-F2 and G1-G2 of FIG. 10B.

The transistor 162 shown in Figs. 10A and 10B can employ the configuration described in the first or second embodiment. In this embodiment, an example in which the same configuration as the transistor 420 in Figs. 1A and 1B is used will be described.

A conductive layer 262 is formed in a region overlapping the electrode layer 142a of the transistor 162 through the gate insulating layer 146, and the electrode layer 142a, the gate insulating layer 146, and the conductive layer 262 are formed. ), the capacitive element 254 is configured. That is, the electrode layer 142a of the transistor 162 functions as one electrode of the capacitor element 254, and the conductive layer 262 functions as the other electrode of the capacitor element 254.

On the transistor 162 and the capacitor 254, an insulating layer 132, an insulating layer 135, and an insulating layer 256 are formed in a single layer or a stack. Further, on the insulating layer 256, a memory cell 250 and a wiring 260 for connecting the memory cell 250 adjacent to the memory cell are formed. The wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 through openings formed in the insulating layer 256, the insulating layer 135, the insulating layer 132, the gate insulating layer 146, and the like. However, the wiring 260 and the electrode layer 142b may be directly connected. Further, the wiring 260 corresponds to the bit line BL in the circuit diagram of Fig. 9A.

10A and 10B, the electrode layer 142b of the transistor 162 may also function as a source electrode layer of a transistor included in an adjacent memory cell. By employing such a planar layout, since the area occupied by the semiconductor device can be reduced, high integration can be achieved.

A plurality of memory cells formed in multiple layers are formed by transistors using oxide semiconductors. Since the transistor using the oxide semiconductor has a small off current, the memory contents can be retained over a long period of time by using this transistor. That is, since the frequency of the refresh operation can be made very low, power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, a transistor with a sufficiently small off current) are used. By integrally providing the memory circuit, it is possible to realize a semiconductor device having characteristics that have not been possible. In addition, the semiconductor device can be integrated by forming a stacked structure of the peripheral circuit and the memory circuit.

As described above, it is possible to provide a semiconductor device that realizes miniaturization and high integration, and is provided with high electrical properties, and a method of manufacturing the semiconductor device.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)

In the present embodiment, an example in which the semiconductor device described in the above-described embodiment is applied to a portable device such as a mobile phone, a smartphone, and an electronic book will be described with reference to FIGS. 11A to 14.

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, there are the following features.

In a typical SRAM, as shown in Fig. 11A, one memory cell is composed of six transistors of transistors 801 to 806, which are driven by the X decoder 807 and the Y decoder 808. The transistor 803 and the transistor 805, and the transistor 804 and the transistor 806 constitute an inverter and enable high-speed driving. However, since one memory cell is composed of six transistors, there is a drawback in that the cell area is large. When the minimum dimension of the design rule is F, the memory cell area of the SRAM is usually 100F ² to 150F ² . As a result, SRAM is the most expensive among various types of memory in unit cost per bit.

On the other hand, in DRAM, a memory cell is composed of a transistor 811 and a storage capacitor 812, as shown in Fig. 11B, which is driven by the X decoder 813 and the Y decoder 814. Since one cell is composed of one transistor and one capacitor, the area is small. DRAM's memory cell area is usually 10F ² or less. However, since the DRAM always needs to perform a refresh operation, power is consumed even while not being rewritten.

However, the memory cell area of the semiconductor device described in the above-described embodiment is ^{around 10F 2} , and frequent refreshing is not required. Accordingly, the memory cell area can be reduced and power consumption can be reduced.

12 is a block diagram of a portable device. The portable device shown in FIG. 12 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, and a flash memory. 910, a display controller 911, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, and the like. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 has a CPU 907, a DSP 908, and an interface (IF) 909. In general, the memory circuit 912 is composed of SRAM or DRAM, and by employing the semiconductor device described in the above-described embodiment for this portion, information is written and read at high speed, and the memory can be maintained over a long period of time, Moreover, power consumption can be sufficiently reduced.

13 shows an example in which the semiconductor device described in the above-described embodiment is used for the memory circuit 950 of the display. The memory circuit 950 shown in FIG. 13 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. Further, the memory circuit 950 is a display controller 956 that reads and controls image data (input image data) input from the signal line, the memory 952, and data (stored image data) stored in the memory 953. ) And a display 957 displayed by a signal from the display controller 956 are connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. Then, the image data (stored image data A) stored in the memory 952 is transmitted to the display 957 through the switch 955 and the display controller 956 for display.

When the input image data A is not changed, the stored image data A is read from the memory 952 via the switch 955 by the display controller 956 at a period of about 30 Hz to 60 Hz.

Next, for example, when the user performs a rewrite operation of the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this period, the stored image data A is periodically read from the memory 952 via the switch 955. After all new image data (memory image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and displayed through the switch 955 and the display controller 956. The stored image data B is transferred to 957 and displayed. This read operation continues until another image data is stored in the memory 952.

In this way, the memory 952 and the memory 953 alternately write image data and read image data to display the display 957. In addition, the memory 952 and the memory 953 are not limited to each other, and one memory may be divided and used. By employing the semiconductor device described in the above-described embodiment in the memory 952 and memory 953, information can be written and read at high speed, storage can be maintained for a long period of time, and power consumption can be sufficiently reduced. .

14 shows a block diagram of an electronic book. The electronic book shown in FIG. 14 includes a battery 1001, a power circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, and a touch panel. It consists of a display 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in the above-described embodiment can be used for the memory circuit 1007 of FIG. 14. The memory circuit 1007 has a function of temporarily holding the contents of a book. As an example of the function, there is a case where the user uses the highlight function. When a user is reading an electronic book, there are cases where he or she wants to mark a specific part. This marking function is called a highlight function, and the difference from the surroundings is indicated by changing the color of the display, drawing an underline, making the character thicker, changing the font of the character, and the like. This is a function that stores and retains information of a location designated by the user. When this information is held over a long period of time, it may be copied to the flash memory 1004. Even in such a case, by employing the semiconductor device described in the above-described embodiment, information can be recorded and read at high speed, storage can be maintained over a long period of time, and power consumption can be sufficiently reduced.

As described above, the semiconductor device according to the above-described embodiment is mounted in the portable device according to the present embodiment. Accordingly, a portable device in which reading is performed at high speed, storage can be maintained over a long period of time, and power consumption is reduced is realized.

The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, methods, and the like described in other embodiments.

(Example)

In this embodiment, it is possible to obtain the shape of the gate electrode layer and the conductive layer formed on the side surface of the gate electrode layer as described in Embodiment 1 by processing the conductive film by applying the method of manufacturing a semiconductor device of one embodiment of the present invention. Confirmed.

Hereinafter, a method of preparing an example sample is described.

First, a silicon substrate was prepared, and a silicon nitride oxide film was formed on the substrate by a CVD method so as to have a thickness of 20 nm. Since the silicon nitride oxide film corresponds to the gate insulating layer of the transistor according to one embodiment of the present invention, it is referred to as a gate insulating layer in the present embodiment below.

Next, a conductive film was formed on the gate insulating layer. As a conductive film, a tantalum nitride film having a thickness of 30 nm was formed by a sputtering method having a pressure of 0.6 Pa and a power supply power of 1 kW in a mixed atmosphere of _{argon and nitrogen (Ar:N 2 =50 sccm:10 sccm), and having a film thickness of 135 nm thereon.} The tungsten film was formed by sputtering under an argon (Ar = 100 sccm) atmosphere with a pressure of 2.0 Pa and a power supply power of 4 kW.

Next, using an ICP (Inductively Coupled Plasma: Inductively Coupled Plasma) etching method, under a _{mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (Cl 2} : CF ₄ : O ₂ =45 sccm: 55 sccm: 55 sccm), power supply power 3 kW , The tungsten film was etched under the conditions of 50 W of bias power and 0.67 Pa of pressure to form a patterned tungsten layer.

_{Next, the tantalum nitride film was etched in a chlorine (Cl 2} =100 sccm) atmosphere under the conditions of a power supply power of 1 kW, a bias power of 60 W, and a pressure of 0.2 Pa using an ICP etching method to form a patterned tantalum nitride layer. Since the laminated structure of the tantalum nitride layer and the tungsten layer corresponds to the gate electrode layer of the transistor according to one embodiment of the present invention, it is referred to as the gate electrode layer in the present embodiment below.

Next, a tungsten film having a thickness of 30 nm was formed so as to cover the gate electrode layer by using a sputtering method. In an argon (Ar = 50 sccm) atmosphere, a pressure of 0.6 Pa and a power supply of 1 kW were used as film formation conditions.

Next, a silicon nitride oxide film having a thickness of 150 nm was formed on the tungsten film by using the CVD method.

Next, the silicon nitride oxide film was etched using the ICP etching method under the conditions of a trifluoromethane and helium (CHF ₃ :He=30 sccm:120 sccm) mixed atmosphere, a power supply power of 3 kW, a bias power of 200 W, and a pressure of 2.0 Pa. I did. Since the silicon nitride oxide layer obtained by the etching treatment corresponds to the sidewall insulating layer of the transistor according to one embodiment of the present invention, it is referred to as a sidewall insulating layer in the present embodiment below.

Next, using the sidewall insulating layer as a mask and using the ICP etching method, under a _{mixed atmosphere of carbon tetrafluoride, chlorine and oxygen (CF 4} :Cl ₂ :O ₂ =50 sccm: 50 sccm: 20 sccm), power supply power 500 W, bias power By etching the tungsten film under conditions of 10 W and a pressure of 1.6 Pa, a conductive layer (tungsten layer in this embodiment) was formed on the side surface of the gate electrode layer.

Fig. 15 shows a cross-sectional photograph (cross-sectional STEM photograph) of an example sample prepared using the above method by a Scanning Transmission Electron Microscopy (STEM).

15, it was confirmed that the shape of the gate electrode layer described in Embodiment 1 and the conductive layer formed on the side surface of the gate electrode layer were obtained using the fabrication method described in this example.

In addition, in the example sample, the height of the sidewall insulating layer (distance from the substrate surface to the uppermost surface of the sidewall insulating layer) is lower than the height of the conductive layer (distance from the substrate surface to the uppermost surface of the conductive layer), as shown in FIG. 7B. In addition, in FIG. 15, the film thickness of the gate insulating layer in the region overlapping the gate electrode layer is thicker than the film thickness in the region overlapping the conductive layer. Specifically, in the example sample, the thickness of the gate insulating layer in the region overlapping the gate electrode layer was 17.9 nm, and the thickness of the gate insulating layer in the region overlapping the conductive layer was 11.2 nm. It can be considered that the reason for this is that the gate insulating layer was also etched when the gate electrode layer was etched.

Further, the side end portion of the conductive layer of the example sample is retracted from the side end portion of the sidewall insulating layer in the channel length direction. However, the technical idea of the described invention lies in that the Lov region is formed in a transistor having a fine structure without using a photolithography process by etching the conductive layer using the sidewall insulating layer formed by self-alignment as a mask. Therefore, in the case of etching using the same mask (or etching the lower layer using a certain layer as a mask), the difference in the degree of deviation at the end caused by the etching conditions, etc., is sufficiently allowed, and the etching treatment using the same mask above. The ends of each layer are to be coincident.

100: substrate
106: element isolation insulating layer
108: gate insulating layer
110: gate electrode layer
116: channel formation region
120: impurity region
124: intermetallic compound region
128: insulating layer
130: insulating layer
132: insulating layer
135: insulating layer
136: electrode layer
137a: conductive layer
137b: conductive layer
138a: sidewall insulating layer
138b: sidewall insulating layer
142a: electrode layer
142b: electrode layer
144: oxide semiconductor layer
146: gate insulating layer
148: gate electrode layer
150: insulating layer
153: conductive layer
156: wiring
160: transistor
162: transistor
164: capacitive element
250: memory cell
251: memory cell array
251a: memory cell array
251b: memory cell array
253: peripheral circuit
254: capacitive element
256: insulating layer
260: wiring
262: conductive layer
400: substrate
401: gate electrode layer
402: gate insulating layer
403: oxide semiconductor layer
403a: impurity region
403b: impurity region
403c: channel formation region
405: conductive film
405a: source electrode layer
405b: drain electrode layer
406: insulating layer
407: insulating layer
411: conductive layer
412: sidewall insulation layer
413: oxide semiconductor layer
415: conductive film
416: insulating layer
420: transistor
422: transistor
424: transistor
426: transistor
428: transistor
430: transistor
431: dopant
435a: wiring layer
435b: wiring layer
436: base insulation layer
801: transistor
803: transistor
804: transistor
805: transistor
806: transistor
807: X decoder
808: Y decoder
811: transistor
812: maintenance capacity
813: X decoder
814: Y decoder
901: RF circuit
902: analog baseband circuit
903: digital baseband circuit
904: battery
905: power circuit
906: application processor
907: CPU
908: DSP
909: interface
910: flash memory
911: display controller
912: memory circuit
913: display
914: display
915: source driver
916: gate driver
917: voice circuit
918: keyboard
919: touch sensor
950: memory circuit
951: memory controller
952: memory
953: memory
954: switch
955: switch
956: display controller
957: display
1001: battery
1002: power circuit
1003: microprocessor
1004: flash memory
1005: voice circuit
1006: keyboard
1007: memory circuit
1008: touch panel
1009: display
1010: display controller

Claims (20)

In a semiconductor device,
A source electrode layer and a drain electrode layer;
An oxide semiconductor layer including a first impurity region, a second impurity region, and a channel formation region sandwiched between the first and second impurity regions, the source electrode layer, the drain electrode layer, and an upper end portion of the oxide semiconductor layer. The oxide semiconductor layer, the planes being coplanar;
A gate insulating layer in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
A gate electrode layer over the gate insulating layer overlapping the channel formation region;
A conductive layer in contact with a side surface of the gate electrode layer;
A semiconductor device comprising a sidewall insulating layer in contact over the conductive layer. The method of claim 1,
A semiconductor device, wherein a side surface of the first impurity region in a channel length direction contacts the source electrode layer, and a side surface of the second impurity region in a channel length direction contacts the drain electrode layer. The method of claim 1,
The semiconductor device, wherein the conductive layer has an L-shape. The method of claim 1,
An insulating layer over the gate electrode layer, the sidewall insulating layer, and the gate insulating layer;
The semiconductor device further comprising a wiring on the insulating layer in contact with the source electrode layer or the drain electrode layer through openings provided in the insulating layer and the gate insulating layer. The method of claim 1,
The semiconductor device, wherein the oxide semiconductor layer comprises a material selected from indium, gallium, and zinc. The method of claim 1,
The semiconductor device, wherein the conductive layer comprises the same material as the gate electrode layer. The method of claim 1,
The semiconductor device, wherein the oxide semiconductor layer has a tapered shape. The method of claim 1,
The semiconductor device, wherein a thickness of the gate insulating layer in a region overlapping the gate electrode layer is greater than a thickness of the gate insulating layer in a region overlapping the conductive layer. The method of claim 1,
A semiconductor device, wherein a thickness of the gate insulating layer in a region overlapping with the conductive layer is greater than a thickness of the gate insulating layer in a region that does not overlap with the conductive layer and also does not overlap with the gate electrode layer. In the method of manufacturing a semiconductor device,
Forming a source electrode layer and a drain electrode layer;
Forming an oxide semiconductor layer covering the source electrode layer and the drain electrode layer;
Forming an opening in the oxide semiconductor layer by removing the oxide semiconductor layer in a region overlapping the source electrode layer and the drain electrode layer by a chemical mechanical polishing method;
Processing the oxide semiconductor layer having the opening into an island-shaped oxide semiconductor layer provided between the source electrode layer and the drain electrode layer;
Forming a gate insulating layer on the island-shaped oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
Forming a gate electrode layer overlapping the island-shaped oxide semiconductor layer on the gate insulating layer;
Forming a first impurity region and a second impurity region in the island-shaped oxide semiconductor layer by introducing impurities into the island-shaped oxide semiconductor layer using the gate electrode layer as a mask;
Forming a conductive film on the gate insulating layer and the gate electrode layer;
Forming an insulating layer on the conductive film;
Processing the insulating layer to form a sidewall insulating layer in contact with a side surface of the conductive layer and not in contact with the gate electrode layer;
Forming a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer by etching the conductive film using the sidewall insulating layer as a mask,
A method of manufacturing a semiconductor device, wherein at least a portion of the second portion overlaps the first impurity region and the second impurity region. The method of claim 10,
The oxide semiconductor layer comprises a material selected from indium, gallium, and zinc. In the method of manufacturing a semiconductor device,
Forming an island-shaped oxide semiconductor layer;
Forming a first conductive film covering the island-shaped oxide semiconductor layer;
Forming an opening in the first conductive film by removing the first conductive film in a region overlapping the island-shaped oxide semiconductor layer by a chemical mechanical polishing method;
Forming a source electrode layer and a drain electrode layer by processing the first conductive film having the opening;
Forming a gate insulating layer on the island-shaped oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
Forming a gate electrode layer overlapping the island-shaped oxide semiconductor layer on the gate insulating layer;
Forming a first impurity region and a second impurity region in the island-shaped oxide semiconductor layer by introducing impurities into the island-shaped oxide semiconductor layer using the gate electrode layer as a mask;
Forming a second conductive film on the gate insulating layer and the gate electrode layer;
Forming an insulating layer on the second conductive layer;
Processing the insulating layer to form a sidewall insulating layer in contact with a side surface of the second conductive layer and not in contact with the gate electrode layer;
Forming a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer by etching the second conductive layer using the sidewall insulating layer as a mask,
A method of manufacturing a semiconductor device, wherein at least a portion of the second portion overlaps the first impurity region and the second impurity region. The method of claim 10 or 12,
A method of manufacturing a semiconductor device, wherein a side end portion of the second portion coincides with a side end portion of the sidewall insulating layer. The method of claim 10 or 12,
The method of manufacturing a semiconductor device, wherein the conductive layer has an L-shape. The method of claim 10 or 12,
Forming an interlayer insulating layer on the gate electrode layer, the sidewall insulating layer, and the gate insulating layer;
The method of manufacturing a semiconductor device further comprising the step of forming a wiring on the interlayer insulating layer in contact with the source electrode layer or the drain electrode layer through openings provided in the interlayer insulating layer and the gate insulating layer. The method of claim 12,
The island-shaped oxide semiconductor layer comprises a material selected from indium, gallium, and zinc. The method of claim 10 or 12,
The method of manufacturing a semiconductor device, wherein the conductive layer contains the same material as the gate electrode layer. The method of claim 10 or 12,
The method of manufacturing a semiconductor device, wherein the island-shaped oxide semiconductor layer has a tapered shape. The method of claim 10 or 12,
A method of manufacturing a semiconductor device, wherein a thickness of the gate insulating layer in a region overlapping with the gate electrode layer is greater than a thickness of the gate insulating layer in a region overlapping with the conductive layer. The method of claim 10 or 12,
A method of manufacturing a semiconductor device, wherein a thickness of the gate insulating layer in a region overlapping with the conductive layer is greater than a thickness of the gate insulating layer in a region that does not overlap with the conductive layer and also does not overlap with the gate electrode layer.

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