JP2017112390A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using an oxide semiconductor, which achieves scaling while maintaining good electrical characteristics.SOLUTION: A transistor including an oxide semiconductor layer, a gate insulation layer which contacts the oxide semiconductor layer and a gate electrode layer which overlaps the oxide semiconductor layer via the gate insulation layer comprises an insulation layer which contacts a top face of the gate insulation layer and a lateral face of the gate electrode layer, and which has oxygen permeability lower than that of the gate insulation layer. Further, a film thickness of the insulation layer in a region contacting the top face of the gate insulation layer is larger than a film thickness of the insulation layer in a region contacting a lateral face of the gate electrode layer.SELECTED DRAWING: Figure 1

Description

One embodiment of the disclosed invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor material has attracted attention as another material.

For example, a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

JP 2007-123861 A JP 2007-96055 A

By the way, in order to achieve high-speed operation of the transistor, low power consumption of the transistor, low price, and the like, it is important to miniaturize the transistor.

In the case of manufacturing a transistor using an oxide semiconductor, oxygen vacancies can be given as a supply source of carriers of the oxide semiconductor. If there are many oxygen vacancies in the oxide semiconductor including the channel formation region of the transistor, electrons are generated in the channel formation region, which causes the threshold voltage of the transistor to fluctuate in the negative direction. Therefore, a semiconductor device using an oxide semiconductor is required to take measures to reduce oxygen vacancies in the oxide semiconductor.

In view of the above problems, an embodiment of the present invention is a semiconductor device including an oxide semiconductor,
Another object is to provide a semiconductor device that achieves miniaturization while maintaining good electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor layer. Another object is to provide a method for manufacturing the semiconductor device.

One embodiment of the invention disclosed in this specification and the like is a transistor including an oxide semiconductor layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping with the oxide semiconductor layer through the gate insulating layer. An insulating layer having a lower permeability to oxygen than the gate insulating layer (having a barrier property to oxygen) is provided in contact with the upper surface of the gate insulating layer and the side surface of the gate electrode layer. In the insulating layer, the thickness of the region in contact with the upper surface of the gate insulating layer is larger than the thickness of the region in contact with the side surface of the gate electrode layer.

By providing the insulating layer having a barrier property against oxygen in contact with the gate insulating layer, desorption of oxygen from the gate insulating layer can be suppressed. Since the gate insulating layer is an insulating layer in contact with the channel formation region of the oxide semiconductor layer, the oxide semiconductor caused by oxygen vacancies contained in the gate insulating layer is suppressed by suppressing release of oxygen from the gate insulating layer. Extraction of oxygen from the layer can be suppressed, and as a result, oxygen vacancies in the oxide semiconductor layer can be suppressed.

The gate insulating layer preferably includes a region containing oxygen in excess of the stoichiometric composition (hereinafter also referred to as an oxygen-excess region). Since the gate insulating layer in contact with the oxide semiconductor layer has an oxygen-excess region, oxygen can be supplied to the oxide semiconductor layer, so that desorption of oxygen from the oxide semiconductor layer is prevented and It becomes possible to compensate for oxygen deficiency.

In the above, the insulating layer in contact with the upper surface of the gate insulating layer and the side surface of the gate electrode layer functions as part of the sidewall insulating layer of the gate electrode layer. Here, the barrier property against oxygen to the gate insulating layer is maintained by configuring the insulating layer so that the thickness of the region in contact with the upper surface of the gate insulating layer is larger than the thickness of the region in contact with the side surface of the gate electrode layer. However, the width of the sidewall insulating layer can be reduced. Thus, the reliability and miniaturization of the transistor can be improved.

One embodiment of the present invention includes an oxide semiconductor layer, a gate insulating layer over the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween, an upper surface of the gate insulating layer, and the gate electrode A first insulating layer in contact with the side surface of the layer; a second insulating layer provided on the side surface of the gate electrode layer through the first insulating layer; and a source electrode layer electrically connected to the oxide semiconductor layer The first insulating layer is less permeable to oxygen than the gate insulating layer, and the thickness of the region of the first insulating layer in contact with the upper surface of the gate insulating layer is The semiconductor device is larger than the thickness of the region in contact with the side surface of the gate electrode layer.

Another embodiment of the present invention is an oxide semiconductor layer, a gate insulating layer over the oxide semiconductor layer,
A gate electrode layer overlapping with the oxide semiconductor layer through the gate insulating layer; a first insulating layer in contact with an upper surface of the gate insulating layer and a side surface of the gate electrode layer; and a gate electrode layer through the first insulating layer A second insulating layer provided on the side surface of the first insulating layer; and a second insulating layer provided in contact with the gate electrode layer;
A third insulating layer in contact with the first insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, and the first insulating layer transmits oxygen more than the gate insulating layer. In the first insulating layer, the thickness of the region in contact with the upper surface of the gate insulating layer is larger than the thickness of the region in contact with the side surface of the gate electrode layer.

In the above semiconductor device, the source electrode layer and the drain electrode layer include the first insulating layer and the second insulating layer.
May be in contact with the insulating layer.

In the above semiconductor device, the end portion of the gate insulating layer and the end portion of the first insulating layer and / or the end portion of the first insulating layer and the end portion of the second insulating layer substantially coincide with each other. .

In the above semiconductor device, in the oxide semiconductor layer, the thickness of the region in contact with the source electrode layer or the drain electrode layer is smaller than the thickness of the region in contact with the gate insulating layer.

Note that in an oxide semiconductor, hydrogen is a supply source of carriers in addition to oxygen vacancies. When hydrogen is contained in the oxide semiconductor, a donor is generated at a shallow level from the conduction band, and the resistance is reduced (n-type). Therefore, in the above semiconductor device, it is preferable to use an insulating layer having a lower permeability to hydrogen than the gate insulating layer in addition to a low permeability to oxygen as the first insulating layer. By using such an insulating layer, mixing of hydrogen or a hydrogen compound into the gate insulating layer and the oxide semiconductor layer in contact with the gate insulating layer can be suppressed, so that the reliability of the semiconductor device can be further improved.

An example of the insulating layer having low permeability to oxygen and hydrogen is an aluminum oxide film. Therefore, for example, an insulating layer including an aluminum oxide film can be used as the first insulating layer included in the semiconductor device.

In this specification and the like, the term “substantially match” is used in a sense that does not require exact matching. For example, the expression “substantially coincidence” includes the degree of coincidence in a shape obtained by etching a plurality of layers using the same mask.

According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor, which can be miniaturized while maintaining favorable electrical characteristics, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device including an oxide semiconductor layer and a manufacturing method thereof can be provided.

4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view, a cross-sectional view, and a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 14 is a perspective view illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. The cross-sectional TEM image of the sample produced in the Example.

Hereinafter, embodiments of the invention disclosed in the present invention will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, when referring to a portion having a similar function, the hatch pattern may be the same, and there may be no particular reference.

In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor layer is described as an example of a semiconductor device.

FIG. 1 illustrates a configuration example of the transistor 420. 1A is a plan view of the transistor 420, FIG. 1B is a cross-sectional view taken along X1-Y1 in FIG. 1A, and FIG.
It is sectional drawing in V1-W1 of FIG. 1 (A). Note that in FIG. 1A, some components of the transistor 420 (eg, the insulating layer 407 and the like) are not illustrated in order to avoid complexity.

A transistor 420 illustrated in FIG. 1 includes an oxide semiconductor layer 403 provided over a substrate 400,
The gate insulating layer 402 over the oxide semiconductor layer 403, the gate electrode layer 401 overlapping with the oxide semiconductor layer 403 with the gate insulating layer 402 interposed therebetween, and the insulating layer in contact with the top surface of the gate insulating layer 402 and the side surface of the gate electrode layer 401 A layer 411; an insulating layer 412 provided on a side surface of the gate electrode layer 401 with the insulating layer 411 provided therebetween; and a source electrode layer 405a and a drain electrode layer 405b which are electrically connected to the oxide semiconductor layer 403.

In the transistor 420, an insulating layer having a barrier property against oxygen is used as the insulating layer 411 in contact with the top surface of the gate insulating layer 402 and the side surface of the gate electrode layer 401. More specifically, an insulating layer having a lower oxygen permeability than the gate insulating layer 402 is used as the insulating layer 411. By providing an insulating layer having a barrier property against oxygen as the insulating layer 411, desorption of oxygen from the gate insulating layer 402 can be suppressed. Since the gate insulating layer 402 is an insulating layer in contact with the channel formation region of the oxide semiconductor layer 403, oxygen is not extracted from the oxide semiconductor layer 403 by suppressing desorption of oxygen from the insulating layer. And oxygen vacancies in the oxide semiconductor layer 403 can be suppressed.

In the insulating layer 411, the thickness of the region in contact with the upper surface of the gate insulating layer 402 is larger than the thickness of the region in contact with the side surface of the gate electrode layer 401. The insulating layer 411 functions as a side wall insulating layer of the gate electrode layer 401 together with the insulating layer 412. Therefore, the insulating layer 411
By reducing the thickness of the region in contact with the side surface of the gate electrode layer, the width of the sidewall insulating layer can be reduced, and the semiconductor device can be miniaturized. On the other hand, the insulating layer 41
1, the thickness of the region in contact with the upper surface of the gate insulating layer 402 is larger than the thickness of the region in contact with the side surface of the gate electrode layer. An effect can be obtained.

As the insulating layer 411, for example, aluminum, aluminum added with magnesium,
An oxide or a nitride such as aluminum, magnesium, or titanium to which titanium is added can be used in a single layer or stacked layers.

Note that as the insulating layer 411, it is more preferable to use a film having a low permeability to impurities such as hydrogen and moisture (a film having a lower permeability to hydrogen than the gate insulating layer 402) in addition to a barrier property to oxygen. As such a film, an aluminum oxide film can be preferably used. By using a film having low permeability to oxygen and hydrogen as the insulating layer 411, not only desorption of oxygen from the gate insulating layer 402 and the oxide semiconductor layer 403 is prevented, but also a factor of variation in electrical characteristics of the transistor can be obtained. The gate insulating layer 4 of impurities such as hydrogen and hydrogen compounds
02 and entry into the oxide semiconductor layer 403 can be suppressed.

In addition, the base insulating layer 436, the insulating layer 407, the insulating layer 414, and the source wiring layer 4 over the substrate 400 are used.
15a or the drain wiring layer 415b may be included in the constituent elements of the transistor 420.

The oxide semiconductor layer 403 included in the transistor 420 may include a non-single crystal.
The non-single crystal has, for example, a CAAC (C Axis Aligned Crystal), a polycrystal (also referred to as a polycrystal), a microcrystal, or an amorphous part. The amorphous part is a microcrystal,
The defect level density is higher than that of CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor including CAAC is formed using a CAAC-OS (C Axis Align
called “Ned Crystalline Oxide Semiconductor”.

For example, the oxide semiconductor layer 403 may include a CAAC-OS. For example, the CAAC-OS is c-axis oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

For example, the oxide semiconductor layer 403 may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor layer includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.

For example, the oxide semiconductor layer 403 may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. The amorphous oxide semiconductor layer has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor layer is, for example, completely amorphous and does not have a crystal part.

Note that the oxide semiconductor layer 403 may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film is, for example,
An amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a CAAC-OS region,
You may have the laminated structure of.

Note that the oxide semiconductor layer 403 may include a single crystal, for example.

The oxide semiconductor layer 403 preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor layer is a CAAC-OS film.

In most cases, a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 100 nm. In addition, a transmission electron microscope (TEM: Transmission El)
In the observation image by Electron Microscope), the boundary between the crystal part and the crystal part included in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, CAAC-O
In the S film, the decrease in electron mobility caused by the grain boundary is suppressed.

The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. When viewed from the direction, the metal atoms are arranged in a triangular shape or a hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, CAA
In the process of forming the C-OS film, in the case where crystal growth is performed from the surface side of the oxide semiconductor layer, the ratio of crystal parts in the vicinity of the surface may be higher in the vicinity of the formation surface. CA
When an impurity is added to the AC-OS film, the crystallinity of the crystal part in the impurity-added region may be lowered.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

A transistor 422 illustrated in FIG. 2 is a modification example of the transistor 420. FIG.
2B is a cross-sectional view taken along line X2-Y2 of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line V2-W2 of FIG. is there. Note that FIG.
In FIG. 5A, some components (eg, the insulating layer 407 and the like) of the transistor 422 are omitted in order to avoid complexity.

A transistor 422 illustrated in FIG. 2 includes an oxide semiconductor layer 403 provided over a substrate 400,
The gate insulating layer 402 over the oxide semiconductor layer 403, the gate electrode layer 401 overlapping with the oxide semiconductor layer 403 with the gate insulating layer 402 interposed therebetween, and the insulating layer in contact with the top surface of the gate insulating layer 402 and the side surface of the gate electrode layer 401 An insulating layer 412 provided on a side surface of the gate electrode layer 401 with the insulating layer 411 provided therebetween, an insulating layer 416 provided in contact with the gate electrode layer 401 and in contact with the insulating layer 411 on the side surface, and an oxide A source electrode layer 405a and a drain electrode layer 405b which are electrically connected to the semiconductor layer 403;

The transistor 422 can have a structure similar to that of the transistor 420 except that the transistor 422 includes the insulating layer 416. In the transistor 422, the insulating layer 416 functions as a hard mask when the gate electrode layer 401 is formed, so that the top surface of the gate electrode layer 401 can be protected. For the insulating layer 416, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used, and the insulating layer 416 is provided with a stacked structure or a single layer structure. In addition, by selecting an insulating layer whose etching rate is lower than that of the insulating layer 412, it is possible to function as an etching protective film that reduces the decrease in the thickness of the gate electrode layer 401 in the etching process for manufacturing the sidewall insulating layer.

Note that the insulating layer 416 may be formed using the same material as the insulating layer 411. In that case, the interface between the insulating layer 411 and the insulating layer 416 may be unclear (unclear).

An example of a method for manufacturing the transistor 420 will be described below with reference to FIGS.

A base insulating layer 436 is formed over the substrate 400 having an insulating surface.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance enough to withstand at least a later heat treatment step. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device having flexibility, the transistor 420 including the oxide semiconductor layer 403 may be directly formed over a flexible substrate, or the transistor including the oxide semiconductor layer 403 over another manufacturing substrate. 420 may be manufactured and then peeled off and transferred to a flexible substrate. Note that the transistor 420 including a manufacturing substrate and an oxide semiconductor layer is used for separation and transfer from the manufacturing substrate to a flexible substrate.
A release layer may be provided between the two.

The base insulating layer 436 can be formed by a plasma CVD method, a sputtering method, or the like, and includes a silicon oxide film, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, A single layer or a stacked layer structure of a film containing hafnium oxide, gallium oxide, or a mixed material thereof can be used. Note that the base insulating layer 436 has a single-layer structure or a stacked structure including an oxide insulating layer.
It is preferable that the oxide insulating layer be in contact with an oxide semiconductor layer 403 to be formed later. Note that the base insulating layer 436 is not necessarily provided.

The base insulating layer 436 preferably includes an oxygen-excess region because excess oxygen contained in the base insulating layer 436 can fill oxygen vacancies in the oxide semiconductor layer 403 to be formed later. In the case where the base insulating layer 436 has a stacked structure, it is preferable that at least a layer in contact with the oxide semiconductor layer 403 (preferably an oxide insulating layer) include an oxygen-excess region. In order to provide the oxygen excess region in the base insulating layer 436, for example, the base insulating layer 43 is formed in an oxygen atmosphere.
6 may be formed. Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the base insulating layer 436 after deposition to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

Further, the base insulating layer 436 is in contact with the lower side of the layer having an oxygen-excess region, and a silicon nitride film,
It is preferable to have a silicon nitride oxide film or an aluminum oxide film. Underlying insulating layer 436
Since the semiconductor includes a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film, diffusion of impurities into the oxide semiconductor layer 403 can be prevented.

Planarization treatment may be performed on a region where the oxide semiconductor layer 403 is in contact with the base insulating layer 436. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Reverse sputtering is RF on the substrate side in an argon atmosphere.
In this method, a voltage is applied using a power source to form plasma in the vicinity of the substrate to modify the surface.
Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the base insulating layer 436 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate depending on the unevenness state of the surface of the base insulating layer 436.

In addition, in order to reduce impurities such as hydrogen (including water and hydroxyl groups) and to be in an oxygen-excess state in the base insulating layer 436, hydrogen (including water and hydroxyl groups) is removed (dehydrated) in the base insulating layer 436. Alternatively, heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping treatment for dehydrogenation may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be performed repeatedly.

Next, an oxide semiconductor layer is formed over the base insulating layer 436 and processed into an island shape to form the oxide semiconductor layer 4.
03 is formed. The thickness of the oxide semiconductor layer 403 is, for example, 1 nm to 30 nm, preferably 5 nm to 10 nm.

The oxide semiconductor layer may have a single layer structure or a stacked structure. Moreover, an amorphous structure may be sufficient and crystallinity may be sufficient. In the case where the oxide semiconductor layer has an amorphous structure, a crystalline oxide semiconductor layer may be formed by performing heat treatment on the oxide semiconductor layer in a later manufacturing process. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor layer is 250.
And higher than or equal to 700 ° C., preferably higher than or equal to 400 ° C., more preferably higher than or equal to 500 ° C., and still more preferably higher than or equal to 550 ° C. Note that the heat treatment can also serve as another heat treatment in the manufacturing process.

As a method for forming the oxide semiconductor layer, a sputtering method, MBE (Molecular Beam) is used.
m Epitaxy), CVD, pulsed laser deposition, ALD (Atomic La)
yer Deposition) method or the like can be used as appropriate.

When forming the oxide semiconductor layer, it is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor layer as much as possible. In order to reduce the hydrogen concentration, for example, when film formation is performed using a sputtering method, impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed as an atmospheric gas supplied into the processing chamber of the sputtering apparatus. High purity noble gas (typically argon)
, Oxygen, and a mixed gas of a rare gas and oxygen are used as appropriate.

In addition, the hydrogen concentration of the formed oxide semiconductor layer can be reduced by introducing a sputtering gas from which hydrogen and moisture are removed while removing residual moisture in the deposition chamber.
In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. The film formation chamber evacuated using a cryopump has a high exhaust capability such as a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as hydrogen molecules and water (H ₂ O). The concentration of impurities contained in the oxide semiconductor layer formed in the film chamber can be reduced.

In the case where the oxide semiconductor layer is formed by a sputtering method, the relative density (filling rate) of the metal oxide target used for film formation is 90% to 100%, preferably 95% to 99.9.
% Or less. By using a metal oxide target having a high relative density, the formed oxide semiconductor layer can be a dense film.

In addition, forming the oxide semiconductor layer with the substrate 400 kept at a high temperature is also effective in reducing the concentration of impurities that can be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150 ° C. or higher and 450 ° C. or lower, and preferably the substrate temperature is 200 ° C. or higher and 3 ° C. or lower.
What is necessary is just to be 50 degrees C or less. In addition, the crystalline oxide semiconductor layer can be formed by heating the substrate at a high temperature during film formation.

An oxide semiconductor used for the oxide semiconductor layer 403 contains at least indium (In). In particular, it is preferable to contain indium and zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. In addition, tin (Sn) as a stabilizer
, Hafnium (Hf), aluminum (Al), or zirconium (Zr) is preferably used.

In addition, as other stabilizers, lanthanoids such as lanthanum (La), cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium ( Tm), ytterbium (Yb), or lutetium (Lu) may be included.

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides In—Zn oxide, In—Mg oxide, In—Ga oxide, ternary metal In-Ga-Zn-based oxides, In-Al-Zn-based oxides, and In-Sn-Zn
Oxide, In—Hf—Zn oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In -Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide Oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide,
In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides that are quaternary metal oxides Oxide, In-S
An n-Hf-Zn-based oxide or an In-Hf-Al-Zn-based oxide can be used.

For example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

In addition, as an oxide semiconductor, InMO ₃ (ZnO) _m (m> 0 and m is not an integer)
A material represented by may be used. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. As an oxide semiconductor, In ₂ SnO
₅ (ZnO) _n (n> 0 and n is an integer) may be used.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Z
n = 2: 2: 1 (= 2/5: 2/5: 1/5), or In: Ga: Zn = 3: 1: 2
An In—Ga—Zn-based oxide having an atomic ratio of (= 1/2: 1/6: 1/3) or an oxide in the vicinity of the composition thereof can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3:
1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1 / 4: 1/8: 5/8) atomic ratio In-Sn
A Zn-based oxide or an oxide in the vicinity of the composition may be used.

However, a transistor including an oxide semiconductor containing indium is not limited thereto, and a transistor having an appropriate composition may be used depending on required electrical characteristics (field-effect mobility, threshold value, variation, and the like). . In order to obtain necessary electrical characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

For example, in a transistor including an In—Sn—Zn-based oxide semiconductor, high field effect mobility can be obtained relatively easily. However, even in a transistor including an In—Ga—Zn-based oxide semiconductor, field-effect mobility can be increased by reducing the defect density in the bulk.

For example, the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b +
The composition of the oxide having c = 1) has an atomic ratio of In: Ga: Zn = A: B: C (A + B + C).
= 1) In the vicinity of the oxide composition, a, b, and c are (a−A) ² + (b−B) ² +
(C−C) ² ≦ r ² is satisfied. For example, r may be 0.05.
The same applies to other oxides.

The oxide semiconductor layer 403 may have a single-layer structure or a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor layer 403 is a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and metal oxides having different compositions are formed on the first oxide semiconductor layer and the second oxide semiconductor layer. You may use thing. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, the first
Both the oxide semiconductor layer and the second oxide semiconductor layer may be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be the same, and the compositions of the elements may be different. For example, the atomic ratio of the first oxide semiconductor layer is set to In: Ga: Zn = 1.
The atomic ratio of the second oxide semiconductor layer may be In: Ga: Zn = 3: 1: 2. The atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 3: 2,
The atomic ratio of the second oxide semiconductor layer may be In: Ga: Zn = 2: 1: 3.

At this time, the In and Ga contents in the oxide semiconductor layer on the side close to the gate electrode (channel side) of the first oxide semiconductor layer and the second oxide semiconductor layer may be In> Ga. In addition, the content of In and Ga in the oxide semiconductor layer far from the gate electrode (back channel side) is set to In ≦
Ga may be used.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation of oxygen deficiency than In, oxygen deficiency is less likely to occur.
An oxide having a composition of In ≦ Ga has stable characteristics as compared with an oxide having a composition of In> Ga.

An oxide semiconductor with a composition In> Ga is applied to the channel side, and In ≦
By using an oxide semiconductor having a Ga composition, the mobility and reliability of the transistor can be further increased.

Alternatively, oxide semiconductor films having different crystallinities may be used for the first oxide semiconductor layer and the second oxide semiconductor layer. In other words, a single crystal oxide semiconductor film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or a CAAC-OS film may be combined as appropriate.

Note that an amorphous oxide semiconductor film easily absorbs impurities such as hydrogen and serves as an n-type because it easily generates oxygen vacancies. Therefore, the oxide semiconductor layer on the channel side is
An oxide semiconductor film having crystallinity such as a CAAC-OS film is preferably used.

The oxide semiconductor layer 403 is preferably subjected to heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) included in the oxide semiconductor layer 403.
The heat treatment temperature is set to be 300 ° C. or higher and 700 ° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere.

By this heat treatment, hydrogen which is an impurity imparting n-type conductivity can be removed from the oxide semiconductor. For example, the concentration of hydrogen contained in the oxide semiconductor layer 403 after dehydration or dehydrogenation treatment can be 5 × 10 ¹⁹ cm ⁻³ or less, preferably 5 × 10 ¹⁸ cm ⁻³ or less.

Note that heat treatment for dehydration or dehydrogenation may be performed at any timing in the manufacturing process of the transistor 420 as long as it is performed after the oxide semiconductor layer is formed. Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatments.

Note that in the case where an insulating layer containing oxygen is provided as the base insulating layer 436, heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor layer is processed into an island shape, so that the base insulating layer 436 includes the heat treatment. It is preferable because oxygen can be prevented from being released by heat treatment.

In the heat treatment, it is preferable that water or hydrogen is not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99).
9999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

In addition, after heating the oxide semiconductor layer 403 by heat treatment, a high-purity oxygen gas, a high-purity dinitrogen monoxide gas, or ultra-dry air is maintained in the same furnace while maintaining the heating temperature or gradually cooling from the heating temperature. Introduced (air of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less) when measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter May be. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or the dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or nitrous oxide introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide is 1 ppm or less, preferably 0.1 ppm or less. ) Is preferable. Oxygen is supplied by supplying oxygen, which is a main component material of the oxide semiconductor, which has been reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas. The physical semiconductor layer 403 can be highly purified and i-type (intrinsic).

In addition, since dehydration or dehydrogenation treatment may cause oxygen, which is a main component material of the oxide semiconductor, to be simultaneously desorbed and reduced, the oxide semiconductor subjected to dehydration or dehydrogenation treatment Oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the layer to supply oxygen into the film.

The oxide semiconductor layer can be highly purified and i-type (intrinsic) by introducing oxygen into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment and supplying oxygen into the film. it can. A transistor including an i-type (intrinsic) oxide semiconductor that is highly purified has a suppressed variation in electrical characteristics and is electrically stable.

In the case of introducing oxygen into the oxide semiconductor layer, oxygen may be directly introduced into the oxide semiconductor layer, or the oxide semiconductor layer 403 passes through another film such as the gate insulating layer 402 or the insulating layer 407 which is formed later.
May be introduced. In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used. In the case where oxygen is directly introduced into the exposed oxide semiconductor layer 403, plasma treatment or the like can be used in addition to the above method.

As the oxygen supply gas, a gas containing O may be used. For example, O ₂ gas, N ₂ O
Gas, CO ₂ gas, CO gas, NO ₂ gas, or the like can be used. Note that a rare gas (eg, Ar) may be included in the oxygen supply gas.

For example, in the case where oxygen ions are implanted into the oxide semiconductor layer 403 by an ion implantation method, the dose may be 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

Alternatively, the insulating layer in contact with the oxide semiconductor layer 403 is a layer including an oxygen-excess region, and heat treatment is performed in a state where the insulating layer and the oxide semiconductor layer 403 are in contact with each other, so that oxygen contained in the insulating layer is excessive. May be diffused into the oxide semiconductor layer 403 and oxygen may be supplied to the oxide semiconductor layer 403. This heat treatment can also serve as another heat treatment in the manufacturing process of the transistor 420.

The timing of supplying oxygen to the oxide semiconductor layer is not particularly limited as long as it is after the formation of the oxide semiconductor layer. In addition, oxygen may be introduced into the oxide semiconductor layer a plurality of times. In the case where the oxide semiconductor layer has a stacked structure of a plurality of layers, heat treatment for dehydration or dehydrogenation and / or supply of oxygen may be separately performed on each oxide semiconductor layer. Alternatively, this may be performed on the oxide semiconductor layer 403 after the stacked structure is formed.

The base insulating layer 436 and the oxide semiconductor layer 403 are preferably formed continuously without being exposed to the air. When the base insulating layer 436 and the oxide semiconductor layer 403 are successively formed without being exposed to the air, impurities such as hydrogen and moisture can be prevented from being adsorbed to the surface of the base insulating layer 436.

Next, a gate insulating film 402a is formed to cover the oxide semiconductor layer 403. Gate insulating film 4
02a is a film thickness of 1 nm or more and 20 nm or less, sputtering method, MBE method, CVD method,
A pulse laser deposition method, an ALD method, or the like can be used as appropriate. Note that high-density plasma CVD using μ waves (for example, a frequency of 2.45 GHz) can form a dense high-quality insulating layer with high withstand voltage, and thus is preferably used for forming the gate insulating film 402a. .

In order to improve the coverage with the gate insulating film 402a, the planarization treatment may also be performed on the surface of the oxide semiconductor layer 403. In particular, when a thin insulating layer is used as the gate insulating film 402a, the surface of the oxide semiconductor layer 403 is preferably flat.

As a material of the gate insulating film 402a, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. The gate insulating film 402a preferably contains oxygen in a portion in contact with the oxide semiconductor layer 403. In particular, the gate insulating film 402a is formed in the film (
It is preferable that at least an oxygen amount exceeding the stoichiometric ratio exists in the bulk). For example, when a silicon oxide film is used as the gate insulating film 402a, SiO _{2 + α} (where α> 0) is set. Further, the gate insulating film 402a is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage with the gate insulating film 402a.

As materials for the gate insulating film 402a, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate added with nitrogen, hafnium aluminate (HfAl _x O _y (HfAl _x O _y ( x> 0, y> 0)), and materials such as lanthanum oxide may be used. Further, the gate insulating film 402a may have a single-layer structure or a stacked structure.

In order for the gate insulating film 402a to be reduced in impurities such as hydrogen (including water and hydroxyl groups) and to be in an oxygen-excess state, hydrogen (including water and hydroxyl groups) is removed (dehydrated or dehydrated) in the gate insulating film 402a. Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping treatment may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be performed repeatedly.

Next, a conductive film is formed over the gate insulating film 402a, and the conductive film is etched to form the gate electrode layer 401 (see FIG. 3A).

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single-layer structure or a stacked structure. The thickness of the gate electrode layer 401 is preferably 50 nm to 300 nm.

The material of the gate electrode layer 401 is indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, oxide A conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Also,
A stacked structure of the conductive material and the metal material may be employed.

Further, as one layer of the gate electrode layer 401 in contact with the gate insulating layer 402, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen or an In—Sn—O film containing nitrogen is used. In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn- containing nitrogen
An O film, an In—O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

Next, an insulating film 411a is formed over the gate insulating film 402a so as to cover the gate electrode layer 401, and then an insulating film 412a is formed over the insulating film 411a (see FIG. 3B).

The insulating film 411a is a film that functions as a barrier film of the transistor 420 by being selectively etched later. As the insulating film 411a, a film having a lower oxygen permeability than the gate insulating film 402a can be used. In addition, it is more preferable to apply a film having a high blocking effect (blocking effect) that does not allow the film to permeate both impurities such as hydrogen and hydrogen compounds (for example, water) and oxygen.

The insulating film 411a can be formed by a sputtering method. The insulating film 411a is
The thickness of a region in contact with the upper surface of the gate insulating film 402a is preferably 5 nm to 20 nm, and more preferably 5 nm to 10 nm. By setting the thickness of the region in contact with the upper surface of the gate insulating film 402a to 5 nm or more, a sufficient barrier effect can be obtained. If the insulating film 411a is too thick,
Although the film formation time is long and the etching time for processing is also long, and the productivity is reduced, the film thickness of the region in contact with the upper surface of the gate insulating film 402a in the insulating film 411a (
That is, by setting the region where the film thickness can be maximized in the insulating film 411a to 20 nm or less, pattern formation can be easily performed in a later process.

In addition, a region that is not perpendicular to the deposition direction (specifically, a region that is in contact with the side surface of the gate electrode layer 401) among the deposition surfaces of the insulating film 411a is a region that is perpendicular to the deposition direction (specifically, In this case, it is difficult to form a film in comparison with the upper surface of the gate insulating film 402a and the upper surface of the gate electrode layer 401, and the film thickness is reduced. The extent to which the film thickness is reduced depends on the taper angle of the gate electrode layer 401, but in the insulating film 411a, a film thickness equivalent to the target film thickness can be obtained in the region in contact with the upper surface of the gate insulating film 402a. In the region in contact with the side surface of the gate electrode layer 401, for example, the film thickness is about half of the target film thickness. Alternatively, the insulating film 411a may not be formed in the region in contact with the side surface of the gate electrode layer.

Note that a metal film is formed over the gate insulating layer 402 by a sputtering method so as to cover the gate electrode layer 401, and then oxygen or nitrogen is introduced into the metal film to form a metal oxide film or a metal nitride film. Thus, the insulating film 411a may be used.

As the insulating film 412a, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used. The insulating film 412a is preferably formed by a CVD method such as an LPCVD method or a plasma CVD method.

The stacked structure of the insulating film 412a and the insulating film 411a is an insulating film that serves as a sidewall insulating layer of the gate electrode layer 401 by being etched in a later step. As described above, in the insulating film 411a, it is difficult to form a film in a region in contact with the side surface of the gate electrode layer 401. Therefore, when the sidewall insulating layer is formed using only the insulating film 411a, the gate electrode layer 401, the source electrode layer, There is a risk of short circuit with the drain electrode layer or electrical failure such as leakage current.

In this embodiment, the side surface of the gate electrode layer 401 can be covered with a sidewall insulating layer with favorable coverage by forming the insulating film 412a over the insulating film 411a and processing the stacked structure.

Next, the insulating film 412a is anisotropically etched to form the insulating layer 412 over the side surface of the gate electrode layer 401 with the insulating film 411a interposed therebetween (see FIG. 3C).

After that, the insulating film 411a and the gate insulating film 402a are etched using the insulating layer 412 as a mask to form the insulating layer 411 and the gate insulating layer 402 (see FIG. 3D).

Note that depending on the etching conditions, the oxide semiconductor layer 403 is etched at the same time by the etching of the gate insulating film 402a as illustrated in FIG.
In some cases, the thickness of a region which does not overlap with the gate insulating layer 402 becomes small. Further, the end portions of the insulating layer 411 and the gate insulating layer 402 formed by etching using the insulating layer 412 as a mask substantially coincide with each other.

Next, a conductive film 404 is formed over the oxide semiconductor layer 403 so as to cover the sidewall insulating layer of the gate electrode layer 401 including the insulating layer 411 and the insulating layer 412 and the gate electrode layer 401 (see FIG. 3E). ).

The conductive film 404 is a film to be a source electrode layer 405a and a drain electrode layer 405b (including wirings formed in the same layer), and examples of the material thereof include Al, Cr, Cu, T
A metal film containing an element selected from a, Ti, Mo, and W, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing the above-described element as a component can be used. In addition, Ti, Mo, or one or both of the lower side or the upper side of a metal film such as Al and Cu
Refractory metal films such as W or their metal nitride films (titanium nitride film, molybdenum nitride film,
A structure in which a tungsten nitride film) is stacked may be employed. Alternatively, the conductive film 404 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In
₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In
₂ O ₃ —SnO ₂ ), indium zinc oxide (In ₂ O ₃ —ZnO), or a metal oxide material containing silicon oxide can be used.

After that, the conductive film 404 is selectively etched with a resist mask using a photolithography process to form a pattern. In the pattern formation here, the gate electrode layer 4
The region overlapping 01 is not etched, and the region other than the region is selectively etched. In this embodiment, the conductive layer 405 is formed by selectively etching a region other than the region overlapping with the gate electrode layer 401 and the sidewall insulating layers (the insulating layers 411 and 412) (
(See FIG. 4A).

After that, an insulating layer 407 is formed over the conductive layer 405 (see FIG. 4B). As the insulating layer 407, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a hafnium oxide film, a magnesium oxide film formed by a plasma CVD method, a sputtering method, an evaporation method, or the like is used. An inorganic insulating film such as a film, a zirconium oxide film, a lanthanum oxide film, or a barium oxide film can be used as a single layer or a stacked structure. Or
As the insulating layer 407, a planarization insulating film may be formed in order to reduce surface unevenness due to the transistor, or an inorganic insulating film and a planarization insulating film may be stacked. As the planarization insulating film, an organic material such as polyimide resin, acrylic resin, or benzocyclobutene resin can be used. Alternatively, a low dielectric constant material (low-k material) or the like can be used in addition to the organic material.

Next, the insulating layer 407 and the conductive layer 405 are subjected to polishing (cutting or grinding), and the conductive layer 405 in a region overlapping with the gate electrode layer 401 is removed, whereby the source electrode layer 405a and the drain electrode layer 405b are formed. (See FIG. 4C). By removing the conductive layer 405 in a region overlapping with the gate electrode layer 401 by polishing treatment, the conductive layer 405 can be divided in the channel length direction without using a resist mask.
Even when 0 has a fine channel length, the source electrode layer 405a and the drain electrode layer 405b can be formed with high accuracy.

As a polishing (cutting, grinding) method, chemical mechanical polishing (Chemical Mechanical)
al Polishing (CMP) treatment can be preferably used. In this embodiment, the conductive layer 405 in a region overlapping with the gate electrode layer 401 is removed by CMP treatment.

The CMP process may be performed only once or a plurality of times. C divided into multiple times
When performing MP treatment, it is preferable to perform final polishing at a low polishing rate after performing primary polishing at a high polishing rate. By combining polishing with different polishing rates in this manner, productivity and surface flatness can be further improved.

Note that in this embodiment, C is removed for removing the conductive layer 405 in a region overlapping with the gate electrode layer 401.
Although the MP process is used, other polishing (grinding and cutting) processes may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where polishing treatment is combined with etching treatment, plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive layer 405.

Note that in this embodiment, the upper end portions of the source electrode layer 405a and the drain electrode layer 405b substantially coincide with the upper end portion of the gate electrode layer 401. However, the source electrode layer 405a
The shape of the drain electrode layer 405b differs depending on the polishing conditions for removing a part of the conductive layer 405. For example, the source electrode layer 405a or the drain electrode layer 405b may be shaped to recede in the film thickness direction from the surface of the gate electrode layer 401.

After that, an insulating layer 414 is formed over the insulating layer 407, and an opening reaching the source electrode layer 405a or the drain electrode layer 405b is formed in the insulating layer 414 and the insulating layer 407. A source wiring layer 415a and a drain electrode layer 405b electrically connected to the source electrode layer 405a in the opening
A drain wiring layer 415b is formed which is electrically connected to (see FIG. 4D).

Through the above steps, a semiconductor device including the transistor 420 described in this embodiment can be manufactured.

In the transistor 420, the insulating layer 411 is a film having lower permeability to oxygen than the gate insulating layer 402, and can function as a barrier film against oxygen. Thus, the provision of the insulating layer 411 can suppress oxygen vacancies in the gate insulating layer 402 and the oxide semiconductor layer 403 in contact with the gate insulating layer 402, so that the reliability of the transistor 420 can be improved.

In the transistor 420, the distance between the source electrode layer 405a and the oxide semiconductor layer 403 (source-side contact region) and the gate electrode layer 401, and the drain electrode layer 405b and the oxide semiconductor layer 403 are in contact with each other. The distance between the region (drain side contact region) and the gate electrode layer 401 is determined by the width in the channel length direction of the sidewall insulating layer of the gate electrode layer 401. Further, when the thickness of the region of the insulating layer 411 in contact with the gate electrode layer 401 is reduced, the width of the sidewall insulating layer in the channel length direction can be reduced. Therefore,
Since the distance between the source-side contact region or the drain-side contact region and the gate electrode layer 401 can be reduced, the resistance of the region can be reduced and the on-state characteristics of the transistor 420 can be improved. Can do.

Note that although an example in which the source electrode layer 405a or the drain electrode layer 405b is provided so as to cover the sidewall insulating layer of the gate electrode layer 401 is described in this embodiment, the present invention is not limited thereto. For example, like the transistor 424 illustrated in FIG.
3 may be formed, and the source electrode layer 405a and the drain electrode layer 405b may be formed in the openings. In the transistor 424 illustrated in FIGS. 5A and 5B, since the conductive film is not polished (cut or ground) in the formation process of the source electrode layer 405a and the drain electrode layer 405b, the manufacturing process of the transistor is simplified and the yield is improved. Can be planned.

5A is a plan view of the transistor 424, FIG. 5B is a cross-sectional view taken along line X3-Y3 in FIG. 5A, and FIG. 5C is a cross-sectional view of FIG. It is sectional drawing in V3-W3. The transistor 424 can have a structure similar to that of the transistor 420 except for the shape of the source electrode layer 405a and the drain electrode layer 405b.

Since the transistor described in this embodiment is in contact with the upper surface of the gate insulating layer 402 and has an insulating layer 411 that has lower permeability to oxygen than the gate insulating layer 402 and has barrier properties,
Release of oxygen from the gate insulating layer 402 and the oxide semiconductor layer 403 can be suppressed. Therefore, in the transistor described in this embodiment, the influence of a parasitic channel can be suppressed, fluctuation in electrical characteristics can be suppressed, and an electrically stable transistor can be obtained. Also,
By using such a transistor, a highly reliable semiconductor device can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a semiconductor device (memory device) that uses the transistor described in this specification, can hold stored data even in a state where power is not supplied, and has no limit on the number of writing times is described in the drawings. Will be described.

FIG. 6 illustrates an example of a structure of a semiconductor device. FIG. 6A illustrates a cross-sectional view of the semiconductor device in FIG.
FIG. 6B is a plan view of the semiconductor device, and FIG. 6C is a circuit diagram of the semiconductor device. Here, FIG. 6A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG.

The semiconductor device illustrated in FIGS. 6A and 6B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. . The transistor 162 is an example to which the structure of the transistor 420 described in Embodiment 1 is applied.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon).
And the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition, a specific structure of the semiconductor device, such as a material used for the semiconductor device and a structure of the semiconductor device, is used except for using the transistor described in Embodiment 1 using an oxide semiconductor to hold information. It is not necessary to limit to what is shown here.

A transistor 160 in FIG. 6A includes a channel formation region 116 provided in a substrate 185 containing a semiconductor material (eg, silicon), an impurity region 120 provided so as to sandwich the channel formation region 116, and an impurity region. It has an intermetallic compound region 124 in contact with 120, a gate insulating layer 108 provided on the channel formation region 116, and a gate electrode layer 110 provided on the gate insulating layer 108. Note that in the drawing, the source electrode layer and the drain electrode layer may not be explicitly provided, but for convenience, the transistor may be referred to as a transistor including such a state. In this case, in order to explain the connection relationship of the transistors,
The source and drain regions may be expressed as the source electrode layer and the drain electrode layer. That is, in this specification, the term “source electrode layer” can include a source region.

An element isolation insulating layer 106 is provided over the substrate 185 so as to surround the transistor 160, and insulating layers 128 and 130 are provided so as to surround the transistor 160.

The transistor 160 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. As a process before formation of the transistor 162 and the capacitor 164,
A CMP process is performed on the insulating layer covering the transistor 160 so that the insulating layers 128 and 130 are planarized, and at the same time, the upper surface of the gate electrode layer of the transistor 160 is exposed.

A transistor 162 illustrated in FIG. 6A is a top-gate transistor using an oxide semiconductor for a channel formation region. Here, the gate insulating layer 1 included in the transistor 162
40 is in contact with the insulating layer 145 whose upper surface has a barrier property against oxygen. Accordingly, release of oxygen from the gate insulating layer 140 and the oxide semiconductor layer 144 can be suppressed, and the reliability of the transistor 162 can be improved. In addition, when an insulating layer having a barrier property against hydrogen in addition to oxygen is applied as the insulating layer 145, intrusion of hydrogen into the gate insulating layer 140 and the oxide semiconductor layer 144 is suppressed in addition to suppression of oxygen desorption. be able to. Thus, the oxide semiconductor layer 144 can be highly purified and i-type (intrinsic). The transistor 162 including the highly purified i-type (intrinsic) oxide semiconductor has extremely excellent off-state characteristics.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. That is, since it becomes possible to provide a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation,
Power consumption can be sufficiently reduced.

An insulating layer 150 is provided as a single layer or a stacked layer over the transistor 162. In addition, in the region overlapping with the electrode layer 142a of the transistor 162 with the insulating layer 150 interposed therebetween, the conductive layer 1
48b is provided, and the capacitor layer 164 includes the electrode layer 142a, the insulating layer 150, and the conductive layer 148b. That is, the electrode layer 142a of the transistor 162 is
The capacitor 164 functions as one electrode, and the conductive layer 148 b functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

An insulating layer 152 is provided over the transistor 162 and the capacitor 164. A transistor 162 and a wiring 156 for connecting another transistor are provided over the insulating layer 152. Although not illustrated in FIG. 6A, the wiring 156 includes the insulating layer 150,
The electrode layer 142b is electrically connected through an electrode layer formed in an opening formed in the insulating layer 152, the insulating layer 150, and the like.

6A and 6B, the transistor 160 and the transistor 162 are
It is preferably provided so that at least part thereof overlaps, and the source or drain region of the transistor 160 overlaps with part of the oxide semiconductor layer 144. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. For example, the conductive layer 148b of the capacitor 164 is provided so as to overlap with at least part of the gate electrode layer 110 of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Next, an example of a circuit configuration corresponding to FIGS. 6A and 6B is illustrated in FIG.

In FIG. 6C, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode layer of the transistor 160 are electrically connected. Connected. The third wiring (3rd Line)
And one of a source electrode layer and a drain electrode layer of the transistor 162 are electrically connected, and a fourth wiring (4th Line) and a gate electrode layer of the transistor 162 are electrically connected. Then, the gate electrode layer of the transistor 160 and the transistor 162
One of the source electrode layer and the drain electrode layer is electrically connected to the other electrode of the capacitor 164, and the fifth wiring (5th Line) and the other electrode of the capacitor 164 are electrically connected. Yes.

In the semiconductor device illustrated in FIG. 6C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode layer of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, predetermined charge is supplied to the gate electrode layer of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off and the transistor 162 is turned off, whereby the charge given to the gate electrode layer of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode layer of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, according to the amount of charge held in the gate electrode layer of the transistor 160, The second wiring takes different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold value V _{th_H in the} case where a high-level charge is applied to the gate electrode layer of the transistor 160 is a low-level charge applied to the gate electrode layer of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L in the} case of Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the potential of the fifth wiring is set to the potential V ₀ between V _{th_H} and V _{th_L} , whereby the transistor 160
The charge applied to the gate electrode layer can be discriminated. For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the retained information can be read by determining the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned off regardless of the state of the gate electrode layer, that is, V _{th_H}
A smaller potential may be supplied to the fifth wiring. Alternatively, a potential at which the transistor 160 is turned on regardless of the state of the gate electrode layer, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. In other words, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, there is no need to inject electrons into the floating gate or withdraw electrons from the floating gate unlike conventional nonvolatile memories.
There is no problem of deterioration of the gate insulating layer. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, a semiconductor device which is miniaturized and highly integrated and has high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, one embodiment of a structure of a memory device, which is different from that in Embodiment 3, will be described.

FIG. 7 is a perspective view of the storage device. The memory device illustrated in FIG. 7 includes a plurality of memory cells as a memory circuit in the upper part, a plurality of memory cell arrays (memory cell array 3400 (1) to memory cell array 3400 (n), n is an integer of 2 or more), and a memory in the lower part. Cell array 3400
(1) to a logic circuit 3004 necessary for operating the memory cell array 3400 (n)
Have

In FIG. 7, a logic circuit 3004, a memory cell array 3400 (1), and a memory cell array 3
400 (2), the memory cell array 3400 (1) or the memory cell array 3
Of the plurality of memory cells included in 400 (2), the memory cell 3170a and the memory cell 3170b are shown as representatives. The memory cell 3170a and the memory cell 3170b can have a configuration similar to the circuit configuration described in the above embodiment, for example.

Note that FIG. 8 illustrates a transistor 3171a included in the memory cell 3170a as a representative.
In addition, a transistor 3171b included in the memory cell 3170b is shown as a representative. The transistor 3171a and the transistor 3171b each include a channel formation region in the oxide semiconductor layer. For the structure of the transistor in which the channel formation region is formed in the oxide semiconductor layer,
Since it is the same as the structure demonstrated in Embodiment 1, description is abbreviate | omitted.

An electrode layer 3501a formed in the same layer as the source or drain electrode layer of the transistor 3171a is electrically connected to the electrode layer 3003a by the electrode layer 3502a. An electrode layer 3501c formed in the same layer as the source or drain electrode layer of the transistor 3171b is electrically connected to the electrode layer 3003c through the electrode layer 3502c.

The logic circuit 3004 includes a transistor 3001 using a semiconductor material other than an oxide semiconductor as a channel formation region. In the transistor 3001, an element isolation insulating layer 3106 is provided over a substrate 3000 containing a semiconductor material (eg, silicon), and the element isolation insulating layer 31 is provided.
A transistor can be obtained by forming a region to be a channel formation region in a region surrounded by 06. Note that the transistor 3001 may be a transistor in which a channel formation region is formed in a semiconductor film such as a polycrystalline silicon film formed over an insulating surface or a silicon film of an SOI substrate. A known structure can be used as the structure of the transistor 3001, and thus the description is omitted.

A wiring 3100a and a wiring 3100b are formed between the layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed. An insulating layer 3140a is provided between the wiring 3100a and the layer where the transistor 3001 is formed, and the wiring 3100a is provided.
An insulating layer 3141a is provided between the wiring 3100b and the wiring 3100b, and an insulating layer 3142a is provided between the wiring 3100b and the layer where the transistor 3171a is formed.

Similarly, a wiring 3100c and a wiring 3100d are formed between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed. Wiring 3100c
Between the wiring 3100c and the wiring 3100d, an insulating layer 3141b is provided between the wiring 3100c and the wiring 3100d.
An insulating layer 3142b is provided between d and the layer over which the transistor 3171b is formed.

Insulating layer 3140a, insulating layer 3141a, insulating layer 3142a, insulating layer 3140b, insulating layer 3
141b and the insulating layer 3142b function as interlayer insulating layers, and the surface thereof can be planarized.

With the wiring 3100a, the wiring 3100b, the wiring 3100c, and the wiring 3100d, an electrical connection between the memory cells, an electrical connection between the logic circuit 3004 and the memory cell, or the like can be performed.

The electrode layer 3303 included in the logic circuit 3004 can be electrically connected to a circuit provided in the upper portion.

For example, as illustrated in FIG. 8, the electrode layer 3303 can be electrically connected to the wiring 3100 a by the electrode layer 3505. The wiring 3100a can be electrically connected to the electrode layer 3501b of the transistor 3171a through the electrode layer 3503a. In this manner, the wiring 3100a and the electrode layer 3303 can be electrically connected to the source or the drain of the transistor 3171a. The electrode layer 3501b which is a source or a drain of the transistor 3171a can be electrically connected to the electrode layer 3003b through the electrode layer 3502b. The electrode layer 3003b can be electrically connected to the wiring 3100c through the electrode layer 3503b.

In FIG. 8, electrical connection between the electrode layer 3303 and the transistor 3171a is performed using the wiring 3100a.
Although an example is shown through FIG. 1, the present invention is not limited to this. Electrode layer 3303 and transistor 31
The electrical connection with 71a may be performed via the wiring 3100b, or may be performed via both the wiring 3100a and the wiring 3100b. Alternatively, the wiring 3100a is also the wiring 3100.
It may be performed using another electrode layer without b being interposed.

In FIG. 8, between the layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed, the wiring layer in which the wiring 3100a is formed and the wiring layer in which the wiring 3100b is formed are 2 Although a configuration in which one wiring layer is provided is shown, the present invention is not limited to this. Between the layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed, 1
One wiring layer may be provided, or three or more wiring layers may be provided.

Further, in FIG. 8, between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed, the wiring layer in which the wiring 3100c is formed and the wiring layer in which the wiring 3100d is formed are 2 Although a configuration in which one wiring layer is provided is shown, the present invention is not limited to this. One wiring layer may be provided between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed, or three or more wiring layers may be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS.

In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing.
On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In a normal SRAM, as shown in FIG. 9A, one memory cell includes transistors 801-8.
06 transistors are driven by an X decoder 807 and a Y decoder 808. Transistor 803, transistor 805, transistor 80
4 and the transistor 806 constitute an inverter, which enables high-speed driving. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is usually 100.
It is a ~150F ^2. For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 9B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. D
The memory cell area of RAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 10 shows a block diagram of a portable device. 10 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. Sensor 919,
An audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, an interface (IF
909. In general, the memory circuit 912 includes an SRAM or a DRAM. By adopting the semiconductor device described in the above embodiment for this portion, information can be written and read at high speed, and long-term storage can be performed. In addition, power consumption can be sufficiently reduced.

FIG. 11 illustrates an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 11 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit reads a signal line from image data (input image data), a memory 952, and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation of rewriting the screen (that is, the input image data A
The application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953,
The stored image data B is read from the next frame of the display 957, and the switch 95
5 and the display controller 956, the stored image data B is sent to the display 957 for display. This reading is continued until new image data is stored in the memory 952 next time.

As described above, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 9
52 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently reduced. it can.

FIG. 12 shows a block diagram of an electronic book. FIG. 12 shows a battery 1001 and a power supply circuit 1002.
, A microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 has a function of temporarily holding the contents of a book. An example of a function is when a user uses a highlight function. When a user is reading an electronic book, the user may want to mark a specific part. This marking function is called a highlight function, and is to show the difference from the surroundings by changing the display color, underlining, making the character thicker, or changing the font of the character. This is a function for storing and holding information on a location designated by the user. When this information is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the above embodiment, writing and reading of information can be performed at high speed, long-term storage can be performed, and power consumption can be sufficiently reduced. Can do.

As described above, the portable device described in this embodiment includes the semiconductor device according to any of the above embodiments. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

In this example, an example in which a sidewall insulating layer of a gate electrode layer is manufactured using the manufacturing method described in Embodiment Mode 1 will be described.

In this example, a sidewall insulating layer including an insulating layer in contact with the top surface of the gate insulating layer and the side surface of the gate electrode layer was formed by the manufacturing method illustrated in FIGS. A manufacturing method will be described below.

First, a silicon oxynitride film with a thickness of 100 nm was formed as a base insulating layer 436 over a silicon substrate used as the substrate 400 by a CVD method.

Next, as the oxide semiconductor layer 403 over the base insulating layer 436, In: Ga: Zn = 3: 1
: An IGZO film having a thickness of 20 nm was formed by a sputtering method using an oxide target of 2 [atomic ratio]. The film forming conditions are oxygen atmosphere (flow rate 45 sccm), pressure 0.4 P.
a, power supply power 500 W, substrate temperature 200 ° C., and distance between substrate 400 and target 60
mm.

Next, the oxide semiconductor layer 403 is formed into an ICP (Inductively Coupled P).
(lasma: inductively coupled plasma) Etching was performed by an etching method and processed into an island shape. Etching conditions include boron trichloride and chlorine mixed gas (BCl ₃ :
Cl ₂ = 60 sccm: 20 sccm), power supply power 450 W, bias power 100
W and pressure were set to 1.9 Pa.

Next, a silicon oxynitride film with a thickness of 10 nm was formed as a gate insulating film 402a over the oxide semiconductor layer 403 by a CVD method.

On the gate insulating film 402a, a tantalum nitride film having a thickness of 30 nm by a sputtering method;
A stack of a tungsten film having a thickness of 200 nm was formed and processed by an etching method, so that the gate electrode layer 401 was formed. The deposition conditions of the tantalum nitride film are argon and nitrogen (Ar: N ₂ =
50 sccm: 10 sccm) Under an atmosphere, pressure 0.6 Pa, power supply power 1 kW, substrate 4
The distance between 00 and the target was 60 mm. The tungsten film was formed under conditions of argon atmosphere (flow rate 100 sccm), pressure 2.0 Pa, power supply power 4 kW, and heated argon gas was flowed at a flow rate of 10 sccm to heat the substrate. The distance between the substrate 400 and the target was 60 mm.

Etching conditions of the tantalum nitride film and the tungsten film are the first etching conditions, and a mixed gas of chlorine, tetrafluoromethane, and oxygen (Cl ₂ : CF ₄ : O as an etching gas).
₂ = 45 sccm: 55 sccm: 55 sccm), the tungsten film was etched with a power supply power of 3 kW, a bias power of 110 W, a pressure of 0.67 Pa, and a substrate temperature of 40 ° C. Thereafter, as a second etching condition, chlorine gas (Cl ₂ = 100) is used as an etching gas.
The tantalum nitride film was etched using a power source power of 2 kW, a pressure of 0.67 Pa, and a bias power of 50 W.

Next, an aluminum oxide film was formed as the insulating film 411 a over the gate insulating film 402 a so as to cover the gate electrode layer 401. The target film thickness of the aluminum oxide film was 10 nm. The conditions for forming the aluminum oxide film are argon and oxygen (Ar: O ₂ = 25 sccm: 2
5 sccm) atmosphere, pressure 0.4 Pa, power supply power 2.5 kW, substrate temperature 250 ° C.,
The distance between the substrate 400 and the target was 60 mm.

Next, a silicon oxynitride film with a thickness of 40 nm was formed as an insulating film 412a over the insulating film 411a by a CVD method.

The insulating film 412a was etched to form an insulating layer 412 on the side surface of the gate electrode layer 401 with the insulating film 411a interposed therebetween. Etching conditions were a mixed gas of trifluoromethane and helium (CHF ₃ : He = 30 sccm: 120 sccm) as an etching gas, a power supply power of 3 kW, a bias power of 200 W, a pressure of 2.0 Pa, and a substrate temperature of −10 ° C. .

Next, the insulating film 411a and the gate insulating film 402a were etched using the insulating layer 412 as a mask, so that a sidewall insulating layer including the insulating layer 412 and the insulating layer 411 and a gate insulating layer 402 were formed. The etching conditions of the insulating film 412a and the gate insulating film 402a were boron trichloride (BCl ₃ = 80 sccm) as an etching gas, a power supply power of 550 W, a bias power of 150 W, a substrate temperature of 70 ° C., and a pressure of 1.0 Pa. .

Cross section TEM (Transmission El) of the sample of the present example obtained through the above steps.
FIG. 13 shows a photograph of an electron microscope (transmission electron microscope).

13A and 13B, the insulating layer 411 which is a part of the sidewall insulating layer of the gate electrode layer 401 has a thickness difference depending on the region, and the thickness of the region in contact with the gate insulating layer 402 is as follows.
It can be confirmed that the film thickness is larger than the film thickness in the region in contact with the side surface. In the insulating layer 411, the thickness d ₁ of the region in contact with the gate insulating layer 402 was 9.4 nm, and the thickness d ₂ of the region in contact with the side surface of the gate electrode layer 401 was 4.3 nm.

In FIG. 13, the width L ₁ of the gate electrode layer 401 was 105 nm, and the width L ₂ of the sidewall insulating layer was 42.7 nm. From the above, it was confirmed that a fine structure was formed with high accuracy.

Note that when the insulating layer 411 and the gate insulating layer 402 were formed, the oxide semiconductor layer 403 was also etched at the same time, and the film thickness was reduced. The insulating layer 411 has a barrier property, but is difficult to be etched when being processed into the sidewall insulating layer. Therefore, the oxide semiconductor layer provided below the film may be etched at the same time. However, in one embodiment of the present invention, the insulating layer functioning as the barrier film is a thin film (for example, 20 nm or less),
The disappearance of the oxide semiconductor layer can be prevented. In the structure illustrated in FIG. 13, in the oxide semiconductor layer 403, the thickness d ₃ of the region in contact with the gate insulating layer 402 is 20 nm, and the thickness d ₄ of the exposed region without overlapping with the gate insulating layer 402 is It was 12.3 nm.

As described above, the insulating layer 411 functioning as a barrier film is manufactured by the manufacturing method of this embodiment.
A sidewall insulating layer containing can be formed. Further, the insulating layer 411 can have a thickness difference in each region without performing additional processing such as etching. By using the structure manufactured in this embodiment for a transistor, the source resistance or the drain resistance can be reduced, and variations in threshold voltage, deterioration in electrical characteristics, and normally-on can be suppressed. A highly reliable transistor can be obtained.

106 element isolation insulating layer 108 gate insulating layer 110 gate electrode layer 116 channel forming region 120 impurity region 124 intermetallic compound region 128 insulating layer 130 insulating layer 140 gate insulating layer 142a electrode layer 142b electrode layer 144 oxide semiconductor layer 145 insulating layer 148b Conductive layer 150 Insulating layer 152 Insulating layer 156 Wiring 160 Transistor 162 Transistor 164 Capacitance element 185 Substrate 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 402a Gate insulating film 403 Oxide semiconductor layer 404 Conductive film 405 Conductive layer 405a Source electrode layer 405b Drain Electrode layer 407 Insulating layer 411 Insulating layer 411a Insulating film 412 Insulating layer 412a Insulating film 414 Insulating layer 415a Source wiring layer 415b Drain wiring layer 416 Insulating layer 420 Transistor 422 transistor Star 424 Transistor 436 Base insulating layer 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X decoder 808 Y decoder 811 Transistor 812 Storage capacitor 813 X decoder 814 Y decoder 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply circuit 906 Application processor 907 CPU
908 DSP
910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash memory 1005 Audio circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller 3000 Substrate 3001 Transistor 3003a Electrode layer 3003b Electrode layer 3003c Electrode layer 3004 Logic circuit 3100a Arrangement 3100b wiring 3100c wiring 3100d wiring 3106 element isolation insulating layer 3140a insulating layer 3140b insulating layer 3141a insulating layer 3141b insulating layer 3142a insulating layer 3142b insulating layer 3170a memory cell 3170b memory cell 3171a transistor 3171b transistor 3303 electrode layer 3400 memory cell array 3501a electrode layer 3501a electrode layer 3501a Layer 3501c electrode layer 3502a electrode layer 3502b electrode layer 3502c electrode layer 3503a electrode layer 3503b electrode layer 3505 electrode layer

Claims (5)

An oxide semiconductor layer;
A gate insulating layer on the oxide semiconductor layer;
A gate electrode layer having a region overlapping with the oxide semiconductor layer through the gate insulating layer;
A first insulating layer having a region in contact with an upper surface of the gate insulating layer and a region in contact with a side surface of the gate electrode layer;
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;
The semiconductor device is characterized in that the first insulating layer is a film having lower permeability to oxygen than the gate insulating layer. An oxide semiconductor layer;
A gate insulating layer on the oxide semiconductor layer;
A gate electrode layer having a region overlapping with the oxide semiconductor layer through the gate insulating layer;
A first insulating layer having a region in contact with an upper surface of the gate insulating layer and a region in contact with a side surface of the gate electrode layer;
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;
The semiconductor device, wherein the first insulating layer is a film having a lower hydrogen permeability than the gate insulating layer. An oxide semiconductor layer;
A gate insulating layer on the oxide semiconductor layer;
A gate electrode layer having a region overlapping with the oxide semiconductor layer through the gate insulating layer;
A first insulating layer having a region in contact with an upper surface of the gate insulating layer and a region in contact with a side surface of the gate electrode layer;
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;
The semiconductor device, wherein the first insulating layer is a film having lower permeability to oxygen and hydrogen than the gate insulating layer. In any one of Claims 1 thru | or 3,
A second insulating layer on the first insulating layer;
The first insulating layer comprises aluminum oxide;
The semiconductor device, wherein the second insulating layer includes silicon oxide. In any one of Claims 1 thru | or 4,
An end portion of the gate insulating layer and an end portion of the first insulating layer substantially coincide with each other.