JP4091025B2 - Polysilicon layer forming method and thin film transistor manufacturing method using the same - Google Patents

Polysilicon layer forming method and thin film transistor manufacturing method using the same Download PDF

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JP4091025B2
JP4091025B2 JP2004226675A JP2004226675A JP4091025B2 JP 4091025 B2 JP4091025 B2 JP 4091025B2 JP 2004226675 A JP2004226675 A JP 2004226675A JP 2004226675 A JP2004226675 A JP 2004226675A JP 4091025 B2 JP4091025 B2 JP 4091025B2
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polysilicon layer
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ユン、ソン、ジン
イム、ジョン、ウク
キム、ヨン、ヘ
ソン、チュン、ヨン
イ、ジン、ホ
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Description

本発明は、ポリシリコン層形成方法及びこれを用いた薄膜トランジスタの製造方法に関する。特に、バッファ層を用いたポリシリコン層形成方法及びこれを用いた薄膜トランジスタの製造方法に関する。   The present invention relates to a method for forming a polysilicon layer and a method for manufacturing a thin film transistor using the same. In particular, the present invention relates to a method for forming a polysilicon layer using a buffer layer and a method for manufacturing a thin film transistor using the same.

情報ディスプレイは、その目的及び用途によってディスプレイの大きさ、解像度、構造などが変わる。駆動方式においても能動駆動(active-matrix：ＡＭ) 方式と受動駆動(passive-matrix：ＰＭ) 方式とに大きく分けられるが、一般に、低消費電力、高解像度、高速で動作するディスプレイであるほど能動駆動方式を採用するようになる。   Information displays vary in size, resolution, structure, etc. depending on their purpose and application. The drive system can be broadly divided into an active-matrix (AM) system and a passive-matrix (PM) system. In general, the more active the display is, the lower the power consumption, the higher the resolution, and the higher the speed. Drive system will be adopted.

能動駆動方式の場合、各ピクセルを独立して駆動できるようにするために、各ピクセル別に独立のトランジスタを製造しなければならない。この際、トランジスタの性能は、一定水準以上の移動度、オン−オフ(ON-OFF)状態の電流の比、ターンオン電圧(Turn-on voltage)などの要求値を満足させなければならない。このようなトランジスタの半導体層の要求特性を充足させるために、ポリシリコン(polycrystalline silicon)層を形成して使用する場合が多いが、ポリシリコン層を形成する工程として最も代表的な方法は、非晶質シリコン(amorphous silicon)層をまず低温で形成した後、レーザなどを使用して熱処理して再結晶化する方法である。   In the case of the active driving method, an independent transistor must be manufactured for each pixel so that each pixel can be driven independently. At this time, the performance of the transistor must satisfy required values such as a mobility above a certain level, a ratio of currents in an on-off state, and a turn-on voltage. In order to satisfy the required characteristics of the semiconductor layer of such a transistor, a polysilicon (polycrystalline silicon) layer is often formed and used. However, the most typical method for forming a polysilicon layer is a non-crystalline method. In this method, an amorphous silicon layer is first formed at a low temperature, and then recrystallized by heat treatment using a laser or the like.

一方、情報ディスプレイは、後面発光のために透明な基板であるガラスを使用したり、ひいては、より軽く且つ柔軟性のあるプラスチック基板を使用する方向に技術発展がつながっている。しかし、価格が低廉なソーダガラスの場合、最高４５０℃程度まで使用可能で、特に、プラスチックの場合、２００℃よりはるかに低い温度で変性されるので、非晶質半導体層を多結晶質半導体層で結晶化する条件は、極めて制限を受けるようになる。   On the other hand, the technical development of the information display has led to the use of glass, which is a transparent substrate, for light emission from the rear surface, and eventually the use of a lighter and more flexible plastic substrate. However, in the case of soda glass, which is inexpensive, it can be used up to about 450 ° C., and in particular, in the case of plastic, it is modified at a temperature much lower than 200 ° C. Therefore, the amorphous semiconductor layer is made into a polycrystalline semiconductor layer. The conditions for crystallizing at are very limited.

従って、基板と非晶質膜との間にバッファ層を形成してより高温で再結晶化工程が進行されても基板が熱的に変性しないようにする。バッファ層が備えるべき条件としては、熱伝逹がより效果的に遮断されなければならず、反面、熱容量が大きくてより低いエネルギーでも再結晶化が起こることができるようにしなければならない。しかし、一般に、より緻密な膜は、熱容量が大きい反面、熱伝逹が活発に起こっており、緻密度の低い膜は、熱伝逹の効率は多少低いが、熱容量が小さく、ストレスなどによって容易に膜が破壊される傾向を見せる。熱伝逹の効率が高くならないようにしようという意図で多孔質シリコンをバッファ層に活用する場合もあるが、この場合、熱容量が小さく、レーザ熱処理時、高い電力が要求され、また基板損傷を效果的に防止することができなかった。従って、熱容量が大きいながらも熱伝導度が小さい特性を有する材料の採用が非常に重要である。   Accordingly, a buffer layer is formed between the substrate and the amorphous film so that the substrate is not thermally denatured even if the recrystallization process proceeds at a higher temperature. As a condition to be provided for the buffer layer, the heat transfer must be more effectively cut off. On the other hand, the heat capacity must be large so that recrystallization can occur even at lower energy. However, in general, a denser film has a large heat capacity, but heat transfer is actively occurring, and a low-density film has a somewhat low heat transfer efficiency but is easily reduced by stress. The film tends to be destroyed. In some cases, porous silicon is used for the buffer layer with the intention of not increasing the efficiency of heat transfer, but in this case, the heat capacity is small, high power is required during laser heat treatment, and substrate damage is effective. Could not be prevented. Therefore, it is very important to use a material having a characteristic of low thermal conductivity while having a large heat capacity.

III−Ｖ族窒化物半導体の異種構造を単結晶性炭化珪素（シリコンカーバイド：SiC）と単結晶性の酸化亜鉛（ZnO）とにより構成された格子整合導電プラットホーム（lattice-matched conducting platform）上に製作する技術が知られている(特許文献１)。   III-V nitride semiconductor heterogeneous structure on a lattice-matched conducting platform composed of monocrystalline silicon carbide (SiC) and monocrystalline zinc oxide (ZnO) The technique to manufacture is known (patent document 1).

室温でシリコン（Si）（００１）基板上に高周波マグネトロンスパッタリング（RF-magnetron sputtering）方法により酸化亜鉛（ZnO）膜を成長する方法が知られている(非特許文献１)。
米国特許第5,670,798号公報 Ｈ．Ｗ．キム、「異なる高周波電力条件の下での室温高周波マグネトロンスパッタ酸化亜鉛膜の構造研究」、材料科学及び工学、Ｂ１０３，第２９７−３０２頁、２００３年（H. W. Kim, “Structural studies of room temperature RF magnetron sputtered ZnO films under different RF powered condition”, Materials science and Engineering, B103, pp297-302, 2003） A method of growing a zinc oxide (ZnO) film on a silicon (Si) (001) substrate at room temperature by a high frequency magnetron sputtering (RF-magnetron sputtering) method is known (Non-patent Document 1).
US Patent No. 5,670,798 H. W. Kim, “Structural studies of room temperature radio frequency magnetron sputtered zinc oxide films under different radio frequency power conditions”, Materials Science and Engineering, B103, pp. 297-302, 2003 (HW Kim, “Structural studies of room temperature RF magnetron sputtered ZnO films under different RF powered conditions ”, Materials science and Engineering, B103, pp297-302, 2003)

従って、本発明は、上述のような問題点を解決するためのもので、本発明の目的は、熱容量が大きいながらも熱伝導度が小さい特性を有するバッファ層を用いたポリシリコン層形成方法及びこれを用いた薄膜トランジスタの製造方法を提供することにある。   Accordingly, the present invention is for solving the above-described problems, and an object of the present invention is to provide a polysilicon layer forming method using a buffer layer having a characteristic of low thermal conductivity while having a large heat capacity, and An object of the present invention is to provide a method of manufacturing a thin film transistor using the same.

上記目的を達成するための技術的手段として、本発明の第１側面は、基板上にウルツ鉱（Wurtzite）酸化亜鉛（ZnO）膜であるバッファ層を形成するステップと、上記バッファ層上にシリコン層を形成するステップと、上記シリコン層をポリシリコン層に再結晶化するステップと、を含むポリシリコン層形成方法を提供する。ここで、シリコン層は、非晶質シリコン層及びポリシリコン層を含む概念である。望ましくは、ポリシリコン層形成方法は、バッファ層を形成した後、不導体であるバリア層を形成するステップをさらに含む。   As technical means for achieving the above object, according to a first aspect of the present invention, there is provided a step of forming a buffer layer which is a wurtzite zinc oxide (ZnO) film on a substrate, and silicon on the buffer layer. There is provided a method for forming a polysilicon layer, comprising: forming a layer; and recrystallizing the silicon layer into a polysilicon layer. Here, the silicon layer is a concept including an amorphous silicon layer and a polysilicon layer. Preferably, the method for forming a polysilicon layer further includes a step of forming a non-conductor barrier layer after forming the buffer layer.

本発明の第２側面は、基板上にウルツ鉱酸化亜鉛（ZnO）膜であるバッファ層を形成するステップと、上記バッファ層上にシリコン層を形成するステップと、上記シリコン層をポリシリコン層に再結晶化するステップと、上記ポリシリコン層をパターンニングし、ドーピングを行い、ソース、チャネル及びドレインを形成するステップと、ゲート絶縁膜を形成するステップと、ゲートを形成するステップと、を含む薄膜トランジスタの製造方法を提供する。望ましくは、薄膜トランジスタの製造方法は、バッファ層を形成した後、不導体であるバリア層を形成するステップをさらに含む。   According to a second aspect of the present invention, there is provided a step of forming a buffer layer that is a wurtzite zinc oxide (ZnO) film on a substrate, a step of forming a silicon layer on the buffer layer, and converting the silicon layer into a polysilicon layer. A thin film transistor comprising: a step of recrystallizing; a step of patterning and doping the polysilicon layer to form a source, a channel and a drain; a step of forming a gate insulating film; and a step of forming a gate. A manufacturing method is provided. Preferably, the method of manufacturing a thin film transistor further includes a step of forming a non-conductor barrier layer after forming the buffer layer.

本発明に係るポリシリコン層形成方法及びこれを用いた薄膜トランジスタの製造方法は、プラスチック、金属ホイール、ガラス等、多少熱に弱い基板上にバッファ層を形成し、その上で高温を要する再結晶化工程を首尾よく行うことができるという長所がある。   A method for forming a polysilicon layer and a method for manufacturing a thin film transistor using the same according to the present invention include forming a buffer layer on a somewhat heat-sensitive substrate such as plastic, metal wheel, glass, etc., and then performing recrystallization that requires high temperature. There is an advantage that the process can be carried out successfully.

また、本発明に係るポリシリコン層形成方法及びこれを用いた薄膜トランジスタの製造方法は、バッファ層上にバリア層を形成することによってバッファ層からポリシリコン層へのイオンの拡散を防止したり、ナノ粉末を使用してバッファ層を形成する場合、予想される表面の粗さを緩和することができるという長所がある。   In addition, the method for forming a polysilicon layer and the method for manufacturing a thin film transistor using the same according to the present invention can prevent diffusion of ions from the buffer layer to the polysilicon layer by forming a barrier layer on the buffer layer. When a buffer layer is formed using a powder, there is an advantage that an expected surface roughness can be reduced.

以下、添付の図面を参照して本発明の好適な実施の形態を詳細に説明する。しかし、本発明の実施の形態等は、様々な形態に変形することができ、本発明の範囲は、以下、詳述する実施の形態等によって限定されて解釈されてはならない。本発明の実施の形態等は、当該技術分野において通常の知識を有する者に本発明をより完全に説明するために提供されているものである。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various forms, and the scope of the present invention should not be construed as being limited to the embodiments described in detail below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

図１乃至図４は、本発明の実施の一形態に係るポリシリコン層形成方法を示す図面である。   1 to 4 are views showing a method for forming a polysilicon layer according to an embodiment of the present invention.

図１を参照すると、基板１上にバッファ層２を蒸着する。基板１は、プラスチック、金属ホイール又はガラスなどであってよい。バッファ層２の必要条件は、可能な限り加えられた熱をよく吸収できるように熱容量が大きく、熱伝導性が小さくなければならない。本発明では、熱伝導率が非常に低く、融点が高く、熱容量が大きいウルツ鉱(Wurtzite)結晶構造を有する酸化亜鉛(Zinc Oxide：ZnO)、即ち、ウルツ鉱（Wurtzite）酸化亜鉛(ZnO)膜をバッファ層２に使用する。   Referring to FIG. 1, a buffer layer 2 is deposited on a substrate 1. The substrate 1 may be a plastic, a metal wheel, glass or the like. The buffer layer 2 must have a large heat capacity and a small thermal conductivity so that the applied heat can be absorbed as much as possible. In the present invention, a zinc oxide (Zinc Oxide: ZnO) having a wurtzite crystal structure having a very low thermal conductivity, a high melting point, and a large heat capacity, that is, a wurtzite zinc oxide (ZnO) film. Is used for the buffer layer 2.

酸化亜鉛(ZnO)は、製造方法によって閃亜鉛鉱(Zinc Blende)型構造又はウルツ鉱(Wurtzite)構造で成長が可能であるが、表１に示すように非常に低い熱伝導率を有するようにするためには、選択的にウルツ鉱(Wurtzite)構造で成長すべきである。結晶性の良いウルツ鉱(Wurtzite)構造（００２）は、回折(diffraction)特性分析で、ピーク(peak)のみ大きく示し、閃亜鉛鉱型(Zinc Blende)構造（００１）の場合、ピーク(peak)を主に示す（Ｈ．Ｗ．キムら、「異なる高周波電力条件の下での室温高周波マグネトロンスパッタ酸化亜鉛膜の構造研究」、材料科学及び工学、Ｂ１０３，第２９７−３０２頁、２００３年（H. W. Kim et al., “Structural studies of room temperature RF magnetron sputtered ZnO films under different RF powered condition”, Materials science and Engineering, B103, pp297-302, 2003））。   Zinc oxide (ZnO) can be grown in a zinc blende structure or a wurtzite structure depending on the manufacturing method, but has a very low thermal conductivity as shown in Table 1. In order to do so, it should selectively grow in a wurtzite structure. The wurtzite structure (002) with good crystallinity shows only the peak in the diffraction characteristic analysis, and the peak in the case of the zinc blende structure (001). (HW Kim et al., “Structural study of room temperature high frequency magnetron sputtered zinc oxide films under different high frequency power conditions”, Materials Science and Engineering, B103, pp. 297-302, 2003 (HW Kim et al., “Structural studies of room temperature RF magnetron sputtered ZnO films under different RF powered conditions”, Materials science and Engineering, B103, pp297-302, 2003)).

ウルツ鉱(Wurtzite)構造のみ選択的に蒸着する方法は、プラズマを用いる蒸着方法であるが、酸素プラズマを導入したスパッタ蒸着法、プラズマ原子層蒸着法、プラズマ化学蒸着法などがそれである。酸素プラズマを用いて亜鉛(Zn)の完全な酸化を誘導するほどウルツ鉱(Wurtzite)構造を選択的に得るのに有利である。そして、バッファ層２を２μｍ以上の厚い膜を使用する場合には、数百ｎｍ以下の大きさのナノ粉末を使用してスクリーンプリンティング法、スプレー法、インクジェットプリンティング法等により膜を形成することができる。   A method for selectively depositing only a wurtzite structure is a deposition method using plasma, but a sputtering deposition method using oxygen plasma, a plasma atomic layer deposition method, a plasma chemical vapor deposition method, or the like. It is advantageous to selectively obtain a wurtzite structure to induce complete oxidation of zinc (Zn) using an oxygen plasma. When a thick film of 2 μm or more is used for the buffer layer 2, the film can be formed by a screen printing method, a spray method, an ink jet printing method, or the like using nano powders having a size of several hundred nm or less. it can.

Figure 0004091025
Figure 0004091025

図２を参照すると、バッファ層２上にバリア層３を蒸着する。プラズマ原子層蒸着法、スパッタ蒸着法、プラズマ化学蒸着法などを使用して３０−３００ｎｍ程度の酸化アルミニウム（Al2O3）、酸窒化アルミニウム（AlON）、窒化シリコン（Si3N4）などの緻密なバリア層をバッファ層２上に形成する。特に、イオンの拡散を防止する目的では、原子層蒸着法により形成した酸化アルミニウム（Al2O3）薄膜が優れるが、はるかに低い工程温度で処理が可能なプラズマ原子層蒸着法を使用すれば、より低温でより緻密な膜を得ることができる(S. J. Yun et al., Electrochem. Solid-StateLett. 7, 2004)。バリア層３は、バッファ層２で一部拡散されて出ることができる亜鉛（Zn）イオンの侵入を防止するために形成される層である。酸素プラズマを使用して亜鉛（Zn）を完全に酸化させるようになるプラズマ蒸着法や既に完全な組成で製造されたナノ粒子等の場合、亜鉛（Zn）の拡散は深刻ではないが、バッファ層２の上部に形成するバリア層３は、再結晶化過程中、非常に少量でも亜鉛（Zn）イオンなどがシリコン層に拡散されるおそれがある敏感な素子の場合に必要である。また、バリア層３は、ウルツ鉱（Wurtzite）酸化亜鉛（ZnO）ナノ粒子を用いて膜を形成する場合には表面の粗さが劣化し得るが、これを平坦化する機能も担うことができる。また、バリア層３は、バリア層３上に形成されるシリコン層の結晶化程度を向上させる機能も担うことができ、必要な場合、結晶性を持つシード(seed)層をウルツ鉱酸化亜鉛（ZnO）バッファ層２又はその上に形成されたバリア層３上に形成できる。バリア層３を蒸着する工程は省略することもできる。 Referring to FIG. 2, a barrier layer 3 is deposited on the buffer layer 2. Using plasma atomic layer deposition, sputter deposition, plasma chemical vapor deposition, etc., about 30-300 nm aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), silicon nitride (Si 3 N 4 ), etc. A dense barrier layer is formed on the buffer layer 2. In particular, for the purpose of preventing ion diffusion, aluminum oxide (Al 2 O 3 ) thin films formed by atomic layer deposition are superior, but if plasma atomic layer deposition is used, which can be processed at much lower process temperatures, A denser film can be obtained at a lower temperature (SJ Yun et al., Electrochem. Solid-State Lett. 7, 2004). The barrier layer 3 is a layer formed to prevent intrusion of zinc (Zn) ions that can be partly diffused by the buffer layer 2 and exit. In the case of a plasma deposition method that uses oxygen plasma to completely oxidize zinc (Zn) or nanoparticles already manufactured with a perfect composition, the diffusion of zinc (Zn) is not serious, but the buffer layer The barrier layer 3 formed on the upper part of 2 is necessary in the case of a sensitive element in which zinc (Zn) ions or the like may be diffused into the silicon layer even in a very small amount during the recrystallization process. In addition, the barrier layer 3 may be deteriorated in surface roughness when a film is formed using wurtzite zinc oxide (ZnO) nanoparticles, but can also have a function of flattening the surface. . In addition, the barrier layer 3 can also have a function of improving the degree of crystallization of the silicon layer formed on the barrier layer 3, and if necessary, a seed layer having crystallinity can be used as a wurtzite zinc oxide ( ZnO) can be formed on the buffer layer 2 or the barrier layer 3 formed thereon. The step of depositing the barrier layer 3 can be omitted.

図３を参照すると、バリア層３上にシリコン層４を蒸着する。蒸着されるシリコンは、非晶質シリコン(amorphous silicon)が代表的であるが、ポリシリコンも蒸着可能である。   Referring to FIG. 3, a silicon layer 4 is deposited on the barrier layer 3. The silicon to be deposited is typically amorphous silicon, but polysilicon can also be deposited.

図４を参照すると、シリコン層をポリシリコン層５に再結晶化する。一例として、レーザを用いてシリコン層に対して再結晶化工程を行い、ポリシリコン層を形成する。また、必要に応じて再結晶化する工程は、シリコン層上にレーザ光をほとんど吸収しない絶縁膜などが追加して形成された以後になされることもできる。   Referring to FIG. 4, the silicon layer is recrystallized into a polysilicon layer 5. As an example, a silicon layer is recrystallized using a laser to form a polysilicon layer. Further, the recrystallization step can be performed after an additional insulating film or the like that hardly absorbs laser light is formed on the silicon layer as necessary.

図５は、本発明の実施の一形態によるポリシリコン層形成方法を用いた薄膜トランジスタの製造方法を説明するための図面である。   FIG. 5 is a view for explaining a method of manufacturing a thin film transistor using a method for forming a polysilicon layer according to an embodiment of the present invention.

図５において、素子は基板１、バッファ層２、バリア層３及びポリシリコン層５を含む薄膜トランジスタ５，６，７を含む。基板１、バッファ層２、バリア層３及びポリシリコン層５は、上記と同様であるので、便宜上、説明を省略する。薄膜トランジスタ５乃至１０は、ポリシリコン層５により形成されたソース８、チャネル９及びドレイン１０と、ゲート絶縁膜６及びゲート７とにより構成される。この素子構造において素子の移動度を決定する事項として、再結晶化したポリシリコン層５の膜質としてより高いエネルギーを受けて結晶粒がより大きく形成された場合、電子の移動がより容易な(速い)模様の結晶が形成された場合、より良い特性を得ることができる。従って、薄膜トランジスタ５乃至１０の特性に最も重要な影響を及ぼすステップが再結晶化ステップであり、基板の変性がない限度内で充分なエネルギーが注入されなければならないが、この際、最も重要な要素が基板１とポリシリコン層５との間の断熱である。   In FIG. 5, the device includes thin film transistors 5, 6, 7 including a substrate 1, a buffer layer 2, a barrier layer 3 and a polysilicon layer 5. Since the substrate 1, the buffer layer 2, the barrier layer 3, and the polysilicon layer 5 are the same as described above, the description thereof is omitted for convenience. The thin film transistors 5 to 10 are composed of a source 8, a channel 9 and a drain 10 formed by the polysilicon layer 5, a gate insulating film 6 and a gate 7. As a matter for determining the mobility of the element in this element structure, when a crystal grain is formed larger by receiving higher energy as the film quality of the recrystallized polysilicon layer 5, the movement of electrons is easier (faster). ) Better characteristics can be obtained when patterned crystals are formed. Therefore, the step that has the most important effect on the characteristics of the thin film transistors 5 to 10 is the recrystallization step, and sufficient energy must be injected within the limit without substrate modification. Is the heat insulation between the substrate 1 and the polysilicon layer 5.

この素子は、上記の図１乃至図４の工程を行った後に、ポリシリコン層５をパターンニングし、部分によってドーピングしてソース８、チャネル９及びドレイン１０を形成した後に、ゲート絶縁膜６を形成し、その上にゲート７を形成する方式により作製される。   After performing the above-described steps shown in FIGS. 1 to 4, the device is formed by patterning the polysilicon layer 5 and doping with portions to form the source 8, the channel 9 and the drain 10, and then forming the gate insulating film 6. It is formed by a method of forming and forming a gate 7 thereon.

ウルツ鉱酸化亜鉛（ZnO）バッファ層２は、プラスチック金属ホイールのような柔軟性基板に適用される場合、膜の特性上、柔軟性が不足してクラック(crack)が発生することがあり、厚さが厚いほどそのような傾向が激しくなる。従って、ソース及びドレインが形成される活性領域を含む領域を島(island)状に残したまま、残余の領域を蝕刻して除去する工程が必要なこともある。   When the wurtzite zinc oxide (ZnO) buffer layer 2 is applied to a flexible substrate such as a plastic metal wheel, the thickness of the wurtzite zinc oxide (ZnO) buffer layer 2 may be insufficient due to the characteristics of the film, resulting in cracks. Such a tendency becomes more severe as the thickness increases. Accordingly, it may be necessary to etch and remove the remaining region while leaving the region including the active region where the source and drain are formed in an island shape.

このような方式で作製された素子は、プラスチックのような柔軟性が大きい基板を使用して、透明な電子素子、発光素子などを製作することによって、その重さを低減し、耐衝撃性を大きくし、実装できるように作製する応用分野などに非常に幅広く使用されることができる。この場合、バッファ層を導入することによって、以前の高温工程を全部低温工程に置換することができる。本発明は、このような応用分野まで活用できる。   The device manufactured in this way uses a highly flexible substrate such as plastic to produce a transparent electronic device, light emitting device, etc., thereby reducing its weight and improving impact resistance. It can be used in a wide range of application fields that are made large and can be mounted. In this case, by introducing the buffer layer, the previous high temperature process can be completely replaced with the low temperature process. The present invention can be utilized up to such application fields.

本発明の技術的思想は、上記好適な実施の形態によって具体的に記述されたが、上記の実施の形態は、その説明のためのものであり、その制限のためのものでないことに注意しなければならない。また、本発明の技術分野の通常の専門家であれば、本発明の技術的思想の範囲内で多様な変更例が可能であることが分かる。   Although the technical idea of the present invention has been specifically described by the above-described preferred embodiments, it should be noted that the above-described embodiments are for explanation and not for limitation. There must be. In addition, it is understood that various modifications can be made within the scope of the technical idea of the present invention by a general expert in the technical field of the present invention.

本発明の実施の一形態に係るポリシリコン層形成方法を示す図面である。1 is a drawing showing a method for forming a polysilicon layer according to an embodiment of the present invention. 本発明の実施の一形態に係るポリシリコン層形成方法を示す図面である。1 is a drawing showing a method for forming a polysilicon layer according to an embodiment of the present invention. 本発明の実施の一形態に係るポリシリコン層形成方法を示す図面である。1 is a drawing showing a method for forming a polysilicon layer according to an embodiment of the present invention. 本発明の実施の一形態に係るポリシリコン層形成方法を示す図面である。1 is a drawing showing a method for forming a polysilicon layer according to an embodiment of the present invention. 本発明の実施の一形態に係るポリシリコン層形成方法を用いた薄膜トランジスタの製造方法を説明するための図面である。1 is a diagram for explaining a method of manufacturing a thin film transistor using a method for forming a polysilicon layer according to an embodiment of the present invention.

Claims (9)

基板上にウルツ鉱（Wurtzite）酸化亜鉛（ZnO）膜であるバッファ層を形成するステップと、
前記バッファ層上にシリコン層を形成するステップと、
前記シリコン層をポリシリコン層に再結晶化するステップと、
を含むことを特徴とするポリシリコン層形成方法。 Forming a buffer layer that is a Wurtzite zinc oxide (ZnO) film on a substrate;
Forming a silicon layer on the buffer layer;
Recrystallizing the silicon layer into a polysilicon layer;
A method for forming a polysilicon layer, comprising: 前記バッファ層を形成するステップは、
前記バッファ層を蒸着するステップと、
前記バッファ層のうち前記ポリシリコンが形成される位置を含む所定領域のバッファ層のみを残し、残余のバッファ層を除去するパターンニングステップと、
を含むことを特徴とする請求項１に記載のポリシリコン層形成方法。 Forming the buffer layer comprises:
Depositing the buffer layer;
A patterning step of leaving only the buffer layer in a predetermined region including the position where the polysilicon is formed in the buffer layer, and removing the remaining buffer layer;
The method for forming a polysilicon layer according to claim 1, comprising: 前記バッファ層を形成した後、不導体であるバリア層を形成するステップをさらに含むことを特徴とする請求項１に記載のポリシリコン層形成方法。   The method for forming a polysilicon layer according to claim 1, further comprising a step of forming a non-conductor barrier layer after forming the buffer layer. 前記バリア層は、酸化アルミニウム（Al2O3）、酸窒化アルミニウム（AlON）及び窒化シリコン（Si3N4）のうちのいずれか一つであることを特徴とする請求項３に記載のポリシリコン層形成方法。 4. The poly according to claim 3, wherein the barrier layer is one of aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), and silicon nitride (Si 3 N 4 ). Silicon layer forming method. 前記基板は、プラスチック基板、金属ホイール基板及びガラス基板のうちのいずれか一つであることを特徴とする請求項１に記載のポリシリコン層形成方法。   The method for forming a polysilicon layer according to claim 1, wherein the substrate is one of a plastic substrate, a metal wheel substrate, and a glass substrate. 前記ウルツ鉱酸化亜鉛（ZnO）膜は、プラズマ蒸着法、スパッタ蒸着法、プラズマ原子層蒸着法、プラズマ化学蒸着法、及び、ナノ粉末を使用して形成する方法のうちのいずれか一つの方法を用いて形成することを特徴とする請求項１に記載のポリシリコン層形成方法。   The wurtzite zinc oxide (ZnO) film may be formed by any one of a plasma deposition method, a sputter deposition method, a plasma atomic layer deposition method, a plasma chemical vapor deposition method, and a method using a nanopowder. The method for forming a polysilicon layer according to claim 1, wherein the polysilicon layer is formed by using. 前記プラズマ蒸着法は、酸素ガスが含まれたプラズマを用いることを特徴とする請求項６に記載のポリシリコン層形成方法。   The method of forming a polysilicon layer according to claim 6, wherein the plasma deposition method uses plasma containing oxygen gas. 前記再結晶化は、レーザを用いて行うことを特徴とする請求項１に記載のポリシリコン層形成方法。   The method for forming a polysilicon layer according to claim 1, wherein the recrystallization is performed using a laser. 請求項１乃至７のいずれか一項によってポリシリコン層を形成するステップと、
前記ポリシリコン層をパターンニングし、ドーピングを行い、ソース、チャネル及びドレインを形成するステップと、
ゲート絶縁膜を形成するステップと、
ゲートを形成するステップと、
を含むことを特徴とする薄膜トランジスタの製造方法。 Forming a polysilicon layer according to any one of claims 1 to 7;
Patterning and doping the polysilicon layer to form a source, a channel and a drain;
Forming a gate insulating film;
Forming a gate;
A method for producing a thin film transistor, comprising:
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