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CN104380473B - The semiconductor device - Google Patents

The semiconductor device Download PDF

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CN104380473B
CN104380473B CN 201380028160 CN201380028160A CN104380473B CN 104380473 B CN104380473 B CN 104380473B CN 201380028160 CN201380028160 CN 201380028160 CN 201380028160 A CN201380028160 A CN 201380028160A CN 104380473 B CN104380473 B CN 104380473B
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CN 201380028160
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CN104380473A (en )
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山崎舜平
肥塚纯
肥塚纯一
岛行德
德永肇
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株式会社半导体能源研究所
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    • HELECTRICITY
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/42312Gate electrodes for field effect devices
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Abstract

本发明的一个方式的目的之一是提供一种在使用氧化物半导体的半导体装置中防止电特性变动的可靠性高的半导体装置。 One object of one embodiment of the present invention is to provide a highly reliable semiconductor device for preventing variation in the electric characteristics of the semiconductor device using an oxide semiconductor. 本发明的一个方式的目的之一是提供一种半导体装置,包括:接触于源电极层及漏电极层的第一氧化物半导体层;以及成为晶体管的主要电流路径(沟道)的第二氧化物半导体层。 One object of one embodiment of the present invention is to provide a semiconductor device, comprising: a source electrode layer and in contact with the first oxide semiconductor layer, the drain electrode layer; and a second oxide as the main current path of the transistor (channel) semiconductor layer. 第一氧化物半导体层用作用来防止源电极层及漏电极层的构成元素扩散到沟道的缓冲层。 A first oxide semiconductor layer is used as a constituent element for preventing the source electrode layer and a drain electrode diffusion layer into the buffer layer channel. 通过设置第一氧化物半导体层,可以防止该构成元素扩散到第一氧化物半导体层与第二氧化物半导体层的界面及第二氧化物半导体层中。 By providing a first oxide semiconductor layer can be prevented from diffusing into the elements constituting the interface between the first oxide semiconductor layer and the second oxide semiconductor layer and the second oxide semiconductor layer.

Description

半导体装置 The semiconductor device

技术领域 FIELD

[0001] 在本说明书等中公开的发明涉及一种半导体装置及半导体装置的制造方法。 [0001] relates to a semiconductor device and a method of manufacturing a semiconductor device disclosed in the present specification and the like in the invention.

[0002] 在本说明书等中,半导体装置是指通过利用半导体特性而能够工作的所有类型的装置,因此电光装置、图像显示装置、半导体电路以及电子设备都是半导体装置。 [0002] In the present specification and the like, a semiconductor device refers to all types of apparatus can operate by using semiconductor characteristics, an electro-optical apparatus, devices, semiconductor circuits, and electronic equipments are all semiconductor image display device.

背景技术 Background technique

[0003] 使用形成在具有绝缘表面的衬底上的半导体薄膜构成晶体管的技术受到关注。 The semiconductor thin film transistor [0003] Use is formed over a substrate having an insulating surface has attracted attention. 该晶体管被广泛地应用于电子装置如集成电路(IC)、图像显示装置(也简称为显示装置)等。 The transistor is widely applied to electronic devices such as integrated circuit (IC), an image display device (also referred to simply as a display device) and the like. 作为可以应用于晶体管的半导体薄膜的材料,硅类半导体材料被广泛地周知,而作为其他材料,氧化物半导体受到注目。 As the material of the semiconductor thin film may be applied to the transistor, a silicon-based semiconductor materials are widely known, as other materials, an oxide semiconductor has been attracting attention.

[0004] 例如,公开了作为氧化物半导体使用氧化锌或In-Ga-Zn类氧化物半导体来制造晶体管的技术(参照专利文献1及专利文献2)。 [0004] For example, discloses a technique of using zinc oxide as the oxide semiconductor, or based In-Ga-Zn oxide semiconductor transistor is manufactured (see Patent Document 1 and Patent Document 2).

[0005] 另外,在非专利文献1中已公开有具有层叠有组成不同的氧化物半导体的结构的晶体管。 [0005] Further, Non-Patent Document 1 has disclosed a transistor having different compositions stacked structure of the oxide semiconductor.

[0006] [参考文献] [0006] [Reference document]

[0007] [专利文献] [0007] [Patent Document]

[0008] [专利文献1]日本专利申请公开2007-123861号公报 [0008] [Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[0009] [专利文献2]日本专利申请公开2007-096055号公报 [0009] [Patent Document 2] Japanese Patent Application Laid-Open Publication No. 2007-096055

[0010] [非专利文南犬] [0010] [Non-Venant dog]

[0011] [非专利文献1] Masashi Ono et al ·,“Novel High Performance IGZ0-TFT with High Mobility over 40 cm2/Vs and High Photostability Incorporated Oxygen Diffusion,,IDff'11 Late-News Paper,pp.1689-1690 [0011] [Patent Document 1] Masashi Ono et al ·, "Novel High Performance IGZ0-TFT with High Mobility over 40 cm2 / Vs and High Photostability Incorporated Oxygen Diffusion ,, IDff'11 Late-News Paper, pp.1689- 1690

发明内容 SUMMARY

[0012] 在使用氧化物半导体的晶体管中,当在氧化物半导体层与接触于该氧化物半导体层的层的界面存在有陷阱能级(也称为界面态)时,成为晶体管的电特性(例如,阈值电压或亚阈值摆幅值(S值))变动的原因。 [0012] In a transistor using an oxide semiconductor, the oxide semiconductor layer when in contact with the oxide semiconductor layer at the interface trap levels exist layer (also referred to as interface state), the electrical characteristics of the transistor become ( For example, the threshold voltage or the reason subthreshold swing (S value)) changes value.

[0013] 例如,在底栅型晶体管中,当源电极层及漏电极层的构成元素扩散到氧化物半导体层的背沟道时,该构成元素形成陷阱能级,使晶体管的电特性变动。 [0013] For example, in the bottom gate type transistor, when the source electrode layer and the drain electrode constituting the element diffusion layer to the back channel of the oxide semiconductor layer, the constituent elements of trap level is formed, the electrical characteristics of the transistor changes. 此外,通过在氧化物半导体层与栅极绝缘层之间的界面存在陷阱能级,也有时引起晶体管的电特性的变动。 Further, by the presence of the interface between the oxide semiconductor layer and the gate insulating layer trap level, sometimes causing changes in the electrical characteristics of the transistor.

[0014] 于是,本发明的一个方式的目的之一是提供一种防止电特性的变动而使可靠性得到提高的包含氧化物半导体的半导体装置。 [0014] Accordingly, an object of one embodiment of the present invention to provide a semiconductor device including an oxide semiconductor changes in the electrical characteristics of the improved reliability prevented.

[0015] 在本发明的一个方式中,在包含氧化物半导体的底栅型晶体管中,至少具有接触于源电极层及漏电极层的第一氧化物半导体层和设置在该第一氧化物半导体层与栅极绝缘层之间的第二氧化物半导体层的叠层结构。 [0015] In one embodiment of the present invention, in the bottom gate type transistor including an oxide semiconductor having at least a layer in contact with the source electrode and the drain electrode layer of the first oxide semiconductor layer and disposed on the first semiconductor oxide second oxide semiconductor layer laminated structure between the layer and the gate insulating layer. 在上述结构中,通过将第二氧化物半导体层用作晶体管的主要的电流路径(沟道)且将第一氧化物半导体层用作用来防止源电极层及漏电极层的构成元素的扩散的缓冲层,由此可以防止晶体管的电特性变动。 In the above configuration, by the main current path of the transistor used as the second oxide semiconductor layer (channel) and the first oxide semiconductor layer used for preventing diffusion source electrode layer and a drain electrode layer of the constituent elements the buffer layer, thereby preventing the variation in the electric characteristics of the transistor. 更具体地说,例如可以采用以下结构。 More specifically, for example, the following structures may be employed.

[0016] 本发明的一个方式是一种半导体装置,包括:栅电极层;栅电极层上的栅极绝缘层;隔着栅极绝缘层重叠于栅电极层的氧化物半导体叠层;以及电连接于氧化物半导体叠层的源电极层及漏电极层,其中,氧化物半导体叠层包括接触于源电极层及漏电极层的第一氧化物半导体层和设置在第一氧化物半导体层与栅极绝缘层之间的第二氧化物半导体层,第一氧化物半导体层至少包含铟及镓且铟的含量为镓的含量以下,第二氧化物半导体层至少包含铟及镓且铟的含量大于镓的含量,并且,第一氧化物半导体层作为杂质包含源电极层及漏电极层的构成元素。 [0016] An embodiment of the present invention is a semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; via a gate insulating layer overlaps with the gate electrode stack of an oxide semiconductor layer; and electrical connected to the stack of the oxide semiconductor layer and a source electrode a drain electrode layer, wherein the oxide semiconductor stack including a contact layer on the source electrode and the drain electrode layer of the first oxide semiconductor layer and disposed on the first oxide semiconductor layer and second oxide semiconductor layer between the gate insulating layer, a first oxide semiconductor layer containing at least indium and gallium and indium content of the Ga content is less, at least a second oxide semiconductor layer comprises indium, gallium and indium content of greater than the Ga content, and the first oxide semiconductor layer containing an impurity element constituting the source electrode layer and a drain electrode layer.

[0017] 本发明的另一个方式是一种半导体装置,包括:栅电极层;栅电极层上的栅极绝缘层;隔着栅极绝缘层重叠于栅电极层的氧化物半导体叠层;以及电连接于氧化物半导体叠层的源电极层及漏电极层,其中,氧化物半导体叠层包括接触于源电极层及漏电极层的第一氧化物半导体层、接触于栅极绝缘层的第三氧化物半导体层及设置在第一氧化物半导体层与第三氧化物半导体层之间的第二氧化物半导体层,第一氧化物半导体层及第三氧化物半导体层至少包含铟及镓且铟的含量为镓的含量以下,第二氧化物半导体层至少包含铟及镓且铟的含量大于镓的含量,并且,第一氧化物半导体层作为杂质包含源电极层及漏电极层的构成元素。 [0017] Another embodiment of the present invention is a semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; via a gate insulating layer overlaps with the gate electrode stack of an oxide semiconductor layer; and electrically connected to the stack of the oxide semiconductor layer and a source electrode a drain electrode layer, wherein the oxide semiconductor layer stack comprises a first oxide semiconductor layer in contact with the source electrode and the drain electrode layer, the gate insulating layer in contact with the first three oxide semiconductor layer and the second oxide semiconductor layer is provided between the first oxide semiconductor layer and the third oxide semiconductor layer, a first oxide semiconductor layer and the third oxide semiconductor layer containing at least indium and gallium, and content of indium gallium content is below the second oxide semiconductor layer containing at least indium and gallium content and content than that of gallium indium, and the first oxide semiconductor layer as a source electrode layer containing an impurity and drain electrode layer constituent element .

[0018] 本发明的另一个方式是一种半导体装置,包括:栅电极层;栅电极层上的栅极绝缘层;隔着栅极绝缘层重叠于栅电极层的氧化物半导体叠层;以及电连接于氧化物半导体叠层的源电极层及漏电极层,其中,氧化物半导体叠层包括接触于源电极层及漏电极层的第一氧化物半导体层、接触于栅极绝缘层的第三氧化物半导体层及设置在第一氧化物半导体层与第三氧化物半导体层之间的第二氧化物半导体层,第一氧化物半导体层及第三氧化物半导体层至少包含铟及镓且铟的含量为镓的含量以下,第二氧化物半导体层至少包含铟及镓且铟的含量大于镓的含量,第一氧化物半导体层作为杂质包含源电极层及漏电极层的构成元素,并且,第三氧化物半导体层作为杂质包含栅极绝缘层的构成元素。 [0018] Another embodiment of the present invention is a semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; via a gate insulating layer overlaps with the gate electrode stack of an oxide semiconductor layer; and electrically connected to the stack of the oxide semiconductor layer and a source electrode a drain electrode layer, wherein the oxide semiconductor layer stack comprises a first oxide semiconductor layer in contact with the source electrode and the drain electrode layer, the gate insulating layer in contact with the first three oxide semiconductor layer and the second oxide semiconductor layer is provided between the first oxide semiconductor layer and the third oxide semiconductor layer, a first oxide semiconductor layer and the third oxide semiconductor layer containing at least indium and gallium, and content of indium gallium content is below the second oxide semiconductor layer containing at least indium and gallium content and the content of indium gallium is greater than the first oxide semiconductor layer containing an impurity element constituting the source electrode layer and a drain electrode layer, and , as a third oxide semiconductor layer containing an impurity element constituting the gate insulating layer.

[0019] 在上述半导体装置中的任一个中,源电极层及漏电极层优选包含铜。 [0019] In any of the above-described semiconductor device, the source electrode layer and a drain electrode layer preferably comprises copper.

[0020] 在上述半导体装置中的任一个中,栅极绝缘层也可以包括氮化硅膜。 [0020] In any of the above-described semiconductor device, the gate insulating layer may include a silicon nitride film.

[0021] 根据本发明的一个方式的结构的效果可以如下所述那样说明。 [0021] The effect of the configuration of one embodiment of the present invention may be described as follows. 注意,以下说明只不过是一个考察而已。 Note that the following description is only a study of it.

[0022] 本发明的一个方式的晶体管包括:接触于源电极层及漏电极层的第一氧化物半导体层;以及成为晶体管的主要的电流路径(沟道)的第二氧化物半导体层。 [0022] The embodiment of the present invention is a transistor comprising: a source electrode layer and in contact with the drain electrode layer of the first oxide semiconductor layer; the main current path (channel), and becomes a second oxide semiconductor layer of the transistor. 在此,第一氧化物半导体层用作用来防止源电极层及漏电极层的构成元素扩散到沟道的缓冲层。 Here, the first oxide semiconductor layer used for preventing the source electrode layer and a drain electrode layer of the constituent elements of the buffer layer diffuse into the channel. 通过设置第一氧化物半导体层,可以防止该构成元素扩散到第一氧化物半导体层与第二氧化物半导体层的界面及第二氧化物半导体层中。 By providing a first oxide semiconductor layer can be prevented from diffusing into the elements constituting the interface between the first oxide semiconductor layer and the second oxide semiconductor layer and the second oxide semiconductor layer.

[0023] 此外,通过使应用于第一氧化物半导体层的金属氧化物的能隙(带隙)大于应用于第二氧化物半导体层的金属氧化物的能隙,可以在第二氧化物半导体层与第一氧化物半导体层之间形成导带偏移(conduction band offset),所以是优选的。 [0023] Further, by making the first oxide semiconductor layer is applied to the metal oxide of the energy gap (band gap) is greater than the second oxide semiconductor layer is applied to the energy gap of the metal oxide, the second oxide semiconductor may be forming conduction band offset (conduction band offset) between the first layer and the oxide semiconductor layer, which is preferable. 当在氧化物半导体叠层中存在有导带偏移时,在第二氧化物半导体层中载流子流过,而不使载流子流过第一氧化物半导体层及其界面,由此即使当在背沟道一侧存在有起因于金属元素的扩散的陷阱能级时,氧化物半导体叠层也不容易受到该陷阱能级的影响。 When there is an offset in the conduction band of the oxide semiconductor stack, the carrier of the second oxide semiconductor layer flows, without allowing carriers flow through the first oxide semiconductor layer and the interface, whereby even when the back channel due to the presence of diffused metal element side trap level, the oxide semiconductor stack is not easily affected by the trap level. 由此,可以实现晶体管的电特性的稳定化。 Thus, stabilization of the electrical characteristics of the transistor can be achieved.

[0024] 另外,本发明的一个方式的晶体管优选除了上述第一氧化物半导体层及第二氧化物半导体层之外还包括设置在第二氧化物半导体层与栅极绝缘层之间并接触于栅极绝缘层的第三氧化物半导体层。 [0024] Further, an embodiment of the present invention is preferably a transistor in addition to the first oxide semiconductor layer and the second oxide semiconductor layer further comprises disposed between the second oxide semiconductor layer and the gate insulating layer and in contact with third oxide semiconductor layer of the gate insulating layer. 第三氧化物半导体层包含选自第二氧化物半导体层的构成元素中的一个或多个金属元素并具有与第二氧化物半导体层相同的性质。 The third constituent element is selected from the oxide semiconductor layer comprises a second oxide semiconductor layer of one or more metal elements, and the second oxide semiconductor layer having the same properties. 因此,通过设置第三氧化物半导体层,可以使用作沟道的第二氧化物半导体层的栅极绝缘层一侧的界面稳定化。 Thus, by providing the third oxide semiconductor layer, a second interface between the gate insulating layer of oxide semiconductor as the channel layer side is stabilized. 就是说,第三氧化物半导体层用作用来防止该界面的劣化的缓冲层。 That is, the third oxide semiconductor layer used for preventing deterioration of the interfacial buffer layer. 尤其是,通过防止在沟道的栅极绝缘层一侧的界面载流子被捕捉,可以减少晶体管的光劣化(例如,光负偏压温度应力劣化),而可以得到可靠性高的晶体管。 In particular, by preventing the carriers captured at the interface of the gate insulating layer side of the channel, the light deterioration of the transistor can be reduced (e.g., negative bias temperature stress light degradation), and a highly reliable transistor can be obtained.

[0025] 此外,与应用于第一氧化物半导体层的金属氧化物同样,优选使应用于第三氧化物半导体层的金属氧化物的能隙大于应用于第二氧化物半导体层的金属氧化物的能隙,可以在第三氧化物半导体层与第二氧化物半导体层之间形成导带偏移,所以是优选的。 [0025] Further, the oxide semiconductor layer is applied to the first metal oxide Likewise, it is preferable that the oxide semiconductor layer is applied to the third metal oxide is greater than the energy gap of the oxide semiconductor layer is applied to the second metal oxide energy gap, conduction band offset can be formed between the third oxide semiconductor layer and the second oxide semiconductor layer, which is preferable. 在通常的MISFET中,在栅极绝缘层与半导体的界面也产生陷阱能级等,而使FET的电特性劣化。 In a typical MISFET are also generated in the trap level like the gate insulating layer and the semiconductor interface, so that the deterioration of the electrical characteristics of the FET. 但是,通过设置第三氧化物半导体层,MISFET具有使载流子流过离栅极绝缘层远的区域的结构(所谓埋入沟道),由此可以降低上述界面的影响。 However, by providing the third oxide semiconductor layer, having MISFETs so that carriers flow through the structure away from the gate insulating layer region (a so-called buried channel), thereby reducing the influence of the above-described interface.

[0026] 当作为第一氧化物半导体、第二氧化物半导体及第三氧化物半导体应用由相同构成元素构成并具有不同组成的金属氧化物时,例如,作为第一氧化物半导体、第二氧化物半导体及第三氧化物半导体可以使用至少含有铟及镓的金属氧化物。 [0026] When the first oxide semiconductor, the second oxide and the third oxide semiconductor composed of the same semiconductor applications and having different constituent element of the metal oxide, for example, as a first oxide semiconductor, a second oxidation and the third oxide semiconductor may be a metal oxide semiconductor containing at least indium and gallium. 在此,相对于其他金属元素的铟的含量的比率越大,金属氧化物的场效应迀移率越高,并且对其他金属元素的镓的含量越大,金属氧化物的能隙越大。 Here, the greater the content of indium with respect to the ratio of the other metal elements, the higher shift ratio of the metal oxide field effect Gan, the greater the content of gallium and other metal elements, the greater the energy gap of the metal oxide. 因此,作为成为沟道形成区的第二氧化物半导体,优选使用铟的含量大于镓的含量的金属氧化物,并且作为用作缓冲层的第一氧化物半导体及第三氧化物半导体,优选使用铟的含量为镓的含量以下的金属氧化物。 Thus, as a second channel formation region of the oxide semiconductor, the indium oxide content is preferably greater than the content of gallium and as a buffer layer as a first semiconductor oxide and the third oxide semiconductor, is preferably used content of indium gallium content is below the metal oxide.

[0027] 根据本发明的一个方式,可以提供一种在包含氧化物半导体的晶体管中可以防止电特性的变动的可靠性高的半导体装置。 The semiconductor device [0027] According to an embodiment of the present invention, to provide a transistor including an oxide semiconductor can be prevented from being varied electric characteristics of high reliability.

附图说明 BRIEF DESCRIPTION

[0028] 图IA至图IC是示出半导体装置的一个方式的平面图及截面图; [0028] FIGS. IA through IC is a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device;

[0029] 图2A至图2D是示出半导体装置的一个方式的平面图、截面图及能带图; [0029] FIGS. 2A to 2D are plan views showing one embodiment of a semiconductor device, a sectional view and an energy band diagram;

[0030] 图3A至图3D是示出半导体装置的制造方法的一个例子的图; [0030] FIGS. 3A through 3D are diagrams illustrating an example of a method of manufacturing a semiconductor device of Figure 1;

[0031] 图4A至图4C是说明半导体装置的一个方式的图; [0031] FIGS. 4A to 4C are explanatory view of one embodiment of a semiconductor device;

[0032] 图5是说明半导体装置的一个方式的图; [0032] FIG. 5 is an explanatory view of an embodiment of a semiconductor device;

[0033] 图6A和图6B是说明半导体装置的一个方式的图; [0033] FIGS. 6A and FIG. 6B is a diagram illustrating one embodiment of a semiconductor device;

[0034] 图7A和图7B是说明半导体装置的一个方式的图; [0034] FIGS. 7A and 7B are diagrams illustrating an embodiment of a semiconductor device;

[0035] 图8A至图8C是示出电子设备的图; [0035] FIGS. 8A to 8C are diagrams showing an electronic device;

[0036] 图9A至图9C是不出电子设备的图; [0036] FIGS. 9A to 9C are not the electronic device of Figure 1;

[0037] 图IOA和图IOB是示出半导体装置的一个方式的截面图; [0037] FIGS. IOA and IOB is a sectional view showing one embodiment of a semiconductor device;

[0038] 图IlA至图IlC是说明半导体装置的一个方式的图; [0038] FIGS IlA to IlC is an explanatory view of one embodiment of a semiconductor device;

[0039] 图12是示出实施例中的SSDP-S頂S的测量结果的图; [0039] FIG. 12 is a diagram showing the measurement results of Example SSDP-S of the top S of the embodiment;

[0040] 图13是说明半导体装置的一个方式的图。 [0040] FIG. 13 is a diagram of one embodiment of a semiconductor device will be described.

具体实施方式 detailed description

[0041] 下面,参照附图对本发明的实施方式及实施例进行详细说明。 [0041] Next, with reference to the accompanying drawings of embodiments of the present invention and embodiments described in detail. 但是,所属技术领域的普通技术人员可以很容易地理解一个事实,就是本发明的方式及详细内容可以被变换为各种各样的形式而不局限于以下说明。 However, those of ordinary skill in the art can be easily understood that modes and details of the present invention may be modified in various forms without being limited to the following description. 因此,本发明不应该被解释为仅局限在以下所示的实施方式及实施例所记载的内容中。 Accordingly, the present invention should not be construed as being limited to the following embodiment modes and embodiments shown in the embodiment described.

[0042] 另外,在以下说明的本发明的结构中,在不同的附图之间共同使用相同的附图标记来表示相同的部分或具有相同功能的部分,而省略其重复说明。 [0042] Further, in the structure of the present invention described below, the same reference numerals used in common in different drawings to denote the same portions or portions having the same functions, and description thereof is omitted. 另外,当表示具有相同功能的部分时有时使用相同的阴影线,而不特别附加附图标记。 Further, when parts having the same functions with the same hatching are sometimes, but not especially denoted by reference numerals.

[0043] 另外,在本说明书所说明的每个附图中,每个构成要素的大小、膜的厚度或区域为了清晰可见而有时被夸大。 [0043] Further, in each of the figures described in this specification, the size of each component, the film thickness or area to be clearly visible and sometimes exaggerated. 因此,它们不一定局限于附图中所示的尺度。 Thus, they are not necessarily limited to the dimensions shown in the drawings.

[0044] 注意,在本说明书等中,为了方便起见,附加了“第一”、“第二”等序数词,而其并不表示工序顺序或叠层顺序。 [0044] Note that in this specification and the like, for convenience, denoted as "first," "second," the ordinal numbers and the like, do not denote the order of steps or order of the stack. 此外,其在本说明书等中不表示用来特定发明的事项的固有名称。 Further, it does not denote particular names which specify the invention in this specification and the like.

[0045] 注意,在本说明书中,“平行”是指两条直线形成的角度为-10°以上且10°以下,因此也包括角度为-5°以上且5°以下的情况。 [0045] Note that in this specification, the term "parallel" refers to an angle formed by two straight lines less than -10 ° and 10 ° or less, thus including an angle of -5 ° to 5 ° or less and the case. 另外,“垂直”是指两条直线形成的角度为80°以上且100°以下,因此也包括角度为85°以上且95°以下的情况。 Furthermore, "vertical" refers to an angle formed by two straight lines is 80 ° or more and 100 ° or less, thus including an angle of 85 ° or more and 95 ° or less.

[0046] 在本说明书中,六方晶系包括二方晶系和菱方晶系。 [0046] In the present specification, it comprises two hexagonal crystal system and rhombohedral.

[0047] 实施方式1 [0047] Embodiment 1

[0048] 在本实施方式中,参照图IA至图3D对半导体装置及半导体装置的制造方法的一个方式进行说明。 [0048] In the present embodiment, FIG. 3D to a method of manufacturing a semiconductor device and a semiconductor device will be described with reference to FIG IA. 在本实施方式中,作为半导体装置的一个例子示出包括氧化物半导体层的底栅型晶体管。 In the present embodiment, as an example of a semiconductor device according to a bottom gate type transistor including an oxide semiconductor layer.

[0049] 图IA至图IC示出晶体管300的结构实例。 [0049] FIGS. IA through IC illustrate a configuration example of transistor 300. 图IA是晶体管300的平面图,图IB是沿着图IA的点划线Xl-Yl的截面图,并且图IC是沿着图IA的点划线Vl-Wl的截面图。 FIG IA is a plan view of a transistor 300, FIG. IB is a sectional view Xl-Yl-dot chain line in FIG. IA along, and is a cross-sectional view of the IC-dot chain line in FIG along Vl-Wl of FIG IA.

[0050] 晶体管300包括:设置在具有绝缘表面的衬底400上的栅电极层402;栅电极层402 上的栅极绝缘层404;在栅极绝缘层404上并与其接触的重叠于栅电极层402的氧化物半导体叠层408;以及电连接于氧化物半导体叠层408的源电极层410a及漏电极层410b。 [0050] 300 transistor comprising: a gate electrode layer disposed on the substrate 402 of the insulating surface 400; the gate electrode layer 404 on the gate insulating layer 402; on the gate insulating layer 404 and in contact with the gate electrode overlaps the stack of the oxide semiconductor layer 402 408; and a laminate electrically connected to the source electrode of the oxide semiconductor layer 408 and drain electrode layers 410a 410b. 另外,晶体管300的构成要素也可以包括覆盖源电极层410a及漏电极层410b并接触于氧化物半导体叠层408的绝缘层412。 Further, the components may also include a transistor 300 to cover the source electrode layer 410a and the drain electrode layer 410b and the oxide semiconductor in contact with the insulating layer 408 of the laminate 412.

[0051] 在晶体管300中,氧化物半导体叠层408包括:接触于源电极层410a及漏电极层410b的氧化物半导体层408a;以及设置在氧化物半导体层408b与栅极绝缘层404之间的氧化物半导体层408b。 [0051] In the transistor 300, the oxide semiconductor stack 408 comprising: contacting the source electrode layer 410a and the drain electrode layer of the oxide semiconductor layer 408a 410b; and disposed between the oxide semiconductor layer 408b and the gate insulating layer 404 oxide semiconductor layer 408b.

[0052] 在氧化物半导体叠层408中,氧化物半导体层408b是形成晶体管300的沟道的区域。 [0052] In the oxide semiconductor stack 408, the oxide semiconductor layer 408b is a channel region of the transistor 300 is formed. 此外,设置在氧化物半导体层408b的背沟道一侧的氧化物半导体层408a用作防止源电极层410a及漏电极层410b的构成元素扩散到氧化物半导体层408b的缓冲层。 Further, the constituent elements disposed in a back channel side of the oxide semiconductor layer oxide semiconductor layer 408b is used to prevent the source electrode layer 408a and the drain electrode layer 410b 410a is diffused into the oxide semiconductor layer is a buffer layer 408b. 就是说,氧化物半导体层408a作为杂质包含源电极层410a及漏电极层410b的构成元素。 That is, the oxide semiconductor layer 408a constituting the element contained as an impurity source electrode layer 410a and the drain electrode layer 410b. 通过设置该缓冲层,可以防止在晶体管300的沟道中形成陷阱能级,由此可以防止起因于陷阱能级的S值的增大。 By providing the buffer layer may prevent the formation of trap level in the channel of the transistor 300, thereby preventing the trap level due to increased S value. 因此,通过防止晶体管的电特性的改变或随时间的劣化,可以提供可靠性高的半导体装置。 Thus, by preventing the deterioration in the electrical characteristics of the transistor to change or with time, a highly reliable semiconductor device can be provided.

[0053] 氧化物半导体层408a及氧化物半导体层408b既可以使氧化物半导体层408a与氧化物半导体层408b的构成元素彼此不同,又可以使两者的构成元素相同但组成不同。 [0053] The oxide semiconductor layer 408a and the oxide semiconductor layer 408b may be the oxide semiconductor layer 408a and the constituent element of the oxide semiconductor layer 408b is different from each other, and can make the same constituent elements but different composition of both. 但是, 作为用作晶体管300的沟道的氧化物半导体层408b,优选应用场效应迀移率高的氧化物半导体。 However, as the oxide semiconductor layer for a channel 408b of the transistor 300, the preferred application rate of the field effect Gan shift oxide semiconductor.

[0054] 例如,当使氧化物半导体层408a及氧化物半导体层408b的构成元素相同并使用至少含有铟及镓的氧化物半导体时,作为氧化物半导体层408b优选使用铟的含量大于镓的含量的氧化物半导体,作为氧化物半导体层408a,优选使用铟的含量为镓的含量以下的氧化物半导体。 [0054] For example, when the oxide semiconductor layer composed of the same elements 408a and 408b and the oxide semiconductor layer using an oxide semiconductor containing at least indium and gallium, indium is used as the oxide semiconductor layer 408b is preferably larger than the content of the Ga content an oxide semiconductor as an oxide semiconductor layer 408a, the indium content is preferably below the content of gallium oxide semiconductor.

[0055] 在氧化物半导体中,重金属的s轨道主要有助于载流子传导,并通过使铟的含有率增多来呈现s轨道的重叠较多的倾向。 [0055] In the oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier conduction, and renders the track more overlapping s tendency by increasing the content ratio of indium. 因此,通过在氧化物半导体层408b中使铟的含量大于镓的含量,氧化物半导体层408b可以与铟的含量低于镓的含量的氧化物相比具有高场效应迀移率。 Accordingly, the content of the Ga content in the oxide semiconductor layer 408b is greater than manipulation of indium oxide semiconductor layer 408b may be less than the content of indium gallium oxide content compared to high field-effect Gan shift rate.

[0056] 另外,由于金属氧化物中相对于其他金属元素的镓的比率越大,金属氧化物的能隙越大,所以通过在氧化物半导体层408a中使铟的含量为镓的含量以下而使氧化物半导体层408a具有比氧化物半导体层408b大的能隙。 [0056] Further, since the metal oxide with respect to the larger ratio of gallium metal elements other, larger energy gap of the metal oxide, the content manipulation through indium gallium oxide semiconductor layer 408a and the content of the following the oxide semiconductor layer 408a has a larger energy gap than the oxide semiconductor layer 408b. 因此,可以在氧化物半导体层408b与氧化物半导体层408a之间形成导带偏移,所以上述结构是优选的。 Thus, the conduction band offset can be formed between the oxide semiconductor layer 408b and the oxide semiconductor layer 408a, so the above structure is preferable. 此外,由于镓的氧空位的形成能量比铟大,所以与铟相比,镓不容易产生氧空位。 Further, since the energy of gallium indium larger than oxygen vacancies, as compared with indium, gallium, oxygen vacancies are not likely to occur. 由此,与铟的含量大于镓的含量的金属氧化物相比,铟的含量为镓的含量以下的金属氧化物具有稳定的特性。 Accordingly, the content of gallium and indium content of the metal oxide is greater than compared to the content of indium gallium content of the metal oxide having the following characteristics stable. 由此,可以使晶体管300的背沟道一侧进一步稳定化。 This can cause a back channel side of the transistor 300 is further stabilized.

[0057] 例如,在将In-Ga-Zn类氧化物半导体用于氧化物半导体层408a及氧化物半导体层408b时,作为氧化物半导体层408a,可以使用具有In:Ga:Zn = 1:1:1 (= 1/3:1/3:1/3)、In: Ga: Zn = 1: 3: 2 ( = 1/6 :3/6: 2/6)、In :Ga: Zn = 2:4:3 ( = 2/9:4/9:3/9)或In:Ga:Zn = 1: 5: 3 (=1/9:5/9: 3/9)的原子数比的In-Ga-Zn类氧化物或与该原子数比相似的金属氧化物。 [0057] For example, when the In-Ga-Zn-based oxide semiconductor used for the oxide semiconductor layer 408a and the oxide semiconductor layer 408b, as the oxide semiconductor layer 408a, may be used with In: Ga: Zn = 1: 1 : 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 1: 3: 2 (= 1/6: 3/6: 2/6), In: Ga: Zn = 2 : 4: 3 (= 2/9: 4/9: 3/9) or in: Ga: Zn = 1: in atomic number ratio of 5: 3 (3/9 = 1/9:: 5/9) -Ga-Zn-based oxide or a similar number of atoms of the metal oxide ratio. 作为氧化物半导体层408b,可以使用具有In:Ga:Zn = 3:1:2 (=3/6:1/6:2/6)、In:Ga:Zn = 4: 2:3 (=4/9:2/9:3/9)、In:Ga:Zn = 5:1:3 (=5/9:1/9:3/9)、In:Ga:Zn = 5:3:4 (=5/12:3/ 12:4/12)、In:Ga:Zn = 6:2:4 (=6/12:2/12:4/12)或In:Ga:Zn = 7:1:3 (=7/11:1/11:3/11) 的原子数比的In-Ga-Zn类氧化物或与该原子数比相似的金属氧化物。 As the oxide semiconductor layer 408b, may be used with In: Ga: Zn = 3: 1: 2 (= 3/6: 1/6: 2/6), In: Ga: Zn = 4: 2: 3 (= 4 / 9: 2/9: 3/9), In: Ga: Zn = 5: 1: 3 (= 5/9: 1/9: 3/9), In: Ga: Zn = 5: 3: 4 ( = 5/12: 3/12: 4/12), In: Ga: Zn = 6: 2: 4 (= 6/12: 2/12: 4/12) or In: Ga: Zn = 7: 1: 3 (= 7/11: 1/11: 3/11) of the in-Ga-Zn-based oxide or of the ratio of the number of atoms with atomic numbers similar to the ratio of the metal oxide.

[0058] 注意,例如表述“In、Ga、Zn的原子数比为I η: Ga: Zn = a: b: c (a+b+c = 1)的氧化物的组成近似于原子数比为In:Ga:Zn = A:B:C(A+B+C=l)的氧化物的组成”是指a、b、c满足式^-△”+(!^”+((^(^^^的关系^例如可以为。^。 [0058] Note that, for example, the number of atoms expressed "In, Ga, Zn ratio I η: Ga: Zn = a: b: c (a + b + c = 1) similar to the composition of the oxide atomic ratio of the number of in: Ga: Zn = a: B: composition of the oxide C (a + B + C = l) "means a, b, c satisfies the formula ^ - △" + (^ "+ ((^ (^! ^ ^ ^ for example, the relationship can be. ^.

[0059] 注意,应用于氧化物半导体叠层408的金属氧化物不局限于此,根据所需要的电特性(场效应迀移率、阈值、偏差等)而使用适当的组成的材料即可。 [0059] Note that, the metal oxide applied to the oxide semiconductor stack 408 is not limited to this, according to the desired electrical characteristics (shift field effect Gan, threshold, deviation, etc.) and using the appropriate composition of a material. 另外,优选采用适当的载流子浓度、杂质浓度、缺陷密度、金属元素及氧的原子数比、原子间距离以及密度等,以得到所需要的电特性。 Further, preferably the appropriate concentration, the impurity concentration of the carrier, the defect density, the atomic number ratio of oxygen and a metal element, the distance between atoms, and density, to obtain the desired electrical characteristics. 例如,可以包含其他金属元素来代替镓。 For example, it may contain other metal elements in place of gallium. 或者,也可以使用不包含锌的金属氧化物。 Alternatively, a metal oxide may be used that does not contain zinc. 但是,在所应用的金属氧化物的组成中包含锌时,较容易使后面形成的氧化物半导体层成为CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor:c轴取向结晶氧化物半导体)膜,所以是优选的。 However, when the composition of the metal comprising zinc oxide in the application, it is easier to make the oxide semiconductor layer to be formed later becomes CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor: c-axis oriented crystalline oxide semiconductor) film, the It is preferred.

[0060] 另外,氧化物半导体层可以利用溅射法形成,通过使溅射靶材包含铟,可以防止在成膜时产生微粒。 [0060] Further, the oxide semiconductor layer can be formed by sputtering, the sputtering target containing indium by making possible to prevent generation of particles during deposition. 由此,优选使氧化物半导体层408a及氧化物半导体层408b包含铟。 Accordingly, it is preferable that the oxide semiconductor layers 408a and 408b of the oxide semiconductor layer comprises indium.

[0061] 下面,对氧化物半导体层的结构进行说明。 [0061] Next, the configuration of the oxide semiconductor layer will be described.

[0062] 氧化物半导体层大致分为单晶氧化物半导体层和非单晶氧化物半导体层。 [0062] The oxide semiconductor layer into a single crystal substantially non-single-crystal oxide semiconductor layer and the oxide semiconductor layer. 非单晶氧化物半导体层包括非晶氧化物半导体层、微晶氧化物半导体层、多晶氧化物半导体层及c 轴取向结晶氧化物半导体(CAAC-OS)膜等。 Non-single-crystal oxide semiconductor layer comprises an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer and the c-axis oriented crystalline oxide semiconductor (CAAC-OS) film.

[0063] 非晶氧化物半导体层具有无序的原子排列并不具有结晶成分。 [0063] The amorphous oxide semiconductor layer having a disordered atomic arrangement does not have a crystalline component. 其典型例子是在微小区域中也不具有结晶部而膜整体具有非晶结构的氧化物半导体层。 A typical example is a crystalline portion not having the minute region and the entire film is an oxide semiconductor layer having an amorphous structure.

[0064] 微晶氧化物半导体层例如包括Inm以上且小于IOnm的尺寸的微晶(也称为纳米晶体)。 [0064] The microcrystalline oxide semiconductor layer includes, for example less than Inm or more and a crystallite size of IOnm (also called nanocrystals). 因此,微晶氧化物半导体层的原子排列的有序度比非晶氧化物半导体层高。 Thus, the microcrystalline order of the atomic arrangement of the oxide semiconductor layer than the amorphous oxide semiconductor storey. 因此,微晶氧化物半导体层的缺陷态密度低于非晶氧化物半导体层。 Thus, the defect density of the oxide semiconductor layer is lower than the microcrystalline amorphous oxide semiconductor layer.

[0065] CAAC-OS膜是包含多个结晶部的氧化物半导体层之一,大部分的结晶部的尺寸为能够容纳于单边短于IOOnm的立方体内的尺寸。 [0065] CAAC-OS film is an oxide semiconductor layer comprises one of a plurality of portions of the crystal, the majority of the size of the crystalline portion can be accommodated to the size of the cube of unilateral shorter than IOOnm. 因此,有时包括在CAAC-OS膜中的结晶部的尺寸为能够容纳于单边短于l〇nm、短于5nm或短于3nm的立方体内的尺寸。 Thus, sometimes it included in CAAC-OS film crystal part to accommodate a shorter l〇nm to unilateral, 5nm less than 3nm, or less within the cube. CAAC-OS膜的缺陷态密度低于微晶氧化物半导体层。 CAAC-OS film defect density is less than the microcrystalline state of the oxide semiconductor layer. 下面,对CAAC-OS膜进行详细的说明。 Next, the CAAC-OS film be described in detail.

[0066] 在CAAC-OS膜的透射电子显微镜(TEM: Transmission Electron Microscope)图像中,观察不到结晶部与结晶部之间的明确的边界,即晶界(grain boundary)。 [0066] CAAC-OS film in a transmission electron microscope (TEM: Transmission Electron Microscope) image observed not clear boundary between the crystalline portion and the crystalline portion, i.e., the grain boundary (grain boundary). 因此,在CAAC-OS膜中,不容易发生起因于晶界的电子迀移率的降低。 Thus, the CAAC-OS film, does not easily occur due to the decrease of the grain boundary Gan electronic shift rate.

[0067] 根据从大致平行于样品面的方向观察的CAAC-OS膜的TEM图像(截面TEM图像)可知在结晶部中金属原子排列为层状。 [0067] The metal atoms are arranged in a layered crystalline portion in the TEM image of the (cross-sectional TEM image) CAAC-OS film was observed from a direction substantially parallel to the sample surface. 各金属原子层具有反映形成CAAC-OS膜的表面(也称为形成表面)或CAAC-OS膜的顶面的形态并以平行于CAAC-OS膜的形成表面或顶面的方式排列。 Each metal atom layer having a surface is formed to reflect CAAC-OS film (also referred to as forming surface) or the top surface morphology CAAC-OS film and is formed in parallel to a top surface or a surface CAAC-OS film arrangement.

[0068] 另一方面,根据从大致垂直于样品面的方向观察的CAAC-OS膜的TEM图像(平面TEM 图像)可知在结晶部中金属原子排列为三角形状或六角形状。 [0068] On the other hand, according to the TEM image (TEM image plane) CAAC-OS film was observed from a direction substantially perpendicular to the sample surface in the crystal portion of the metal atoms are arranged in a triangular or hexagonal shape. 但是,在不同的结晶部之间金属原子的排列没有规律性。 However, between the different crystalline portions is not regular arrangement of metal atoms.

[0069] 由截面TEM图像及平面TEM图像可知,CAAC-OS膜的结晶部具有取向性。 [0069] apparent from a sectional TEM image and a planar TEM image, the crystalline portion having a CAAC-OS film orientation.

[0070] 使用X射线衍射(XRD:X-Ray Diffraction)装置对CAAC-OS膜进行结构分析。 [0070] X-ray diffraction (XRD: X-Ray Diffraction) device CAAC-OS film subjected to structural analysis. 例如, 当利用out-of-plane法分析包括InGaZnO4结晶的CAAC-OS膜时,在衍射角(2Θ)为31°附近时出现峰值。 For example, InGaZnO4 including CAAC-OS film during crystallization peak appears at a diffraction angle (2 [Theta) is around 31 ° when using out-of-plane Method. 由于该峰值来源于InGaZnO4结晶的(009)面,由此可以确认CAAC-OS膜中的结晶具有c轴取向性,并且c轴取向于大致垂直于CAAC-OS膜的形成表面或顶面的方向。 This peak is derived (009) crystal plane InGaZnO4, whereby it was confirmed CAAC-OS film having a crystal c-axis orientation and the c-axis orientation direction or top surface is formed in substantially perpendicular to the film CAAC-OS .

[0071] 另一方面,当利用从大致垂直于c轴的方向使X射线入射到样品的in-plane法分析CAAC-OS膜时,在2Θ为56 °附近时出现峰值。 [0071] On the other hand, a peak appears in the vicinity of 2Θ is 56 ° when the incident X-rays using a sample in-plane CAAC-OS film was analyzed from a direction substantially perpendicular to the c-axis. 该峰值来源于InGaZnO4结晶的(I 10)面。 This peak is derived InGaZnO4 crystals (I 10) surface. 在此,将2Θ固定为56°附近并在以样品面的法线向量为轴(Φ轴)旋转样品的条件下进行分析(Φ扫描)。 Here, the vicinity of 56 ° 2Θ is fixed and analyzed (Scan [Phi]) at the sample surface to an axis normal vector ([Phi] axis) of the sample conditions. 当该样品是InGaZnO4的单晶氧化物半导体层时,出现六个峰值。 When the sample is a single crystal oxide InGaZnO4 semiconductor layer, six peaks. 该六个峰值来源于相当于(110)面的结晶面。 The six peaks are derived from crystal plane equivalent to (110) plane. 另一方面,当该样品是CAAC-OS膜时,即使在将2Θ固定为56°附近的状态下进行Φ扫描也不能观察到明确的峰值。 On the other hand, when the sample is a CAAC-OS film, Φ scan performed even in a case fixed to the vicinity of 56 ° 2Θ state can not be clearly observed peak.

[0072] 由上述结果可知,在具有c轴取向的CAAC-OS膜中,虽然a轴及b轴的方向在结晶部之间不同,但是c轴都取向平行于形成表面或顶面的法线向量的方向。 [0072] From these results, in the CAAC-OS film having a c-axis orientation, while the a-axis and b-axis orientation differs between the crystalline portion, the c-axes are oriented parallel to or normal to the top surface of the forming surface direction of the vector. 因此,在上述截面TEM 图像中观察到的排列为层状的各金属原子层相当于与结晶的ab面平行的面。 Thus, the cross section observed in the TEM images arranged in a layered metal atom layer corresponds to each of the crystal plane parallel to the ab plane.

[0073] 注意,结晶部在形成CAAC-OS膜或进行加热处理等结晶处理时形成。 [0073] Note that the crystal is formed in a portion CAAC-OS film formed during the heat treatment or crystallization treatment and the like. 如上所述,结晶的c轴朝向平行于CAAC-OS膜的形成表面或顶面的法线向量的方向。 As described above, the direction parallel to the normal vector CAAC-OS film surface or top surface of the c-axis orientation is formed. 由此,例如,当CAAC- OS膜的形状因蚀刻等而发生改变时,结晶的C轴不一定平行于CAAC-OS膜的形成表面或顶面的法线向量。 Thus, for example, when the shape of CAAC- OS film by etching or the like changes, the crystalline C-axis is not necessarily parallel to the normal vector or top surface is formed CAAC-OS film.

[0074] 此外,CAAC-OS膜中的结晶度不一定均匀。 [0074] Further, the crystallinity of the CAAC-OS film is not necessarily uniform. 例如,当CAAC-OS膜的结晶部是由CAAC-OS膜的顶面近旁的结晶成长而形成时,有时顶面附近的结晶度高于形成表面附近的结晶度。 For example, when the crystalline portion CAAC-OS film is grown from a top surface of the crystal in the vicinity CAAC-OS film is formed, sometimes the degree of crystallinity is higher than near the top surface is formed near the surface crystallinity. 另外,当对CAAC-OS膜添加杂质时,添加了杂质的区域的结晶度改变,所以有时CAAC-OS 膜中的结晶度根据区域而不同。 Further, when the impurity is added to CAAC-OS film, crystallinity of the added impurity region changes, it is sometimes crystallinity CAAC-OS film differ according to regions.

[0075] 注意,当利用out-of-plane法分析包括InGaZnO4结晶的CAAC-OS膜时,除了在2Θ为31°附近的峰值之外,有时还在2Θ为36°附近观察到峰值。 [0075] Note that, when analyzed using the method of-plane out-CAAC-OS film comprising crystalline when InGaZnO4, except in the vicinity of 31 ° 2Θ peak outside, sometimes in the vicinity of 36 ° 2Θ observed as a peak. 2Θ为36°附近的峰值意味着CAAC-OS膜的一部分中含有不具有c轴取向的结晶。 It means that the peak portion of the CAAC-OS film is around 36 ° 2Θ contains no crystal having c-axis orientation. 优选的是,在CAAC-OS膜中在2Θ为31°附近时出现峰值而在2Θ为36 °附近时不出现峰值。 Preferably, a peak appears at around 31 ° 2Θ is in the CAAC-OS film does not occur while the peak at 2Θ is around 36 °.

[0076] 在使用CAAC-OS膜的晶体管中,起因于可见光或紫外光的照射的电特性的变动小。 Small changes in the electrical properties [0076] In a transistor using CAAC-OS film, due to the irradiation with visible light or ultraviolet light. 因此,该晶体管具有高可靠性。 Thus, the transistor has high reliability.

[0077] 注意,氧化物半导体层例如也可以是包括非晶氧化物半导体层、微晶氧化物半导体层和CAAC-OS膜中的两种以上的叠层膜。 [0077] Note that the oxide semiconductor layer may be, for example, comprise amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer and two or more films stacked film CAAC-OS.

[0078] CAAC-OS膜例如可以通过使用多晶的金属氧化物溅射靶材的溅射法形成。 [0078] CAAC-OS film may be formed by using a polycrystalline metal oxide sputtering target sputtering method. 当离子碰撞到该溅射用靶材时,有时包含在溅射用靶材中的结晶区域从靶材沿ab面劈开,S卩,具有平行于a_b面的面的平板状或颗粒状的溅射粒子从溅射靶材中剥离。 When the ions collide with the crystalline region of the target during sputtering, sometimes contained in the sputtering target material from the target is split along the ab plane, S Jie, parallel to the plane of the flat surface a_b or granular sputtered particles peeled off from the sputtering target. 此时,通过该平板状的溅射粒子保持结晶状态到达衬底,可以形成CAAC-OS膜。 In this case, to maintain the crystalline state by the plate-like sputtered particles reaching the substrate can be formed CAAC-OS film.

[0079] 另外,为了形成CAAC-OS膜,优选应用如下条件。 [0079] Further, in order to form CAAC-OS film, the following conditions are preferably applied.

[0080] 通过降低形成CAAC-OS膜时的杂质的混入量,可以防止因杂质导致的结晶状态损坏。 When the mixed amount of impurities [0080] CAAC-OS film is formed by reducing the crystal state can be prevented from damage caused by impurities. 例如,可以降低存在于成膜室内的杂质(氢、水、二氧化碳及氮等)的浓度。 For example, it is possible to reduce the concentration of impurities (hydrogen, water, carbon dioxide and nitrogen) present in the deposition chamber. 另外,可以降低成膜气体中的杂质浓度。 Further, it is possible to reduce the impurity concentration in the film forming gas. 具体而言,使用露点为-80°C以下,优选为-100°C以下的成膜气体。 Specifically, a dew point of -80 ° C or less, preferably a film-forming gas of -100 ° C or less.

[0081] 另外,通过提高成膜时的衬底加热温度,在溅射粒子附着到衬底表面之后可能发生溅射粒子的迀移。 [0081] Further, by heating the substrate temperature during deposition increased, after the sputtered particles attached to the substrate surface may occur Gan sputtered particles move. 具体而言,在将衬底加热温度设定为l〇〇°C以上且740°C以下,优选为200°C以上且500°C以下的状态下进行成膜。 Specifically, in the film formation state of 500 ° C and less than 200 ° C The substrate heating temperature is set to l〇〇 ° C and are 740 ° C or less, preferably. 通过提高成膜时的衬底加热温度,当平板状的溅射粒子到达衬底时,在衬底表面上发生迀移,平板状溅射粒子的平坦的面附着到衬底。 By heating the substrate temperature during deposition increased, when the sputtered particles reaching the flat plate-like substrate, Gan shift occurs on the substrate surface, a flat surface of the plate-like sputtered particles attached to the substrate.

[0082] 另外,优选的是,通过增高成膜气体中的氧比例并对电力进行最优化,以减轻成膜时的等离子体损伤。 [0082] Further, preferably, optimized by increasing the proportion of oxygen in the deposition gas and power, in order to reduce plasma damage at the deposition. 将成膜气体中的氧比例设定为30vo 1 %以上,优选为IOOvo 1 %。 The proportion of oxygen in the deposition gas is set not less than 30vo 1%, preferably IOOvo 1%.

[0083] 以下,作为溅射用金属氧化物靶材的一个例子,示出In-Ga-Zn-O化合物靶材。 [0083] Here, as an example of a metal oxide sputtering target, shown In-Ga-Zn-O compound target.

[0084] 将InOx粉末、GaOY粉末及ZnOz粉末以预定的比率混合,进行加压处理,然后在1000 °C以上且1500°C以下的温度下进行加热处理,由此得到作为多晶的In-Ga-Zn-O化合物靶材。 [0084] The powder InOx, GaOY ZnOz powder and mixed powder at a predetermined ratio, pressure treatment, and then subjected to heat treatment at a temperature of 1500 ° C or less above 1000 ° C, to thereby obtain a polycrystalline In- ga-Zn-O compound target. 另外,X、Y及Z为任意正数。 Further, X, Y and Z are arbitrary positive number. 在此,InOx粉末、GaOY粉末及ZnOz粉末的预定的摩尔数比例如为2:2:1、8:4:3、3:1:1、1:1:1、4:2:3或3:1:2。 Here, InOx powder, a predetermined number of molar ratio GaOY ZnOz powder and powder such as 2: 2: 1, 8: 4: 3,3: 1: 1,1: 1: 1,4: 2: 3 or 3 : 1: 2. 另外,粉末的种类及其混合摩尔数比可以根据所需要的溅射用靶材适当地改变。 Further, the type of powder and mixing molar number may be appropriately changed according to a sputtering target material ratio desired.

[0085] 另外,也可以使氧化物半导体层408a的结晶性与氧化物半导体层408b不同。 [0085] Further, the oxide semiconductor layer may 408a crystalline oxide semiconductor layer 408b are different. 但是, 作为用作晶体管300的沟道的氧化物半导体层408b,优选应用CAAC-OS膜。 However, as transistor 300 functions as a channel of the oxide semiconductor layer 408b, is preferably applied CAAC-OS film. 此外,在氧化物半导体层408b使用CAAC-OS膜形成时,在氧化物半导体层408b上并与其接触的氧化物半导体层408a中发生前体(precursor)的取向,S卩,通过使该前体具有所谓秩序性,有时可以使氧化物半导体层408a成为CAAC-OS膜。 The alignment precursor (precursor) occurs in the oxide semiconductor layer 408a in the oxide semiconductor layer 408b using CAAC-OS film is formed on the oxide semiconductor layer 408b in contact therewith, S Jie, the precursor by with so-called order, and sometimes can be the oxide semiconductor layer 408a CAAC-OS film. 在设置在背沟道一侧的氧化物半导体层408a由非晶氧化物半导体形成的情况下,由于形成源电极层410a及漏电极层410b时的蚀刻处理而产生氧空位而容易使氧化物半导体层408a成为η型。 In the case where the oxide semiconductor layer is disposed on the back side of the channel 408a is formed of an amorphous oxide semiconductor, since the source electrode layer 410a and the drain electrode upon etching layer 410b generate oxygen vacancy in the oxide semiconductor is easily η-type layer 408a becomes. 因此,优选将具有结晶性的氧化物半导体应用于氧化物半导体层408a。 Thus, preferably having a crystallinity of an oxide semiconductor is applied to the oxide semiconductor layer 408a.

[0086] 此外,在本实施方式中,氧化物半导体层408a和氧化物半导体层408b是使用相同构成元素形成的氧化物半导体叠层。 [0086] In the present embodiment, the oxide semiconductor layer 408a and the oxide semiconductor is an oxide semiconductor layer 408b laminate formed using the same constituent elements. 此时,根据氧化物半导体层的材料或成膜条件的不同, 各氧化物半导体层之间的界面有时不明确。 At this time, depending on the material or the film formation conditions of the oxide semiconductor layer, the interface between the oxide semiconductor layer is sometimes not clear. 因此,在图IA至图IC中,以虚线示意性地示出氧化物半导体层408a和氧化物半导体层408b的界面。 Thus, in FIGS. IA to IC, a broken line schematically shows the interface of the oxide semiconductor layers 408a and 408b of the oxide semiconductor layer. 这是与后面的各附图同样。 This is the same with the accompanying drawings later.

[0087] 图2A至图2C示出晶体管310的结构实例。 [0087] Figures 2A to 2C show an example of the structure of transistor 310. 图2A是晶体管310的平面图,图2B是沿着图2A的点划线X2-Y2的截面图,图2C是沿着图2A的点划线V2-W2的截面图。 2A is a plan view of a transistor 310, FIG. 2B is a sectional view taken along the dot-dash line X2-Y2 of FIG. 2A, FIG. 2C is a sectional view dot chain line along the V2-W2 in FIG. 2A. 与图IA至图IC所示的晶体管300同样,图2A至图2C所示的晶体管310包括:设置在具有绝缘表面的衬底400上的栅电极层402;栅电极层402上的栅极绝缘层404;接触于栅极绝缘层404上并重叠于栅电极层402的氧化物半导体叠层408;以及电连接于氧化物半导体叠层408的源电极层410a及漏电极层410b。 FIG IA to IC transistor Similarly, FIGS. 2A to 2C transistor 300 shown 310 includes: a gate electrode layer disposed on the substrate 402 of the insulating surface 400; a gate insulating layer on the gate electrode 402 layer 404; 404 in contact with the gate insulating layer and overlaps with the gate electrode layer 402, an oxide semiconductor stack 408; and a laminate electrically connected to the source electrode of the oxide semiconductor layer 408 and drain electrode layers 410a 410b. 另外,晶体管310的构成要素也可以包括覆盖源电极层410a及漏电极层410b 并接触于氧化物半导体叠层408的绝缘层412。 Further, the components may also include a transistor 310 to cover the source electrode layer 410a and the drain electrode layer 410b and the oxide semiconductor in contact with the insulating layer 408 of the laminate 412.

[0088] 晶体管310与晶体管300不同之处是:晶体管310在氧化物半导体层408b与栅极绝缘层404之间包括氧化物半导体层408c。 [0088] The transistor 310 is different from the transistor 300 is: a transistor 310 between the oxide semiconductor layer 408b and the gate insulating layer 404 includes an oxide semiconductor layer 408c. 就是说,在晶体管310中,氧化物半导体叠层408具有氧化物半导体层408a、氧化物半导体层408b及氧化物半导体层408c的叠层结构。 That is, the transistor 310, the stack of the oxide semiconductor layer 408 having the oxide semiconductor 408a, 408b and the oxide semiconductor layer stacked structure of the oxide semiconductor layer 408c.

[0089] 注意,除了氧化物半导体层408c之外,晶体管310的结构与晶体管300相同,因而可以参照关于晶体管300的说明。 [0089] Note that, in addition to an oxide semiconductor layer 408c, transistor 310 and transistor 300 of the same structure, and therefore can be referred to the description of the transistor 300.

[0090] 通过在晶体管310中的形成沟道的氧化物半导体层408b与栅极绝缘层404之间设置氧化物半导体层408c,使晶体管310具有载流子流过离栅极绝缘层404远的区域的结构(所谓埋入沟道)。 [0090] By forming a channel of the oxide semiconductor layer in the transistor 310 is provided between the oxide semiconductor layer 408c 408b and the gate insulating layer 404, the transistor 310 has a carrier 404 away from the flow through the gate insulating layer area of ​​the structure (so-called buried channel). 由此,可以使栅极绝缘层404与沟道的界面稳定化,而可以防止在该界面形成陷阱能级。 Thereby, the gate insulating layer 404 and the channel interface is stabilized, and prevents the formation of trap level at the interface. 由此,防止晶体管的劣化,尤其是光负偏压温度应力劣化等光劣化,从而可以制造可靠性尚的晶体管。 This prevents deterioration of the transistor, especially in light deterioration negative bias temperature stress photodegradation, so that the reliability can be manufactured still transistor.

[0091] 在含有铟和镓的金属氧化物中,相对于其他金属元素的镓的含量的比率越大,能隙越大。 [0091] The metal oxide containing indium and gallium, the larger with respect to the Ga content ratio of the other metal element, the energy gap increases. 此外,由于氧化物半导体层408c与氧化物半导体层408b之间的带隙之差形成导带偏移。 Further, since the oxide semiconductor layer 408c is formed with the conduction band offset between the band gap difference between the oxide semiconductor layer 408b. 因此,当作为氧化物半导体层408c使用铟的含量为镓的含量以下的金属氧化物时,在氧化物半导体层408b中能够有效地形成沟道,所以是优选的。 Thus, when the metal oxide 408c as indium content of the oxide semiconductor layer below a gallium content, in the oxide semiconductor layer 408b in the channel can be formed efficiently, which is preferable.

[0092] 在将In-Ga-Zn类氧化物半导体用于氧化物半导体层408c时,作为氧化物半导体层408(3,可以使用具有1]1:6&:211 = 1:1:1(=1/3:1/3:1/3)、111:6&:211 = 1:3:2(=1/6:3/6:2/ 6)、In:Ga:Zn = 2:4:3 (=2/9:4/9:3/9)或In:Ga:Zn=l:5:3 (=1/9:5/9:3/9)的原子数比的In-Ga-Zn类氧化物或与该原子数比相似的氧化物。另外,作为氧化物半导体层408a和氧化物半导体层408c优选都使用铟的含量为镓的含量以下的金属氧化物。在此,氧化物半导体层408a的组成与氧化物半导体层408c的组成既可以是相同,又可以是不同。 [0092] When the In-Ga-Zn-based oxide semiconductor used for the oxide semiconductor layer 408c, the oxide semiconductor layer 408 (3, having 1] 1: 6 & amp;: 211 = 1: 1: 1 ( = 1/3: 1/3: 1/3), 111: 6 & amp;: 211 = 1: 3: 2 (= 1/6: 3/6: 2/6), In: Ga: Zn = 2: 4 : 3 (= 2/9: 4/9: 3/9) or in: Ga: Zn = l: 5: 3 (= 1/9: 5/9: 3/9) than the number of atoms of in-Ga -Zn-based oxide or similar to the atomic ratio of the oxide. Further, the oxide semiconductor layer 408a and the oxide semiconductor layer 408c are preferably used for the gallium content in the indium content of the metal oxide or less. here, the oxidation semiconductor layer, the oxide semiconductor layers 408a and 408c of the composition may be the same, but may be different.

[0093] —般而言,氧化物半导体层的大部分利用溅射法形成。 [0093] - In general, the majority is formed by sputtering the oxide semiconductor layer. 另一方面,当利用溅射法形成氧化物半导体层时,有时被离子化的稀有气体元素(例如,氩)或从溅射靶材表面弹出的粒子将栅极绝缘层等的成为氧化物半导体层的形成表面的膜的粒子弹出。 On the other hand, when the oxide semiconductor layer is formed by a sputtering method, sometimes ionized rare gas elements (e.g., argon), or from the sputtering surface of the target particles will eject the gate insulating layer such as an oxide semiconductor particle film forming the surface layer of the pop-up. 因此,从成为氧化物半导体层的形成表面的膜弹出的粒子作为杂质元素进入到氧化物半导体层。 Thus, ejected from the surface of the oxide semiconductor layer be formed of a film into particles of the oxide semiconductor layer as an impurity element. 尤其是, 有高浓度的杂质元素进入到形成表面附近的氧化物半导体层中的担忧。 In particular, there is a high concentration of an impurity element into the surface of the oxide semiconductor layer is formed concerns in nearby. 另外,当杂质元素残留在形成表面附近的氧化物半导体层中时,该氧化物半导体层的电阻增高而成为晶体管的电特性下降的原因。 Further, when the impurity element remains in the oxide semiconductor layer is formed in the vicinity of the surface resistance of the oxide semiconductor layer is increased and cause the electrical characteristics of the transistor deteriorate.

[0094] 然而,在图2A至图2C所示的晶体管310中,通过在形成沟道的氧化物半导体层408b 与栅极绝缘层404之间包括氧化物半导体层408c,可以防止栅极绝缘层404的构成元素扩散到沟道中。 [0094] However, in the transistor 310 illustrated in FIGS. 2A to 2C, the oxide semiconductor layer comprises a channel is formed between the oxide semiconductor layer 408c 404 408b through the gate insulating layer, a gate insulating layer can be prevented diffusion of constituent element 404 into the channel. 就是说,氧化物半导体层408c有时作为杂质包含栅极绝缘层404的构成元素(例如,娃)。 That is, the oxide semiconductor layer 408c as an impurity may comprise a constituent element (e.g., Wa) of the gate insulating layer 404. 通过包括氧化物半导体层408c,可以使晶体管310的电特性进一步稳定化,从而可以提供可靠性高的半导体装置。 By including the oxide semiconductor layer 408c, the electrical characteristics of the transistor 310 can be further stabilized, so that a highly reliable semiconductor device can be provided.

[0095] 另外,图2D是示出图2B中的厚度方向(D-D'间)上的能带图。 [0095] Further, FIG. 2D is a diagram illustrating an energy band diagram in the thickness direction (D-D 'between) in FIG 2B. 在本实施方式中,使用In-Ga-Zn类氧化物半导体形成氧化物半导体层408a至氧化物半导体层408c。 In the present embodiment, using the In-Ga-Zn-based oxide semiconductor, the oxide semiconductor layer 408a to the oxide semiconductor layer 408c. 此外,作为氧化物半导体层408a及氧化物半导体层408c应用铟的含量为镓的含量以下的金属氧化物,作为氧化物半导体层408b应用铟的含量大于镓的含量的金属氧化物。 Further, the content of the oxide semiconductor layers 408a and 408c application indium oxide semiconductor layer is a gallium content of the metal oxide, the content of the application 408b indium oxide semiconductor layer is greater than the metal oxide content of gallium. 由此,如图2D的能带图所示,本实施方式所示的氧化物半导体叠层408能够具有所谓埋入沟道。 Thus, as shown in FIG. 2D band, the oxide semiconductor stack 408 described in this embodiment can have a so-called buried channel.

[0096] 以下,使用图3A至图3D示出晶体管310的制造方法的一个例子。 [0096] Here, FIGS. 3A through 3D illustrate an example of a method of manufacturing a transistor 310.

[0097] 首先,在具有绝缘表面的衬底400上形成栅电极层402 (包括用与此相同的层形成的布线)。 [0097] First, a gate electrode layer 402 (including the wiring layer formed in this same) on a substrate 400 having an insulating surface.

[0098] 对可用作具有绝缘表面的衬底400的衬底没有特别的限制,但是衬底400至少需要具有能够承受后面进行的热处理的程度的耐热性。 [0098] substrate having an insulating surface may be used as the substrate 400 is not particularly limited, but the substrate 400 is required to have at least a degree to withstand heat treatment performed later heat resistance. 例如,可以使用玻璃衬底如硼硅酸钡玻璃和硼硅酸铝玻璃等、陶瓷衬底、石英衬底、或蓝宝石衬底等。 For example, a glass substrate such as barium borosilicate glass and alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. 另外,作为衬底400,可以采用以硅或碳化硅等为材料的单晶半导体衬底或多晶半导体衬底、以硅锗等为材料的化合物半导体衬底、SOI衬底等,并且也可以使用在这些衬底上设置有半导体元件的衬底400。 Further, as the substrate 400, may be employed in other single crystal semiconductor substrate is silicon or silicon carbide substrate or a polycrystalline semiconductor material, a material such as silicon germanium, a compound semiconductor substrate, the SOI substrate or the like, and may also using a substrate provided with a semiconductor element 400 on these substrates. 此外, 也可以在衬底400上形成基底绝缘层。 In addition, the base insulating layer may be formed on the substrate 400.

[0099] 可以使用诸如钼、钛、钽、钨、铝、铜、铬、钕、钪等的金属材料或以这些材料为主要成分的合金材料来形成栅电极层402。 [0099] may be used a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium or an alloy material of these materials as a main component to form the gate electrode layer 402. 此外,栅电极层402可以使用以掺杂有磷等杂质元素的多晶硅膜为代表的半导体膜、或镍硅化物膜等硅化物膜。 Further, the gate electrode layer 402 may be a semiconductor film doped with an impurity element such as phosphorus, represented by a polycrystalline silicon film, silicide film, or a nickel silicide film. 栅电极层402既可以是单层结构,又可以是叠层结构。 The gate electrode layer 402 may be a single-layer structure may be a laminated structure. 也可以使栅电极层402具有锥形形状,例如可以将锥角设定为15°以上且70°以下。 May be the gate electrode layer 402 has a tapered shape, for example, the taper angle may be set to 15 ° or more and 70 ° or less. 在此,锥角是指具有锥形形状的层的侧面与该层的底面之间的角度。 Here, the taper angle refers to an angle between a side surface having a tapered shape with a bottom surface layer of the layer.

[0100] 另外,作为栅电极层402的材料还可以使用氧化铟氧化锡、含有氧化钨的氧化铟、 含有氧化钨的氧化铟锌、含有氧化钛的氧化铟、含有氧化钛的氧化铟锡、氧化铟氧化锌、或添加有氧化硅的氧化铟锡等导电材料。 [0100] Further, as a material of the gate electrode layer 402 may be used indium oxide, tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, zinc oxide, indium oxide, or indium tin oxide added with a conductive material such as silicon oxide.

[0101] 或者,作为栅电极层402的材料还可以使用含有氮的In-Ga-Zn类氧化物、含有氮的In-Sn类氧化物、含有氮的In-Ga类氧化物、含有氮的In-Zn类氧化物、含有氮的Sn类氧化物、 含有氮的In类氧化物、或金属氮化物膜(氮化铟膜、氮化锌膜、氮化钽模、或氮化钨膜等)。 [0101] Alternatively, as the material of the gate electrode layer 402 may also be used In-Ga-Zn-based oxide containing nitrogen, nitrogen-containing oxides of In-Sn-based, In-Ga-based oxide containing nitrogen, nitrogen-containing in-Zn-based oxide, an oxide of nitrogen-containing Sn-based, in-based oxide containing nitrogen, or a metal nitride film (film of indium nitride, zinc nitride film, a tantalum nitride mold, tungsten nitride film, or ). 由于上述材料具有5eV以上的功函数,所以通过使用上述材料形成栅电极层402,可以使晶体管的阈值电压成为正值,由此可以实现常关型(normally-off)的开关晶体管。 Since the above material having a work function of 5eV or more, so that the gate electrode layer 402 is formed by using the above material, the threshold voltage of the transistor becomes positive, thereby to realize a normally-off (normally-off) of the switching transistor.

[0102] 接着,以覆盖栅电极层402的方式在栅电极层402上形成栅极绝缘层404 (参照图3A)。 [0102] Next, the gate insulating layer 404 (see FIG. 3A) so as to cover the gate electrode layer 402 is formed over the gate electrode layer 402. 作为栅极绝缘层404,通过等离子体CVD法、溅射法等以单层或叠层形成包含选自氧化硅膜、氧氮化硅膜、氮氧化硅膜、氮化硅膜、氧化铝膜、氧化铪膜、氧化钇膜、氧化锆膜、氧化镓膜、氧化钽膜、氧化镁膜、氧化镧膜、氧化铈膜和氧化钕膜中的一种以上的膜。 As the gate insulating layer 404 is formed comprising a selected silicon oxide film, a silicon oxynitride film, a silicon oxynitride film, a silicon nitride film, aluminum oxide film by a plasma CVD method, a sputtering method or the like in a single layer or stacked , hafnium oxide film, yttrium oxide film, zirconium oxide film, a gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide and neodymium oxide film of one or more films.

[0103] 另外,在栅极绝缘层404中,接触于后面形成的氧化物半导体叠层408的区域优选使用氧化物绝缘层形成,更优选包括氧过剩区。 [0103] Further, in the gate insulating layer 404, in contact with the oxide semiconductor stack of the rear region is preferably formed using an oxide insulating layer 408 is formed, and more preferably comprising an oxygen excess region. 为了在栅极绝缘层404设置氧过剩区,例如在氧气氛下形成栅极绝缘层404即可。 For an oxygen excess region 404 provided in the gate insulating layer, for example, the gate insulating layer 404 can be formed in an oxygen atmosphere. 或者,也可以将氧引入到成膜后的栅极绝缘层404中而形成氧过剩区。 Alternatively, oxygen may be introduced into the gate insulating layer 404 after film formation is formed in an oxygen excess region. 作为氧的引入方法,可以使用离子注入法、离子掺杂法、等离子体浸没式离子注入法、等离子体处理等。 As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like.

[0104] 接着,在栅极绝缘层404上依次形成成为氧化物半导体层408c的氧化物半导体膜、 成为氧化物半导体层408b的氧化物半导体膜及成为氧化物半导体层408a的氧化物半导体膜,通过利用光刻法的蚀刻处理将这些氧化物半导体膜加工为岛状,来形成氧化物半导体叠层408(参照图3B)。 [0104] Next, sequentially formed on the gate insulating layer 404 becomes an oxide semiconductor film of the oxide semiconductor layer 408c, the oxide semiconductor film and the oxide semiconductor layer 408b of the oxide semiconductor film is an oxide semiconductor layer 408a, photolithography by etching processing these semiconductor film is processed into the island-shaped oxide, 408 (see FIG. 3B) to form the oxide semiconductor stack.

[0105] 氧化物半导体层408c、氧化物半导体层408b及氧化物半导体层408a分别既可以是非晶氧化物半导体,又可以是结晶氧化物半导体。 [0105] 408c of the oxide semiconductor layer, the oxide semiconductor layer 408b and the oxide semiconductor layer 408a, respectively, may be an amorphous oxide semiconductor, but may be a crystalline oxide semiconductor. 但是,作为用作晶体管310的沟道的氧化物半导体层408b,优选使用结晶氧化物半导体。 However, transistor 310 is used as the oxide semiconductor layer 408b is a channel, preferably using crystalline oxide semiconductor. 此外,通过对非晶氧化物半导体进行热处理,可以形成结晶氧化物半导体。 Further, by heat treatment of the amorphous oxide semiconductor can be formed crystalline oxide semiconductor. 将使非晶氧化物半导体晶化的热处理的温度设定为250°C 以上且700°C以下,优选为400°C以上,更优选为500°C以上,进一步优选为550°C以上。 Will cause an amorphous oxide semiconductor crystallization heat treatment temperature is set to at least 250 ° C and to 700 ° C, preferably less than 400 ° C, more preferably 500 ° C, more preferably not less than 550 ° C. 该热处理也可以兼作制造工序中的其他加热处理。 The heat treatment may also be another heat treatment process serves to manufacture.

[0106] 作为各氧化物半导体膜的成膜方法,可以适当地利用派射法、MBE (Molecular Beam Epitaxy:分子束外延)法、CVD法、脉冲激光沉积法、ALD (Atomic Layer Deposition: 原子层堆积)法等。 [0106] As the film formation method of each of the oxide semiconductor film can be formed by sputtering method to send, MBE (Molecular Beam Epitaxy: MBE) method, CVD method, a pulsed laser deposition method, ALD (Atomic Layer Deposition: Atomic Layer accumulation) method.

[0107] 当形成氧化物半导体膜时,优选尽可能地降低膜中的氢浓度。 [0107] When the oxide semiconductor film is formed, the hydrogen concentration in the film is preferably reduced as much as possible. 为了降低氢浓度,例如,在通过溅射法进行成膜时,作为供应到溅射装置的成膜室内的气氛气体适当地使用:如氢、水、羟基或者氢化物等杂质被去除的高纯度的稀有气体(典型的有氩)、氧、稀有气体和氧的混合气体。 In order to reduce the hydrogen concentration, e.g., at the time of film formation by sputtering, suitably used as the atmosphere gas supplied to the deposition chamber of a sputtering apparatus: such as hydrogen, water, a hydroxyl group, or hydride is removed impurities such as high-purity a rare gas (typically argon), mixed gas of oxygen, rare gas and oxygen.

[0108] 另外,通过在去除残留在成膜室内的水分的同时引入去除了氢及水分的溅射气体来进行成膜,可以降低形成的氧化物半导体膜的氢浓度。 [0108] Further, a sputtering gas of hydrogen and moisture is performed by introducing a deposition while removing moisture remaining in the deposition chamber can reduce the hydrogen concentration in the oxide semiconductor film is formed. 为了去除残留在成膜室内的水分, 优选使用吸附型真空栗,例如,低温栗、离子栗、钛升华栗。 In order to remove moisture remaining in the deposition chamber, preferably using a vacuum adsorption type Li, e.g., low Li, Li ions, or a titanium sublimation Li. 此外,真空栗也可以使用具备冷阱的涡轮分子栗。 In addition, vacuum may be Li Li turbomolecular includes a cold trap. 由于低温栗对如氢分子、水(H2O)等包含氢原子的化合物(优选还包括包含碳原子的化合物)等进行排出的能力较高,所以可以降低使用该低温栗进行排气的成膜室中形成的氧化物半导体膜中的杂质浓度。 Because of the low temperatures, such as hydrogen molecules chestnut, water (H2O) and other hydrogen atoms (preferably further comprises a compound containing a carbon atom) and the like for containing a high discharge capacity, the film-forming chamber can be reduced using the low temperature exhaust of Li the impurity concentration in the oxide semiconductor film is formed.

[0109] 另外,优选以不暴露于大气的方式连续地形成栅极绝缘层404和氧化物半导体膜。 [0109] Further, preferably without being exposed to the air gate insulating layer 404 and the oxide semiconductor film is formed continuously. 通过以不暴露于大气的方式连续地形成栅极绝缘层404和氧化物半导体膜,可以防止氢或氢化合物(例如,吸附水等)附着于氧化物半导体膜表面,所以可以防止杂质的混入。 By way without exposure to air the gate insulating layer 404 and the oxide semiconductor film are formed continuously can be prevented from hydrogen or hydrogen compound (e.g., adsorbed water) adhered to the surface of the oxide semiconductor film, so inclusion of impurities can be prevented.

[0110] 另外,在通过溅射法形成氧化物半导体膜的情况下,使用于成膜的金属氧化物靶材的相对密度(填充率)为90 %以上且100 %以下,优选为95 %以上且99.9 %以下。 [0110] Further, in the case where the oxide semiconductor film formed by a sputtering method using a metal oxide target film formation relative density (filling rate) is 90% to 100%, preferably 95% or more and 99.9% or less. 通过使用相对密度高的金属氧化物靶材,可以形成致密的膜。 By using a relatively high density of the metal oxide target, a dense film can be formed.

[0111] 另外,为了降低有可能包含在氧化物半导体膜中的杂质的浓度,在将衬底400保持为高温的状态下形成氧化物半导体膜也是有效的。 [0111] Further, it is possible to reduce the concentration of the impurity in the oxide semiconductor film, an oxide semiconductor film 400 is formed in the substrate holding state at a high temperature is also effective. 将加热衬底400的温度设定为150°C以上且450°C以下,优选将衬底温度设定为200°C以上且350°C以下即可。 The heating temperature of the substrate 400 is set to at least 150 ° C and 450 ° C or less, preferably the substrate temperature is set to 200 ° C and to below 350 ° C. 另外,通过在进行成膜时以高温加热衬底,可以形成结晶氧化物半导体膜。 Further, when film formation is performed by heating the substrate at a high temperature, a crystalline oxide semiconductor film can be formed.

[0112] 当作为氧化物半导体层(例如,氧化物半导体层408b)使用CAAC-OS膜时,作为获得该CAAC-OS膜的方法,可以使用以下任何方法,例如可以将成膜温度设定为200 °C以上且450 °C以下来形成氧化物半导体膜,而实现大致垂直于其表面的c轴取向。 [0112] When CAAC-OS film is used as an oxide semiconductor layer (e.g., an oxide semiconductor layer 408b), as a method for obtaining the CAAC-OS film may be used any of the following methods, for example, the film formation temperature can be set to above 200 ° C and 450 ° C or less to form an oxide semiconductor film, c-axis orientation is realized substantially perpendicular to its surface. 或者,也可以在形成薄的氧化物半导体膜之后,进行200°C以上且700°C以下的加热处理,而实现大致垂直于其表面的c轴取向。 Alternatively, after a thin oxide semiconductor film is formed, a heat treatment above 200 ° C and to 700 ° C, the c-axis orientation is achieved substantially perpendicular to its surface. 或者,也可以在形成薄的第一层氧化物半导体膜之后,进行200°C以上且700°C以下的加热处理,然后形成第二层氧化物半导体膜,而实现大致垂直于其表面的c轴取向。 Alternatively, after a thin oxide film of the first semiconductor layer is formed, for more than 200 ° C to 700 ° C and heat treatment, and then forming a second layer of an oxide semiconductor film, to achieve substantially perpendicular to its surface c axis orientation.

[0113] 用于氧化物半导体层408a至氧化物半导体层408c的氧化物半导体至少含有铟(In)。 [0113] the oxide semiconductor layer used for the oxide semiconductor layers 408a to 408c of the oxide semiconductor containing at least indium (In). 尤其优选含有铟及锌(Zn)。 Especially preferred containing indium and zinc (Zn). 此外,作为用来减小使用该氧化物半导体的晶体管的电特性的改变的稳定剂(stabilizer),优选除了上述元素以外还含有镓(Ga)。 Further, as for the electrical characteristics of a transistor using the oxide semiconductor reduce the change of stabilizer (Stabilizer), preferably further comprises in addition to the elements gallium (Ga).

[0114] 另外,如上所述,作为用作用来降低陷阱能级的影响的缓冲层的氧化物半导体层408a及氧化物半导体层408c,优选使用铟的含量为镓的含量以下的金属氧化物,作为成为沟道形成区的氧化物半导体层408b,优选使用铟的含量大于镓的含量的金属氧化物。 [0114] As described above, the oxide semiconductor layer is used as the trap level to reduce the influence of the buffer layer 408a to 408c and the oxide semiconductor layer, the indium content is preferably below the content of metal oxides of gallium, a channel formation region of the oxide semiconductor layer 408b, indium oxide content is preferably greater than the content of the metal gallium.

[0115] 此外,作为稳定剂,也可以代替镓(Ga)或除了镓(Ga)以外还包含锡(Sn)、铪(Hf)、 铝(Al)和锆(Zr)中的一种或多种。 One kind of [0115] Further, as a stabilizer, may be used instead of gallium (Ga) or in addition to gallium (Ga) further comprises tin (Sn), hafnium (Hf), aluminum (Al) and zirconium (Zr) or in species. 另外,作为其它稳定剂,也可以含有镧(La)等镧系元素、 铈(Ce)、镨(Pr)、钕(Nd)、钐(Sm)、铕(Eu)、钆0M)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、 镱(Yb)、镥(Lu)中的一种或多种。 Further, other stabilizers may be contained lanthanum (La) and other lanthanides, cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium 0M), terbium ( Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) in.

[0116] 例如,作为氧化物半导体,可以使用:作为一元金属氧化物的氧化铟、氧化锡、氧化锌等;作为二元金属氧化物的In-Zn类氧化物、In-Mg类氧化物、In-Ga类氧化物等;作为三元金属氧化物的In-Ga-Zn类氧化物、In-Al-Zn类氧化物、In-Sn-Zn类氧化物、In-Hf-Zn类氧化物、In-La-Zn类氧化物、In-Ce-Zn类氧化物、In-Pr-Zn类氧化物、In-Nd-Zn类氧化物、In-Sm-Zn类氧化物、In-Eu-Zn类氧化物、In-Gd-Zn类氧化物、In-Tb-Zn类氧化物、In-Dy-Zn类氧化物、In-Ho-Zn类氧化物、In-Er-Zn类氧化物、In-Tm-Zn类氧化物、In-Yb-Zn类氧化物、In-Lu-Zn类氧化物等;以及作为四元金属氧化物的In-Sn-Ga-Zn类氧化物、In-Hf-Ga-Zn类氧化物、 In-Al-Ga-Zn 类氧化物、In-Sn-Al-Zn 类氧化物、In-Sn-Hf-Zn 类氧化物、In-Hf-Al-Zn 类氧化物等。 [0116] For example, as the oxide semiconductor, may be used: indium oxide as one yuan metal oxide, tin oxide, zinc oxide and the like; as an In-Zn-based oxide binary metal oxide, In-Mg-based oxide, in-Ga-based oxide and the like; as an in-Ga-Zn-based oxide ternary metal oxide, in-Al-Zn-based oxide, in-Sn-Zn-based oxide, in-Hf-Zn-based oxide , In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu- Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, in-Tm-Zn-based oxide, in-Yb-Zn-based oxide, in-Lu-Zn-based oxide and the like; and a four-component metal oxide, in-Sn-Ga-Zn-based oxide, in-Hf -Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide and the like.

[0117] 例如,In-Ga-Zn类氧化物是指作为主要成分含有In、Ga、Zn的氧化物,对In、Ga、Zn 的比率没有限制。 [0117] For example, In-Ga-Zn based oxide as a main component refers to containing In, Ga, Zn oxide of In, Ga, Zn ratio is not limited. 此外,也可以含有In、Ga、Zn以外的金属元素。 In addition, it may contain a metal element other than In, Ga, Zn.

[0118] 另外,作为氧化物半导体,也可以使用以InMO3 (ZnO)m (m>0,且m不是整数)表示的材料。 [0118] Further, as the oxide semiconductor, may be used material InMO3 (ZnO) m (m> 0, and m is not an integer) representation. 注意,M表示选自Ga、Fe、Mn和Co中的一种金属元素或多种金属元素。 Note, M is one metallic element selected from Ga, Fe, Mn, and Co or more metal elements. 另外,作为氧化物半导体,也可以使用以In2SnO5 (ZnO) n (n>0,且η是自然数)表示的材料。 Further, as the oxide semiconductor, may be used In2SnO5 (ZnO) n (n> 0, and η is a natural number) material represented.

[0119] 优选对氧化物半导体叠层408进行用来去除过剩的氢(包括水及羟基)的加热处理(脱水化或脱氢化)。 [0119] Preferably the stack of the oxide semiconductor 408 a heat treatment for removing excess hydrogen (including water and a hydroxyl group) (dehydration or dehydrogenation). 将加热处理的温度设定为300°C以上且700°C以下或低于衬底的应变点。 The heat treatment temperature was set to 300 ° C above and to 700 ° C or lower than the strain point of the substrate. 加热处理可以在减压下或氮气氛下等进行。 The heat treatment may be carried out under reduced pressure or the like under a nitrogen atmosphere. 通过进行该加热处理可以去除赋予η型导电性的杂质的氢。 The heat treatment may be carried out by removing a hydrogen η-type conductivity imparting impurity.

[0120] 另外,用于脱水化或脱氢化的加热处理只要在形成氧化物半导体膜之后就可以在晶体管的制造工序中的任何时序进行。 [0120] Further, heat treatment for dehydration or dehydrogenation can be any timing in a manufacturing process of the transistor is performed after the oxide semiconductor film is formed long. 另外,用于脱水化或脱氢化的加热处理也可以多次进行,还可以兼作其他加热处理。 Further, heat treatment for dehydration or dehydrogenation may be performed multiple times, it may also serve as another heat treatment.

[0121] 在加热处理中,氮或氦、氖、氩等稀有气体优选不包含水、氢等。 [0121] In the heat treatment, nitrogen or helium, neon, argon and other rare gas preferably does not contain water, hydrogen and the like. 另外,优选将引入到加热处理装置中的氮或氦、氖、氩等稀有气体的纯度设定为6Ν (99.9999%)以上,优选设定为7N(99.99999%)以上(即,将杂质浓度设定为Ippm以下,优选设定为0. Ippm以下)。 Further, the purity is preferably introduced into a heat treatment apparatus in nitrogen or a rare gas as helium, neon, argon and the like is set to 6Ν (99.9999%) or more, preferably set to 7N (99.99999%) or more (i.e., the impurity concentration provided as IPPM less, preferably set to be 0. Ippm less).

[0122] 另外,可以在通过加热处理对氧化物半导体层(或氧化物半导体叠层)进行加热之后,在维持该加热温度的状态下或在从该加热温度降温的过程中,对相同炉内引入高纯度的氧气体、高纯度的一氧化二氮气体或超干燥空气(使用CRDS (Cavity Ring Down laser Spectroscopy:光腔衰荡光谱法)方式的露点计进行测试时的水分量是20ppm (换算为露点-55°C)以下,优选的是Ippm以下,更优选的是IOppb以下的空气)。 [0122] Further, by the heat treatment may be performed after the oxide semiconductor layer (or the stack of the oxide semiconductor) heating, the heating temperature is maintained in a state or during cooling from the heating temperature, the same furnace introducing high-purity oxygen and high purity of nitrous oxide gas, or ultra-dry air (using CRDS (cavity Ring Down laser Spectroscopy: cavity ring-down spectroscopy) type dew-point meter the amount of moisture at the time of the test is 20ppm (in terms of dew point -55 ° C) or less, preferably Ippm less, and more preferably less IOppb air). 优选不使氧气体或一氧化二氮气体包含水、氢等。 Preferably no oxygen or nitrous oxide gas comprises water, hydrogen and the like. 或者,优选将引入到加热处理装置中的氧气体或一氧化二氮气体的纯度设定为6N以上,优选为7N以上(也就是说,将氧气体或一氧化二氮气体中的杂质浓度设定为Ippm以下,优选设定为0. Ippm以下)。 Or, preferably, the purity oxygen gas is introduced into the heat treatment apparatus is one or two nitrogen monoxide is preferably 6N or more, more preferably 7N (i.e., oxygen or nitrous oxide in nitrogen impurity concentration provided as IPPM less, preferably set to be 0. Ippm less). 即使在利用脱水化处理或脱氢化处理的杂质排出工序中氧化物半导体的主要构成要素的氧减少,也可以通过利用氧气体或一氧化二氮气体供给氧,来使氧化物半导体层高纯度化且电性i型(本征)化。 Even impurities in the oxygen utilization dehydration or dehydrogenation treatment step of discharging the main constituent elements of an oxide semiconductor is reduced, or by using oxygen or nitrous oxide gas supplying oxygen to the oxide semiconductor storey purified and electrically i-type (intrinsic).

[0123] 另外,当进行脱水化处理或脱氢化处理时氧有可能脱离而减少,所以可以对经过脱水化处理或脱氢化处理的氧化物半导体层引入氧(包括氧自由基、氧原子和氧离子中的至少一种)来对该层供应氧。 [0123] Further, when the dehydration or dehydrogenation treatment is possible from reduced oxygen, oxygen can be introduced through the dehydration or dehydrogenation of the oxide semiconductor layer treatment (including oxygen radicals, oxygen atoms and oxygen at least one) of the layer is supplied with oxygen ions.

[0124] 通过对经过脱水化处理或脱氢化处理的氧化物半导体层引入氧而供应氧,可以使氧化物半导体层高纯度化且i型(本征)化。 [0124] introducing oxygen supplied by the oxygen treatment of the dehydrated or dehydrogenated oxide semiconductor layer process, the oxide semiconductor storey purified and i-type (intrinsic). 包含高纯度化且i型(本征)化的氧化物半导体的晶体管的电特性变动被抑制,所以该晶体管在电性上稳定。 The electrical characteristics of a transistor comprising a high purity and an i-type (intrinsic) oxide semiconductor fluctuation is suppressed, so that the transistor is electrically stable properties.

[0125] 当对氧化物半导体层引入氧时,既可以对氧化物半导体层直接引入氧,又可以以透过在后面形成的绝缘层的方式对氧化物半导体层引入氧。 [0125] When oxygen is introduced to the oxide semiconductor layer, oxygen may be directly introduced into the oxide semiconductor layer, and oxygen may be introduced into the oxide semiconductor layer through the insulating layer is formed later. 作为氧(包括氧自由基、氧原子和氧离子中的至少一种)的引入方法,可以使用离子注入法、离子掺杂法、等离子体浸没式离子注入法、等离子体处理等。 As a method of introducing oxygen (including oxygen radicals, at least one oxygen atom, and an oxygen ion) can be used an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like. 另外,可以使用含有氧的气体进行氧的引入处理。 In addition, a gas containing oxygen is introduced into the process of oxygen. 作为含有氧的气体,可以使用氧、一氧化二氮、二氧化氮、二氧化碳、一氧化碳等。 As the oxygen-containing gas may be oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide and carbon monoxide. 此外,在氧的引入处理中,也可以使含有氧的气体包含稀有气体。 Further, in the process of oxygen introduced may be oxygen-containing gas comprises a noble gas.

[0126] 例如当通过离子注入法对氧化物半导体层注入氧离子时,可以将剂量设定为IX 1〇13;[0118/0112以上且5\1016;[0118/0112以下。 [0126] For example, when the ion implantation by implanting oxygen ions into the oxide semiconductor layer, the dose may be set IX 1〇13; [0118/0112 or more and 5 \ 1016; [0118/0112 or less.

[0127] 另外,对氧化物半导体层供应氧的工序只要在形成氧化物半导体膜之后就可以在晶体管的制造工序中的任何时序进行。 Can be any timing in the manufacturing process of the transistor is performed after [0127] Further, the oxide semiconductor layer as long as the step of supplying oxygen in the oxide semiconductor film. 另外,向氧化物半导体层的氧的引入也可以多次进行。 Further, a plurality of times may be the introduction of oxygen to the oxide semiconductor layer.

[0128] 接着,在氧化物半导体叠层408上形成导电膜并对其进行加工来形成源电极层410a及漏电极层410b (包括用与此相同的层形成的布线)(参照图3C)。 [0128] Next, a conductive film is formed over the oxide semiconductor stack 408 and subjected to processing to form the source electrode layer 410a and the drain electrode layer 410b (including a wiring layer formed in this same a) (see FIG. 3C).

[0129] 作为源电极层410a及漏电极层410b,例如可以使用含有选自Al、Cr、Cu、Ta、Ti、Mo 和W中的元素的金属膜或以上述元素为成分的金属氮化物膜(氮化钛膜、氮化钼膜、或氮化妈膜)等。 [0129] As the source electrode layer 410a and the drain electrode layer 410b, for example containing selected from Al, a metal film of Cr, Cu, Ta, Ti, Mo and W or an element of the above elements as a component a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a nitride film mother) or the like. 另外,还可以在Al、Cu等的金属膜的下侧和上侧中的一方或双方上层叠Ti、Mo、W等的高熔点金属膜或它们的金属氮化物膜(氮化钛膜、氮化钼膜、或氮化钨膜)。 In addition, and also on one side in the lower side of the metal film is Al, Cu or the like is laminated on both Ti, Mo, W and the like of a refractory metal film or a metal nitride film (titanium nitride film, a nitrogen molybdenum film, or a tungsten nitride film). 另外,源电极层410a及漏电极层410b也可以使用导电金属氧化物形成。 Further, the source electrode layer 410a and the drain electrode layer 410b may be formed using a conductive metal oxide. 导电金属氧化物例如可以使用氧化铟(In2〇3)、氧化锡(Sn〇2)、氧化锌(ZnO)、氧化铟氧化锡(In2〇3_Sn〇2)、氧化铟氧化锌(In2O3-ZnO)或者使这些金属氧化物材料含有氧化硅的材料。 Conductive metal oxides such as indium oxide (In2〇3), tin oxide (Sn〇2), zinc oxide (ZnO), tin oxide, indium oxide (In2〇3_Sn〇2), indium zinc oxide (In2O3-ZnO) of these metal oxide materials or a material containing silicon oxide.

[0130] 另外,作为源电极层410a及漏电极层410b可以使用含有氮的In-Ga-Zn-O膜、含有氮的In-Sn-O膜、含有氮的In-Ga-O膜、含有氮的In-Zn-O膜、含有氮的Sn-O膜、含有氮的In-O 膜等金属氮化物膜。 [0130] Further, as the source electrode layer 410a and the drain electrode layer 410b may be used In-Ga-Zn-O film containing nitrogen, containing the In-Sn-O film containing nitrogen, containing In-Ga-O film containing nitrogen, comprising nitrogen in-Zn-O film, a Sn-O film containing nitrogen, the in-O film containing a metal nitride film containing nitrogen. 由于这些膜含有与氧化物半导体叠层408相同的构成元素,所以可以使源电极层410a或漏电极层410b与氧化物半导体叠层408之间的界面稳定。 Since these films contain the same stack 408 with the oxide semiconductor constituent element, it is possible that the source electrode layer 410a or drain electrode layer 410b and the interfacial stability between the oxide semiconductor stack 408.

[0131] 此外,当作为源电极层410a及漏电极层410b应用包含铜的导电膜时可以降低布线电阻,所以是优选的。 [0131] Further, when a drain electrode layers 410a and 410b application source electrode layer comprising a conductive film of copper wiring resistance can be reduced, which is preferable. 一般而言,由于铜容易扩散到半导体或氧化硅膜中,所以有可能使半导体装置的操作不稳定而使成品率明显降低。 In general, since copper easily diffuses into the semiconductor or silicon oxide film, it is possible to make the operation unstable yield of the semiconductor device is significantly reduced. 但是,由于晶体管310包括接触于源电极层410a及漏电极层410b并用作用来防止该电极层的构成元素(在此,为铜)扩散的缓冲层的氧化物半导体层408a,所以可以降低因铜的扩散而产生的背沟道一侧的陷阱能级的影响,优选的是完全防止背沟道一侧的陷阱能级的影响。 However, since the transistor 310 includes a source electrode layer 410a in contact with the drain electrode layer 410b serves to prevent the constituent elements and functions as the electrode layer (here, copper) of the oxide semiconductor buffer layer diffused 408a, it can be reduced by copper Effect of diffusion is generated on the back channel side of the trap level, preferably completely prevent the influence of a back channel side of the trap energy level.

[0132] 接着,以覆盖源电极层410a、漏电极层410b以及露出的氧化物半导体叠层408的方式形成绝缘层412 (参照图3D)。 [0132] Next, as to cover the source electrode layer 410a, the drain electrode layer 410b and the oxide semiconductor laminate embodiment 408 is exposed insulating layer 412 is formed (see Figure 3D).

[0133] 绝缘层412可以利用等离子体CVD法、或溅射法并使用氧化硅膜、氧化镓膜、氧化铝膜、氮化硅膜、氧氮化硅膜、氧氮化铝膜或者氮氧化硅膜等的单层或叠层形成。 [0133] The insulating layer 412 may be a plasma CVD method, or a sputtering method and a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxynitride oxynitride silicon film of single layer or stacked form. 注意,当作为绝缘层412形成氧化物绝缘层时,能够利用该氧化物绝缘层将氧供应到氧化物半导体叠层408,所以是优选的。 Note that, when an oxide insulating layer 412 is formed as an insulating layer, the oxide insulating layer can be utilized to supply the oxygen to the oxide semiconductor stack 408, which is preferable.

[0134] 可以在形成绝缘层412之后进行加热处理。 [0134] can be formed in the insulating layer 412 after the heat treatment. 将加热处理的温度优选设定为200 °C以上,例如可以设定为220°C。 The heat treatment temperature is preferably set to at least 200 ° C, may be set to 220 ° C.

[0135] 通过上述步骤可以形成本实施方式的晶体管310。 [0135] Embodiment of the present embodiment may be formed by the above-described steps transistor 310.

[0136] 本实施方式所示的晶体管包括:用作防止源电极层或漏电极层的构成元素扩散到沟道中的缓冲层的第一氧化物半导体层;以及用作沟道的第二氧化物半导体层。 Transistor illustrated [0136] embodiment of the present embodiment comprises: a first oxide semiconductor layer is prevented as a source electrode layer or the drain electrode layer constituting the element diffused into the buffer layer in the channel; and a second channel as oxide The semiconductor layer. 通过该结构,可以降低能够在晶体管的背沟道一侧形成的界面态的影响。 This structure can reduce the influence of the interface state can be formed at the back side of the transistor channel. 另外,更优选的是,本实施方式所示的晶体管包括设置在用作沟道的氧化物半导体层与栅极绝缘层之间并用作用来防止沟道的栅极绝缘层一侧的界面的劣化的缓冲层的第三氧化物半导体层。 Further, more preferably, the transistor of the present embodiment illustrated embodiment includes as a channel disposed between the oxide semiconductor layer and the gate insulating layer and serves as the interface to prevent degradation of the gate insulating layer side of the channel the third oxide semiconductor layer of the buffer layer. 通过包括第三氧化物半导体层,可以减少晶体管的光劣化(例如,光负偏压温度应力劣化),从而可以提供可靠性高的半导体装置。 By including a third oxide semiconductor layer, the light deterioration of the transistor can be reduced (e.g., negative bias temperature stress light degradation), so that a highly reliable semiconductor device can be provided.

[0137] 本实施方式所示的结构、方法等可以与其他实施方式所示的结构、方法等适当地组合而使用。 As shown in [0137] the structure of the present embodiment, a method may be used in appropriate combination shown another embodiment of the structure, and methods.

[0138] 实施方式2 [0138] Embodiment 2

[0139] 在本实施方式中,参照图IOA和图IOB说明与实施方式1不同的半导体装置的一个方式。 [0139] In the present embodiment, with reference to one embodiment of FIGS. IOA and IOB 1 FIG different semiconductor device according to the embodiment described. 具体而言,说明具有与实施方式1所示的晶体管不同的栅极绝缘层的结构的晶体管。 Specifically, a transistor having a transistor described in Embodiment 1 shown in different gate insulating layer structure.

[0140] 图IOA示出晶体管3 2 0的结构实例。 [0140] FIG IOA illustrates an example of the structure of the transistor 320. 与图2 A至图2D所示的晶体管310同样,图IOA所示的晶体管320包括:设置在具有绝缘表面的衬底400上的栅电极层402;栅电极层402上的栅极绝缘层403、406;接触于栅极绝缘层406并重叠于栅电极层402的氧化物半导体叠层408;以及电连接于氧化物半导体叠层408的源电极层410a及漏电极层410b。 FIG 2 A to 2D transistor 310 shown Similarly, transistor 320 shown in FIG IOA comprising: a gate electrode layer disposed on the substrate 402 of the insulating surface 400; the gate insulating layer 403 on the gate electrode layer 402 , 406; 406 in contact with the gate insulating layer and overlaps with the gate electrode stack of the oxide semiconductor layer 402, 408; and an electrical connection to the stack of the oxide semiconductor layer 408 a source electrode 410a and drain electrode layer 410b. 在晶体管320 中,氧化物半导体叠层408包括:接触于栅极绝缘层406的氧化物半导体层408c;在氧化物半导体层408c上并与其接触的氧化物半导体层408b;在氧化物半导体层408b上并与其接触的接触于源电极层410a及漏电极层410b的氧化物半导体层408a。 In the transistor 320, the oxide semiconductor stack 408 comprising: contacting the gate insulating layer 408c of the oxide semiconductor layer 406; an oxide semiconductor layer over the oxide semiconductor layer 408c and 408b in contact therewith; oxide semiconductor layer 408b and in contact with the contacts on the source electrode layer 410a and the oxide semiconductor layer, the drain electrode layer 410b to 408a. 另外,晶体管320的构成要素也可以包括覆盖源电极层410a及漏电极层410b并接触于氧化物半导体叠层408的绝缘层412〇 Further, the components may also include a transistor 320 to cover the source electrode layer 410a and the drain electrode layer 410b and the oxide semiconductor in contact with the insulating layer stack 408 412〇

[0141] 晶体管320与晶体管310的不同之处是:栅极绝缘层具有第一栅极绝缘层403与第二栅极绝缘层406的叠层结构,该第一栅极绝缘层403从栅电极层402—侧包括栅极绝缘层403a、栅极绝缘层403b及栅极绝缘层403c。 [0141] is different from the transistor 320 and the transistor 310 is: a gate insulating layer 403 having a stacked structure of a first gate insulating layer and a second gate insulating layer 406, the gate insulating layer 403 from the first gate electrode 402- side layer comprises a gate insulating layer 403a, a gate insulating layer 403b and the gate insulating layer 403c.

[0142] 注意,除了栅极绝缘层之外,晶体管320的结构与晶体管310相同,而可以参照关于晶体管310的说明。 [0142] Note that, in addition to the gate insulating layer, the same structure as the transistor 320 the transistor 310, and can be referred to the description of the transistor 310.

[0143] 在晶体管320中,作为第一栅极绝缘层403应用包含氮的硅膜。 [0143] In the transistor 320, a silicon film containing nitrogen as the gate insulating layer 403 comprises a first application. 由于包含氮的硅膜的相对介电常数比氧化硅膜高而在获得与氧化硅膜相等的静电电容时包含氮的硅膜需要的厚度比氧化硅膜大,所以可以使栅极绝缘层在物理上厚膜化。 The thickness of the silicon film has a relative permittivity higher than that of silicon containing nitrogen oxide film comprising a silicon nitrogen film required in obtaining a silicon oxide film is equal to the electrostatic capacitance larger than a silicon oxide film, the gate insulating layer can be made physically thick film. 由此,可以防止晶体管320 的耐受电压的下降。 This can prevent a decrease in withstand voltage of the transistor 320. 再者,通过提高耐受电压可以防止半导体装置的静电损坏。 Further, the withstand voltage can be prevented by improving the electrostatic breakdown of the semiconductor device.

[0144] 此外,作为接触于氧化物半导体叠层408的第二栅极绝缘层406,应用包含氧的绝缘层如氧化硅膜、氧化镓膜、或氧化铝膜等。 [0144] Further, as a second gate insulating layer 408 is in contact with the oxide semiconductor stack 406, an insulating layer containing oxygen applications such as a silicon oxide film, a gallium oxide film, or an alumina film. 第二栅极绝缘层406优选包括包含超过化学计量组成的氧的区域(氧过剩区)。 A second gate insulating layer 406 preferably comprises a region (oxygen excess region) contains more than the stoichiometric composition of oxygen. 这是因为如下缘故:通过与氧化物半导体叠层408接触的绝缘层包括氧过剩区域,可以向氧化物半导体叠层408供应氧,由此可以防止氧从氧化物半导体叠层408脱离并填补氧化物半导体叠层408中的氧空位。 This is because: through the insulating layer in contact with the oxide semiconductor stack 408 includes an oxygen excess region, oxygen can be supplied to the oxide semiconductor stack 408, thereby to prevent oxygen from the oxide semiconductor stack 408 from oxidation and to fill oxygen vacancies in the semiconductor laminate 408. 为了在第二栅极绝缘层406设置氧过剩区,例如在氧气氛下形成第二栅极绝缘层406即可。 To the second gate insulating layer 406 is provided an oxygen excess region, a second gate insulating layer 406 can be formed, for example in an oxygen atmosphere. 或者,也可以将氧引入到成膜后的第二栅极绝缘层406中而形成氧过剩区。 Alternatively, oxygen may be introduced into the second gate insulating layer 406 after film formation is formed in an oxygen excess region.

[0145] 虽然作为应用于第一栅极绝缘层403的含有氮的硅膜例如可以举出氮化硅膜、氮氧化硅膜、氧氮化硅膜,但是由于相对于氧的氮含量越多,相对介电常数越高,所以优选采用氮化娃膜。 [0145] Although the silicon film containing nitrogen is applied as a first gate insulating layer 403 may include, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxynitride film, but since the relative oxygen content of more nitrogen , the higher the relative dielectric constant, and is preferably a nitride film baby. 此外,由于与氧化娃的能隙8eV相比氮化娃的能隙低,为5.5eV,相应的氧化娃的电阻率也低,所以通过使用氮化娃膜可以提高耐ESD (Electro-Static Discharge;静电放电)性能。 Further, as compared with the energy gap of the oxide baby doll nitride 8eV low energy gap of 5.5 eV or, oxidation of the corresponding baby resistivity is low, so the doll by using the nitride film resistance can be improved ESD (Electro-Static Discharge ; ESD) properties. 注意,在本说明书中,“氧氮化硅膜”是指在其组成中氧含量多于氮含量的膜,而“氮氧化硅膜”是指在其组成中氮含量多于氧含量的膜。 Note that, in this specification, "a silicon oxynitride film" refers to a film oxygen content in its composition than nitrogen, and "a silicon oxynitride film" refers to a film in which the nitrogen content than the oxygen content of the composition .

[0146] 接触于栅电极层402的栅极绝缘层403a是氨含量至少小于栅极绝缘层403b的硅膜。 [0146] in contact with the gate electrode layer 403a of the gate insulating layer 402 is less than the ammonia content of at least silicon film 403b, the gate insulating layer. 由于氮原子上的孤对电子的作用,氨用作金属配合物的配体。 Since the nitrogen atom lone pair of electrons acting, ammonia is used as a ligand in metal complexes. 因此,例如在将铜用于栅电极层402的情况下,如果以与该栅电极层接触的方式形成氨含量多的栅极绝缘层,则通过如下式(1)所示的反应,铜有可能扩散到栅极绝缘层中。 Thus, for example, in the case where copper is used for the gate electrode layer 402, are formed if ammonia content of more gate insulating layer in contact with the gate electrode layer, the following reaction formula (1) by copper has It may diffuse into the gate insulating layer.

Figure CN104380473BD00181

[0148] 在晶体管320中,通过以与栅电极层402接触的方式形成氨含量低(至少比栅极绝缘层403b低)的栅极绝缘层403a,可以防止栅电极层402的材料(例如,铜)扩散到第一栅极绝缘层403中。 [0148] In the transistor 320, formed by contact with the gate electrode layer 402 a low ammonia content (at least lower than the gate insulating layer 403b) of the gate insulating layer 403a, the gate electrode material layer 402 (e.g., can be prevented, copper) into the first gate insulating layer 403. 换句话说,栅极绝缘层403a可以用作栅电极层402中包含的金属材料的阻挡膜。 In other words, the gate insulating layer 403a may serve as a barrier metal film comprising a material layer 402 of the gate electrode. 通过设置栅极绝缘层403a,可以进一步提高晶体管的可靠性。 By providing the gate insulating layer 403a, may further improve the reliability of the transistor.

[0149] 栅极绝缘层403b是具有比栅极绝缘层403a厚的膜厚且减少膜中缺陷数量的包含氮的娃膜。 [0149] The gate insulating layer 403b having a film thickness of the gate insulating layer 403a is thicker than the film and reduces the number of defects in the baby film containing nitrogen. 例如,将栅极绝缘层403b的厚度设定为300nm以上且400nm以下。 For example, the thickness of the gate insulating layer 403b is set to 300nm or more and 400nm or less. 另外,在用作栅极绝缘层403b的包含氮的娃膜中,在通过电子自旋共振(;ESR:Electron Spin Resonance) 法测量的信号中在此中心&值为2.003)出现的信号的自旋密度为1\1017叩11^/〇113以下, 优选为5X1016spins/cm3以下。 Further, as a gate insulating film containing nitrogen baby layer 403b of, by electron spin resonance (; ESR: Electron Spin Resonance) method of measuring this signal, the center & amp; 2.003) signal appearing in the spin density of 1 \ 1017 11 ^ rapping / 〇113 less, preferably 5X1016spins / cm3 or less. 如此,通过作为栅极绝缘层403b使用减少膜中缺陷数量且厚度大(例如,300nm以上)的包含氮的硅膜,例如可以将栅极绝缘层403b的ESD耐性提高到300V以上。 Thus, by using the gate insulating layer 403b to reduce the number of defects and a large film thickness (e.g., 300 nm or more) of a silicon film containing nitrogen, for example, the gate insulating layer to improve ESD tolerance 403b of 300V or more.

[0150] 此外,栅极绝缘层403c使用减少氢浓度的包含氮的硅膜。 [0150] Further, the gate insulating layer 403c silicon film containing nitrogen to reduce the hydrogen concentration. 将栅极绝缘层403c的氢浓度设定为至少比栅极绝缘层403b低的浓度。 The hydrogen concentration of the gate insulating layer 403c is set to be at least lower than the gate insulating layer 403b concentrations. 例如,在利用等离子体CVD法形成栅极绝缘层403c的情况下,通过使包含在供应气体中的氢浓度低于用来形成栅极绝缘层403b的供应气体中的氢浓度,可以使栅极绝缘层403c的氢浓度低于栅极绝缘层403b。 For example, the plasma CVD method is formed in the gate insulating layer 403c of the case, by making the concentration of the hydrogen contained in the supplied gas is lower than the hydrogen concentration in the supply gas used to form the gate insulating layer 403b in, the gate can be the hydrogen concentration in the insulating layer 403c is lower than the gate insulating layer 403b. 具体而言,当作为栅极绝缘层403b及栅极绝缘层403c形成氮化硅膜时,使用来形成栅极绝缘层403c的供应气体中的氨流量低于用来形成栅极绝缘层403b的供应气体中的氨流量,或者在不使用氨的情况下形成栅极绝缘层403c即可。 Specifically, when the silicon nitride film 403c is formed as a gate insulating layer 403b and the gate insulating layer is formed using ammonia gas supply flow rate of the gate insulating layer 403c is lower than the gate insulating layer 403b is formed for the supply flow rate of ammonia gas, or the gate insulating layer 403c can be formed without using ammonia.

[0151] 作为栅极绝缘层403c设置减少氢浓度的氮化硅膜,这样可以防止氢或氢化合物(例如,水)混入到第二栅极绝缘层406及氧化物半导体叠层408。 [0151] 403c is provided to reduce the hydrogen concentration of the silicon nitride film as the gate insulating layer, which can prevent hydrogen or hydrogen compound (e.g., water) is mixed to the second gate insulating layer 406 and the oxide semiconductor stack 408. 由于通过使氢与氧化物半导体键合,氢的一部分成为供体,生成作为载流子的电子,而有可能成为使晶体管的阈值电压向负方向改变(转移)的要因,所以通过作为栅极绝缘层403c设置减少氢浓度的氮化硅膜,可以使晶体管具有稳定的电特性。 Since by hydrogen to the oxide semiconductor bonding, a portion of the hydrogen becomes a donor, generating electrons as carriers, but may become the threshold voltage of the transistor in the negative direction of the change (transfer) to cause, so by the gate the insulating layer 403c is provided to reduce the hydrogen concentration of the silicon nitride film, the transistor can have stable electric characteristics. 另外,通过作为栅极绝缘层403c设置减少氢浓度的氮化硅膜,栅极绝缘层403c还用作防止栅极绝缘层403b所含有的氢或氢化合物等杂质扩散到氧化物半导体叠层408中的阻挡膜。 Further, as the gate insulating layer 403c is provided to reduce the hydrogen concentration of the silicon nitride film, the gate insulating layer 403c also serves to prevent impurities like hydrogen or hydrogen compound contained in the gate insulating layer 403b is diffused into the oxide semiconductor stack 408 the barrier film.

[0152] 在本实施方式中,作为构成第一栅极绝缘层403的栅极绝缘层403a、栅极绝缘层403b及栅极绝缘层403c使用氮化硅膜,作为第二栅极绝缘层406使用氧氮化硅膜,各栅极绝缘层利用等离子体CVD法连续地形成。 [0152] In the present embodiment, a silicon nitride film 403c as 403a, a gate insulating layer 403b and the gate insulating layer constituting the gate insulating layer, a first gate insulating layer 403, a second gate insulating layer 406 silicon oxynitride film, the gate insulating layer are continuously formed by a plasma CVD method. 具体而言,在供应硅烷(SiH4)与氮(N2)的混合气体而形成用作栅极绝缘层403a的氮化硅膜之后,将供应气体转换为硅烷(SiH4)、氮(N2)及氨(NH3)的混合气体而形成用作栅极绝缘层403b的氮化硅膜,然后将供应气体转换为硅烷(SiH4)与氮(N2)的混合气体,形成用作栅极绝缘层403c的氮化硅膜,然后将供应气体转换为硅烷(SiH4)与一氧化二氮(N2O)的混合气体,形成用作第二栅极绝缘层406的氧氮化硅膜。 Specifically, after the silicon nitride film serves as a gate insulating layer 403a in the supply of silane (SiH4) is formed with a nitrogen (N2) mixed gas, the supply gas is converted to silane (SiH4), nitrogen (N2) and ammonia (NH3) to form a mixed gas of a silicon nitride film as the gate insulating layer 403b, and then supply the converted gas of silane (SiH4) and a mixed gas of nitrogen (N2) and nitrogen is formed as a gate insulating layer 403c of silicon film, and then the supply gas is converted to silane (SiH4) and nitrous oxide (N2O) gas mixture, a silicon oxynitride film is formed as the second gate insulating layer 406. [0153] 优选将栅极绝缘层403a的厚度设定为30nm以上且IOOnm以下,更优选设定为30nm 以上且50nm以下。 [0153] The thickness of the gate insulating layer 403a is set to 30nm or more and IOOnm or less, more preferably 30nm or more and 50nm or less. 另外,优选将用来防止晶体管的静电破坏而设置的栅极绝缘层403b的厚度设定为300nm以上且400nm以下,优选将用作防止氢扩散到氧化物半导体叠层408中的阻挡膜的栅极绝缘层403c的厚度设定为25nm以上且150nm以下。 It is preferable that the gate insulating layer for preventing electrostatic breakdown of the transistor 403b is provided to set the thickness of 300nm or more and 400nm or less, preferably serving as a barrier film to prevent diffusion of hydrogen into the oxide semiconductor 408 a gate stack the thickness of the gate insulating layer 403c is set to 25nm or more and 150nm or less. 此外,优选将第二栅极绝缘层406的厚度设定为25nm以上且IOOnm以下。 Further, preferably the thickness of the second gate insulating layer 406 is set to 25nm or more and less IOOnm. 注意,优选适当地调节各栅极绝缘层的厚度,来使第一栅极绝缘层403的厚度(栅极绝缘层403a、栅极绝缘层403b及栅极绝缘层403c的厚度的总和)与第二栅极绝缘层406的厚度的总和为355nm以上且550nm以下。 Note that, preferably appropriately adjusted thickness of the gate insulating layer to a thickness of the first gate insulating layer 403 (gate insulating layer 403a, the thickness of the gate insulating layer 403b and the gate insulating layer 403c sum) and the second the sum of the two thicknesses of the gate insulating layer 406 is 355nm or more and 550nm or less.

[0154] 另外,如图IOB所示的晶体管330所示,也可以组合包括第一栅极绝缘层403及第二栅极绝缘层406的叠层的栅极绝缘层和包括氧化物半导体层408b及氧化物半导体层408a的叠层的氧化物半导体叠层408而使用。 [0154] Further, the transistor shown in Fig. IOB, the composition may be a gate insulating layer 330 includes a first stack 403 and the second gate insulating layer 406 and the gate insulating layer comprises an oxide semiconductor layer 408b and the oxide semiconductor layer 408a of the stack of the oxide semiconductor stack 408 is used.

[0155] 本实施方式所示的晶体管包括:用作防止源电极层和漏电极层的构成元素扩散到沟道中的缓冲层的第一氧化物半导体层;以及用作沟道的第二氧化物半导体层。 Transistor illustrated [0155] embodiment of the present embodiment comprises: a first oxide semiconductor layer is prevented as a constituent element source electrode layer and a drain electrode diffusion layer into the buffer layer in the channel; and a second channel as oxide The semiconductor layer. 通过该结构,可以降低能够在晶体管的背沟道一侧形成的界面态的影响。 This structure can reduce the influence of the interface state can be formed at the back side of the transistor channel. 另外,更优选的是,本实施方式所示的晶体管还包括设置在用作沟道的氧化物半导体层与栅极绝缘层之间并用作用来防止沟道的栅极绝缘层一侧的界面的劣化的缓冲层的第三氧化物半导体层。 Further, more preferably, the transistor shown embodiment of the present embodiment further includes as a channel disposed between the oxide semiconductor layer and the gate insulating layer and serves as interface between the gate insulating layer to prevent a side of the channel third oxide semiconductor layer, the buffer layer is deteriorated. 通过包括第三氧化物半导体层,可以减少晶体管的光劣化(例如,光负偏压温度应力劣化),而可以提供可靠性高的半导体装置。 By including a third oxide semiconductor layer, the light deterioration of the transistor can be reduced (e.g., negative bias temperature stress light degradation), and a highly reliable semiconductor device can be provided.

[0156] 另外,本实施方式所示的晶体管作为栅极绝缘层包括具有包含氮的硅膜的第一栅极绝缘层以及包含氧的第二栅极绝缘层的叠层。 [0156] In addition, the transistor described in this embodiment, as the gate insulating layer includes a first gate insulating layer comprises silicon film containing nitrogen and a second gate insulating layer laminate containing oxygen. 该第一栅极绝缘层包括:用作对栅电极层的构成元素(例如,铜)的阻挡膜的包含氮的硅膜;厚度大(例如,300nm厚)且减少膜中缺陷数的包含氮的硅膜;以及对氢具有阻挡性的包含氮的硅膜。 The first gate insulating layer comprising: a barrier film is used as an element constituting the gate electrode layer (e.g., copper) nitrogen containing silicon film; large thickness (e.g., 300 nm thick) and reduces the number of defects in the film containing nitrogen silicon film; and a silicon film containing nitrogen having barrier properties against hydrogen. 因此,本实施方式的晶体管的电特性变动及静电破坏得到抑制。 Thus, variation in electric characteristics and electrostatic breakdown of the transistor according to the present embodiment is suppressed. 通过使用这种晶体管,可以以高成品率地制造高可靠性的半导体装置。 By using such a transistor can be manufactured at a high yield a highly reliable semiconductor device.

[0157] 本实施方式所示的结构、方法等可以与其他实施方式所示的结构、方法等适当地组合而使用。 As shown in [0157] the structure of the present embodiment, a method may be used in appropriate combination shown another embodiment of the structure, and methods.

[0158] 实施方式3 [0158] Embodiment 3

[0159] 通过使用实施方式1或2所示的晶体管可以制造具有显示功能的半导体装置(也称为显示装置)。 [0159] By using the transistor described in Embodiment 1 or 2 can be manufactured in a semiconductor device having a display function (also called a display device). 此外,通过将包括晶体管的驱动电路的一部分或全部与像素部一体地形成在相同的衬底上,可以形成系统整合型面板(system-on-panel)。 Further, by including a driving circuit for a transistor part or all of the pixel portion is formed integrally on the same substrate, a panel forming system integrated (system-on-panel).

[0160] 在图4A中,以围绕设置在衬底4001上的像素部4002的方式设置密封剂4005,像素部4002使用衬底4006进行密封。 Mode the pixel portion 4002 [0160] In FIG. 4A, is provided to surround the substrate 4001 disposed on the sealant 4005, the pixel portion 4002 using the sealing substrate 4006. 在图4A中,在衬底4001上的与由密封剂4005围绕的区域不同的区域中安装有使用单晶半导体膜或多晶半导体膜形成在IC芯片或另行准备的衬底上的扫描线驱动电路4004、信号线驱动电路4003。 In FIG. 4A, the substrate 4001 is mounted on a region surrounded by the sealant 4005 is formed with a different region of a single crystal semiconductor film or a polycrystalline semiconductor film in a scanning line on an IC chip or a substrate separately prepared driving circuit 4004, the signal line driver circuit 4003. 此外,通过信号线驱动电路4003和扫描线驱动电路4004供应到像素部4002的各种信号及电位由FPC (Flexible printed circuit:柔性印刷电路)4018a及4018b供应。 Further, the signal line driver circuit 4003 and the scanning line driver circuit 4004, a variety of signals and potentials supplied to the pixel portion 4002 from the FPC: Supply (Flexible printed circuit flexible printed circuit) 4018a and 4018b.

[0161] 在图4B和图4C中,以围绕设置在衬底4001上的像素部4002和扫描线驱动电路4004 的方式设置有密封剂4005。 The pixel portion 4002 and the scan lines [0161] In FIGS. 4B and 4C, the disposed to surround the substrate 4001 provided in the driver circuit 4004 with a sealant 4005. 此外,在像素部4002和扫描线驱动电路4004上设置有衬底4006。 Further, the pixel portion 4002 and the scan line driver circuit 4004 is provided with a substrate 4006. 因此,像素部4002、扫描线驱动电路4004与显示元件一起由衬底4001、密封剂4005以及衬底4006密封。 Thus, the pixel portion 4002, the scanning line driver circuit 4004 and the display 4001, the sealant 4005 and the substrate 4006 with the sealing element by the substrate. 在图4B和图4C中,在衬底4001上的与由密封剂4005围绕的区域不同的区域中安装有使用单晶半导体膜或多晶半导体膜形成在IC芯片或另行准备的衬底上的信号线驱动电路4003。 In FIGS. 4B and 4C, the mounting region surrounded by the sealant 4005 in different areas using a single crystal semiconductor film or a polycrystalline semiconductor film is formed on an IC chip or a substrate separately prepared on a substrate 4001 a signal line driver circuit 4003. 在图4B和图4C中,通过信号线驱动电路4003和扫描线驱动电路4004供应到像素部4002的各种信号及电位由FPC4018供应。 In FIGS. 4B and 4C, the scanning line driver circuit 4003 through the signal line driver circuit 4004 of various signals and potentials supplied to the pixel portion 4002 by FPC4018 supply.

[0162] 此外,图4B和图4C示出另行形成信号线驱动电路4003并且将该信号线驱动电路4003安装到衬底4001的例子,但是不局限于该结构。 [0162] Further, FIGS. 4B and FIG. 4C shows a separately formed signal line driver circuit 4003 and the substrate 4001 of an example of a signal line driver circuit 4003 is mounted to, but is not limited to this structure. 既可以另行形成扫描线驱动电路并进行安装,又可以仅另行形成信号线驱动电路的一部分或者扫描线驱动电路的一部分并进行安装。 It may be separately formed and the scan line driver circuit is mounted, but also a portion of the signal line or the scanning line driving circuit only the driving circuit is formed separately and mounted.

[0163] 另外,对另行形成的驱动电路的连接方法没有特别的限制,而可以采用COG (Chip On Glass:玻璃上芯片)方法、引线键合方法、TAB (Tape Automated Bonding:卷带式自动接合)方法等。 [0163] Further, there is no particular limitation on the connection method of the driver circuit is separately formed, and can be used COG (Chip On Glass: Chip On Glass) method, a wire bonding method, TAB (Tape Automated Bonding: Tape Automated Bonding ) methods. 图4A是通过COG方法安装信号线驱动电路4003、扫描线驱动电路4004的例子,图4B是通过COG方法安装信号线驱动电路4003的例子,图4C是通过TAB方法安装信号线驱动电路4003的例子。 4A is mounted by a COG method the signal line driver circuit 4003, an example of the scan line driver circuit 4004, FIG. 4B is an example of a signal line driver circuit 4003 is mounted by a COG method, and FIG. 4C is a signal line driver circuit 4003 is an example mounted by a TAB method .

[0164] 此外,显示装置包括显示元件处于密封状态的面板和在该面板中安装有包括控制器的IC等状态的模块。 [0164] The display device includes a display panel in a sealed state element and including a controller mounted with an IC module and the like in a state of the panel. 注意,本说明书中的显示装置是指图像显示装置、显示装置或光源(包括照明装置)。 Note that a display device in this specification means an image display device, a display device or a light source (including a lighting device). 另外,显示装置除了密封有显示元件的面板之外还包括:安装有诸如FPC 或TCP等连接器的模块;在TCP的端部设置有印刷线路板的模块;或者通过COG方法将IC (集成电路)直接安装到显示元件的模块。 Further, the display device other than a display panel in addition to sealing element further comprises: mounted such as TCP or FPC connector module; module provided with a printed wiring board at the end portion of the TCP; by a COG method or an IC (Integrated Circuit ) module mounted directly to the display element.

[0165] 此外,设置在衬底上的像素部及扫描线驱动电路具有多个晶体管,可以应用实施方式1或2所示的晶体管。 [0165] Further, provided on the substrate of the pixel portion and the scanning line driver circuit having a plurality of transistors, the transistor shown in Embodiment 1 or 2 may be applied.

[0166] 作为设置在显示装置中的显示元件,可以使用液晶元件(也称为液晶显示元件)、 发光元件(也称为发光显示元件)。 [0166] As the display element provided in a display device, a liquid crystal element (also called a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element). 发光元件包括由电流或电压控制亮度的元件,具体而言, 包括无机ELGilectro Luminescence:电致发光)、有机EL等。 A light emitting element comprises a luminance element is controlled by current or voltage, and specifically includes an inorganic ELGilectro Luminescence: Electroluminescence), an organic EL. 此外,也可以应用电子墨水显示装置(电子纸)等的对比度因电作用而发生变化的显示媒介。 Furthermore, contrast medium may be applied display device (electronic paper) or the like changes by an electric action of electronic ink display.

[0167] 使用图4A至图5对半导体装置的一个方式进行说明。 [0167] FIG. 4A to FIG. 5 of a semiconductor device will be described. 图5相当于沿着图4B的线MN 的截面图。 FIG 5 corresponds to a sectional view taken along line 4B of the MN. 图5示出将液晶元件用作显示元件的液晶显示装置的例子。 Figure 5 shows an example of a liquid crystal element as a display element of the liquid crystal display device.

[0168] 但是,只要显示装置以设置在像素部4002中的晶体管4010电连接到显示元件的方式构成,并且只要该显示元件能够进行显示就没有特别的限制,而可以使用各种各样的显示元件。 Transistor [0168] However, as long as the display device 4002 provided in the pixel portion 4010 is electrically connected to the display element configuration mode, and as long as the display element can be displayed is not particularly limited, and you can use various display element.

[0169] 如图4A至图5所示那样,半导体装置包括连接端子电极4015及端子电极4016,连接端子电极4015及端子电极4016通过各向异性导电层4019电连接到FPC4018 (4018a、4018b) 所具有的端子。 [0169] As shown in FIG. 4A to FIG. 5, a semiconductor device includes a connection terminal electrode 4015 and the terminal electrode 4016, a connection terminal electrode 4015 and the terminal electrode 4016 is electrically connected through the anisotropic conductive layer 4019 to FPC4018 (4018a, 4018b) of the having terminal.

[0170] 连接端子电极4015由与第一电极层4034相同的导电层形成,并且,端子电极4016 由与晶体管4010、4011的源电极层及漏电极层相同的导电层形成。 [0170] The connection terminal electrode 4015, and the terminal electrode 4016 is formed of the same conductive layer forming a first electrode layer 4034 and the source electrode layer and the same conductive layer as the drain electrode layer of the transistor 4010 and 4011.

[0171] 此外,设置在衬底4001上的像素部4002和扫描线驱动电路4004具有多个晶体管, 图4A至图5例示出像素部4002所包括的晶体管4010以及扫描线驱动电路4004所包括的晶体管4011。 [0171] The pixel portion 4001 is provided on the substrate 4002 and the scan line driver circuit 4004 having a plurality of transistors, FIGS. 4A to 5 illustrate a pixel transistor portion included 40,024,010 and a scanning line driver circuit 4004 included transistor 4011. 在图5中,在晶体管40ΠΚ4011上设置有绝缘层4032。 In FIG. 5, is provided over the transistor 40ΠΚ4011 insulating layer 4032.

[0172] 作为晶体管4010、4011,可以使用实施方式1或2所示的晶体管。 [0172] As transistors 4010 and 4011, a transistor may be used as shown in embodiment 1 or embodiment 2. 在本实施方式中示出应用具有与实施方式1所示的晶体管310相同的结构的晶体管的例子。 In the present embodiment shows an example of application of the transistor 310 having an embodiment shown in the same manner as the transistor structure. 晶体管4010、4011 是底栅结构的晶体管。 Transistors 4010 and 4011 is a transistor of a bottom gate structure.

[0173] 晶体管4010、4011包括:用作用来防止源电极层和漏电极层的构成元素扩散到沟道的缓冲层的第一氧化物半导体层;用作沟道的第二氧化物半导体层;以及设置在用作沟道的氧化物半导体层与栅极绝缘层之间并用作用来防止沟道与栅极绝缘层的界面劣化的缓冲层的第三氧化物半导体层。 [0173] transistors 4010 and 4011 comprises: as a first oxide semiconductor layer for preventing the constituent element of the source electrode layer and a drain electrode diffusion layer of the channel into the buffer layer; a second oxide semiconductor layer as a channel; as a channel provided between the oxide semiconductor layer and the gate insulating layer and serves as a third oxide semiconductor layer to prevent the buffer layer at the interface deterioration of the channel and the gate insulating layer. 因此,晶体管40KK4011是降低有可能形成在背沟道一侧的界面态的影响并减少晶体管的光劣化(例如光负偏压温度应力劣化)的可靠性高的晶体管。 Thus, it is possible to reduce the transistor 40KK4011 is formed on the back channel side impact of interface states and reduce the light deterioration of the transistor (e.g., negative bias temperature stress optical degradation) of the high reliability of the transistor.

[0174] 此外,可以在与驱动电路用的晶体管4011的氧化物半导体层的沟道形成区域重叠的位置还设置导电层。 Position [0174] In addition, the overlapping region may be formed in the channel of the drive circuit of the oxide semiconductor layer of the transistor 4011 is also provided with a conductive layer. 通过将导电层设置在与氧化物半导体层的沟道形成区域重叠的位置,可以进一步降低晶体管4011的阈值电压的变化量。 By conductive layer is formed at a position overlapping with the channel region of the oxide semiconductor layer, a transistor can be further reduced value of the voltage change amount of the threshold 4011. 此外,导电层的电位可以与晶体管4011的栅电极层的电位相同或不同,并且,还可以将导电层用作第二栅电极层。 Further, the potential of the conductive layer may be the same or different from the potential of the gate electrode layer of the transistor 4011, and the conductive layer may also be used as the second gate electrode layer. 此外,导电层的电位可以处于浮动状态。 Further, the potential of the conductive layer may be in a floating state.

[0175] 此外,该导电层还具有遮蔽外部的电场,即不使外部的电场影响到内部(包括晶体管的电路部)的功能(尤其是,遮蔽静电的静电遮蔽功能)。 [0175] Further, the conductive shield layer also has an external electric field, i.e., no external electric field affects the internal functions (including a transistor circuit portion) (in particular, electrostatic shielding of electrostatic shielding function). 通过利用导电层的遮蔽功能,可以防止由于静电等外部电场的影响而使晶体管的电特性变动。 By using shielding function of the conductive layer can be prevented variation in the electric characteristics due to the influence of an external electric field such as static electricity of the transistor.

[0176] 在图5中,液晶元件4013包括第一电极层4034、第二电极层4031以及液晶层4008。 [0176] In FIG. 5, the liquid crystal element 4013 includes a first electrode layer 4034, the second electrode layer 4031 and a liquid crystal layer 4008. 另外,以夹持液晶层4008的方式设置有用作取向膜的绝缘层4038、4033。 Further, as to sandwich the liquid crystal layer 4008 is provided 4038,4033 insulating layer serving as an alignment film. 第二电极层4031设置在衬底4006—侧,第一电极层4034和第二电极层4031隔着液晶层4008而层叠。 The second electrode layer disposed on the substrate 4006- 4031 side, the first electrode layer 4034 and the second electrode layer 4031 via the liquid crystal layer 4008 are stacked.

[0177] 作为第一电极层4034、第二电极层4031,可以使用含有氧化钨的铟氧化物、含有氧化钨的铟锌氧化物、含有氧化钛的铟氧化物、含有氧化钛的铟锡氧化物、铟锡氧化物、铟锌氧化物、添加有氧化硅的铟锡氧化物、石墨烯等具有透光性的导电材料。 [0177] As the first electrode layer 4034, the second electrode layer 4031, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide thereof, indium tin oxide, indium zinc oxide, or a conductive material having a light-transmitting indium tin oxide to which silicon oxide, or graphene.

[0178] 此外,第一电极层4034、第二电极层4031可以使用钨(W)、钼(Mo)、锆(Zr)、铪(Hf)、 钒(V)、铌(Nb)、钽(Ta)、铬(Cr)、钴(Co)、镍(Ni)、钛(Ti)、铂(Pt)、铝(Al)、铜(Cu)、银(Ag)等金属、其合金或者其金属氮化物中的一种或多种来形成。 [0178] In addition, the first electrode layer 4034, the second electrode layer 4031 can be formed using tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum ( Ta), chromium (Cr), cobalt (Co), Nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, alloys thereof, or metal one or more nitrides formed.

[0179] 此外,第一电极层4034、第二电极层4031可以使用包括导电高分子(也称为导电聚合体)的导电组合物来形成。 [0179] In addition, the first electrode layer 4034, the second electrode layer 4031 may be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer) is. 作为导电高分子,可以使用所谓的η电子共辄导电高分子。 As the conductive polymer can be used a so-called co-η Noir electron conducting polymer. 例如,可以举出聚苯胺或其衍生物、聚吡咯或其衍生物、聚噻吩或其衍生物或者由苯胺、吡咯和噻吩中的两种以上构成的共聚物或其衍生物等。 For example, polyaniline or a derivative thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, or of two of aniline, pyrrole, and thiophene or a derivative thereof and a copolymer of the above and the like.

[0180] 此外,间隔物4035是通过对绝缘层进行选择性地蚀刻而获得的柱状间隔物,并且它是为了控制液晶层4008的厚度(单元间隙(cell gap))而设置的。 [0180] In addition, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer is obtained, and it is to control the thickness of the liquid crystal layer (cell gap (cell gap)) 4008 being provided. 另外,也可以使用球状间隔物。 Further, a spherical spacer may be used.

[0181] 当作为显不兀件使用液晶兀件时,可以使用热致液晶、铁电液晶、反铁电液晶等。 [0181] When not as significant Wu Wu member using a liquid crystal element, a thermotropic liquid crystal, a ferroelectric liquid crystal, antiferroelectric liquid crystal and the like. 上述液晶材料既可以是低分子化合物又可以是高分子化合物。 The liquid crystal material may be either a low molecular compound but also a polymer compound. 上述液晶材料(液晶组合物) 根据条件而呈现胆留相、近晶相、立方相、手征向列相、各向同性相等。 The liquid crystal material (liquid crystal composition) according to the conditions presented bile stay phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase.

[0182] 另外,也可以作为液晶层4008使用不使用取向膜的呈现蓝相的液晶组合物。 [0182] Further, the liquid crystal layer 4008 may be used as an alignment film without using the liquid crystal composition exhibits a blue phase. 此时, 液晶层4008与第一电极层4034及第二电极层4031接触。 In this case, the liquid crystal layer 4008 in contact with the first electrode layer 4034 and the second electrode layer 4031. 蓝相是液晶相的一种,是指当使胆甾相液晶的温度上升时即将从胆留相转变到各向同性相之前出现的相。 Blue phase is one of liquid crystal phases, means that when the cholesteric phase transition occurs just before leaving from the bladder to the isotropic phase when the temperature increase of the liquid crystal phase. 使用混合了液晶及手性试剂的液晶组合物可以呈现蓝相。 Mixed liquid crystal and the chiral agent may be liquid crystal composition exhibits a blue phase. 此外,为了扩大呈现蓝相的温度范围,通过对呈现蓝相的液晶组合物添加聚合性单体及聚合引发剂等,并进行高分子稳定化处理可以形成液晶层。 Further, in order to expand the temperature range blue phase is exhibited, by adding a polymerizable monomer to the liquid crystal composition exhibits a blue phase and a polymerization initiator, and polymer stabilization treatment may be formed in the liquid crystal layer. 由于呈现蓝相的液晶组合物的响应时间短,并且其具有光学各向同性,所以不需要取向处理,且视角依赖性小。 Since the blue phase exhibits a short response time of the liquid crystal composition has optical isotropy, which makes the alignment process unneeded, and a small viewing angle dependence. 另外,由于不需要设置取向膜而不需要摩擦处理,因此可以防止由于摩擦处理而引起的静电放电损伤,并可以降低制造工序中的液晶显示装置的不良、破损。 Further, since the need to provide an alignment film without rubbing treatment, it is possible to prevent electrostatic discharge damage due to friction caused by process, and can reduce the manufacturing process of the liquid crystal display device defects and damage. 因此,可以提尚液晶显不装置的生广率。 Thus, the rate can be improved Shengguang not yet liquid crystal display device.

[0183] 此外,液晶材料的电阻率为1Χ109Ω · cm以上,优选为1Χ1〇ηΩ · cm以上,更优选为1Χ1012Ω .cm以上。 [0183] In addition, the resistance of the liquid crystal material was 1Χ109Ω · cm or more, preferably 1Χ1〇ηΩ · cm or more, more preferably 1Χ1012Ω .cm. 另外,本说明书中的电阻率为在20°C下测量的值。 Further, the value of resistivity of this specification at 20 ° C measured.

[0184] 考虑到配置在像素部中的晶体管的泄漏电流等而以能够在规定期间保持电荷的方式设定设置在液晶显示装置中的存储电容器的大小。 [0184] Considering the leakage current or the like arranged in the pixel portion transistor and the charge can be held in a predetermined period is provided to set the size of the storage capacitor of the liquid crystal display device. 根据晶体管的关态电流(off-state current)等设定存储电容器的大小即可。 According to the size of the off-state current of the transistor (off-state current) is set and the like of the storage capacitor. 通过使用具有本说明书所公开的氧化物半导体层的晶体管,设置具有各像素中的液晶电容的1/3以下,优选为1/5以下的电容的存储电容器, 就足够了。 By using a transistor having an oxide semiconductor layer disclosed in the present specification is provided with a liquid crystal capacitance of each pixel is 1/3 or less, preferably 1/5 or less of the storage capacitance of the capacitor, is sufficient.

[0185] 使用本说明书所公开的氧化物半导体层的晶体管可以将关断状态下的电流值(关态电流值)控制为低。 [0185] transistor including an oxide semiconductor layer disclosed in the present specification may be off-current value (OFF-state current value) in the control off state is low. 因此,可以延长图像信号等电信号的保持时间,也可以延长写入间隔。 Thus, the holding time can be extended electrical image signals, writing interval can be extended. 因此,可以降低刷新工作的频度,所以有抑制耗电量的效果。 Thus, it is possible to reduce the frequency of refresh operation, it has the effect of suppressing power consumption.

[0186] 此外,使用本说明书所公开的氧化物半导体层的晶体管可以得到较高的场效应迀移率,所以能够高速驱动电路。 [0186] Further, a transistor using an oxide semiconductor layer disclosed in the present specification can be obtained high field-effect Gan drift rate, it is possible to high-speed driving circuit. 例如,通过将这种晶体管用于液晶显示装置,可以在同一衬底上形成像素部的开关晶体管及用于驱动电路部的驱动晶体管。 For example, such a transistor by a liquid crystal display device, a switching transistor and a pixel portion may be formed in the driver circuit portion for driving the transistor on the same substrate. 另外,在像素部中也通过使用这种晶体管,可以提供高质量的图像。 Further, in the pixel portion by using such a transistor is also possible to provide a high quality image.

[0187] 液晶显示装置可以采用TN (Twisted Nematic :扭曲向列)模式、IPS (In-Plane-Switching:平面内转换)模式、FFS (Fringe Field Switching:边缘场转换)模式、ASM (Axially Symmetric aligned Micro-cell:轴对称排列微单元)模式、OCB (Optical Compensated Birefringence:光学补偿弯曲)模式、FLC (Ferroelectric Liquid Crystal : 铁电性液晶)模式、AFLC (Anti Ferroelectric Liquid Crystal:反铁电性液晶)模式等。 [0187] The liquid crystal display device can be used TN (Twisted Nematic: twisted nematic), IPS mode (In-Plane-Switching: In-Plane Switching) mode, FFS (Fringe Field Switching: Fringe Field Switching) mode, ASM (Axially Symmetric aligned micro-cell: axially symmetric aligned microcell) mode, OCB (optical compensated Birefringence: optically compensated bend) mode, FLC (ferroelectric liquid crystal: ferroelectric liquid crystal) mode, AFLC (anti ferroelectric liquid crystal: anti-ferroelectric liquid crystal) mode.

[0188] 此外,也可以使用常黑型液晶显示装置,例如采用垂直配向(VA)模式的透射型液晶显示装置。 [0188] Further, use may be normally black type liquid crystal display device, for example, vertical alignment (VA) mode transmissive liquid crystal display device. 作为垂直配向模式,可以举出几个例子,例如可以使用MVA (Multi-Domain Vertical Alignment:多域垂直取向)模式、PVA (Patterned Vertical Alignment:图案化垂直取向)模式、ASV (Advanced Super View:高级超视觉)模式等。 As the vertical alignment mode, a few examples include, for example, may be used MVA (Multi-Domain Vertical Alignment: multi-domain vertical alignment) mode, PVA (Patterned Vertical Alignment: patterned vertical alignment) mode, ASV (Advanced Super View: Advanced super View) mode. 另外,也可以用于VA型液晶显示装置。 Further, it may also be used for a VA liquid crystal display device. VA型液晶显示装置是一种控制液晶显示面板的液晶分子的排列的方式。 VA-type liquid crystal display device is for controlling alignment of the liquid crystal molecules of the liquid crystal display panel of the embodiment. VA型液晶显示装置是在不被施加电压时液晶分子朝向垂直于面板表面的方向的方式。 VA-type liquid crystal display device when the voltage is not applied to the liquid crystal molecules toward a direction perpendicular to the panel surface manner. 此外,也可以使用将像素(pixel)分成几个区域(子像素)并且使分子在各自的区域内分别取向于不同方向的被称为多域化或多域设计的方法。 Further, the pixel may be used (pixel) is divided into several regions (subpixels), and a method referred to as multi-domain or multi-domain design molecules in the respective regions are oriented in different directions.

[0189] 此外,在显示装置中,适当地设置黑矩阵(遮光层)、偏振构件、相位差构件、抗反射构件等的光学构件(光学衬底)等。 [0189] Further, in the display device, the optical member appropriately setting a black matrix (light shielding layer), a polarizing member, a retardation member, such as anti-reflection member (optical substrate) and the like. 例如,也可以使用利用偏振衬底以及相位差衬底而得到的圆偏振。 For example, circular polarization may be used using a polarizing substrate and a retardation substrate obtained. 此外,作为光源,也可以使用背光灯、侧光灯等。 Further, as the light source may be used a backlight, a sidelight, and the like.

[0190] 此外,作为像素部中的显示方式,可以采用逐行扫描方式或隔行扫描方式等。 [0190] Further, as the display pixel portion can be progressive scanning or interlaced scanning mode and the like. 此夕卜,作为当进行彩色显示时在像素中控制的颜色因素,不局限于R、G、B(R表示红色,G表示绿色,B表示蓝色)这三种颜色。 Bu this evening, when the color elements in the display control color pixel is not limited to R, G, B (R represents red, G represents green, B represents blue) of three colors. 例如,也可以采用R、G、B、W(W表示白色)或对R、G、B追加黄色(yellow)、青色(cyan)、品红色(magenta)等中的一种以上的颜色。 For example, use may be R, G, B, W (W corresponds to white) or to R, G, B is added yellow (Yellow), the above cyan (Cyan), magenta (Magenta) color, and the like. 另外,各个色素的点的显示区域的大小可以不同。 Further, the size of the display region of each dye spot may be different. 但是,所公开的发明一个方式不局限于彩色显示的显示装置,而也可以应用于单色显示的显示装置。 However, an embodiment of the disclosed invention is not limited to the display device for color display, but may also be applied to a display device for monochrome display.

[0191] 图IlA至图IlC示出在图5所示的显示装置中将用来电连接于设置在衬底4006上的第二电极层4031的共同连接部(焊盘部)形成在衬底4001上的例子。 [0191] FIGS IlA to IlC will be shown in the display device shown in FIG. 5 for electrically connecting a second electrode layer disposed on a substrate 4006, 4031 is the common connection portion (a pad portion) is formed in the substrate 4001 examples on.

[0192] 共同连接部配置在与用来粘合衬底4001和衬底4006的密封剂重叠的位置,并且通过密封剂所包含的导电粒子与第二电极层4031电连接。 [0192] and the common connection portion is disposed at the bonded substrate 4001 to the substrate 4006 and the position overlapping the sealant and the sealant through the conductive particles contained in the electrically connected to the second electrode layer 4031. 或者,也可以在不与密封剂重叠的位置(但是在像素部以外)设置共同连接部,并且,以与共同连接部重叠的方式将包括导电粒子的膏剂与密封剂分开设置,而使共同连接部与第二电极层4031电连接。 Alternatively, the sealant does not overlap with the position (but other than the pixel portion) is provided common connection portion, and the manner and overlaps the common connection portion comprises the conductive particles is provided separately from the sealant paste, connected to the common portion of the second electrode layer 4031 is electrically connected.

[0193] 图IIA是共同连接部的截面图,图IIA相当于沿着图11B所示的俯视图中的线GI-G2 的截面。 [0193] FIG IIA is a sectional view of the common connection portion, corresponding to FIG IIA sectional plan view shown in FIG. 11B along line the GI-G2.

[0194] 共同电位线491设置在栅极绝缘层4020上并利用与图5所示的晶体管4010、4011的源电极层和漏电极层相同的材料及工序制造。 [0194] The common potential line 491 is provided on the gate insulating layer 4020 using transistors 4010 and 4011 shown in FIG. 5 of the source electrode layers and drain electrode layers of the same materials and manufacturing processes.

[0195] 此外,共同电位线491由绝缘层4032覆盖,并且绝缘层4032在与共同电位线491重叠的位置具有多个开口部。 [0195] In addition, the common potential line 491 is covered by the insulating layer 4032 and insulating layer 4032 having a plurality of openings at positions overlapping the common potential line 491. 该开口部通过与连接晶体管4010的源电极层和漏电极层中的一方与第一电极层4034的接触孔相同的工序来形成。 The opening portion is formed by the contact hole of the source electrode layer and a drain electrode layer connected to the transistor 4010 in one of the first electrode layer 4034 and the same step.

[0196] 另外,共同电极492设置在绝缘层4032上,并利用与连接端子电极4015和像素部的第一电极层4034相同的材料及工序而形成。 [0196] Further, the common electrode 492 is disposed on the insulating layer 4032, and the connection terminal electrode 4015 using the same material as the first electrode layer and the step of the pixel portion 4034 is formed.

[0197] 如此,可以利用像素部4002的开关元件的制造工序来形成共同连接部。 [0197] Thus, the common connection portion can be formed by using a manufacturing process of a pixel portion 4002 of the switching element.

[0198] 共同电极492是与包括在密封剂中的导电粒子接触的电极,与衬底4006的第二电极层4031电连接。 [0198] The common electrode 492 is connected to the second electrode layer 4031 and the dielectric substrate 4006 including the conductive particles in the electrode in contact with the sealant.

[0199] 另外,如图IlC所示,共同电位线491可以利用与晶体管4010、4011的栅电极层相同的材料及工序而形成。 [0199] Further, as shown in FIG IlC, the common potential line 491 can be used the same material as the gate electrode layer and the step of transistors 4010 and 4011 is formed.

[0200] 在图lie所示的共同连接部中,共同电位线491设置在栅极绝缘层4020及绝缘层4032的下层中,并且栅极绝缘层4020及绝缘层4032在与共同电位线491重叠的位置具有多个开口部。 [0200] In the common connection portion shown in FIG. Lie, the common potential line 491 is provided in the lower gate insulating layer 4020 and the insulating layer 4032, and the gate insulating layer 4020 and insulating layer 4032 and the common potential line 491 overlap location having a plurality of openings. 该开口部在通过与连接晶体管4010的源电极层和漏电极层中的一方与第一电极层4034的接触孔相同的工序对绝缘层4032进行蚀刻之后,对栅极绝缘层4020选择性地进行蚀刻来形成。 After the opening portion through the contact hole of the source electrode layer and a drain electrode layer connected to the transistor 4010 in one of the first electrode layer 4034 is the same process of the insulating layer 4032 is etched, the gate insulating layer 4020 is selectively performed etching.

[0201] 此外,作为显示装置所包括的显示元件,可以应用利用电致发光的发光元件。 [0201] Further, as a display device comprising a display element may be applied using an electroluminescent light emitting element. 利用电致发光的发光元件根据发光材料是有机化合物还是无机化合物来区分,一般地,前者被称为有机EL元件,而后者被称为无机EL元件。 A light emitting element using electroluminescence light emitting material is to distinguish between an organic compound or an inorganic compound, in general, the former is referred to as organic EL element and the latter is called an inorganic EL element.

[0202] 在有机EL元件中,通过对发光元件施加电压,电子及空穴分别从一对电极注入到包括发光性有机化合物的层,于是电流流过。 [0202] In the organic EL element, injected by applying a voltage, electrons and holes respectively from the light-emitting element comprising a pair of electrodes into the organic light-emitting layer, so the current flows. 并且,通过这些载流子(电子及空穴)的重新结合,发光性有机化合物形成激发态,当从该激发态回到基态时发光。 Then, by recombination of these carriers (electrons and holes), a light emitting organic compound is excited when the light emission from the excited state returns to a ground state. 由于这种机理,这种发光元件被称为电流激发型发光元件。 Because of such a mechanism, such a light emitting element is called a current-excitation light-emitting element. 在本实施方式中,示出作为发光元件使用有机EL元件的例子。 In the present embodiment, an example using an organic EL element as a light emitting element.

[0203] 无机EL元件根据其元件结构而分类为分散型无机EL元件和薄膜型无机EL元件。 [0203] The inorganic EL elements are classified according to their element structures into a dispersion type inorganic EL element and a thin-film inorganic EL element. 分散型无机EL元件具有发光材料的粒子分散在粘合剂中的发光层,其发光机理是利用供体能级和受体能级的供体-受体重新结合型发光。 Particle dispersion-type inorganic EL element has a light-emitting material are dispersed in the light-emitting layer binder, and its light emission mechanism is donor utilizes a donor level and an acceptor level - acceptor recombination type light emission. 薄膜型无机EL元件具有发光层夹在介电层之间且该介电层由电极夹住的结构,其发光机理是利用金属离子的内壳层电子跃迀的定域型发光(localized type light emission)。 Thin-film type inorganic EL element has a light emitting layer interposed between the dielectric layer and the dielectric layer is sandwiched by the electrode structure, its light emission mechanism is the use of metal ions of the inner-shell electron transitions Gan localized type light emission (localized type light emission). 在此,作为发光元件使用有机EL元件进行说明。 Here, an organic EL element will be described as a light emitting element.

[0204] 为了从发光元件取出发光,使发光元件的一对电极中的至少一个具有透光性即可。 [0204] In order to extract light from the light emitting element, the pair of electrodes of the light emitting element in at least a light-transmitting property. 作为发光元件,有:从与衬底相反一侧的表面取出发光的顶部发射结构的发光元件;从衬底一侧的表面取出发光的底部发射结构的发光元件;以及从衬底一侧及与衬底相反一侧的表面取出发光的双面发射结构的发光元件,可以应用上述任一种发射结构的发光元件。 As the light emitting element, there is: removed from the surface opposite to the substrate of the light emitting element having a top emission structure emitting; bottom emission structure emitting light emitting element is taken out from a side surface of the substrate; and from the substrate side and with remove the opposite surface of the substrate the light emitting element having a dual emission structure to emit light, the light emitting device can be applied to any of these emission structures.

[0205] 图6A、图6B及图13示出作为显示元件使用发光元件的发光装置的例子。 [0205] FIGS. 6A, 6B, and FIG. 13 shows an example of using the light emitting device emitting element as a display element.

[0206] 图6A是发光装置的截面图,图6A中的以点划线S1-T1、S2-T2及S3-T3切断的截面相当于图6B。 [0206] FIG 6A is a dotted line S1-T1-sectional view of a light emitting device, FIG. 6A, S2-T2 and S3-T3 corresponds to a cross-sectional cut of Fig. 6B. 另外,图13相当于图6A中的以点划线S4-T4切断的截面图。 Further, FIG 13 corresponds to a sectional view S4-T4-dot chain line in FIG. 6A cut. 另外,在图6A的平面图中,省略场致发光层542及第二电极层543而未图不。 Further, in the plan view of FIG. 6A, the electroluminescent layer 542 is omitted and the second electrode layer 543 is not without FIG.

[0207] 图6A和图6B所示的发光装置在衬底500上具有晶体管510、电容元件520、布线层交叉部530,晶体管510与发光元件540电连接。 [0207] light emitting device shown in FIGS. 6A and 6B a transistor 510 over a substrate 500, a capacitor element 520, the wiring layer crossing portion 530, transistor 510 is electrically connected to the light emitting element 540. 另外,图6A和图6B示出经过衬底500从发光元件540取光的底面发射型结构的发光装置。 Further, FIGS. 6A and FIG. 6B shows a bottom-emission type light emitting device structure 540 taken from the light emitting element 500 through the substrate.

[0208] 作为晶体管510,可以使用实施方式1或2所示的晶体管。 [0208] As the transistor 510, the transistor may be used as shown in embodiment 1 or embodiment 2. 在本实施方式中示出应用具有与实施方式2所示的晶体管330相同的结构的晶体管的例子。 In the present embodiment shows an example having the same transistor shown in Embodiment transistor structure 2330 application. 晶体管510是底栅结构的晶体管。 Transistor 510 is a transistor of a bottom gate structure.

[0209] 晶体管510包括:栅电极层51 la、栅电极层51 Ib;包括栅极绝缘层502a、栅极绝缘层502b及栅极绝缘层502c的栅极绝缘层502;包括氧化物半导体层512b及氧化物半导体层512a的氧化物半导体叠层512;以及用作源电极层和漏电极层的导电层513a、导电层513b。 [0209] Transistor 510 includes: a gate electrode layer 51 la, the gate electrode layer 51 Ib; includes a gate insulating layer 502a, a gate insulating layer 502b and the gate insulating layer 502c of the gate insulating layer 502; includes an oxide semiconductor layer 512b stack of the oxide semiconductor and the oxide semiconductor layer 512a is 512; and a conductive layer 513a, a conductive layer 513b serving as a source electrode layer and a drain electrode layer. 另外,在晶体管510上形成有绝缘层525。 Further, the transistor 510 is formed on the insulating layer 525.

[0210] 电容元件520包括:导电层521a、导电层521b;栅极绝缘层502;包括氧化物半导体层522b及氧化物半导体层522a的氧化物半导体叠层522;以及导电层523。 [0210] 520 capacitor element comprising: a conductive layer 521a, a conductive layer 521b; a gate insulating layer 502; layer 522b includes an oxide semiconductor layer 522a and the oxide semiconductor is an oxide semiconductor stack 522; 523 and a conductive layer. 并且,以由导电层521a、导电层521b以及导电层523夹着栅极绝缘层502及氧化物半导体叠层522的结构来形成电容器。 Further, the structure of the gate insulating layer to a conductive layer 521a, 521b and the conductive layer 502 sandwiched between the conductive layer 523 and the oxide semiconductor stack 522 to form a capacitor.

[0211] 布线层交叉部530是栅电极层511a、栅电极层511b和导电层533的交叉部,并且栅电极层511a、栅电极层511b和导电层533隔着栅极绝缘层502交叉。 [0211] intersecting the wiring layer 530 is a gate electrode layer 511a, a gate electrode layer 511b and the conductive layer 533 of the intersection, and the gate electrode layer 511a, a gate electrode layer 511b and the conductive layer 533 through the gate insulating layer 502 intersect.

[0212] 在本实施方式中,作为栅电极层511a及导电层521a使用30nm厚的钛膜,作为栅电极层511b及导电层521b使用200nm厚的铜膜。 [0212] In the present embodiment, 521a 30nm thick titanium film is used as the gate electrode layer 511a and the conductive layer, a 200nm thick copper film as a gate electrode layer 511b and the conductive layer 521b. 因此,栅电极层具有钛膜和铜膜的叠层结构。 Thus, the gate electrode layer has a laminated structure of a titanium film and a copper film.

[0213] 晶体管510包括:用作沟道的氧化物半导体层512b;以及用作用来防止导电层513a 及导电层513b的构成元素扩散到沟道的缓冲层的氧化物半导体层512a。 [0213] Transistor 510 includes: an oxide semiconductor as a channel layer 512b; and 513a as the conductive layer for preventing the constituent element and the conductive layer 513b is diffused into the oxide semiconductor layer, the buffer layer 512a channel. 因此,晶体管510是降低有可能形成在背沟道一侧的界面态的影响的可靠性高的晶体管。 Thus, transistor 510 is likely to reduce the reliability of the transistor formed in the high side of the back channel influence of the interface state.

[0214] 此外,晶体管510包括:用作栅极绝缘层502c的氨的含量少的用作阻挡铜的阻挡膜的含有氮的硅膜;用作栅极绝缘层502a的厚度大(例如,300nm厚)且缺陷少的含有氮的硅膜;以及用作栅极绝缘层502b的氢浓度低的含有氮的硅膜。 [0214] Further, the transistor 510 includes: as the ammonia content of the gate insulating layer 502c is used as a silicon film containing less nitrogen blocking barrier film of copper; large thickness as a gate insulating layer 502a (e.g., 300 nm thick) and low defect silicon film containing nitrogen; as a gate insulating layer 502b, and a low hydrogen concentration of the silicon film containing nitrogen. 通过采用上述结构,可以改善晶体管510的电特性,还可以防止晶体管510的静电破坏。 With the above configuration, the electrical characteristics of the transistor 510 can be improved, but also prevents electrostatic breakdown of the transistor 510. 由此,可以以高成品率制造高可靠性的半导体装置。 Thus, high reliability can be manufactured with a high yield of the semiconductor device.

[0215] 在晶体管510、电容元件520、布线层交叉部530上形成有层间绝缘层504,并且在层间绝缘层504上的与发光元件540重叠的区域设置有彩色滤光层505。 An interlayer insulating layer 504 [0215] is formed over the transistor 510, a capacitor element 520, the wiring layer crossing portion 530, and is provided with a color filter layer 505 overlaps with the light emitting element region 540 on the interlayer insulating layer 504. 在层间绝缘层504及彩色滤光层505上设置有用作平坦化绝缘层的绝缘层506。 On the interlayer insulating layer 504 and the color filter layer 505 is provided with an insulating layer 506 as a planarizing insulating layer.

[0216] 在绝缘层506上设置有包含依次层叠第一电极层541、场致发光层542、第二电极层543的叠层结构的发光元件540。 [0216] disposed on the insulating layer 506 with a layer comprising sequentially laminating a first electrode 541, an electroluminescent layer 542, the light emitting element of the laminated structure 543 of the second electrode layer 540. 通过在到达导电层513a且在形成在绝缘层506及层间绝缘层504的开口中第一电极层541与导电层513a彼此接触,发光元件540与晶体管510电连接。 And reaches the conductive layer 513a is formed in contact with the first electrode layer 541 and the conductive layer 513a in the opening of another interlayer insulating layer 506 and the interlayer insulating layer 504, the light emitting element 540 and the transistor 510 is electrically connected through. 此外,以覆盖第一电极层541的一部分及该开口的方式设置有隔壁507。 In addition, the opening portion and covers the first embodiment of the electrode layer 541 is provided with a partition wall 507.

[0217] 作为绝缘层506可以使用1500nm厚的感光性丙烯酸膜,作为隔壁507可以使用1500nm厚的感光性聚酰亚胺膜。 [0217] may be used a photosensitive acrylic film 1500nm thick as the insulating layer 506, the photosensitive polyimide film may be used as a partition wall thickness of 507 1500nm.

[0218] 作为彩色滤光层505,例如可以使用彩色的透光树脂。 [0218] As the color filter layer 505, may be used, for example, colored light-transmitting resin. 作为彩色透光树脂,可以使用感光性有机树脂、非感光性有机树脂。 As a color light-transmitting resin, a photosensitive organic resin may be used, non-photosensitive organic resin. 当使用感光性有机树脂层时,可以减少抗蚀剂掩模数量而简化工序,所以是优选的。 When the photosensitive organic resin layer, the number of resist masks can be reduced and simplified process, which is preferable.

[0219] 彩色是指如黑色、灰色和白色等非彩色以外的颜色。 [0219] Color refers to the color such as black, gray and white than the non-colored. 彩色滤光层由只使彩色光透过的材料形成。 A color filter layer formed of only the colored light-permeable material. 至于彩色,可以使用红色、绿色、蓝色等。 As for color, you can use red, green, blue and so on. 另外,还可以使用青色(cyan)、品红色(magenta)、黄色(yellow)等。 Further, it may also be used cyan (Cyan), magenta (Magenta), yellow (Yellow) and the like. “只使彩色光透过”意味着:透过彩色滤光层的光在其彩色光的波长中具有峰值。 "Only the colored light transmission" means: having a peak at a wavelength in which the color of light transmitted through the light color filter layer. 关于彩色滤光层的厚度,可以根据所包含的着色材料的浓度与光的透射率的关系适当地控制为最适合的膜厚度。 The thickness of the color filter layer, may be suitably controlled to the most suitable film thickness in accordance with the relationship between the light transmittance of the concentration of the coloring material contained. 例如,将彩色滤光层505的厚度设定为1500nm 以上且2000nm以下即可。 For example, the thickness of the color filter layer 505 is set to be more than 1500nm and 2000nm or less.

[0220] 隔壁507可使用有机绝缘材料或无机绝缘材料形成。 [0220] partition wall 507 may be formed using an organic insulating material or inorganic insulating material. 尤其是,隔壁507优选使用感光树脂材料形成,且在第一电极层541上形成开口部,并且将该开口部的侧壁形成为具有连续曲率的倾斜面。 In particular, the partition wall 507 is preferably formed using a photosensitive resin material, and an opening portion is formed on the first electrode layer 541, and the sidewall of the opening portion is formed as an inclined surface with continuous curvature.

[0221] 场致发光层542可以使用一个层构成,也可以使用多个层的叠层构成。 [0221] The electroluminescent layer 542 may use a layer configuration may also be used a plurality of layers constituting the laminate.

[0222] 为了防止氧、氢、水分、二氧化碳等侵入到发光元件540中,也可以在第二电极层543及隔壁507上形成保护膜。 [0222] In order to prevent entry of the light emitting element 540 to the oxygen, hydrogen, moisture, carbon dioxide, and the like, a protective film may be formed on the second electrode layer 543 and the partition 507. 作为保护膜,可以形成氮化硅膜、氮氧化硅膜、DLC膜等。 As the protective film, a silicon nitride film, a silicon oxynitride film, the DLC film.

[0223] 另外,为了不使氧、氢、水分、二氧化碳等侵入到发光元件540,也可以通过蒸镀法形成覆盖发光元件540的包含有机化合物的层。 [0223] In order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide or the like into the light emitting element 540 may comprise an organic compound layer 540 covering the light emitting element is formed by a vapor deposition method.

[0224] 另外,如果需要,也可以在发光元件的射出表面上适当地设置诸如偏振片或者圆偏振片(包括椭圆偏振片)、相位差板(λ/4板,λ/2板)、彩色滤光片等的光学薄膜。 [0224] Further, if desired, can be appropriately set, such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate) on the exit surface of the light emitting element, a retardation plate (λ / 4 plate, λ / 2 plate), color an optical filter film or the like. 此外,也可以在偏振片或圆偏振片上设置防反射膜。 Further, an antireflection film may be provided on a polarizing plate or circularly polarizing plate. 例如,可以进行抗眩光处理,该处理是利用表面的凹凸来扩散反射光而可以降低眩光的处理。 For example, anti-glare treatment, the treatment is treatment with an uneven surface to diffused light reflected glare can be reduced.

[0225] 此外,作为显示装置,也可以提供驱动电子墨水的电子纸。 [0225] In addition, as the display device, it may also provide the electronic paper that drives electronic ink. 电子纸也称为电泳显示装置(电泳显示器),并具有如下优点:与纸同样水平的易读性;其耗电量比其他显示装置的耗电量低;形状薄且轻。 The electronic paper is also called an electrophoretic display device (electrophoretic display) and has the following advantages: the same level of readability of the paper; the less power consumption than other display devices; thin and light form.

[0226] 作为电泳显示装置,可以有各种各样的形式,它是包括多个具有正电荷的第一粒子和具有负电荷的第二粒子的微囊分散在溶剂中,并且,通过对微囊施加电场,使微囊中的粒子向彼此相反的方向移动,只显示集合在一侧的粒子的颜色的装置。 [0226] As the electrophoretic display device can have various forms, which include a plurality of second particles and microcapsules having a negative charge of positively charged particles are dispersed in a first solvent, and, through the micro- bladder applying an electric field, the particles in the microcapsules move in opposite directions to each other, only the color display device set in the side of the particle. 另外,第一粒子和第二粒子都包括色素,当没有电场时不移动。 Further, both the first and second particles include pigments, do not move without an electric field. 此外,第一粒子的颜色和第二粒子的颜色不同(包括无色)。 Further, the color of the color of the first particles and the second particles are different (including colorless).

[0227] 分散有上述微囊的溶剂被称为电子墨水。 [0227] solvent in which the microcapsules are dispersed is referred to as electronic ink. 还可以通过使用彩色滤光片、具有色素的粒子来进行彩色显示。 It can also be achieved by a color display using a color filter, having a pigment particle.

[0228] 另外,作为用作平坦化绝缘层的绝缘层506,可以使用丙烯酸树脂、聚酰亚胺树脂、 苯并环丁烯类树脂、聚酰胺树脂、环氧树脂等具有耐热性的有机材料。 [0228] Further, a planarization insulating layer used as the insulating layer 506, an acrylic resin, a polyimide having a heat resistance organic resin, benzocyclobutene-based resin, a polyamide resin, an epoxy resin material. 此外,除了上述有机材料以外,还可以使用硅氧烷类树脂、PSG (磷硅玻璃)、BPSG (硼磷硅玻璃)等低介电常数材料(low-k材料)。 Further, in addition to the above organic materials may also be used a silicone-based resin, PSG (phosphosilicate glass), the BPSG (borophosphosilicate glass), and other low dielectric constant material (low-k material). 另外,也可以通过层叠多个由上述材料形成的绝缘层形成绝缘层506。 Further, the insulating layer 506 may be formed of an insulating layer of the material formed by laminating a plurality.

[0229] 对绝缘层506的形成方法没有特别的限制,可以根据其材料利用溅射法、旋涂法、 浸渍法、喷涂法、液滴喷射法(喷墨法等)、印刷法(丝网印刷、胶版印刷等)等。 [0229] There is no particular limitation on the method of forming the insulating layer 506, depending on the material may be a sputtering method, a spin coating method, dipping method, spray coating method, a droplet discharge method (inkjet method), a printing method (a screen printing, offset printing, etc.) and the like.

[0230] 作为第一电极层541、第二电极层543,可以应用与图5所示的显示装置的第一电极层4034、第二电极层4031相同的材料。 [0230] The first electrode layer 541, the second electrode layer 543, a first electrode layer may be applied to the display device 4034 shown in FIG. 5, the same material as the second electrode layer 4031.

[0231] 在本实施方式中,图6A和图6B所示的发光装置具有底部发射型结构,所以第一电极层541具有透光性,第二电极层543具有反射性。 [0231] In the present embodiment, the light emitting device shown in FIGS. 6A and FIG. 6B having a bottom emission structure, the first electrode layer 541 having a light-transmitting, second electrode 543 having a reflective layer. 因此,当作为第一电极层541使用金属膜时,将该金属膜的厚度优选形成得薄到具有透光性的程度。 Therefore, when the metal film 541 used as the first electrode layer, the thickness of the metal thin film is preferably formed to the extent of having a light transmissive property. 当作为第二电极层543使用具有透光性的导电层时,可以层叠具有反射性的导电层。 When the second electrode layer 543 having a light-transmitting conductive layer may be laminated with a reflective conductive layer.

[0232] 此外,也可以设置驱动电路保护用的保护电路。 [0232] Further, the driving circuit may be provided with a protection circuit protection. 保护电路优选使用非线性元件构成。 The protection circuit is preferably formed using a nonlinear element.

[0233] 如上所述,通过应用实施方式1或2所示的晶体管,可以提供具有各种各样的功能的半导体装置。 [0233] As described above, by application of the transistor shown in Embodiment 1 or 2, the semiconductor device can have a variety of functions.

[0234] 本实施方式所示的结构、方法等可以与其他实施方式所示的结构、方法等适当地组合而实施。 [0234] structures, methods, etc. described in this embodiment can be implemented in appropriate combination with the structure shown in another embodiment, and methods.

[0235] 实施方式4 [0235] Embodiment 4

[0236] 通过使用实施方式1或2所示的晶体管,可以制造具有读取对象物的信息的图像传感器功能的半导体装置。 [0236] By using the transistor described in Embodiment 1 or 2, for manufacturing a semiconductor device can read information from the object having an image sensor function.

[0237] 图7A示出具有图像传感器功能的半导体装置的一个例子。 [0237] FIG 7A illustrates an example of a semiconductor device having an image sensor function. 图7A是光电传感器的等效电路,而图7B是示出光电传感器的一部分的截面图。 7A is an equivalent circuit of a photoelectric sensor, and FIG. 7B is a sectional view illustrating a part of the photosensor.

[0238] 光电二极管602的一个电极电连接到光电二极管复位信号线658,而光电二极管602的另一个电极电连接到晶体管640的栅极。 [0238] One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode of the photodiode 602 is electrically connected to the gate of the transistor 640. 晶体管640的源极和漏极中的一个电连接到光电传感器基准信号线672,而晶体管640的源极和漏极中的另一个电连接到晶体管656的源极和漏极中的一个。 A source and a drain of the transistor 640 is electrically connected to a photosensor reference signal line 672, and the other of the source and the drain of the transistor 640 is connected to a source and a drain of the transistor 656. 晶体管656的栅极电连接到栅极信号线659,晶体管656的源极和漏极中的另一个电连接到光电传感器输出信号线671。 The gate of the transistor 656 is connected to the gate signal line 659, the source and the drain of the transistor 656 is electrically connected to a photosensor output signal line 671.

[0239] 注意,在本说明书的电路图中,为了使使用氧化物半导体层的晶体管一目了然,将使用氧化物半导体层的晶体管的符号表示为“0S”。 [0239] Note that, in this specification in the circuit diagram, so that the transistors using an oxide semiconductor layer is clear, the use of symbols oxide semiconductor layer of the transistor is represented as "0S". 在图7A中,晶体管640、656可以应用实施方式1或2所示的晶体管,是使用氧化物半导体层的晶体管。 In Figure 7A, the transistors 640,656 can be applied to the transistor shown in Embodiment 1 or Embodiment 2, a transistor using an oxide semiconductor layer. 在本实施方式中示出应用具有与实施方式1所示的晶体管320相同结构的晶体管的例子。 In the present embodiment shows an example of application of a transistor 320 having the same structure of the transistor shown in Embodiment 1 of the embodiment. 晶体管640是底栅结构的晶体管。 Transistor 640 is a transistor with a bottom gate structure.

[0240] 图7B是示出光电传感器中的光电二极管602和晶体管640的截面图,其中在具有绝缘表面的衬底601 (元件衬底)上设置有用作传感器的光电二极管602和晶体管640。 [0240] FIG. 7B is a diagram illustrating a photodiode photosensor 602 and a cross-sectional view of the transistor 640, which is provided with a photodiode used as a sensor 602 and a transistor 640 on a substrate 601 (element substrate) having an insulating surface. 通过使用粘合层608,在光电二极管602和晶体管640上设置有衬底613。 608, is provided on the photodiode 602 and the transistor 640 through the substrate 613 using an adhesive layer.

[0241] 在晶体管640上设置有绝缘层632、层间绝缘层633以及层间绝缘层634。 [0241] An insulating layer 632 is provided over the transistor 640, an interlayer insulating layer 633 and the interlayer insulating layer 634. 光电二极管602具有:形成在层间绝缘层633上的电极层641b;在电极层641b上依次层叠的第一半导体膜606a、第二半导体膜606b、第三半导体膜606c;设置在层间绝缘层634上的通过第一半导体膜至第三半导体膜与电极层641b电连接的电极层642;以及设置在与电极层641b同样的层中的与电极层642电连接的电极层641a。 The photodiode 602 has: an electrode layer 641b is formed on the interlayer insulating layer 633; ​​a first semiconductor film 606a on the electrode layer 641b are sequentially stacked, the second semiconductor film 606b, the third semiconductor film 606c; interlayer insulating layer provided on a semiconductor layer of the first electrode film through the third semiconductor film and the electrode layer 641b is electrically connected by a 634 642; and an electrode layer 641a disposed on the same layer with the electrode layer 641b is electrically connected to the electrode layer 642.

[0242] 电极层641b与形成在层间绝缘层634中的导电层643电连接,并且电极层642通过电极层641a与导电层645电连接。 Electrically conductive layer 643 [0242] electrode layer 641b formed on the interlayer insulating layer 634 is connected, and the electrode layer 642 via the conductive layer 641a and the electrode layer 645. 导电层645与晶体管640的栅电极层电连接,并且光电二极管602与晶体管640电连接。 The gate electrode layer is electrically conductive layer 645 is connected to the transistor 640, the transistor 602 and the photodiode 640 is electrically connected.

[0243] 在此,例示出一种pin型光电二极管,其中层叠用作第一半导体膜606a的具有p型导电型的半导体膜、用作第二半导体膜606b的高电阻的半导体膜(i型半导体膜)、用作第三半导体膜606c的具有η型导电型的半导体膜。 [0243] Here, for example, shows a pin photodiode, wherein the laminate film 606a is used as the first semiconductor having p-type conductivity type semiconductor film, a semiconductor film of high resistance is used as the second semiconductor film 606b (i-type semiconductor film), the third semiconductor film as a semiconductor film 606c having η-type conductivity.

[0244] 第一半导体膜606a是ρ型半导体膜,可以使用包含赋予ρ型导电型的杂质元素的非晶硅膜形成。 [0244] The first semiconductor film 606a is ρ-type semiconductor film, an amorphous silicon film containing ρ-type conductivity imparting impurity element is formed. 使用包含属于周期表中的第13族的杂质元素(例如,硼(B))的半导体材料气体通过等离子体CVD法来形成第一半导体膜606a。 Containing an impurity element belonging to Group 13 in the periodic table (e.g., boron (B)) of a semiconductor material gas to form the first semiconductor film 606a by plasma CVD. 作为半导体材料气体,可以使用硅烷(SiH4)。 As the semiconductor material gas, a silane (SiH4). 另外,可以使用3丨2!16、3丨!12(:12、3丨!1(:13、3丨(:14、3丨?4等。另外,也可以使用如下方法:在形成不包含杂质元素的非晶硅膜之后,使用扩散法或离子注入法将杂质元素导入到该非晶硅膜。优选在使用离子注入法等导入杂质元素之后进行加热等来使杂质元素扩散。在此情况下,作为形成非晶硅膜的方法,可以使用LPCVD法、化学气相沉积法或溅射法等。优选将第一半导体膜606a的厚度设定为IOnm以上且50nm以下。 Further, using 3 Shu Shu 16,3 12 2 (:!! 1 12,3 Shu (:! 13,3 Shu (?: 4 14,3 Shu et Further, a method may be used: in the formation not included after the amorphous silicon film including an impurity element, using a diffusion method or an ion implantation method of the impurity element introduced into the amorphous silicon film is preferably carried out using an ion implantation method, after heating the impurity element introduced to diffuse the impurity element. in this case, , the method of forming the amorphous silicon film, an LPCVD method, a chemical vapor deposition or sputtering, etc. the thickness of the first semiconductor film 606a is preferably set to be IOnm or more and 50nm or less.

[0245] 第二半导体膜606b是i型半导体膜(本征半导体膜),使用非晶硅膜形成。 [0245] 606b second semiconductor film is an i-type semiconductor film (intrinsic semiconductor film), amorphous silicon film. 为了形成第二半导体膜606b,通过等离子体CVD法使用半导体材料气体来形成非晶硅膜。 In order to form the second semiconductor film 606b, using a semiconductor material gas by a plasma CVD method to form an amorphous silicon film. 作为半导体材料气体,可以使用硅烷(SiH4)。 As the semiconductor material gas, a silane (SiH4). 或者,也可以使用3丨2!16、3池(:12、3丨!1(:13、3扣14或3丨?4等。也可以通过LPCVD法、化学气相沉积法、溅射法等形成第二半导体膜606b。优选将第二半导体膜606b的厚度设定为200nm以上且IOOOnm以下。 Alternatively, you can use the pool 16,3 2 3 Shu (:! 12,3 Shu 1 (:! 3 Shu 13.3 buckle 14 or the like 4 and the like may also be LPCVD method, a chemical vapor deposition method, a sputtering method?. forming a second semiconductor film 606b. the thickness of the second semiconductor film 606b is set to 200nm or more and less IOOOnm.

[0246] 第三半导体膜606c是η型半导体膜,使用包含赋予η型导电型的杂质元素的非晶娃膜形成。 [0246] The third semiconductor film 606c is η-type semiconductor film, a film containing an amorphous baby η-type conductivity imparting impurity element is formed. 使用包含属于周期表中的第15族的杂质元素(例如,磷(P))的半导体材料气体通过等离子体CVD法形成第三半导体膜606c。 Containing an impurity element belonging to Group 15 in the periodic table (e.g., phosphorus (P)) of a semiconductor material forming a third semiconductor film 606c gas by a plasma CVD method. 作为半导体材料气体,可以使用硅烷(SiH4)。 As the semiconductor material gas, a silane (SiH4). 或者, 也可以使用512116、3川2(:12、31!1(:13、31(:14或31?4等。另外,也可以使用如下方法:在形成不包含杂质元素的非晶硅膜之后,使用扩散法或离子注入法将杂质元素导入到该非晶硅膜。优选在使用离子注入法等导入杂质元素之后进行加热等来使杂质元素扩散。在此情况下,作为形成非晶硅膜的方法,可以使用LPCVD法、化学气相沉积法或溅射法等。优选将第三半导体膜606c的厚度设定为20nm以上且200nm以下。 Alternatively, use may be 512116,3 Chuan 2 (:! 12, 31 1 (: 13, 31 (?: 14 or 314, etc. Further, a method may be used: forming an amorphous silicon film containing an impurity element of not Thereafter, using a diffusion method or an ion implantation method of the impurity element introduced into the amorphous silicon film is preferably heated using an ion implantation method or the like after introducing the impurity elements diffuse the impurity element. in this case, for forming an amorphous silicon the method of the film, an LPCVD method, a chemical vapor deposition or sputtering, etc. the thickness of the third semiconductor film 606c is preferably set to 20nm or more and 200nm or less.

[0247] 此外,第一半导体膜606a、第二半导体膜606b以及第三半导体膜606c也可以不使用非晶半导体形成,而使用多晶半导体或微晶半导体(Semi Amorphous Semiconductor: SAS)形成。 [0247] Further, a first semiconductor film 606a, the second semiconductor film 606b, and a third semiconductor film 606c may not be formed using an amorphous semiconductor, and using a polycrystalline semiconductor or a microcrystalline semiconductor (Semi Amorphous Semiconductor: SAS) is formed.

[0248] 此外,由于通过光电效应生成的空穴的迀移率低于电子的迀移率,因此当将p型半导体膜侧的表面用作光接收面时,Pin型光电二极管具有较好的特性。 [0248] Further, since the holes generated by the photoelectric effect Gan shift rate is lower than the electron drift rate Gan, so that when the surface of the p-type semiconductor film is used as the light receiving surface side, Pin-type photodiode having a good characteristic. 在此示出将光电二极管602从形成有pin型光电二极管的衬底601的面接收的光转换为电信号的例子。 In the example shown here the photodiode 602 converts light has a substrate 601 pin type photodiode is formed from the surface of the electrical signal received. 此外,来自其导电型与用作光接收面的半导体膜的导电型相反的半导体膜的光是干扰光,因此,电极层优选使用具有遮光性的导电层。 In addition, the semiconductor light interference film opposite conductivity type from the conductivity type of the semiconductor film serving as a light receiving face of the light, and therefore, the electrode layer is preferably electrically conductive layer having a light shielding property. 另外,也可以将η型半导体膜一侧的表面用作光接收面。 Further, the surface may be η-type semiconductor film used as the light receiving surface side.

[0249] 晶体管640包括:用作用来防止源电极层和漏电极层的构成元素扩散到沟道的缓冲层的第一氧化物半导体层;用作沟道的第二氧化物半导体层;以及设置在用作沟道的氧化物半导体层与栅极绝缘层631之间并用作用来防止沟道与栅极绝缘层631的界面劣化的缓冲层的第三氧化物半导体层。 [0249] Transistor 640 includes: preventing a constituent element used for the source electrode layer and a drain diffusion layer of the first oxide semiconductor layer to the buffer layer channel; second oxide semiconductor layer as a channel; and provided between the oxide semiconductor layer and the gate insulating layer 631 as a channel and used to prevent the third oxide semiconductor layer, a buffer layer at the interface deterioration of the channel 631 and the gate insulating layer. 因此,晶体管640是降低有可能形成在背沟道一侧的界面态的影响并减少晶体管的光劣化(例如光负偏压温度应力劣化)的可靠性高的晶体管。 Thus, it is possible to reduce the transistor 640 is formed on the back channel side affect of reducing the interface state and deterioration of the transistor of the light (e.g., light deterioration of negative bias temperature stress) transistor with high reliability.

[0250] 通过使用绝缘材料且根据其材料使用溅射法、等离子体CVD法、旋涂法、浸渍法、喷涂法、液滴喷射法(例如喷墨法等)、印刷法(例如丝网印刷、胶版印刷)等,可以形成绝缘层632、层间绝缘层633、634。 [0250] By using an insulating material and the material used in accordance with a sputtering method, a plasma CVD method, a spin coating method, dipping method, spray coating method, a droplet discharge method (e.g., an inkjet method), a printing method (such as screen printing , flexographic printing) or the like, an interlayer insulating layer 633, 634 may be formed in the insulating layer 632.

[0251] 作为层间绝缘层633、634,优选采用用来减少表面粗糙度的用作平坦化绝缘层的绝缘层。 [0251] As the interlayer insulating layer 633, 634 is preferably used to reduce the surface roughness of the insulating layer as a planarizing insulating layer. 作为层间绝缘层633、634,例如可以使用聚酰亚胺树脂、丙烯酸树脂、苯并环丁烯类树脂、聚酰胺树脂、环氧树脂等具有耐热性的有机绝缘材料。 As the interlayer insulating layer 633 and 634, for example, a polyimide resin, an acrylic resin, benzocyclobutene-based resin, a polyamide resin, an organic insulating material such as epoxy resin having heat resistance. 此外,除了上述有机绝缘材料以外,还可以使用低介电常数材料(l〇wk材料)、硅氧烷类树脂、PSG (磷硅玻璃)、BPSG (硼磷硅玻璃)等的单层或叠层。 Further, in addition to the above-described organic insulating material, a low dielectric constant material may be used (l〇wk material), a siloxane-based resin, PSG (phosphosilicate glass), the BPSG (borophosphosilicate glass) or the like stacked monolayers Floor.

[0252] 通过检测入射到光电二极管602的光,可以读取检测对象的信息。 [0252] By detecting the light incident to the photodiode 602, you can read information object to be detected. 另外,在读取检测对象的信息时,可以使用背光灯等的光源。 Further, when reading the information object to be detected, it may be used a light source such as a backlight.

[0253] 本实施方式所示的结构、方法等可以与其他实施方式所示的结构、方法等适当地组合而实施。 [0253] structures, methods, etc. described in this embodiment can be implemented in appropriate combination with the structure shown in another embodiment, and methods.

[0254] 实施方式5 [0254] Embodiment 5

[0255] 本说明书所公开的半导体装置可以应用于各种电子设备(也包括游戏机)。 The semiconductor device [0255] disclosed in this specification may be applied to a variety of electronic appliances (including game machines). 作为电子设备,可以举出电视装置(也称为电视或电视接收机)、用于计算机等的显示器、数码相机和数码摄像机等影像拍摄装置、数码相框、移动电话机、便携式游戏机、便携式信息终端、声音再现装置、游戏机(弹珠机(pachinko machine)或投币机(slot machine)等)、框体游戏机。 Examples of electronic devices include television sets (also called TV or a television receiver), a computer used for image pickup or the like monitors, digital cameras and digital video cameras and other devices, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproducing device, a game machine (pachinko machine (pachinko machine) or a slot machine (slot machine), etc.), a game console. 图8A至图8C不出上述电子设备的具体例子。 8A to 8C no specific examples of the electronic device.

[0256] 图8A示出具有显示部的桌子9000。 [0256] FIG. 8A shows a table 9000 having a display portion. 在桌子9000中,框体9001组装有显示部9003,利用显示部9003可以显示映像。 In the table 9000, a housing 9001 and a display portion 9003 is incorporated in the display section 9003 can display images. 另外,示出利用四个桌腿部9002支撑框体9001的结构。 Further, the use of four tables illustrates the structure of a support leg portion 9002 of the housing 9001. 另外, 框体9001具有用于供应电力的电源供应线9005。 Further, the housing 9001 for supplying power to the power supply line 9005.

[0257] 可以将上述实施方式中任一个所示的半导体装置用于显示部9003,由此可以对电子设备赋予高可靠性。 [0257] The semiconductor device may be any of the above-described embodiment shown for a display portion 9003, thereby imparting high reliability electronic device.

[0258] 显示部9003具有触屏输入功能,使用者通过用手指等按触显示于桌子9000的显示部9003中的显示按钮9004可以进行屏面操作和信息输入。 Display button [0258] display portion 9003 has a touch-input function, by the user by touch with a finger or the like on the display unit 9003 of the table 9000 may be 9004 and the operation information input screen. 当桌子能够与其他家电产品进行通信的功能或能够控制其他家电产品的功能,桌子9000也可以用作控制装置,通过屏面操作控制家电产品。 When the table can be a function of communicating with the home appliances can be controlled or function of the home appliances, the table 9000 may be used as a control means for controlling operation of household appliances through the screen. 例如,通过使用实施方式3所示的具有图像传感器功能的半导体装置,可以使显示部9003具有触屏输入功能。 For example, by using the embodiment of a semiconductor device having an image sensor function is shown in Figure 3, the display portion 9003 has a touch-input function.

[0259] 另外,利用设置于框体9001的铰链也可以将显示部9003的屏面以垂直于地板的方式立起来,从而也可以将桌子9000用作电视装置。 [0259] Further, the use of a hinge member provided on the housing 9001 may be a display screen unit 9003 is perpendicular to a floor in a manner so that the table 9000 may be used as a television set. 虽然当在小房间里设置大屏面的电视装置时自由使用的空间变小,但是若在桌子内安装有显示部则可以有效地利用房间的空间。 Although the space provided when the device with a large screen television in a small room, the use of smaller free, but if the table is mounted in a display unit can effectively utilize the space of the room.

[0260] 图8B示出电视装置9100的一个例子。 [0260] FIG 8B shows an example of a television device 9100. 在电视装置9100中,框体9101组装有显示部9103,并且利用显示部9103可以显示映像。 In the television set 9100, a housing 9101 and a display portion 9103 is incorporated, and the display portion 9103 can display images. 此外,在此示出利用支架9105支撑框体9101的结构。 Further, by using the structure shown here the support frame bracket 9105 9101.

[0261] 通过利用框体9101所具备的操作开关、另外提供的遥控操作机9110,可以进行电视装置9100的控制。 [0261] By using a housing 9101 includes an operation switch or a separate remote controller 9110, may control the television apparatus 9100. 通过利用遥控操作机9110所具备的操作键9109,可以进行频道及音量的控制,并可以对在显示部9103上显示的映像进行操作。 By using a remote controller 9110 includes an operation key 9109, Channels and volume can be controlled, and can operate on an image displayed on the display unit 9103. 此外,也可以采用在遥控操作机9110中设置用于显示从该遥控操作机9110输出的信息的显示部9107的结构。 Further, the display is provided for the remote controller 9110 in the configuration of the display unit 9110 of information outputted from the remote controller 9107 may also be employed.

[0262] 图8B所示的电视装置9100具备接收机及调制解调器等。 The television device shown in [0262] FIG 8B 9100 includes a receiver, a modem and the like. 电视装置9100可以利用接收机接收一般的电视广播。 Television receiving apparatus 9100 may utilize a receiver, general television broadcasting. 再者,电视装置9100通过调制解调器连接到有线或无线方式的通信网络,也可以进行单向(从发送者到接收者)或双向(发送者和接收者之间或接收者之间等)的信息通信。 Moreover, the television set 9100 is connected to a wired or wireless communication network via a modem, it may be one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers and the like) information communication .

[0263] 可以将上述实施方式中任一个所示的半导体装置用于显示部9103、9107,而能够对电视装置及遥控操作机赋予高可靠性。 [0263] The semiconductor device may be any one of the above-described embodiment shown in the display portion 9103,9107, and high reliability can be imparted to the apparatus and the television remote controller.

[0264] 图8C示出计算机,该计算机包括主体9201、框体9202、显示部9203、键盘9204、外部连接端口9205、指向装置9206等。 [0264] FIG 8C illustrates a computer which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

[0265] 可以将上述实施方式中任一个所示的半导体装置用于显示部9203,而能够对计算机赋予高可靠性。 [0265] The semiconductor device may be any of the above-described embodiment shown for a display unit 9203, the computer can be provided with high reliability.

[0266] 图9A和图9B是能够折叠的平板终端。 [0266] FIGS. 9A and 9B are foldable tablet terminal. 图9A是平板终端打开的状态,并且平板终端包括框体9630、显示部9631a、显示部9631b、显示模式切换开关9034、电源开关9035、省电模式切换开关9036、扣环9033以及操作开关9038。 9A is a tablet terminal opened, and the terminal plate includes a housing 9630, a display unit 9631 a, 9631 b a display unit, a display mode changeover switch 9034, a power switch 9035, power switch 9036, an operation switch 9033, and 9038 buckle.

[0267] 可以将上述实施方式中任一个所示的半导体装置用于显示部9631a、9631b,而能够实现可靠性高的平板终端。 [0267] The semiconductor device may be any of the above-described embodiment shown for a display unit 9631a, 9631b, and high reliability can be realized tablet terminal.

[0268] 在显示部9631a中,可以将其一部分用作触摸屏的区域9632a,并且可以通过按触所显示的操作键9638来输入数据。 [0268] In the display unit 9631a, the area may be used as part of a touch panel 9632a, and may be 9638 by operating the key input data displayed by touch. 此外,作为一个例子,图9A示出:显示部9631a的一半区域只具有显示的功能,并且另一半区域具有触摸屏的功能,但是显示部9631a不局限于该结构。 Further, as an example, FIG. 9A shows: one half area of ​​the display unit 9631a has only a display function, and the other half region having a touch panel function, the display unit 9631a is not limited to this structure. 也可以采用显示部9631a的全部区域具有触摸屏的功能的结构。 The entire area of ​​the display portion 9631a may be used having the structural function of the touch screen. 例如,可以使显示部9631a的整个面显示键盘按钮来将其用作触摸屏,并且将显示部9631b用作显示屏面。 For example, the entire surface of the display unit 9631a of the display keyboard buttons serve as a touch screen, and the display screen as the display portion 9631b.

[0269] 此外,显示部9631b也与显示部9631a同样,可以将其一部分用作触摸屏的区域9632b。 [0269] In addition, the display unit display unit 9631a and 9631b are also the same area, which can be used as part of a touch panel 9632b. 此外,通过使用手指或触屏笔等按触触摸屏的显示键盘显示切换按钮9639的位置, 可以在显示部9631b上显示键盘按钮。 Further, by using a finger or a touch pen or the like the position of the switching button 9639 of the touch screen display by a touch keypad, keyboard buttons may be displayed on the display portion 9631b.

[0270] 此外,也可以对触摸屏的区域9632a和触摸屏的区域9632b同时进行按触输入。 [0270] It is also possible for the area of ​​the touch screen and the touch panel region 9632a 9632b simultaneously by touch input.

[0271] 另外,显示模式切换开关9034能够进行竖屏显示和横屏显示等显示方向的切换以及黑白显示和彩色显示等的切换等。 [0271] Further, the display mode changeover switch 9034 can switch and monochrome display and color display vertical and horizontal screen display displaying direction of the display screen switching. 根据内置于平板终端中的光传感器所检测的使用平板终端时的外部光量,省电模式切换开关9036可以将显示的亮度设定为最适合的亮度。 The brightness of the external light quantity when using tablet terminal plate included in the optical sensor is detected in the terminal, the power saving switch 9036 can be set to display the most suitable brightness. 平板终端除了光传感器以外还可以内置陀螺仪和加速度传感器等检测倾斜度的传感器等其他检测装置。 Tablet addition to the optical sensor may be incorporated in other inclination detecting means for detecting the acceleration sensor and a gyro sensor.

[0272] 此外,图9A示出显示部9631b的显示面积与显示部9631a的显示面积相同的例子, 但是不局限于此,一方的尺寸和另一方的尺寸可以不同,并且它们的显示质量也可以不同。 [0272] Further, FIG. 9A shows the same display area of ​​the display area of ​​the display unit and the display unit 9631a 9631b of example, but not limited to, the size and dimensions of the other party may be different, and the display quality thereof may be different. 例如显不部963 Ia和显不部963 Ib中的一方可以进彳丁比另一方更尚精细的显不。 For example, one portion 963 Ia and is not significant not significant portions 963 Ib may butoxy stimulation was still more finely than the other was not.

[0273] 图9B是平板终端合上的状态,并且平板终端包括框体9630、太阳能电池9633、充放电控制电路9634。 [0273] FIG. 9B is a state bonded on a terminal plate and the terminal plate includes a housing 9630, a solar cell 9633, the charge and discharge control circuit 9634. 此外,在图9B中,作为充放电控制电路9634的一个例子示出具有电池9635 和D⑶C转换器9636的结构。 Further, in FIG. 9B, as an example of the discharge control circuit 9634 having the structure shown D⑶C battery 9635 and converter 9636.

[0274] 此外,平板终端可以折叠,因此不使用时可以合上框体9630。 [0274] In addition, the terminal can be folded flat, so the frame 9630 can be closed when not in use. 因此,可以保护显示部9631a和显示部9631b,而可以提供一种具有良好的耐久性且从长期使用的观点来看具有良好的可靠性的平板终端。 Thus, it is possible to protect the display unit 9631a, and a display unit 9631 b, and can be provided having excellent durability and excellent reliability tablet terminal long-term use.

[0275] 此外,图9A和图9B所示的平板终端还可以具有如下功能:显示各种各样的信息(静态图像、动态图像、文字图像等);将日历、日期或时刻等显示在显示部上;对显示在显示部上的信息进行操作或编辑的触摸输入;通过各种各样的软件(程序)控制处理等。 [0275] Further, FIG. 9A tablet terminal shown in FIG. 9B and may also have the following functions: displaying a variety of information (still image, moving image, and a text image); the displayed calendar, a date or time display upper portion; displayed on a display unit or a touch input operation information edited; by various kinds of software (programs) control process and the like.

[0276] 通过利用安装在平板终端的表面上的太阳能电池9633,可以将电力供应到触摸屏、显示部或图像信号处理部等。 [0276] The solar cell mounted on the surface of the terminal plate 9633, may supply power to the touch screen, the display section or the image signal processing unit and the like. 注意,太阳能电池9633可以设置在框体9630的一面或两面,因此可以进行高效的电池9635的充电。 Note that, the solar cell 9633 may be provided at block 9630 one or both sides of the battery 9635 can be charged and therefore efficient. 另外,当作为电池9635使用锂离子电池时,有可以实现小型化等的优点。 Further, when using a lithium ion battery as the battery 9635, there are advantages such as downsizing can be achieved.

[0277] 另外,参照图9C所示的方框图对图9B所示的充放电控制电路96 34的结构和工作进行说明。 A block diagram [0277] Further, as shown with reference to FIG. 9C of FIG. 9B shown in the charge and discharge control circuit 9634 configuration and operation will be described. 图9C示出太阳能电池9633、电池9635、D⑶C转换器9636、转换器9637、开关SWl至SW3 以及显示部9631,电池9635、D⑶C转换器9636、转换器9637、开关SWl至SW3对应于图9B所示的充放电控制电路9634。 FIG 9C illustrates the solar cell 9633, the battery 9635, D⑶C converter 9636, the converter 9637, switches SWl to SW3, and a display portion 9631, a battery 9635, D⑶C converter 9636, the converter 9637, switches SWl to SW3 correspond to FIG. 9B shows charge and discharge control circuit 9634.

[0278] 首先,说明在利用外部光使太阳能电池9633发电时的工作的例子。 [0278] First, in the working example using external light when the power generation of the solar cell 9633. 使用DCDC转换器9636对太阳能电池9633所产生的电力进行升压或降压以使它成为用来对电池9635进行充电的电压。 DCDC converter 9636 using the power generated by the solar cell 9633 is raised or lowered so that it becomes a voltage for charging the battery 9635. 并且,当利用来自太阳能电池9633的电力使显示部9631工作时使开关SWl开启,并且,利用转换器9637将其升压或降压到显示部9631所需要的电压。 Then, when power from the solar cell 9633 causes the display unit 9631 when the switch SWl is turned on, and, by the converter 9637 to be raised or lowered to the voltage required for the display portion 9631. 另外,当不进行显示部9631中的显示时,可以使SWl关闭而SW2开启来对电池9635进行充电的结构。 Further, when no display portion 9631 can be made closed and SW2 open configuration SWl to charge the battery 9635.

[0279] 注意,作为发电单元的一个例子示出太阳能电池9633,但是电池9635的充电方式不局限于此,也可以使用压电元件(piezoelectric element)或热电转换元件(¾耳帖元件(Peltier element))等其他发电单元进行电池9635的充电。 [0279] Note that, as an example of the power generation unit of a photovoltaic cell 9633, but charging the battery 9635 are not limited thereto, may be used a piezoelectric element (piezoelectric element) or a thermoelectric conversion element (Peltier element ¾ (Peltier element )), and other power generation means for charging the battery 9635. 例如,也可以使用能够以无线(不接触)的方式收发电力来进行充电的不接触电力传输模块或组合其他充电方法进行充电。 For example, it may be capable of wireless (contactless) receiving power to charge non-contact power transmission module, or a combination of other charging means.

[0280] 本实施方式所示的结构、方法等可以与其他实施方式所示的结构、方法等适当地组合而实施。 [0280] structures, methods, etc. described in this embodiment can be implemented in appropriate combination with the structure shown in another embodiment, and methods.

[0281] 实施例 [0281] Example

[0282] 在本实施例中,示出在层叠有氧化物半导体层的晶体管中对各氧化物半导体层所含有的源电极层或漏电极层的构成元素的浓度进行测量的结果。 [0282] In the present embodiment, it shows the results of measuring the concentration of a constituent element of the source electrode layer or a drain electrode layer of each of the oxide semiconductor transistor layer contained in the oxide semiconductor stacked layer. 具体而言,示出作为源电极层及漏电极层形成包括铜膜的电极层并对各氧化物半导体层中的铜的浓度进行测量的结果。 Specifically, there is shown a source electrode layer and a drain electrode layer forming the electrode layer comprises a film and a copper concentration of each oxide semiconductor layer of the results of measuring the copper. 利用SSDP-SIMS (Substrate Side Depth Profile Secondary Ion Mass Spectrometry:衬底侧深度分布的二次离子质谱)测量铜浓度。 Using SSDP-SIMS (Substrate Side Depth Profile Secondary Ion Mass Spectrometry: substrate side SIMS depth profile) measured copper concentration.

[0283] 以下说明在本实施例中用于测量的晶体管的制造方法。 [0283] The following Example illustrates a method for producing a transistor for measuring in the present embodiment. 在本实施例中,制造具有与实施方式1的晶体管300相同的结构的晶体管。 In the present embodiment, having manufacturing the transistor 300 in Embodiment 1, the same transistor structure. 以下,使用与晶体管300相同的符号进行说明。 Hereinafter, using the same reference numerals transistor 300 will be described.

[0284] 首先,在衬底400上作为栅电极层402形成厚度为IOOnm的钨膜。 [0284] First, on a substrate 400 as a gate electrode layer 402 is formed of a tungsten film having a thickness of IOOnm.

[0285] 接着,作为覆盖栅电极层402的栅极绝缘层404,利用等离子体CVD法连续地形成50nm厚的氮化娃膜和200nm厚的氧氮化娃膜。 [0285] Next, the gate insulating layer 402 covering the gate electrode layer 404, successively baby nitride film 50nm thick and 200nm thick baby oxynitride film is formed by plasma CVD method.

[0286] 通过将等离子体CVD装置的处理室的压力控制为60Pa,用27.12MHz的高频电源供应150W的功率,将衬底温度设定为350°C,供应硅烷和氮的混合气体(SiH4:N2 = 5〇SCCm: 5000sCCm),来形成氮化硅膜。 [0286] By the plasma processing chamber pressure is controlled to 60Pa CVD apparatus, a power supply 150W 27.12MHz frequency power supply, and the substrate temperature was set to 350 ° C, a mixed gas of silane and nitrogen supply (of SiH4 : N2 = 5〇SCCm: 5000sCCm), to form a silicon nitride film. 另外,该等离子体CVD装置是电极面积为6000cm2的平行平板型等离子体CVD装置。 Further, the plasma CVD apparatus is a parallel plate electrode area 6000cm2 the plasma CVD apparatus. 另外,通过在相同的处理室内将压力设定为40Pa,在维持高频电源的功率及衬底温度的状态下供应硅烷和一氧化二氮的混合气体(SiH4: N2O = 2〇SCCm: 3000sccm),来形成氧氮化娃膜。 Further, by the same process chamber pressure of 40 Pa is set, supplying a mixed gas of silane and nitrous oxide at a substrate temperature and maintaining the power of the RF power supply state (SiH4: N2O = 2〇SCCm: 3000sccm) to form an oxynitride film baby.

[0287] 接着,通过利用使用In:Ga:Zn = l:l:l [原子数比]的金属氧化物靶材的溅射法,在栅极绝缘层404上形成厚度为IOnm的氧化物半导体层408b。 [0287] Next, by using using the In: Ga: Zn = l: l: l [atomic ratio] of the metal oxide target sputtering method, thickness is formed on the gate insulating layer 404 as an oxide semiconductor IOnm layer 408b. 成膜条件为如下:含氧50%的气氛下;压力为〇· 6Pa;功率为5kW;衬底温度为170°C。 Deposition conditions are as follows: 50% of an oxygen-containing atmosphere; pressure square · 6Pa; 5kW power; the substrate temperature is 170 ° C.

[0288] 然后,通过利用使用In: Ga: Zn = 3:1:2 [原子数比]的金属氧化物靶材的溅射法,在氧化物半导体层408b上形成厚度为30nm的氧化物半导体层408a。 [0288] Then, by using using the In: Ga: Zn = 3: 1: 2 [atomic ratio] of the metal oxide target sputtering method, thickness is formed on the oxide semiconductor layer 408b is 30nm of oxide semiconductor layer 408a. 成膜条件为如下:含氧50%的气氛下;压力为0 · 6Pa;功率为5kW;衬底温度为170°C。 Deposition conditions are as follows: 50% of an oxygen-containing atmosphere; the pressure is 0 · 6Pa; 5kW power; the substrate temperature is 170 ° C.

[0289] 在将氧化物半导体层408a及氧化物半导体层408b加工为岛状的氧化物半导体叠层408之后,在氮气氛下以450°C的温度对氧化物半导体叠层408进行1小时的加热处理,然后在含有氮及氧的气氛下以450°C的温度对氧化物半导体叠层408进行1小时的加热处理。 [0289] In the oxide semiconductor layer after the oxide semiconductor layers 408a and 408b are processed into the island-shaped oxide semiconductor stack 408, an oxide semiconductor for 1 hour under a nitrogen atmosphere stack 408 at a temperature of 450 ° C heat treatment at a temperature of 450 ° C and then the oxide semiconductor stack 408 for 1 hour to heat treatment in an atmosphere containing nitrogen and oxygen.

[0290] 接着,形成接触于氧化物半导体叠层408的源电极层410a及漏电极层410b。 [0290] Next, the oxide semiconductor is formed in contact with the source electrode layer stack 408 and drain electrode layers 410a 410b.

[0291] 在本实施例中,通过在栅极绝缘层404及氧化物半导体叠层408上层叠厚度为35nm 的钛膜和厚度为200nm的铜膜并对该钛膜的一部分及铜膜的一部分选择性地进行蚀刻,来形成源电极层410a及漏电极层410b。 [0291] In the present embodiment, the laminate 408 by laminating a thickness of the gate insulating layer 404 and the oxide semiconductor is a titanium film and a thickness of 35nm to 200nm and a part of the copper film and the titanium film of the copper film portion selectively etched, 410a and the drain electrode layer 410b to form a source electrode layer.

[0292] 然后,作为覆盖氧化物半导体叠层408、源电极层410a及漏电极层410b的绝缘层412,通过等离子体CVD法形成厚度为400nm的氧氮化硅膜。 [0292] Then, the oxide semiconductor laminate as the cover 408, the source electrode layer 410a and the drain electrode layer 410b of the insulating layer 412, a silicon oxynitride film having a thickness of 400nm by a plasma CVD method.

[0293] 通过将等离子体CVD装置的处理室的压力控制为200Pa,用27.12MHz的高频电源供应1500W的功率,将衬底温度设定为220°C,供应硅烷和一氧化二氮的混合气体(SiH4: N2O = 160sccm:4000sccm),来形成氧氮化娃膜。 [0293] By controlling the pressure of the plasma processing chamber is a CVD apparatus 200Pa, 27.12MHz high frequency power supply 1500W power, the substrate temperature was set to 220 ° C, mixed and Silane of nitrous oxide gas (SiH4: N2O = 160sccm: 4000sccm), baby oxynitride film is formed.

[0294] 在含有氮及氧的气氛下以300°C的温度进行1小时的加热处理,然后作为平坦化膜形成厚度为1.5μπι的丙烯酸树脂膜。 [0294] a heat treatment at a temperature of 1 hour to 300 ° C in an atmosphere containing nitrogen and oxygen, an acrylic resin film having a thickness of 1.5μπι then formed as the planarizing film. 此后,在氮气氛下以250°C的温度进行1小时的加热处理。 Thereafter, under a nitrogen atmosphere for 1 hour at a temperature of the heat treatment to 250 ° C.

[0295] 通过上述步骤制造本实施例的晶体管。 [0295] manufacturing a transistor according to the present embodiment by the above steps.

[0296] 使用SSDP-SIMS测量包含在所制造的晶体管中的氧化物半导体叠层408的铜的浓度。 [0296] using the SSDP-SIMS measurement of the concentration of copper contained in the stack of the oxide semiconductor transistor 408 manufactured. 图12示出SSDP-S頂S的测量结果。 FIG 12 shows the measurement results of the S top SSDP-S. 注意,对源电极层41 Oa与漏电极层41 Ob之间的区域(形成沟道的区域)进行测量。 Note that for the source electrode layer 41 Oa and the region between the drain electrode layer 41 Ob (channel forming region) is measured.

[0297] 由图12可知,虽然观察到源电极层410a及漏电极层410b的构成元素的铜扩散到氧化物半导体叠层408内,但是该铜没有扩散到氧化物半导体层408a外部,由此确认该铜没有到达用作晶体管的电流路径(沟道)的氧化物半导体层408b。 [0297] apparent from FIG 12, constituent elements was observed although the source electrode layer 410a and the drain electrode layer 410b of copper diffusion into the oxide semiconductor stack 408, but the copper is not diffused to the outside of the oxide semiconductor layer 408a, whereby confirmed that the copper does not reach the current path as the transistor (channel) of the oxide semiconductor layer 408b.

[0298] 如上所述,通过在氧化物半导体叠层408中的成为电流路径的氧化物半导体层408b的背沟道一侧设置氧化物半导体层408a,可以将该氧化物半导体层408a用作用来防止源电极层410a及漏电极层410b的构成元素扩散的缓冲层。 [0298] As described above, the oxide semiconductor layer through the current path in the oxide semiconductor stack 408 back channel 408b provided on the side of the oxide semiconductor layer 408a, may be used for the oxide semiconductor layer 408a the buffer layer to prevent diffusion of a constituent element of the source electrode layer 410a and the drain electrode layer 410b. 由此可知,可以防止包括氧化物半导体叠层408的晶体管的电特性变动。 It can be seen, variations can be prevented electrical characteristics of the transistor including an oxide semiconductor stack 408.

[0299] 符号说明 [0299] Description of Symbols

[0300] 300:晶体管;310:晶体管;320 :晶体管;330:晶体管;400:衬底;402 :概电极层; 403:栅极绝缘层;403a:栅极绝缘层;403b:栅极绝缘层;403c:栅极绝缘层;404:栅极绝缘层;406:栅极绝缘层;408:氧化物半导体叠层;408a:氧化物半导体层;408b:氧化物半导体层;408c:氧化物半导体层;410a:源电极层;410b:漏电极层;412:绝缘层;491:共同电位线; 492:共同电极;500:衬底;502:栅极绝缘层;502a:栅极绝缘层;502b:栅极绝缘层;502c:栅极绝缘层;504:层间绝缘层;505:彩色滤光层;506:绝缘层;507:隔壁;510 :晶体管;51 Ia:栅电极层;511b:栅电极层;512:氧化物半导体叠层;512a:氧化物半导体层;512b:氧化物半导体层;513a:导电层;513b:导电层;520:电容元件;521a:导电层;521b:导电层;522:氧化物半导体叠层;522a:氧化物半导体层;522b:氧化物半导体层;523:导电层;525:绝缘层;530: 布线层交叉部;533:导电层;540:发光元件;541:电极层;542:场致 [0300] 300: transistor; 310: transistor; 320: transistor; 330: transistor; 400: a substrate; 402: Almost electrode layer; 403: a gate insulating layer; 403a: gate insulating layer; 403b: gate insulating layer ; 403c: gate insulating layer; 404: a gate insulating layer; 406: a gate insulating layer; 408: an oxide semiconductor stack; 408a: an oxide semiconductor layer; 408b: an oxide semiconductor layer; 408c: an oxide semiconductor layer ; 410a: source electrode layer; 410b: drain electrode layer; 412: insulating layer; 491: common potential line; 492: a common electrode; 500: a substrate; 502: a gate insulating layer; 502a: gate insulating layer; 502b: a gate insulating layer; 502c: gate insulating layer; 504: interlayer insulating layer; 505: color filter layer; 506: insulating layer; 507: partition wall; 510: transistor; 51 Ia: a gate electrode layer; 511 b: gate electrode layer; 512: an oxide semiconductor stack; 512a: an oxide semiconductor layer; 512b: an oxide semiconductor layer; 513a: a conductive layer; 513b: conductive layer; 520: a capacitive element; 521a: a conductive layer; 521b: conductive layer; 522 : an oxide semiconductor stack; 522a: an oxide semiconductor layer; 522b: an oxide semiconductor layer; 523: conductive layer; 525: insulating layer; 530: crossing a wiring layer portion; 533: conductive layer; 540: a light emitting element; 541: electrode layer; 542: field 光层;543:电极层; 601:衬底;602:光电二极管;606a:半导体膜;606b:半导体膜;606c:半导体膜;608:粘合层; 613:衬底;631:栅极绝缘层;632:绝缘层;633:层间绝缘层;634:层间绝缘层;640:晶体管; 641a:电极层;641b:电极层;642:电极层;643:导电层;645:导电层;656 :晶体管;658:光电二极管复位信号线;659:栅极信号线;671:光电传感器输出信号线;672:光电传感器基准信号线;4001:衬底;4002:像素部;4003:信号线驱动电路;4004:扫描线驱动电路;4005:密封剂;4006:衬底;4008:液晶层;4010:晶体管;4011:晶体管;4013:液晶兀件;4015:连接端子电极;4016:端子电极;4018:FPC;4019:各向异性导电层;4020:栅极绝缘层;4031:电极层; 4032:绝缘层;4033:绝缘层;4034:电极层;4035:间隔物;4038:绝缘层;9000:桌子;9001:框体;9002:桌腿部;9003:显示部;9004:显示按钮;9005:电源供应线;9033:扣环;9034:开关; 9035:电源开关;9036:开关;9038:操作开关;9100:电视装置;9101:框 The light absorbing layer; 543: electrode layer; 601: a substrate; 602: photodiode; 606a: a semiconductor film; 606b: semiconductor film; 606c: a semiconductor film; 608: adhesive layer; 613: a substrate; 631: a gate insulating layer ; 632: insulating layer; 633: interlayer insulating layer; 634: interlayer insulating layer; 640: transistor; 641a: an electrode layer; 641b: an electrode layer; 642: electrode layer; 643: conductive layer; 645: conductive layer; 656 : transistor; 658: photodiode reset signal line; 659: gate signal line; 671: photo sensor output signal line; 672: photo sensor reference signal line; 4001: a substrate; 4002: a pixel portion; 4003: the signal line driver circuit ; 4004: a scanning line driving circuit; 4005: sealant; 4006: a substrate; 4008: a liquid crystal layer; 4010: a transistor; 4011: a transistor; 4013: Wu crystal member; 4015: a connection terminal electrode; 4016: terminal electrode; 4018: FPC; 4019: anisotropic conductive layer; 4020: gate insulating layer; 4031: an electrode layer; 4032: insulating layer; 4033: insulating layer; 4034: an electrode layer; 4035: spacer; 4038: insulating layer; 9000: tables ; 9001: frame body; 9002: Table leg portion; 9003: display unit; 9004: display button; 9005: power supply line; 9033: clasp; 9034: switch; 9035: power switch; 9036: switch; 9038: an operation switch ; 9100: television; 9101: frame 体;9103:显示部; 9105:支架;9107:显示部;9109:操作键;9110:遥控操作机;9201:主体;9202:框体;9203:显示部;9204:键盘;9205:外部连接端口; 9206:指向装置;9630:框体;9631:显示部;9631a:显示部;963Ib:显示部;9632a:区域;9632b:区域;9633:太阳能电池;9634:充放电控制电路; 9635:电池;9636: DCDC转换器;9637:转换器;9638:操作键;9639:按钮。 Thereof; 9103: display unit; 9105: bracket; 9107: display unit; 9109: operation key; 9110: remote controller; 9201: a body; 9202: frame body; 9203: display unit; 9204: Keyboard; 9205: external connection port ; 9206: pointing means; 9630: frame body; 9631: display unit; 9631 a: a display unit; 963Ib: a display unit; 9632 a: region; 9632 b: area; 9633: a solar cell; 9634: discharge control circuit; 9635: a battery; 9636: DCDC converter; 9637: converter; 9638: operation key; 9639: button.

[0301] 本申请基于2012年5月31日提交到日本专利局的日本专利申请No.2012-125432, 通过引用将其完整内容并入在此。 [0301] The present application is based on 2012 May 31 submitted to the Japan Patent Office Japanese Patent Application No.2012-125432, by reference the entire contents of which are hereby incorporated.

Claims (18)

  1. 1. 一种半导体装置,包括: 栅电极层; 所述栅电极层上的栅极绝缘层; 所述栅极绝缘层上的第一氧化物半导体层,该第一氧化物半导体层包含铟及镓; 所述第一氧化物半导体层上的第二氧化物半导体层,该第二氧化物半导体层包含铟及镓; 所述第二氧化物半导体层上的源电极层;以及所述第二氧化物半导体层上的漏电极层, 其中,在所述第一氧化物半导体层中所述铟的含量大于所述镓的含量, 在所述第二氧化物半导体层中所述铟的含量为所述镓的含量以下, 所述第二氧化物半导体层包含所述源电极层和所述漏电极层的构成元素中的至少一种, 并且,所述第二氧化物半导体层是结晶氧化物半导体层。 1. A semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; a first oxide semiconductor layer on the gate insulating layer, the first oxide semiconductor layer including indium and gallium; second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer including indium and gallium; a source electrode layer on the second oxide semiconductor layer; and the second a drain electrode layer over the oxide semiconductor layer, wherein the first oxide semiconductor layer indium content is greater than the content of the gallium, the second oxide semiconductor layer indium content is in the the content of the gallium, the second oxide semiconductor layer including the source electrode layer and at least one constituent element of said drain electrode layer and the second oxide semiconductor layer is a crystalline oxide The semiconductor layer.
  2. 2. 根据权利要求1所述的半导体装置, 其中,所述源电极层及所述漏电极层包含铜, 并且,所述第二氧化物半导体层中的所述源电极层和所述漏电极层的构成元素是铜。 The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer comprises copper, and wherein the second oxide layer to the source electrode and the semiconductor layer drain electrode a copper layer is a constituent element.
  3. 3. 根据权利要求1所述的半导体装置, 其中,所述栅极绝缘层包括氮化硅膜。 The semiconductor device according to claim 1, wherein said gate insulating layer comprises a silicon nitride film.
  4. 4. 根据权利要求1所述的半导体装置, 其中,所述第一氧化物半导体层及所述第二氧化物半导体层分别包含锌。 The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprises zinc respectively.
  5. 5. 根据权利要求1所述的半导体装置, 其中,所述半导体装置是显示装置。 The semiconductor device according to claim 1, wherein said semiconductor device is a display device.
  6. 6. —种半导体装置,包括: 栅电极层; 所述栅电极层上的栅极绝缘层; 所述栅极绝缘层上的第一氧化物半导体层,该第一氧化物半导体层包含铟及镓; 所述第一氧化物半导体层上的第二氧化物半导体层,该第二氧化物半导体层包含铟及镓; 所述第二氧化物半导体层上的第三氧化物半导体层,该第三氧化物半导体层包含铟及镓; 电接触于所述第二氧化物半导体层的源电极层;以及电接触于所述第二氧化物半导体层的漏电极层, 其中,在所述第一氧化物半导体层中所述铟的含量为所述镓的含量以下, 在所述第二氧化物半导体层中所述铟的含量大于所述镓的含量, 在所述第三氧化物半导体层中所述铟的含量为所述镓的含量以下, 所述第三氧化物半导体层包含所述源电极层和所述漏电极层的构成元素中的至少一种, 并且,所述第三氧化物半导体层 6. - semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; a first oxide semiconductor layer on the gate insulating layer, the first oxide semiconductor layer including indium and gallium; second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer including indium and gallium; third oxide semiconductor layer on the second oxide semiconductor layer, the second three of the oxide semiconductor layer including indium and gallium; electrical contact with the source electrode layer, the second oxide semiconductor layer; and electrical contact with the second oxide semiconductor layer is a drain electrode layer, wherein, in the first the oxide semiconductor layer indium content of the gallium content is below the second oxide semiconductor layer indium content is greater than the content of the gallium, the third oxide semiconductor layer in the the indium content of the gallium content is below the third oxide semiconductor layer including the source electrode layer and at least one constituent element of said drain electrode layer, and said third oxide The semiconductor layer 结晶氧化物半导体层。 Crystalline oxide semiconductor layer.
  7. 7. 根据权利要求6所述的半导体装置, 其中,所述源电极层是在所述第三氧化物半导体层上, 并且,所述漏电极层是在所述第三氧化物半导体层上。 The semiconductor device according to claim 6, wherein the source electrode layer on said third oxide semiconductor layer, and the drain electrode layer over the third oxide semiconductor layer.
  8. 8. 根据权利要求6所述的半导体装置, 其中,所述源电极层及所述漏电极层包含铜, 并且,所述第三氧化物半导体层中的所述源电极层和所述漏电极层的构成元素是铜。 The semiconductor device according to claim 6, wherein the source electrode layer and the drain electrode layer comprises copper, and the source electrode layer and the third oxide semiconductor layer and said drain electrode a copper layer is a constituent element.
  9. 9. 根据权利要求6所述的半导体装置, 其中,所述栅极绝缘层包括氮化硅膜。 The semiconductor device according to claim 6, wherein said gate insulating layer comprises a silicon nitride film.
  10. 10. 根据权利要求6所述的半导体装置, 其中,所述第一氧化物半导体层、所述第二氧化物半导体层及所述第三氧化物半导体层分别包含锌。 The semiconductor device according to claim 6, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprises zinc respectively.
  11. 11. 根据权利要求6所述的半导体装置, 其中,所述半导体装置是显示装置。 The semiconductor device according to claim 6, wherein said semiconductor device is a display device.
  12. 12. —种半导体装置,包括: 栅电极层; 所述栅电极层上的栅极绝缘层; 所述栅极绝缘层上的第一氧化物半导体层,该第一氧化物半导体层包含铟及镓; 所述第一氧化物半导体层上的第二氧化物半导体层,该第二氧化物半导体层包含铟及镓; 所述第二氧化物半导体层上的第三氧化物半导体层,该第三氧化物半导体层包含铟及镓; 电接触于所述第二氧化物半导体层的源电极层;以及电接触于所述第二氧化物半导体层的漏电极层, 其中,在所述第一氧化物半导体层中所述铟的含量为所述镓的含量以下, 在所述第二氧化物半导体层中所述铟的含量大于所述镓的含量, 在所述第三氧化物半导体层中所述铟的含量为所述镓的含量以下, 所述第三氧化物半导体层包含所述源电极层和所述漏电极层的构成元素中的至少一种, 所述第一氧化物半导体层包含所 12. - semiconductor device, comprising: a gate electrode layer; a gate insulating layer on the gate electrode layer; a first oxide semiconductor layer on the gate insulating layer, the first oxide semiconductor layer including indium and gallium; second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer including indium and gallium; third oxide semiconductor layer on the second oxide semiconductor layer, the second three of the oxide semiconductor layer including indium and gallium; electrical contact with the source electrode layer, the second oxide semiconductor layer; and electrical contact with the second oxide semiconductor layer is a drain electrode layer, wherein, in the first the oxide semiconductor layer indium content of the gallium content is below the second oxide semiconductor layer indium content is greater than the content of the gallium, the third oxide semiconductor layer in the the indium content of the gallium content is below the third oxide semiconductor layer including the source electrode layer and the drain electrode layer of at least one constituent element in the first oxide semiconductor layer containing the 栅极绝缘层的构成元素中的至少一种, 并且,所述第三氧化物半导体层是结晶氧化物半导体层。 A constituent element of the gate insulating layer of at least one, and the third oxide semiconductor layer is a crystalline oxide semiconductor layer.
  13. 13. 根据权利要求12所述的半导体装置, 其中,所述源电极层是在所述第三氧化物半导体层上, 并且,所述漏电极层是在所述第三氧化物半导体层上。 The semiconductor device according to claim 12, wherein the source electrode layer on said third oxide semiconductor layer, and the drain electrode layer over the third oxide semiconductor layer.
  14. 14. 根据权利要求12所述的半导体装置, 其中,所述源电极层及所述漏电极层包含铜, 并且,所述第三氧化物半导体层中的所述源电极层和所述漏电极层的构成元素是铜。 14. The semiconductor device according to claim 12, wherein the source electrode layer and the drain electrode layer comprises copper, and wherein the third oxide semiconductor layer and the source electrode of the drain electrode layer a copper layer is a constituent element.
  15. 15. 根据权利要求12所述的半导体装置, 其中,所述栅极绝缘层包括氮化硅膜, 并且,所述第一氧化物半导体层中的栅极绝缘层的构成元素是硅。 The semiconductor device according to claim 12, wherein said gate insulating layer comprises a silicon nitride film, and the constituent element of the first oxide semiconductor layer, a gate insulating layer is silicon.
  16. 16. 根据权利要求12所述的半导体装置, 其中,所述第一氧化物半导体层、所述第二氧化物半导体层及所述第三氧化物半导体层分别包含锌。 The semiconductor device according to claim 12, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprises zinc respectively.
  17. 17. 根据权利要求12所述的半导体装置, 其中,所述半导体装置是显示装置。 The semiconductor device according to claim 12, wherein said semiconductor device is a display device.
  18. 18. 根据权利要求1、6和12任一项所述的半导体装置, 其中,所述栅极绝缘层包括氧化物绝缘层,所述氧化物绝缘层包含超过化学计量组成的氧。 1,6 and 18. The semiconductor device according to any one of claim 12, wherein said gate insulating layer comprises an oxide insulating layer, the oxide insulating layer comprises a composition of a stoichiometric excess of oxygen.
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