DE102013022449B3 - Semiconductor device and electronic device - Google Patents

Semiconductor device and electronic device

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Publication number
DE102013022449B3
DE102013022449B3 DE102013022449.7A DE102013022449A DE102013022449B3 DE 102013022449 B3 DE102013022449 B3 DE 102013022449B3 DE 102013022449 A DE102013022449 A DE 102013022449A DE 102013022449 B3 DE102013022449 B3 DE 102013022449B3
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Prior art keywords
transistor
power source
potential
gate
circuit
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DE102013022449.7A
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German (de)
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Shunpei Yamazaki
Jun Koyama
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2012109475 priority
Priority to JP2012125706 priority
Priority to JP2012-125706 priority
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30Modifications for providing a predetermined threshold before switching
    • H03K17/302Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K2217/00Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018Special modifications or use of the back gate voltage of a FET
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K2217/00Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036Means reducing energy consumption

Abstract

A semiconductor device, comprising:
a first circuit including a first transistor;
a second transistor;
a third transistor;
a second circuit configured to generate a first potential; and
a third circuit configured to generate a second potential
wherein a back gate of the first transistor is configured to be set in an open state by turning off the second transistor after the first potential, which is a negative potential, is supplied to the back gate of the first transistor through the second transistor, and
wherein the back gate of the first transistor is configured to be set in an open state by turning off the third transistor after the second potential, which is a positive potential, is supplied to the back gate of the first transistor through the third transistor;
wherein supply of power source voltage to the second circuit is configured to be stopped after the second transistor turns off, and
wherein a supply of power source voltage to the third circuit is configured to be stopped after the third transistor turns off.

Description

  • Background of the invention
  • Field of the invention
  • The present invention relates to a semiconductor device. In addition, the present invention relates to an electronic device including the semiconductor device.
  • Description of the Prior Art
  • In recent years, development of semiconductor devices including transistors has been promoted.
  • In the above semiconductor devices, the control of the threshold voltage of the transistors is important. For example, a "normally on" transistor causes several problems: it is likely to cause interference during operation, and out of service, power consumption is increased.
  • As a method of controlling the threshold voltage of a transistor, a method of shifting the threshold voltage of a transistor by supplying a power source potential to a back gate of the transistor is known (see Patent Document 1).
  • [Reference]
  • [Patent Document 1] Japanese Patent Laid-Open Publication JP 2006 - 165 808 A provides a differential amplification circuit capable of operating at low voltage.
  • US Pat. No. 7,205,825 B2 deals with the emulation of a long delay chain through a ring oscillator with potential-free body-bound devices. After a ring oscillator has been turned on, become transistors M3 . M4 . M5 and M6 shut off, leaving transistors M1 and M2 as potential-free body devices can switch.
  • US 6,351,176 B1 deals with the timing of a body potential to achieve an improved performance of an integrated MOS circuit. An embodiment includes a circuit portion and a body potential adjustment portion. A body potential of a p-channel transistor in the circuit is pulled by a p-channel tuning transistor to a low pulse voltage VSS.
  • DE 698 20 825 T2 provides an oscillator circuit, an electronic circuit, a semiconductor device, an electronic device and a clock that can be operated with low power consumption.
  • US Pat. No. 6,462,723 B1 provides a semiconductor device and a method of manufacturing the same.
  • US 2010/0 013 541 A1 provides a method and apparatus for a dynamically self-priming switch.
  • US 2011/0 278 564 A1 provides a semiconductor device. A semiconductor device is proposed in which power consumption by a complementary logic circuit capable of reducing a through current can be suppressed.
  • Summary of the invention
  • Nevertheless, the conventional method for controlling the threshold voltage of a transistor has a problem with a large power consumption.
  • For example, in a semiconductor device disclosed in Patent Document 1, it is necessary to constantly supply a power source potential to a back gate of a transistor in operation. As a result, for example, a power source circuit for generating the power source potential must always be kept in operation; thus, it is difficult to reduce the power consumption.
  • In view of the above problem, an object of one embodiment of the present invention is to reduce power consumption.
  • The invention provides a semiconductor device according to claim 1. Advantageous developments are provided by the dependent claims.
  • In one embodiment of the present invention, a power source potential is temporarily supplied to a backgate of a transistor from a power source circuit using a power supply control switch. Here, the power supply control switch is formed, for example, using a control transistor with a small current in off-state current.
  • By means of the power supply control switch, the potential of the return gate can be held for a certain period while the power supply control switch is turned off, that is, when the back gate of the transistor is in a floating state. Therefore, it is unnecessary to turn on the back gate of the transistor To constantly supply power source potential from the power source circuit; thereby, the supply of a power source voltage to the power source circuit can be stopped when it is not needed.
  • In one embodiment of the present invention, the supply of a power source potential from a power source circuit to a backgate of a transistor is temporarily stopped in this manner, so that the power consumption can be reduced.
  • A semiconductor device embodying the present invention includes: a power source circuit for generating a power source potential and a power supply control switch for controlling the supply of the power source potential from the power source circuit to a backgate of a transistor. In the semiconductor device, the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by turning on or off in accordance with a pulse signal output to a control terminal of the control transistor.
  • Further, in one embodiment of the present invention, the power source potential supplied to the backgate of the transistor is between bivalent (binary) power source potentials, e.g. B., switched between a negative power source potential and a positive power source potential; whereby the current is reduced in the off state when the transistor is turned off, and the current is increased in the on state when the transistor is turned on. It should be noted that the power source potential supplied to the backgate of the transistor may be switched not only between the bivalent (binary) power source potentials but also between trivalent or polyvalent power source potentials.
  • A semiconductor device as another embodiment of the present invention includes: a first power source circuit for generating a first power source potential, a first power supply control switch for controlling the supply of the first power source potential from the first power source circuit to a backgate of a transistor, a first power source switch for controlling the supply of a first power source voltage the first power source circuit, a second power source circuit for generating a second power source potential, a second power supply control switch for controlling the supply of the second power source potential from the second power source circuit to the back gate of the transistor, and a second power source switch for controlling the supply of a second power source voltage to the second power source circuit. In the semiconductor device, the first power supply control switch includes a first control transistor for controlling conduction between the first power source circuit and the back gate of the transistor by turning on or off according to a first pulse signal output to a control terminal of the first control transistor. The second power supply control switch includes a second control transistor for controlling conduction between the second power source circuit and the backgate of the transistor by turning on or off in accordance with a second pulse signal output to a control terminal of the second control transistor. The currents in the off state per micron of the channel width of the first control transistor and the second control transistor are less than or equal to 100 zA. When one of the first pulse signal and the second pulse signal is at a high level, the other of the first pulse signal and the second pulse signal is at a low level. When the first power source switch is turned off, the first control transistor is turned off. When the second power source switch is turned off, the second control transistor is turned off.
  • Another embodiment of the present invention is an electronic device incorporating one of the above semiconductor devices.
  • According to an embodiment of the present invention, the supply of a power source potential to a back gate of a transistor can be temporarily stopped even in the case where the threshold voltage of the transistor is controlled, so that the power consumption can be reduced.
  • list of figures
    • 1 shows an example of a semiconductor device.
    • 2 shows a current of a transistor in off-state (off-state current).
    • 3A and 3B show examples of a method for driving a semiconductor device.
    • 4A-1 . 4A-2 . 4B-1 and 4B-2 show examples of a semiconductor device.
    • 5 shows an example of the behavior of a function circuit.
    • 6 shows an example of a semiconductor device.
    • 7 shows an example of a semiconductor device.
    • 8th shows an example of a method for driving a semiconductor device.
    • 9 shows an example of a method for driving a semiconductor device.
    • 10 shows an example of a method for driving a semiconductor device.
    • 11A to 11D show examples of a functional circuit.
    • 12A and 12B show examples of a power source circuit.
    • 13A and 13B show examples of a power source circuit.
    • 14 shows an example of a power source circuit.
    • 15A and 15B show examples of a power source circuit.
    • 16A and 16B show examples of a power source circuit.
    • 17 shows an example of a semiconductor device.
    • 18 shows an example of a gate driver.
    • 19A and 19B show an example of a flip-flop.
    • 20A-1 . 20A-2 . 20B-1 and 20B-2 show examples of inverters.
    • 21 FIG. 11 is a timing chart showing an example of a method of driving a semiconductor device. FIG.
    • 22A and 22B show an example of a pixel circuit.
    • 23 shows a structural example of a semiconductor device.
    • 24 shows an example of a semiconductor device.
    • 25 shows an example of a memory cell.
    • 26 shows an example of a memory cell.
    • 27A and 27B show an example of a semiconductor device.
    • 28A and 28B show structural examples of a semiconductor device.
    • 29A to 29F show examples of an electronic device.
  • Detailed description of the invention
  • Embodiments of the present invention will be described below. It should be understood that one of ordinary skill in the art can easily understand that details of the embodiments may be changed in various ways without departing from the spirit and scope of the present invention. Accordingly, for example, the present invention should not be limited to the description of the following embodiments.
  • It should be noted that the contents of various embodiments may be combined with each other as appropriate. In addition, the contents of the embodiments may be interchanged as appropriate.
  • Furthermore, the ordinal numbers such. "First" and "second" are used to avoid confusion between components and do not limit the number of each component.
  • [Embodiment 1]
  • In this embodiment, an example of a semiconductor device according to an embodiment of the present invention will be described.
  • It should be noted that in this specification, a semiconductor device refers to all devices that can operate by applying semiconductor characteristics, and that integrated circuits such. As sensors or large-scale integration (LSI), display devices and the like are all semiconductor devices.
  • A structural example of a semiconductor device will be described with reference to FIG 1 described.
  • A semiconductor device in 1 includes a power source circuit 101 and a power supply control switch (also referred to as PSW) 102.
  • Further, a transistor 110 in 1 a transistor in which a back gate potential (also referred to as VBG) can be controlled. The transistor 110 is for example in a functional circuit 100 provided in the semiconductor device.
  • As the functional circuit 100 Different circuits with specific functions can be used. For example, the functional circuit comprises 100 a semiconductor device or the like including a gate driver, a source driver, an LSI, a sensor or a pixel portion.
  • The power source circuit 101 in 1 has a function of generating a power source potential Vx based on an input power source voltage. It should be noted that the power source voltage is a potential difference between a power source potential VDD and a power source potential VSS. There will also be a switch 104 turned off, so that the supply of a power source voltage to the power source circuit 101 is stopped. It should be noted that the example does not refer to the structure in 1 is limited, and that the supply of the power source potential VSS to the power source circuit 101 from the switch 104 can be controlled.
  • The power source circuit 101 includes, for example, a charge pump or an inverting converter. Alternatively, the power source circuit 101 include a Cuk-type transducer.
  • The power supply control switch 102 has a function of controlling the supply of the power source potential from the power source circuit 101 to the backgate of the transistor 110 ,
  • The power supply control switch 102 includes a control transistor 120 , The control transistor 120 has a function of controlling the line between the power source circuit 101 and the backgate of the transistor 110 in that it is turned on or off according to a pulse signal which is delivered to a control terminal. In 1 is a gate of the transistor as an example 120 represented as the control port. Furthermore, the example is not based on the structure in 1 limited, and the power supply control switch 102 For example, using an analog switch or the like that controls the control transistor 120 includes, be trained.
  • Here, for example, the pulse signal from a pulse output circuit 105 in the gate of the control transistor 120 entered. A distance between pulses of the pulse signal is preferably 1 second or longer, more preferably 30 seconds or longer, still more preferably 1 minute or longer. For example, the distance between the pulses of the pulse signal coming from the pulse output circuit 105 is output, be controlled by a control signal or the like. It should be noted that the distance between the pulses is not necessarily constant. Alternatively, the pulse output circuit 105 be contained in the semiconductor device.
  • A transistor with a small off-state current can be considered the control transistor 120 be used. It should be noted that the value of the reverse current of the control transistor 120 preferably smaller than the value of the reverse current of the transistor 110 is. For example, when the ratio between the channel length (L) and the channel width (W) (also referred to as L / W ratio) of the control transistor 120 greater than the L / W ratio of the transistor 110 is made, the value of the reverse current of the control transistor 120 less than the value of the reverse current of the transistor 110 be made.
  • The transistor having a small off-state current may be, for example, a transistor having a channel formation region including an oxide semiconductor having a band gap larger than silicon and being substantially type-I. Here, the carrier density of the oxide semiconductor is preferably lower than 1 × 10 14 atoms / cm 3 , more preferably lower than 1 × 10 12 atoms / cm 3 , even more preferably lower than 1 × 10 11 atoms / cm 3 . The transistor containing the oxide semiconductor can be made such that, for example, impurities such as. As hydrogen or water can be reduced as much as possible and oxygen vacancies are reduced by the supply of oxygen as much as possible. Here, the amount of hydrogen regarded as donor impurity in the channel formation region is preferably less than or equal to 1 × 10 19 atoms / cm 3 , more preferably less than or equal to 1 × 10 18 atoms / cm 3 .
  • For example, an In-based metal oxide, a Zn-based metal oxide, an In-Zn-based metal oxide, or an In-Ga-Zn-based metal oxide may be used as the oxide semiconductor. Alternatively, a metal oxide containing another metal element in place of a part or all of Ga in the In-Ga-Zn based metal oxide may be used.
  • Alternatively, it is preferable to use as another metal element one or more of titanium, zirconium, hafnium, germanium, tin, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and to use lutetium. These metal elements serve as a stabilizer. It should be noted that the amount of such a metal element added is determined so that the metal oxide can serve as a semiconductor.
  • A structure of an oxide semiconductor layer will be described below.
  • An oxide semiconductor layer is roughly divided into a single-crystal oxide semiconductor layer and a non-single-crystal oxide semiconductor layer. The non-single crystal oxide semiconductor layer includes one of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a crystalline oxide semiconductor layer with c-axis aligned crystalline oxide semiconductor (CAAC-OS) layer, and the like.
  • The amorphous oxide semiconductor layer has a disordered atomic arrangement and no crystalline component. A typical example of this is an oxide semiconductor layer in which even in a microscopic area no crystal area exists and the whole layer is amorphous.
  • The microcrystalline oxide semiconductor layer includes, for example, a microcrystal (also referred to as a nanocrystal) having a size larger than or equal to 1 nm and smaller than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a higher degree of atomic order than the amorphous oxide semiconductor layer. Accordingly, the density of the defect states of the microcrystalline oxide semiconductor layer is lower than that of the amorphous oxide semiconductor layer.
  • The CAAC-OS layer is one of oxide semiconductor layers containing a plurality of crystal regions, and most of the crystal regions fit into a cube having an edge length of less than 100 nm. Therefore, there is a case where a crystal region is included in the CAAC. OS layer fits into a cube with an edge length of less than 10 nm, less than 5 nm or less than 3 nm. The density of the defect states of the CAAC-OS layer is lower than that of the microcrystalline oxide semiconductor layer. The CAAC-OS layer will be described in detail below.
  • In a transmission electron microscope (TEM) image of the CAAC-OS layer, a boundary between crystal regions, i. H. a grain boundary, not clearly observed. As a result, it is unlikely that the electron mobility due to the grain boundary is reduced in the CAAC-OS layer.
  • According to the TEM image of the CAAC-OS layer, which is observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are in a layered manner in the Crystal areas arranged. Each metal atomic layer has a shape that is in the form of a surface over which the CAAC-OS layer is formed (a surface over which the CAAC-OS layer is formed, hereinafter referred to as a formation surface), or the shape of a top surface of the CAAC-OS layer, and each metal atom layer is disposed in parallel with the formation surface or the upwardly facing surface of the CAAC-OS layer.
  • On the other hand, according to the TEM image of the CAAC-OS layer observed in a direction substantially perpendicular to the sample surface (area TEM image, plan TEM image), metal atoms are in a triangular or hexagonal configuration in FIG the crystal areas arranged. However, there is no regularity of arrangement of metal atoms between different crystal regions.
  • From the results of the cross-sectional TEM image and the area TEM image, alignment is found in the crystal areas in the CAAC-OS layer.
  • In this specification, a term "parallel" means that the angle formed between two straight lines is greater than or equal to -10 ° and less than or equal to 10 °, and therefore, the expression also includes the case where the Angle greater than or equal to -5 ° and less than or equal to 5 °. In addition, a term "perpendicular" means that the angle formed between two straight lines is greater than or equal to 80 ° and less than or equal to 100 °, and therefore, the expression also includes the case where the angle is larger than or equal to 85 ° and less than or equal to 95 °.
  • In this specification, the trigonal and rhombohedral crystal systems are contained in the hexagonal crystal system.
  • A CAAC-OS layer is subjected to structural analysis by means of an X-ray diffraction (XRD) device. For example, when the CAAC-OS layer containing an InGaZnO 4 crystal is analyzed by an out-of-plane method, a peak often appears at a diffraction angle (2θ) of about 31 °. This peak is from the (009) face of the InGaZnO 4 crystal, indicating that crystals in the CAAC-OS layer have alignment with the c-axis and that the c-axes are aligned in one direction, which is substantially perpendicular to the formation surface or the upwardly facing surface of the CAAC-OS layer.
  • On the other hand, when the CAAC-OS layer is analyzed by an in-plane method in which an X-ray enters a sample in a direction perpendicular to the c-axis, it often appears as a peak at 2θ of about 56 °. This peak comes from the (110) face of the InGaZnO 4 crystal. Here, the analysis (Φ-scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (Φ-axis), where 2θ is set at about 56 °. In the case where the sample comprises a single crystal oxide semiconductor layer InGaZnO is 4 , six peaks appear. The six peaks are from crystal facets that are equal to the (110) face. On the other hand, in the case of a CAAC-OS layer, a peak is not clearly observed even when a φ-scan is performed, with 2θ being set at about 56 °.
  • According to the above results, in the CAAC-OS layer aligned with the c-axis, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of an upwardly facing surface, while the directions of a-axes and b-axes are different between crystal regions. Each metal atomic layer observed to be in a layered manner in the cross-sectional TEM image, therefore, corresponds to an area parallel to the a-b surface of the crystal.
  • It should be noted that the crystal region is formed simultaneously with a deposition of the CAAC-OS layer or by a crystallization treatment such as. B. a heat treatment is formed. As described above, the c-axis of the crystal is oriented in a direction parallel to a normal vector of a formation surface or a normal vector of an upward surface. Therefore, for example, in the case where a shape of the CAAC-OS layer is changed by etching or the like, the c-axis may not always be parallel to a normal vector of a formation surface or a normal vector of an upward facing surface of the CAAC-OS layer be.
  • In addition, the degree of crystallinity in the CAAC-OS layer is not necessarily uniform. For example, in the case where crystal growth for forming the CAAC-OS layer starts from the vicinity of the upwardly facing surface of the layer, the degree of crystallinity in the vicinity of the upwardly facing surface may be higher than that in FIG near the training surface. Further, when an impurity is added to the CAAC-OS layer, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS layer varies depending on the location.
  • It should be noted that when the CAAC-OS layer containing an InGaZnO 4 crystal is analyzed by an out-of-plane method, a peak at 2θ of about 36 ° is also added to the peak at 2θ of about 31 ° can be observed. The peak at 2θ of about 36 ° comes from the (311) face of a ZnGa 2 O 4 crystal; such a peak indicates that a ZnGa 2 O 4 crystal is contained in a part of the CAAC-OS layer containing the InGaZnO 4 crystal. It is preferable that in the CAAC-OS layer, a peak appears at 2θ of about 31 ° and no peak appears at 2θ of about 36 °.
  • In a transistor using the CAAC-OS layer, the change in electrical characteristics due to irradiation with visible light or UV light is small. As a result, the transistor has high reliability.
  • It should be noted that an oxide semiconductor layer may be a stacked layer including, for example, two or more layers of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and a CAAC-OS layer.
  • Since the transistor including the oxide semiconductor has a larger bandgap, a leakage current generated by thermal excitation is small, and the number of carriers in a semiconductor layer is very small; Thus, the current in the off state (off-state current) can be reduced. For example, the current in the off state per micron of channel width of the transistor at room temperature (25 ° C) is less than or equal to 1 x 10 -19 A (100 zA), preferably less than or equal to 1 x 10 -22 A (100 yA). , It is preferable that the power in the off state of the transistor is as small as possible; the smallest value of the current in the off state of the transistor is estimated to be approximately 1 × 10 -30 A / μm.
  • As the transistor having a small current in the off state, a transistor whose channel forming region is formed by using an oxide semiconductor containing indium, zinc and gallium is used, and the value of its current in the off state will be described here.
  • Since the value of the current in the off state of the transistor is very small, it is necessary for measuring the current in the off state to produce a comparatively large transistor and to estimate an off-state current that is actually flowing.
  • As an example shows 2 for a transistor having a channel width W of 1 m (1,000, 000 μm) and a channel length L of 3 μm, an Arrhenius plot of the value of the current in the off state, based on the value of the off-current current per micron of the channel width W is estimated, with the temperature being changed to 150 ° C, 125 ° C and 85 ° C.
  • As in 2 is shown, for example, the current in the off state of the transistor per micron of channel width W at 27 ° C is less than or equal to 1 × 10 -25 A. It will off 2 found that the transistor whose channel formation region is formed using the oxide semiconductor containing indium, zinc and gallium has a very small current in the off state.
  • The above is the description of the power supply control switch 102 ,
  • Next, an example of a method of driving the semiconductor device shown in FIG 1 shown is based on 3A and 3B described. As an example, here are the control transistor 120 and the transistor 110 N-channel transistors, and the potential, the back gate of the transistor 110 is supplied, is a negative power source potential -Vx.
  • First, the control transistor 120 as in 3A shown turned on. For example, when a pulse of a pulse signal from the pulse output circuit 105 in the gate of the control transistor 120 is input, the gate has a high potential (H), so that the control transistor 120 is turned on. It should be noted that by turning on the switch 104 before turning on the control transistor 120 a power source voltage of the power source circuit 101 is supplied and the power source circuit 101 is turned on in advance.
  • When the control transistor 120 is turned on, for example, a current flows like an arrow in 3A indicates the negative power source potential -Vx is from the power source circuit 101 the backgate of the transistor 110 and the level of the potential of the return gate (VBG) becomes equal to the level of the negative power source potential -Vx.
  • At this time, the threshold voltage of the transistor shifts 110 in a positive direction.
  • Here is a change in the threshold voltage of the transistor 110 due to the potential of the back gate based on 4A-1 . 4A-2 . 4B-1 and 4B-2 described.
  • 4A-1 shows the case where the back gate potential of the transistor 110 a reference potential V0 is and 4A-2 shows the threshold voltage of the transistor 110 in the case where its back gate potential is the reference potential V0 is. It should be noted that the reference potential V0 For example, 0 V, a source potential or a ground potential may be.
  • 4B-1 shows the case where the back gate potential of the transistor 110 a negative power source potential is -Vg, and 4B-2 shows the threshold voltage of the transistor 110 in the case where its back gate potential is the negative power source potential -Vg.
  • For example, the threshold voltage of an N-channel transistor whose channel formation region includes an oxide semiconductor shifts in the positive direction because, if its backgate has a negative potential, the width of a depletion layer increases, so that a current through the body volume is unlikely to increase flows. When the backgate potential of the transistor 110 the reference potential V0 is, the threshold voltage is as in 4A-2 shown. On the other hand, when the back gate potential of the transistor is the negative power source potential -Vg, the threshold voltage shifts in the positive direction as in FIG 4B-2 shown. The backgate potential of the transistor 110 is controlled in this way, whereby, for example, a normally-on (normally-on) transistor can be changed to a normally-off transistor.
  • Further, the control transistor 120 as in 3B shown off. For example, when inputting a pulse signal from the pulse output circuit 105 in the control transistor 120 is stopped has the gate of the control transistor 120 a low potential (L), so that the control transistor 120 is turned off. It should be noted that after turning off the control transistor 120 the desk 104 is switched off, whereby the supply of a power source voltage to the power source circuit 101 is stopped, so that the power source circuit 101 is turned off.
  • When the control transistor 120 is off, is the power source circuit 101 turned off, and the supply of a power source potential from the power source circuit 101 to the backgate of the transistor 110 is stopped. Furthermore, the backgate of the transistor is located 110 in an open state (floating state), and the potential of the return gate ( VBG ) is held.
  • Further, a power source potential may again be the back gate of the transistor 110 be supplied (also as recharging (recharging) of the back gate of the transistor 110 designated), that the control transistor 120 is turned on when the power source circuit 101 as in 3A is shown turned on. In the semiconductor device disclosed in 1 is shown, the control transistor 120 always on when a pulse of the pulse signal from the Pulse output circuit 105 is entered. This allows the backgate of the transistor 110 be reloaded every time when the control transistor 120 is turned on.
  • A change of a potential in the case where the back gate of the transistor 110 is recharged in the time chart in 5 shown.
  • In 5 becomes the gate potential of the control transistor 120 (The potential is also called VG 120 designated) to a high potential (H) in a period of time T1 , At this time, the control transistor 120 turned on, and the back gate potential of the transistor 110 (The potential is also called VBG 110 ) becomes -Vx.
  • In a time span T2 becomes VG 120 to a low potential (L), and the control transistor 120 is switched off. Here is the backgate of the transistor 110 in an open state; however, in some cases the potential of the return gate is gradually increased to more than -Vx.
  • Nevertheless, the gate potential of the control transistor becomes 120 (The potential is also called VG 120 again) to a high potential (H) in a period of time T3 , whereby the control transistor 120 is turned on, and the back gate potential of the transistor 110 (The potential is also called VBG 110 ) can be returned to -Vx (the backgate can be recharged).
  • As in 5 is shown, the back gate of the transistor 110 recharged, whereby, for example, the back gate potential of the transistor 110 can be kept at a negative power source potential. In addition, the back gate of the transistor 110 reloaded temporarily; therefore it is not necessary to use the power source circuit 101 to operate constantly; Thus, the power consumption can be reduced.
  • The above is the description of the example of the method for driving the semiconductor device 1 ,
  • As above based on 1 . 2 . 3A . 3B . 4A-1 . 4A-2 . 4B-1 . 4B-2 and 5 has been described, in the example of the semiconductor device, the supply of a power source potential from a power source circuit to a backgate of a transistor is controlled by a power supply control switch. With the above structure, the back gate potential can be maintained when the power supply control switch is turned off, and the supply of a power source voltage to the power source circuit can be temporarily stopped; Thus, the power consumption can be reduced.
  • It should be noted that in the semiconductor device, the potential corresponding to the back gate of the transistor 110 is fed, can be switched between a variety of potentials. An example of a structure in which the back gate of the transistor 110 supplied potential is switched by means of 6 described.
  • A semiconductor device according to this embodiment of the invention in FIG 6 includes power source circuits 101_1 and 101_2 , Power supply control switch (also called PSW) 102_1 and 102_2 and power source switch 104_1 and 104_2 , It should be noted that the number of power source circuits does not match that in FIG 6 is limited, and
    in that the power supply control switches and the power source switches may be provided according to the number of the power source circuits.
  • Furthermore, in 6 the transistor 110 a transistor in which a backgate potential (also called VBG can be controlled). The transistor 110 is for example in the function circuit 100 provided in the semiconductor device.
  • The power source circuit 101_1 has a function of generating a power source potential Vx1 based on an input first power source voltage. It should be noted that the first power source voltage corresponds to a potential difference between a power source potential VDD1 and a power source potential VSS. In addition, the power source switch becomes 104_1 turned off, allowing the supply of the power source potential VDD1 to the power source circuit 101_1 can be stopped and thus the supply of the first power source voltage can be stopped. The power source switch 104_1 has a function of controlling the supply of the first power source voltage to the power source circuit 101_1 , It should be noted that an embodiment of the present invention is not limited to the structure in FIG 6 is limited, and the supply of the power source potential VSS to the power source circuit 101_1 can from the switch 104_1 can be controlled.
  • The power source circuit 101_2 has a function of generating a power source potential Vx2 based on an input second power source voltage. It should be noted that the second power source voltage corresponds to a potential difference between a power source potential VDD2 and a power source potential VSS. In addition, the Power source switch 104_2 turned off, allowing the supply of the power source potential VDD2 to the power source circuit 101_2 can be stopped and thus the supply of the second power source voltage can be stopped. The power source switch 104_2 has a function of controlling the supply of the second power source voltage to the power source circuit 101_2 , It should be noted that an embodiment of the present invention is not limited to the structure in FIG 6 is limited, and the supply of the power source potential VSS to the power source circuit 101_2 from the switch 104 2 can be controlled. The heights of the first power source voltage and the second power source voltage may be different.
  • It should be noted that in the case of using a clock signal C_CLK for the power source circuit 101 the power source circuit 101 can be turned off such that a clock supply control switch 106 for controlling the supply of the clock signal C_CLK to the power source circuit 101 is provided and the supply of the clock signal C_CLK is stopped. For example, in the case of using the clock signals C_CLK for the power source circuits 101_1 and 101_2 the power source circuit 101_1 or the power source circuit 101_2 can be turned off so that as in 7 shown a clock supply control switch 106_1 for controlling the supply of the clock signal C_CLK to the power source circuit 101_1 and a clock supply control switch 106_2 for controlling the supply of the clock signal C_CLK to the power source circuit 101_2 are provided and the supply of the clock signal C_CLK to the power source circuit 101_1 or 101_2 is stopped.
  • In 6 has the power supply control switch 102_1 a function for controlling the supply of the power source potential from the power source circuit 101_1 to the backgate of the transistor 110 , and the power supply control switch 102_2 has a function of controlling the supply of the power source potential from the power source circuit 101_2 to the backgate of the transistor 110 ,
  • The power supply control switch 102_1 includes a control transistor 120_1 , and the power supply control switch 102_2 includes a control transistor 120_2 , The control transistor 120_1 has a function of controlling the line between the power source circuit 101_1 and the backgate of the transistor 110 by being turned on or off in accordance with a first pulse signal output to a control terminal and the control transistor 120_2 has a function of controlling the line between the power source circuit 101_2 and the backgate of the transistor 110 by being turned on or off in accordance with a second pulse signal output to a control terminal. In 6 are as an example gates of the transistors 120_1 and 120_2 represented as the control terminals. Furthermore, an embodiment of the present invention is not based on the structure in FIG 6 limited, and the power supply control switch 102_1 For example, using an analog switch or the like, the control transistor 120_1 includes, be formed, and the power supply control switch 102_2 For example, using an analog switch or the like, the control transistor 120_2 includes, be trained.
  • Here, the first pulse signal from a pulse output circuit 105_1 in the control transistor 120_1 is input, and the second pulse signal is from a pulse output circuit 105_2 in the control transistor 120_2 entered. It should be noted that a pulse of the first pulse signal and a pulse of the second pulse signal preferably do not overlap one another; For example, when one of the first pulse signal and the second pulse signal is at a high level, the other pulse signal is preferably at a low level. Further, a distance between pulses of each of the first pulse signal and the second pulse signal 1 Second or longer, preferably 30 seconds or longer, more preferably one minute or longer. For example, the distance between the pulses can be controlled by a control signal. It should be noted that the distance between the pulses is not necessarily constant. Alternatively, the pulse output circuits 105_1 and 105_2 be contained in the semiconductor device.
  • The above transistor with a small current in the off state may be used as the control transistors 120_1 and 120_2 be used.
  • The above is the description of the power supply control switches 102_1 and 102_2 ,
  • Next, examples of a method for driving the semiconductor device shown in FIG 6 shown is based on 8th . 9 and 10 described. As an example, here are the control transistors 120_1 and 120_2 and the transistor 110 N-channel transistors.
  • For example, if the transistor 110 is turned off, as in 8th shown, the control transistor 120_1 turned on and the control transistor 120_2 is switched off. For example, the control transistor 120_1 be turned on when the gate of the control transistor 120_1 one high potential (H) from the pulse output circuit 105_1 has, and the control transistor 120_2 can be turned off when the gate of the control transistor 120_2 has a low potential (L). It should be noted that by turning on the power source switch 104_1 before turning on the control transistor 120_1 the first power source voltage of the power source circuit 101_1 is supplied and the power source circuit 101_1 is turned on in advance. In addition, by turning off the power source switch 104_2 the supply of the second power source voltage to the power source circuit 101_2 stopped, and the power source circuit 101_2 will be switched off in advance.
  • Here, a negative power source potential -Vx from the power source circuit becomes 101_1 the backgate of the transistor 110 and the level of the potential of the return gate (VBG) becomes equal to the level of the negative power source potential -Vx.
  • Furthermore, the threshold voltage of the transistor shifts 110 in a positive direction. Thus, for example, a normally-on transistor may be changed to a normally-off transistor.
  • When the transistor 110 is turned on, as in 9 shown the control transistor 120_2 turned on and the control transistor 120_1 is switched off. For example, the control transistor 120_1 are turned off when the gate of the control transistor 120_1 from the pulse output circuit 105_1 has a low potential (L), and the control transistor 120_2 can be turned on when the gate of the control transistor 120_2 has a high potential (H). It should be noted that by turning on the power source switch 104_2 before turning on the control transistor 120_2 the second power source voltage of the power source circuit 101_2 is supplied and the power source circuit 101_2 is turned on in advance. In addition, the supply of the first power source voltage to the power source circuit becomes 101_1 stopped, and the power source circuit 101_1 is turned off in advance by turning off the power source switch 104_1 ,
  • Here, a positive power source potential + Vx from the power source circuit becomes 101_2 the backgate of the transistor 110 and the level of the potential of the return gate (VBG) becomes equal to the level of the positive power source potential + Vx.
  • Furthermore, the threshold voltage of the transistor shifts 110 in a negative direction. Consequently, for example, the on-state current of the transistor can be improved.
  • Further, the control transistors 120_1 and 120_2 as in 10 shown off after the negative power source potential -Vx or the positive power source potential + Vx the back gate of the transistor 110 has been supplied. By turning off the power source switch 104_1 and 104_2 become the supply of the first power source voltage to the power source circuit 101_1 and the supply of the second power source voltage to the power source circuit 101_2 stopped, and the power source circuits 101_1 and 101_2 are turned off.
  • At this time, the backgate of the transistor is located 110 in an open state (floating state), and the potential of the return gate ( VBG ) is held.
  • Thereafter, a power source potential may be the back gate of the transistor 110 be supplied again (also as a recharge of the return gate of the transistor 110 designated), that the control transistor 120_1 is turned on and the control transistor 120_2 is turned off when the transistor 110 is off. Alternatively, a power source potential may be the backgate of the transistor 110 be supplied again (also as a recharge of the return gate of the transistor 110 designated), that the control transistor 120_2 is turned on and the control transistor 120_1 is turned off when the transistor 110 is turned on.
  • The above is the description of the example of the method for driving the semiconductor device in FIG 6 ,
  • As based on 6 . 7 . 8th . 9 and 10 has been described, in the examples of the semiconductor device in this embodiment, the supply of a power source potential from a power source circuit to a backgate of a transistor is controlled by a power supply control switch. With the above structure, the back gate potential can be maintained when the power supply control switch is turned off, and the supply of a power source voltage to the power source circuit can be temporarily stopped; Thus, the power consumption can be reduced.
  • Further, in any of the examples of the semiconductor device in this Embodiment, for example, the power in the off state reduced when the transistor is turned off, and the current in the on state increased when the transistor is turned on, when the potential that is supplied to the back gate of the transistor is switched between a plurality of power source potentials. Thus, the state of the transistor can be optimized.
  • Now an example of the function circuit 100 , in the 1 or 6 shown is based on 11A to 11D described.
  • 11A shows the case where the function circuit 100 is a gate driver.
  • As in 11A is shown, the semiconductor device includes a gate driver. The gate driver further includes a shift register 200 , The shift register 200 includes even more flip flops (also known as FF) 201_1 to 201_n (n is a natural number). It should be noted that 11A shows the case where n is greater than or equal to 3.
  • Each of the flip flops 201_1 to 201_n includes a transistor 211 and a transistor 212 , The transistors 211 and 212 each control an output signal of the flip-flop. In this case, for example, back gates of the transistors 211 and 212 each electrically connected to a power supply control switch. The power supply control switch controls the line between the power source circuit and the back gate of the transistor 211 and the line between the power source circuit and the back gate of the transistor 212 by being turned on or off in accordance with a pulse signal. That means the transistors 211 and 212 each transistor 110 in 1 correspond.
  • Pulses of signals OUT_1 to Out_n , the output signals of the flip-flops 201_1 to 201_n are sequentially from the shift register 200 output.
  • It should be noted that the structure in 11A not just a gate driver, but also some other circuit such as B. a source driver can be applied.
  • 11B shows the case where the function circuit 100 a large scale integration (LSI) is.
  • As in 11B 1, the semiconductor device may include a logic circuit 220 include.
  • The logic circuit 220 includes a transistor 231 and a transistor 232 , At the transistor 231 That is, a power source potential VDD is supplied to one of source and drain, and a potential of the other of source and drain corresponds to a potential of an output signal OUT. Further, a potential Vy becomes a gate of the transistor 231 supplied, and the channel resistance of the transistor 231 depends on the potential Vy from. In addition, at the transistor 232 one of source and drain is supplied with a power source potential VSS, and the other of source and drain is electrically connected to the other of source and drain of the transistor 231 connected. In addition, a potential of a gate of the transistor corresponds 232 a potential of an input signal IN , It should be noted that regarding the power source potential VDD and the power source potential VSS, the power source potential VDD is a high power source potential, which is relatively higher, and that the power source potential VSS is a low power source potential that is relatively lower. The transistor 231 controls whether the potential of the output signal OUT is set to a first potential or not while the transistor 232 controls whether the potential of the output signal OUT is set to a second potential or not. Furthermore, the back gates of the transistors 231 and 232 electrically connected to the power supply control switch. The power supply control switch controls the line between the power source circuit and the back gate of the transistor 231 and the line between the power source circuit and the back gate of the transistor 232 by being turned on or off in accordance with a pulse signal. The potentials of the back gates of the transistors 231 and 232 are controlled, whereby, for example, the transistors 231 and 232 as normally-off transistors can also be driven in the case of normally-on transistors. It should be noted that although the example in which the logic circuit 220 an inverter is in 11B is shown, but the logic circuit 220 is not limited to one inverter and another logic circuit can be used.
  • 11C shows the case where the function circuit 100 a sensor is.
  • As in 11C is shown, the semiconductor device includes a sensor element 240 , an amplifier transistor 241 and a selection transistor 242 ,
  • As the sensor element 240 For example, a photosensor element or a temperature sensor element can be used.
  • A potential of a source or a drain of the amplifier transistor 241 corresponds to a potential of an output signal.
  • A backgate of the selection transistor 242 is electrically connected to a power supply control switch. Here, the power supply control switch controls the line between the power source circuit and the back gate of the selection transistor 242 by being turned on or off in accordance with a pulse signal. The potential of the return gate of the selection transistor 242 is controlled, whereby, for example, the selection transistor 242 as a normally-off (transistor) can be controlled even in the case of a normally-on transistor. The selection transistor 242 has a function of controlling the conduction between the sensor element 240 and a gate of the amplifier transistor 241 be switched on or off.
  • 11D Fig. 15 shows the case of a semiconductor device including a pixel portion.
  • As in 11D is shown, the semiconductor device includes a light-emitting element 260 , a driver transistor 261 , a selection transistor 262 and a storage capacitor 263 ,
  • The display state of the light-emitting element 260 is regulated according to a data signal input to a pixel.
  • A backgate of the driver transistor 261 For example, it is electrically connected to a power supply control switch. The driver transistor 261 has a function of fixing the amount of a current passing through the light-emitting element 260 flows according to a data signal. The power supply control switch controls the line between the power source circuit and the back gate of the driver transistor 261 by being turned on or off in accordance with a pulse signal. The potential of the back gate of the driver transistor 261 is controlled, whereby, for example, the driver transistor 261 as a normally-off (transistor) can be controlled even in the case of a normally-on transistor.
  • The input of the data signal into the pixel is made by turning on or off the selection transistor 262 controlled. It should be noted that the potential of a return gate of the selection transistor 262 can be controlled.
  • The storage capacitor 263 has a function of holding a potential according to the data signal input to the pixel. It should be noted that the storage capacitor 263 is not necessarily provided.
  • The pixel includes, as in 11D shown, at least one display element and a transistor.
  • As in 11A to 11D 12, the semiconductor device in this embodiment may include various functional circuits. Further, in this embodiment, the semiconductor device is not limited to the various functional circuits, and may be formed of a memory device, a processor, or the like.
  • Next, an example of the power source circuit 101_1 , in the 6 is shown in 12A and 12B . 13A and 13B and 14 shown. It should be noted that the structure is based on the power source circuit 101_1 can be applied, even on the power source circuit 101 can be applied.
  • The power source circuit 101_1 in 12A includes diodes 311a_1 to 311a_n (n is a natural number), capacitors 312a_1 to 312a_n and a capacitor 313a , It should be noted that 12A shows the case where n is greater than or equal to 4, for example.
  • A power source potential VDD1 (the power source potential VDD in 1 ) becomes a cathode of the diode 311a_1 fed.
  • A cathode of the diode 311a_k ( k is a natural number greater than or equal to 2) is electrically connected to an anode of the diode 311a_k-1 connected.
  • At the condenser 312a_m ( m is a natural number that is less than or equal to n is) becomes a clock signal C_CLK is input to one of a pair of electrodes of the capacitor whose m is an odd number.
  • At the condenser 312a_m is an inverted clock signal / C_CLK which is an inverted signal of the clock signal C_CLK is input to one of a pair of electrodes of the capacitor whose m is an even number.
  • Further, the other of the pair of electrodes of the capacitor 312a_m electrically connected to the anode of the diode 311a_m connected.
  • One of a pair of electrodes of the capacitor 313a is supplied with a power source potential VSS, and the other of the pair of electrodes is electrically connected to an anode of the diode 311a_n connected.
  • At the power source circuit 101_1 in 12A are voltages of the capacitors 312a_1 to 312a_n so diminished that the clock signal C_CLK and the inverted clock signal / C_CLK is alternately switched to a high level or a low level. Further, the voltage of the capacitor 312a_k lower than the voltage of the capacitor 312a_k -1. Consequently, a negative power source potential -Vx is output as a signal OUT.
  • The power source circuit 101_1 in 12B includes transistors 321a_1 to 321a_3 , Capacitors 322a_1 to 322a_3 , Transistors 323a_1 to 323a_3 , Transistors 324a_1 to 324a_3 , a transistor 325a and a capacitor 326a , It should be noted that although the power source circuit 101_1 in 12B shows the case where a power source potential that is three times as high as an input power source potential VDD1 is generated, an embodiment of the present invention is not limited to such a case.
  • The power source potential VDD1 becomes one of the source and drain of the transistor 321a_i ( i is a natural number less than or equal to 3). Further, a clock signal C_CLK in a gate of the transistor 321a_i entered.
  • One of a pair of electrodes of the capacitor 322a_i is electrically connected to the other of the source and drain of the transistor 321a_i connected.
  • At the transistor 323a_1 For example, one of source and drain is supplied with a power source potential VSS, and the other of source and drain is electrically connected to one of the pair of electrodes of the capacitor 322a_1 connected. Further, an inverted clock signal / C_CLK becomes a gate of the transistor 323a_1 entered.
  • At the transistor 323a_j ( j is a natural number greater than or equal to 2 and less than or equal to 3) one of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 322a_j -1, and the other of source and drain is electrically connected to one of the pair of electrodes of the capacitor 322a_j connected. In addition, the inverted clock signal / C_CLK becomes a gate of the transistor 323a_j entered.
  • At the transistor 324a_i becomes one of source and drain with the power source potential VSS and the other of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 322a_i connected.
  • One of the source and drain of the transistor 325a is electrically connected to one of the pair of electrodes of the capacitor 322a_3 connected. Further, the inverted clock signal / CLK becomes a gate of the transistor 325a entered.
  • At the condenser 326a becomes one of a pair of electrodes having the power source potential VDD1 and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 325a connected.
  • At the power source circuit 101_1 in 12B are voltages of the capacitors 322a_1 to 322a_3 so diminished that the clock signal C_CLK and the inverted clock signal / C CLK be alternately changed to a high level or a low level. Consequently, a negative power source potential -Vx is output as a signal OUT.
  • The power source circuit 101_1 in 13A includes transistors 331a to 334a and capacitors 335a and 336a ,
  • A power source potential VDD1 becomes one of the source and drain of the transistor 331a fed. Further, a clock signal C_CLK in a gate of the transistor 331a entered.
  • A power source potential VSS becomes one of the source and drain of the transistor 332a fed. Further, the clock signal becomes C_CLK in a gate of the transistor 332a entered.
  • At the transistor 333a one of source and drain is electrically connected to the other of the source and drain of the transistor 331a connected, and the other of the source and drain is supplied with a power source potential VSS. Further, an inverted clock signal / C_CLK of the clock signal C_CLK in a gate of the transistor 333a entered.
  • At the transistor 334a one of source and drain is electrically connected to the other of the source and drain of the transistor 332a connected, and the potential of the other of source and drain corresponds to a potential of an output signal OUT, that is, a power source potential in the back gate of the transistor 110 is to spend. The inverted clock signal / C CLK gets into a gate of the transistor 334a entered.
  • At the condenser 335a For example, one of a pair of electrodes is electrically connected to the other of the source and drain of the transistor 331a and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 332a connected.
  • At the condenser 336a For example, one of a pair of electrodes is supplied with a power source potential VSS, and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 334a connected.
  • At the power source circuit 101_1 in 13A can be a power source potential in the backgate of the transistor 110 is to be generated in such a way that the transistors 331a and 332a and the transistors 333a and 334a alternately turned on or off, and that the input first power source voltage according to the clock signal C_CLK and the inverted clock signal / C CLK is reduced.
  • The power source circuit 101_1 in 13B includes a transistor 341a , a diode 342a , a coil 343a and a capacitor 344a ,
  • A power source potential VDD1 becomes one of the source and drain of the transistor 341a fed. A pulse signal becomes a gate of the transistor 341a entered.
  • At the diode 342a A potential of an anode corresponds to a potential of an output signal OUT, that is, a power source potential applied to the back gate of the transistor 110 and one cathode is electrically connected to the other of the source and drain of the transistor 341a connected.
  • At the coil 343a one terminal is electrically connected to the other of the source and drain of the transistor 341a connected, and the other terminal is supplied with a power source potential VSS.
  • At the condenser 344a is one of a pair of electrodes electrically connected to the anode of the diode 342a and the other of the pair of electrodes is supplied with the power source potential VSS.
  • At the power source circuit 101_1 in 13B becomes the transistor 341a turned on, causing the diode 342a not in a conducting state and a current through the coil 343a flows. This is electromotive force V1 to the coil 343a created. It should be noted that the voltage applied to the capacitor 344a is created, not changed. In addition, the transistor 341a switched off, causing electromotive force V2 in the direction that the direction of the electromotive force V1 is opposite, in the coil 343a is generated to suppress a change in their magnetic field, and the diode 342a is in a line state. At this time, a current flows through the coil 343a and the diode 342a , and the voltage applied to the capacitor 344a is applied, is changed, creating a power source potential in the backgate of the transistor 110 is to be entered can be generated.
  • The power source circuit 101_1 in 14 includes transistors 361_1 to 361_3 , Capacitors 362_1 to 362_3 , Transistors 363_1 to 363_3 , Transistors 364_1 to 364_3 , Transistors 365 to 368 and capacitors 369 and 370 , It should be noted that although the power source circuit 101_1 in 14 shows the case where a power source potential that is three times lower than an input power source potential VDD1 is generated, an embodiment of the present invention is not limited to such a case.
  • A power source potential VSS becomes one of the source and drain of the transistor 361_i ( i is a natural number less than or equal to 3). Further, a clock signal C_CLK in a gate of the transistor 361_i entered.
  • One of a pair of electrodes of the capacitor 362_i is electrically connected to the other of the source and drain of the transistor 361_i connected.
  • At the transistor 363_1 becomes one of source and drain with a power source potential VDD1 and the other of source and drain is electrically connected to one of the pair of electrodes of the capacitor 362_1 connected. Further, an inverted clock signal / C_CLK becomes a gate of the transistor 363_1 entered.
  • At the transistor 363J ( j is a natural number greater than or equal to 2 and less than or equal to 3) one of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 362_j-1 and the other of the source and drain is electrically connected to one of the pair of electrodes of the capacitor 362J connected. In addition, the inverted clock signal / C_CLK becomes a gate of the transistor 363J entered.
  • At the transistor 364_i becomes one of source and drain with the power source potential VDD1 and the other of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 362_i connected.
  • One of the source and drain of the transistor 365 is electrically connected to the other of the pair of electrodes of the capacitor 362a_3 connected. Further, the inverted clock signal / C_CLK becomes a gate of the transistor 365 entered.
  • The power source potential VSS becomes one of the source and drain of the transistor 366 fed. Further, the inverted clock signal / C_CLK becomes a gate of the transistor 366 entered.
  • At the transistor 367 one of source and drain is electrically connected to the other of the source and drain of the transistor 365 connected, and the other of the source and drain is supplied with the power source potential VSS. Further, the clock signal becomes C_CLK in a gate of the transistor 367 entered.
  • At the transistor 368 one of source and drain is electrically connected to the other of the source and drain of the transistor 366 connected, and the potential of the other of source and drain corresponds to a potential of an output signal OUT, that is, a power source potential in the back gate of the transistor 110 is to spend. The clock signal C_CLK gets into a gate of the transistor 368 entered.
  • At the condenser 369 For example, one of a pair of electrodes is electrically connected to the other of the source and drain of the transistor 365 and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 366 connected.
  • At the condenser 370 becomes one of a pair of electrodes having the power source potential VSS and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 368 connected.
  • At the power source circuit 101_1 in 14 are voltages of the capacitors 362_1 to 362_3 according to the clock signal C_CLK and the inverted clock signal / C_CLK. Furthermore, a power source potential flowing into the backgate of the transistor 110 is to be generated in such a way that the transistors 365 and 366 and the transistors 367 and 368 alternately turned on or off, and that the voltage of the capacitor 362_3 is reduced to a negative voltage.
  • Further, an example of the power source circuit 101_2 in 15A and 15B and 16A and 16B shown.
  • The power source circuit 101_2 in 15A includes diodes 311b_1 to 311b_n (n is a natural number), capacitors 312b_1 to 312b_n and a capacitor 313b , It should be noted that 15A shows the case where n is greater than or equal to 4, for example.
  • A power source potential VDD2 becomes an anode of the diode 311b_1 fed.
  • An anode of the diode 311bk (k is a natural number greater than or equal to 2) is electrically connected to a cathode of the diode 311b_k -1 connected.
  • At the condenser 312b_m (m is a natural number less than or equal to n) becomes a clock signal C_CLK is input to one of a pair of electrodes of the capacitor whose m is an odd number.
  • At the condenser 312b_m is an inverted clock signal / C_CLK which is an inverted signal of the clock signal C_CLK is input to one of a pair of electrodes of the capacitor whose m is an even number.
  • Further, the other of the pair of electrodes of the capacitor 312b_m electrically with a cathode of the diode 311b_m connected.
  • One of a pair of electrodes of the capacitor 313b comes with a power source potential VSS and the other of the pair of electrodes is electrically connected to the cathode of the diode 311b_n connected.
  • At the power source circuit 101_2 in 15A are voltages of the capacitors 312b_1 to 312b_n so amplified that the clock signal C_CLK and the inverted clock signal / C CLK is alternately changed to a high level or a low level. Further, the voltage of the capacitor 312b_k higher than the voltage of the capacitor 312b_k -1. Consequently, a positive power source potential + Vx is output as a signal OUT.
  • The power source circuit 101_2 in 15B includes transistors 321b_1 to 321b_3 , Capacitors 322b_1 to 322b_3 , Transistors 323b_1 to 323b_3 , Transistors 324b_1 to 324b_3 , a transistor 325b and a capacitor 326b , It should be noted that although the power source circuit 101_2 in 15B shows the case where a power source potential that is three times as high as an input power source potential VDD2 is generated, an embodiment of the present invention is not limited to such a case.
  • A power source potential VSS becomes one of the source and drain of the transistor 321b_i ( i is a natural number less than or equal to 3). Further, a clock signal C_CLK in a gate of the transistor 321b_i entered.
  • One of a pair of electrodes of the capacitor 322b_i is electrically connected to the other of the source and drain of the transistor 321b_i connected.
  • At the transistor 323b_1 becomes one of source and drain with a power source potential VDD2 and the other of source and drain is electrically connected to one of the pair of electrodes of the capacitor 322b_1 connected. Further, an inverted clock signal / C_CLK becomes a gate of the transistor 323b_1 entered.
  • At the transistor 323b_j (j is a natural number greater than or equal to 2 and less than or equal to 3) one of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 322b_j -1, and the other of source and drain is electrically connected to one of the pair of electrodes of the capacitor 322b_j connected. In addition, the inverted clock signal / C_CLK becomes a gate of the transistor 323b_j entered.
  • At the transistor 324b_i becomes one of source and drain with the power source potential VDD2 and the other of source and drain is electrically connected to the other of the pair of electrodes of the capacitor 322b_i connected.
  • One of the source and drain of the transistor 325b is electrically connected to the other of the pair of electrodes of the capacitor 322b_3 connected. Further, the inverted clock signal / C_CLK becomes a gate of the transistor 325b entered.
  • At the condenser 326b For example, one of a pair of electrodes is supplied with the power source potential VSS, and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 325b connected.
  • At the power source circuit 101_2 in 15B are voltages of the capacitors 322b_1 to 322b_3 so amplified that the clock signal C_CLK and the inverted clock signal / C CLK is alternately changed to a high level or a low level. Consequently, a positive power source potential + Vx is output as a signal OUT.
  • The power source circuit 101 2 in 16A includes transistors 331b to 334b and capacitors 335b and 336b ,
  • A power source potential VSS becomes one of source and drain of the transistor 331b fed. Further, a clock signal C_CLK in a gate of the transistor 331b entered.
  • A power source potential VDD2 becomes one of the source and drain of the transistor 332b fed. Further, the clock signal becomes C_CLK in a gate of the transistor 332b entered.
  • At the transistor 333b one of source and drain is electrically connected to the other of the source and drain of the transistor 331b connected, and the other of the source and drain is connected to a power source potential VDD2 provided. Further, an inverted clock signal / C_CLK which is an inverted signal of the clock signal C_CLK is, in a gate of the transistor 333b entered.
  • At the transistor 334b one of source and drain is electrically connected to the other of the source and drain of the transistor 332b connected, and the potential of the other of source and drain corresponds to a potential of an output signal OUT, that is, a power source potential in the back gate of the transistor 110 to give is. The inverted clock signal / C_CLK becomes a gate of the transistor 334b entered.
  • At the condenser 335b For example, one of a pair of electrodes is electrically connected to the other of the source and drain of the transistor 331b and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 332b connected.
  • At the condenser 336b For example, one of a pair of electrodes is supplied with a power source potential VSS, and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 334b connected.
  • At the power source circuit 101_2 in 16A can be a power source potential in the backgate of the transistor 110 is to be generated in such a way that the transistors 331b and 332b and the transistors 333b and 334b alternately turned on or off, and that the second power source voltage to be input is in accordance with the clock signal C_CLK and the inverted clock signal / C_CLK is reinforced.
  • The power source circuit 101_2 in 16B includes a transistor 341b , a diode 342b , a coil 343b and a capacitor 344b ,
  • A power source potential VSS becomes one of source and drain of the transistor 341b fed. A pulse signal becomes a gate of the transistor 341b entered.
  • At the diode 342b one anode is electrically connected to the other of the source and drain of the transistor 341b and a potential of a cathode corresponds to a potential of an output signal OUT, ie, a power source potential Vx2 that is in the backgate of the transistor 110 is to enter.
  • At the coil 343b becomes a connection with a power source potential VDD2 supplied, and the other terminal is electrically connected to the other of the source and drain of the transistor 341b connected.
  • One of a pair of electrodes of the capacitor 344b is supplied with the power source potential VSS, and the other of the pair of electrodes is electrically connected to the cathode of the diode 342b connected.
  • At the power source circuit 101_2 in 16B becomes the transistor 341b turned on, causing the diode 342b is not in a conduction state, and a current flows through the coil 343b , This is electromotive force V1 to the coil 343b created. It should be noted that the voltage applied to the capacitor 344b is created, not changed. In addition, the transistor 341b switched off, causing electromotive force V2 in the direction that the direction of the electromotive force V1 is opposite, in the coil 343b is generated to suppress a change in its magnetic field, and the diode 342b is in a line state. At this time, a current flows through the coil 343b and the diode 342b , and the voltage applied to the capacitor 344b is applied, is changed, creating a power source potential in the backgate of the transistor 110 is to be entered can be generated.
  • The above is the description of the example of the power source circuit 101_2 ,
  • [Embodiment 2]
  • In this embodiment, an example of a semiconductor device capable of displaying images will be described.
  • First, a structural example of the semiconductor device in this embodiment will be described with reference to FIG 17 described.
  • A semiconductor device in 17 includes a plurality of pixel circuits 910 , in the X Lines and Y Columns ( X and Y are natural numbers greater than or equal to 2), a source driver 901 , Data signal lines DL_1 to DL_Y , a gate driver 902 , Gate signal lines GL_1 to GL_X , a power source circuit 903 , a power supply control switch 921 and a power supply control switch 922 , It should be noted that as each of the gate signal lines GL_1 to GL_X a plurality of gate signal lines may be provided for each gate signal.
  • For example, one pixel consists of three pixel circuits 910 to display red (R), green (G) and blue (B).
  • The potentials of the data signal lines DL_1 to DL_Y be from the source driver 901 controlled. The source driver 901 may for example be formed using an analog switch, a latch circuit and an operational amplifier. In the semiconductor device in 17 Data becomes the plurality of pixel circuits 910 over the data signal lines DL_1 to DL_Y entered.
  • The potentials of the gate signal lines GL_1 to GL_X be from the gate driver 902 controlled. It should be noted that the gate driver 902 and the pixel circuits 910 can be formed over a substrate in the same manufacturing process. The gate driver 902 is formed using, for example, a shift register. The gate signal lines GL_1 to GL_X are each a line into which a gate signal to select the pixel circuit 910 is entered for data entry.
  • Further, the pixel circuits become 910 , the source driver 901 and the gate driver 902 a power source potential or a power source voltage from the power source circuit 903 fed. It should be noted that the power source circuit 903 may be formed over a substrate different from that of the pixel circuits 910 is, and may be connected via a line or the like.
  • In addition, a potential BG1 and a potential BG2 a backgate of a transistor in the gate driver 902 via the power supply control switch 921 or the power supply control switch 922 fed. The potential BG1 and the potential BG2 are potentials supplied to the back gate of the transistor. As the structures of the power supply control switch 921 and the power supply control switch 922 can the structure of the power supply control switch 102 be used.
  • Further, an example of the gate driver 902 in 18 shown.
  • The gate driver 902 in 18 includes a shift register 30 , Inverter 42_1 to 42_N + 1 and inverter 53_1 to 53_N + 1 , In addition, the shift register includes 30 Flip flops ( FF ) 31_1 to 31_n + 1 ,
  • Further, components of the gate driver in 18 based on 19A and 19B . 20A-1 . 20A-2 . 20B-1 and 20B-2 and 21 described.
  • As in 19A is shown in each of the flip-flops 31_1 to 31_N in 18 a set signal LIN, a reset signal RIN, clock signals CLK1 and CLK2 , Pulse width control signals PWC1 and pwc2 and an initialization signal INIRES entered. It should be noted that in 18 Terminals in which the power source potential and the potentials BG1 and BG2 are input are omitted for the sake of simplicity. Furthermore, from the flip flop in 19A a signal FFOUT, a signal GOUT1 and a signal GOUT2 are output. It should be noted that, for example, the initialization signal INIRES is a signal for initializing a flip-flop. A pulse of the initialization signal INIRES is input to the flip-flop, whereby the flip-flop is initialized. It is not always necessary to input the initialization signal INIRES into the flip-flop.
  • It should be noted that the structure of the flip-flop 31_n + 1 same as that of the other flip-flop except that the reset signal RIN is not input.
  • Also includes the flip flop in 19A as in 19B shown transistors 61 to 75 and a capacitor 76 ,
  • A power source potential G_VDD becomes one of the source and drain of the transistor 61 fed. Further, the set signal LIN becomes a gate of the transistor 61 entered, and the potential BG1 becomes a backgate of the transistor 61 fed.
  • A power source potential G_VSS becomes one of the source and drain of the transistor 62 fed. Further, the set signal LIN becomes a gate of the transistor 62 entered, and the potential BG2 becomes a backgate of the transistor 62 fed. Here is the level of the potential BG2 preferably lower than the level of the potential BG1 , That's because then, when the threshold voltage of the transistor, with the potential BG1 is too high, probably causing a malfunction of the semiconductor device. It should be noted that regarding the power source potential G_VDD and the power source potential G_VSS the power source potential G_VDD is a high power source potential, which is relatively higher, and the power source potential G_VSS is a low power source potential that is relatively lower. A potential difference between the power source potential G_VDD and the power source potential G_VSS is a power source voltage.
  • A power source potential G_VDD becomes one of the source and drain of the transistor 63 fed. Further, the reset signal becomes RIN in a gate of the transistor 63 entered, and the potential BG2 becomes a backgate of the transistor 63 fed.
  • A power source potential G_VDD becomes one of the source and drain of the transistor 64 fed. Further, the clock signal becomes CLK2 in a gate of the transistor 64 entered, and the potential BG2 becomes a backgate of the transistor 64 fed.
  • At the transistor 65 becomes the clock signal CLK1 is input to one of source and drain, and the potential of the other of source and drain corresponds to the potential of signal FFOUT. Further, the potential becomes BG2 a backgate of the transistor 65 fed.
  • At the transistor 66 becomes one of source and drain with the power source potential G_VSS and the other of source and drain is electrically connected to the other of the source and drain of the transistor 65 connected. Further, a gate of the transistor 66 electrically to the other of the source and drain of the transistor 63 connected, and a backgate of the transistor 66 becomes with the potential BG2 provided.
  • At the transistor 67 becomes one of source and drain with the power source potential G_VSS and the other of source and drain is electrically connected to the other of the source and drain of the transistor 61 connected. Further, a gate of the transistor 67 electrically to the other of the source and drain of the transistor 63 connected, and a backgate of the transistor 67 becomes with the potential BG2 provided.
  • At the transistor 68 one of source and drain is electrically connected to the other of the source and drain of the transistor 61 and the other of source and drain is electrically connected to a gate of the transistor 65 connected. Further, a gate of the transistor 68 with a power source potential G_VDD supplied, and a backgate of the transistor 68 becomes with the potential BG1 provided.
  • At the transistor 69 becomes the pulse width control signal PWC1 input to one of source and drain, and the potential of the other of source and drain corresponds to the potential of the signal GOUT1 , Further, the potential becomes BG2 a backgate of the transistor 69 fed.
  • At the transistor 70 becomes one of source and drain with a potential G_VEE1 and the other of source and drain is electrically connected to the other of the source and drain of the transistor 69 connected. The potential G_VEE1 is a given potential. Further, a gate of the transistor 70 electrically to the other of the source and drain of the transistor 63 connected, and a backgate of the transistor 70 becomes with the potential BG2 provided.
  • At the transistor 71 one of source and drain is electrically connected to the other of the source and drain of the transistor 61 and the other of source and drain is electrically connected to a gate of the transistor 69 connected. Further, a gate of the transistor 71 with a power source potential G_VDD supplied, and a backgate of the transistor 71 becomes with the potential BG1 provided.
  • At the transistor 72 becomes the pulse width control signal pwc2 input to one of source and drain, and the potential of the other of source and drain corresponds to the potential of the signal GOUT2 , Further, a back gate of the transistor 72 with the potential BG2 provided.
  • At the transistor 73 becomes one of source and drain with the power source potential G_VSS and the other of source and drain is electrically connected to the other of the source and drain of the transistor 72 connected. Further, a gate of the transistor 73 electrically to the other of the source and drain of the transistor 63 connected, and a backgate of the transistor 73 becomes with the potential BG2 provided.
  • At the transistor 74 one of source and drain is electrically connected to the other of the source and drain of the transistor 61 and the other of source and drain is electrically connected to a gate of the transistor 72 connected. Further, a gate of the transistor 74 with a power source potential G_VDD supplied, and a backgate of the transistor 74 becomes with the potential BG1 provided.
  • At the transistor 75 becomes one of source and drain with a power source potential G_VDD and the other of source and drain is electrically connected to the other of the source and drain of the transistor 63 connected. Further, the initialization signal INIRES becomes a gate of the transistor 75 entered, and the potential BG2 becomes a backgate of the transistor 75 fed.
  • At the condenser 76 becomes one of a pair of electrodes having the power source potential G_VSS and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 63 connected. It should be noted that the capacitor 76 is not necessarily provided.
  • At the flipflop in 19B Then, when a pulse of the set signal LIN is input, the transistor 61 turned on and then the transistors 65 . 69 and 72 turned on, reducing the level of the potential of the signal FFOUT equal to the level of the potential of the clock signal CLK1 becomes, the level of the potential of the signal GOUT1 equal to the level of the potential of the pulse width control signal PWC1 and the level of the potential of the signal GOUT2 equal to the level of the potential of the pulse width control signal pwc2 becomes. At this time are the transistors 66 . 70 and 73 switched off. In addition, in the flip-flop in 19B when the transistor 63 according to the reset signal RIN is turned on, the transistors 66 . 70 and 73 turned on, reducing the level of the potential of the signal FFOUT equal to the level of the power source potential G_VSS becomes, the level of the potential of the signal GOUT1 equal to the level of the power source potential G_VEE1 and the level of the potential of the signal GOUT2 equal to the level of the power source potential G_VSS becomes. At this time are the transistors 65 . 69 and 72 switched off. Consequently, the flip-flop outputs a pulse signal.
  • As the setting signal LIN of the flip-flop 31_1 becomes a start pulse signal SP in the shift register 30 in 18 entered.
  • It should be noted that a protection circuit is electrically connected to a line for inputting the start pulse signal SP to the gate driver 902 can be connected.
  • As the setting signal LIN of the flip-flop 31_K ( K is a natural number greater than or equal to 2 and less than or equal to X is) a signal FFOUT of the flip-flop 31_K -1 in the shift register 30 entered.
  • In addition, as the reset signal RIN of the flip-flop 31_M (M is a natural number smaller than N) becomes a signal FFOUT of the flip-flop 31_M + 1 into the shift register 30 entered.
  • As the clock signal CLK1 and the clock signal CLK2 of the flip-flop 31_1 become a clock signal G_CLK1 or a clock signal G_CLK2 in the shift register 30 entered. Furthermore, as with respect to the flip-flop 31_1 , the clock signal G_CLK1 and the clock signal G_CLK2 as the clock signal CLK1 or the clock signal CLK2 entered into every third flip flop.
  • As the clock signal CLK1 and the clock signal CLK2 of the flip-flop 31_2 become the clock signal G_CLK2 or a clock signal G_CLK3 in the shift register 30 entered. Furthermore, as with respect to the flip-flop 31_2 , the clock signal G_CLK2 and the clock signal G_CLK3 as the clock signal CLK1 or the clock signal CLK2 entered into every third flip flop.
  • As the clock signal CLK1 and the clock signal CLK2 of the flip-flop 31_3 become the clock signal G_CLK3 or a clock signal G_CLK4 in the shift register 30 entered. Furthermore, as in Reference to the flip-flop 31_3 , the clock signal G_CLK3 and the clock signal G_CLK4 as the clock signal CLK1 or the clock signal CLK2 entered into every third flip flop.
  • As the clock signal CLK1 and the clock signal CLK2 of the flip-flop 31_4 become the clock signal G_CLK4 or the clock signal G_CLK1 in the shift register 30 entered. Furthermore, as with respect to the flip-flop 31_4 , the clock signal G_CLK4 and the clock signal G_CLK1 as the clock signal CLK1 or the clock signal CLK2 entered into every third flip flop.
  • It should be noted that a protection circuit is electrically connected to lines for inputting the clock signals G_CLK1 to G_CLK4 can be connected.
  • At the shift register 30 become a pulse width control signal G_PWC1 and a pulse width control signal G_PWCA as the pulse width control signal PWC1 or the pulse width control signal pwc2 of the flip-flop 31_1 entered. Furthermore, as with respect to the flip-flop 31_1 , the pulse width control signal G_PWC1 and the pulse width control signal G_PWCA as the pulse width control signal PWC1 or the pulse width control signal pwc2 entered into every third flip flop.
  • At the shift register 30 become a pulse width control signal G_PWC2 and a pulse width control signal G_PWCB as the pulse width control signal PWC1 or the pulse width control signal pwc2 of the flip-flop 31_2 entered. Furthermore, as with respect to the flip-flop 31_2 , the pulse width control signal G_PWC2 and the pulse width control signal G_PWCB as the pulse width control signal PWC1 or the pulse width control signal pwc2 entered into every third flip flop.
  • At the shift register 30 become a pulse width control signal G_PWC3 and a pulse width control signal G_PWCC as the pulse width control signal PWC1 or the pulse width control signal pwc2 of the flip-flop 31_3 entered. Furthermore, as with respect to the flip-flop 31_3 , the pulse width control signal G_PWC3 and the pulse width control signal G_PWCC as the pulse width control signal PWC1 or the pulse width control signal pwc2 entered into every third flip flop.
  • At the shift register 30 become a pulse width control signal G_PWC4 and a pulse width control signal G_PWCD as the pulse width control signal PWC1 or the pulse width control signal pwc2 of the flip-flop 31_4 entered. Furthermore, with respect to the flip-flop 31_4 , the pulse width control signal G_PWC4 and the pulse width control signal G_PWCD as the pulse width control signal PWC1 or the pulse width control signal pwc2 entered into every third flip flop.
  • In addition, in the shift register 30 the signal GOUT1 of the flip-flop 31_M to a gate signal G1_M ,
  • The above is the description of the flip-flops.
  • 20A-1 . 20A-2 . 20B-1 and 20B-2 show examples of the structure of the inverter.
  • As in 20A-1 is shown, a pulse signal IN1 and a reset signal INV_RIN in each of the inverters 42_1 to 42_N + 1 in 18 entered. Each of the inverters 42_1 to 42_N + 1 in 18 outputs a signal INVOUT1.
  • Also includes as in 20A-2 shown each of the inverters 42_1 to 42_N + 1 in 20A-1 transistors 81 to 85 and a capacitor 86 ,
  • One of the source and drain of the transistor 81 comes with a power source potential G_VDD provided. Further, the reset signal INV_RIN becomes a gate of the transistor 81 is input, and the potential BG2 becomes a back gate of the transistor 81 fed.
  • At the transistor 82 becomes one of source and drain with a power source potential G_VSS1 and the other of source and drain is electrically connected to the other of the source and drain of the transistor 81 connected. Further, the pulse signal becomes IN1 in a gate of the transistor 82 entered, and the potential BG2 becomes a backgate of the transistor 82 fed.
  • At the transistor 83 becomes one of source and drain with a power source potential G_VCC1 and a potential of the other of source and drain corresponds to a potential of the signal INVOUT1. The signal INVOUT1 corresponds to one of the signals G2_1 to G2_N + 1 in 18 , The power source potential G_VCC1 is any potential. Further, a back gate of the transistor 83 with the potential BG2 provided.
  • At the transistor 84 becomes one of source and drain with a power source potential G_VEE2 and the other of source and drain is electrically connected to the other of the source and drain of the transistor 83 connected. The potential G_VEE2 is any potential. Further, the pulse signal IN1 becomes a gate of the transistor 84 is input, and the potential BG2 becomes a back gate of the transistor 84 fed.
  • At the transistor 85 one of source and drain is electrically connected to the other of the source and drain of the transistor 81 and the other of source and drain is electrically connected to a gate of the transistor 83 connected. Further, a gate of the transistor 85 with a power source potential G_VDD supplied, and a backgate of the transistor 85 becomes with the potential BG1 provided.
  • At the condenser 86 For example, one of a pair of electrodes is electrically connected to the gate of the transistor 83 and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 83 connected.
  • As in 20B-1 is further shown, a pulse signal IN2 and a reset signal INV_RIN in each of the inverters 53_1 to 53_N + 1 in 18 entered. Each of the inverters 53_1 to 53_N + 1 in 18 outputs a signal INVOUT2.
  • Also includes as in 20B-2 shown each of the inverters 53_1 to 53_N + 1 in 20B-1 transistors 91 to 95 and a capacitor 96 ,
  • At the transistor 91 becomes one of source and drain with a power source potential G_VDD provided. Further, the reset signal INV_RIN becomes a gate of the transistor 91 is input, and the potential BG2 becomes a back gate of the transistor 91 fed.
  • At the transistor 92 becomes one of source and drain with a power source potential G_VSS1 and the other of source and drain is electrically connected to the other of the source and drain of the transistor 91 connected. Further, the pulse signal becomes IN 2 in a gate of the transistor 92 entered, and the potential BG2 becomes a backgate of the transistor 92 fed.
  • At the transistor 93 becomes one of source and drain with a power source potential G_VCC2 supplied, and a potential of the other of source and drain corresponds to a potential of the signal INVOUT2 , The signal INVOUT2 corresponds to one of the signals G3_1 to G3_N + 1 in 18 , Further, a back gate of the transistor 93 supplied with the potential BG2.
  • At the transistor 94 becomes one of source and drain with a power source potential G_VEE3 and the other of source and drain is electrically connected to the other of the source and drain of the transistor 93 connected. The potential G_VEE3 is any potential. Further, the pulse signal IN2 becomes a gate of the transistor 94 is input, and the potential BG2 becomes a back gate of the transistor 94 fed.
  • At the transistor 95 one of source and drain is electrically connected to the other of the source and drain of the transistor 91 and the other of source and drain is electrically connected to a gate of the transistor 93 connected. Further, a gate of the transistor 95 with a power source potential G_VDD supplied, and a backgate of the transistor 95 becomes with the potential BG1 provided.
  • At the condenser 96 For example, one of a pair of electrodes is electrically connected to the gate of the transistor 93 and the other of the pair of electrodes is electrically connected to the other of the source and drain of the transistor 93 connected.
  • Further, the signal FFOUT of the flip-flop 31_M as the pulse signal IN1 of the inverter 42_M entered, and the signal GOUT2 of the flip-flop 31_M is called the pulse signal IN 2 of the inverter 53_M entered. The signal INVOUT1 of the inverter 42_M serves as a gate signal G2_M , and the signal INVOUT2 of the inverter 53_M serves as a gate signal G3_M ,
  • The clock signal G_CLK2 is called the reset signal INV_RIN the inverter 42_1 and 53_1 entered. Furthermore, as with respect to the inverter 42_1 , the clock signal G_CLK2 as the reset signal INV RIN entered into every third inverter.
  • The clock signal G CLK3 is called the reset signal INV_RIN the inverter 42_2 and 53_2 entered. Furthermore, as with respect to the inverter 42_2 , the clock signal G_CLK3 as the reset signal INV-RIN entered into every third inverter.
  • The clock signal G CLK3 is called the reset signal INV_RIN the inverter 42_3 and 53_3 entered. Furthermore, as with respect to the inverter 42_3 , the clock signal G_CLK3 as the reset signal INV_RIN entered into every third inverter.
  • The clock signal G_CLK4 is called the reset signal INV_RIN the inverter 42_4 and 53_4 entered. Furthermore, as with respect to the inverter 42_4 the clock signal G_CLK4 as the reset signal INV_RIN entered into every third inverter.
  • The above is the description of the inverter.
  • Next, the example of a method of driving the gate driver in FIG 18 on the basis of a time diagram in 21 described.
  • In the example of the method for driving the gate driver in 18 will be like in 21 shown a pulse of the start pulse signal SP input, whereby pulses of gate signals G1_1 to G1_N are output sequentially, pulses of the gate signals G2_1 to G2_N are output sequentially and pulses of the gate signals G3_1 to G3_N be issued sequentially. When the start pulse signal SP at a time T1 is at a high level, there is, for example, the gate signal G2_1 at a time T2 at a low level, the gate signal G1_1 is at a time T3 at a high level and the gate signal G3_1 is at a time T4 at a low level. Furthermore, there is the gate signal G1_1 at a time T5 at a low level, and the gate signals G2_1 and G3_1 are at one time T6 at high levels.
  • The above is the description of the method of driving the gate driver in FIG 18 ,
  • Next, a structural example of the pixel circuit will be described 910 in 22A and 22B shown.
  • A pixel circuit in 22A includes a light-emitting element 950 , Transistors 951 to 955 and a capacitor 956 , It should be noted that a capacitor 957 as the capacity of the light-emitting element 950 is shown.
  • The light-emitting element 950 has a function of emitting light in accordance with the amount of current flowing between an anode and a cathode. A cathode potential (also referred to as CATHODE) becomes the cathode of the light-emitting element 950 fed.
  • An anode potential (also referred to as ANODE) becomes a drain of the transistor 951 fed. The transistor 951 serves as a driver transistor.
  • A data signal data becomes one of source and drain of the transistor 952 entered, and a gate signal G1 gets into a gate of the transistor 952 entered. The gate signal G1 corresponds to the gate signal G1_M in 18 ,
  • At the transistor 953 becomes one of source and drain with a potential V0 and the other of source and drain is electrically connected to a gate of the transistor 951 connected. Further, the gate signal becomes G1 in a gate of the transistor 953 entered.
  • One of the source and drain of the transistor 954 is electrically connected to the gate of the transistor 951 connected, and a gate signal G2 gets into a gate of the transistor 954 entered. The gate signal G2 corresponds to the gate signal G2_M in 18 ,
  • At the transistor 955 one of source and drain is electrically connected to a source of the transistor 951 and the other of source and drain is electrically connected to the anode of the light-emitting element 950 connected. Further, a gate signal G3 in a gate of the transistor 955 entered. The gate signal G3 corresponds to the gate signal G3_M in 18 ,
  • At the condenser 956 For example, one of a pair of electrodes is electrically connected to the other of the source and drain of the transistor 952 and with the other of the source and drain of the transistor 954 and the other of the pair of electrodes is electrically connected to the source of the transistor 951 connected.
  • Next, the example of a method of driving the pixel circuit in FIG 22A on the basis of a time diagram in 22B described.
  • A period T1 in 22B is an initialization period. In the period T1 becomes the transistor 955 turned on, and the transistors 952 . 953 and 954 are turned off.
  • At this time, the level of the source potential of the transistor 951 lower than the level of the potential V0 ,
  • A period T2 is a period of time during which a threshold is determined. In the period T2 become the transistors 952 and 953 turned on, and the transistors 954 and 955 are turned off.
  • At this time, the transistor becomes 951 turned off when the gate potential of the transistor 951 the potential V0 corresponds and the level of a voltage between the gate and the source of the transistor 951 (The voltage is also called Vgs 951 designated) the level of a threshold voltage of the transistor 951 (The threshold voltage is also called Vth 951 designated) corresponds. Here, the source potential of the transistor 951 from the formula V0 - Vth 951 to be obtained. In addition, the level of the potential corresponds to one of the pair of electrodes of the capacitor 956 the level of the potential Vdata of the data signal data.
  • A period T3 is a light-emitting period. In the period T3 become the transistors 954 and 955 turned on, and the transistors 952 and 953 are turned off.
  • Here, the level corresponds to the gate potential of the transistor 951 the level of the potential Vdata of the data signal data, and Vgs 951 can be obtained from the formula Vdata - Vth 951 + V0. Consequently, a current that hangs between the source and the drain of the transistor 951 flows in a saturation region (the current is also called Ids 951 ), not from Vth 951 but from Vdata; thus, the influence of the fluctuation of Vth 951 be suppressed.
  • Further, the light-emitting element emits 950 Light according to Ids 951 ,
  • The above is the description of the method for driving the pixel circuit.
  • Next, a structural example of the semiconductor device in this embodiment will be described in FIG 23 shown. Note that, in this embodiment, a light-emitting element in the semiconductor device emits light to the upward-facing side of the semiconductor device; however, structures of semiconductor devices according to an embodiment of the present invention are not limited thereto. The semiconductor device may emit light to the base surface side or both the upwardly facing side and the base surface side.
  • A healer device in 23 includes a peripheral circuit section 981 where a power source circuit and a driver circuit such. B. a gate driver are provided, and a pixel portion 982 where pixel circuits are provided.
  • The semiconductor device in 23 includes conductive layers 962a and 962b , an insulating layer 963 , Semiconductor layers 964a and 964b , conductive layers 965a to 965d , an insulating layer 966 , an insulating layer 967 , conductive layers 968a and 968b , an insulating layer 969 a light-emitting layer 970 , a conductive layer 971 , a coloring layer 973 and insulating layers 974 . 975 and 976 ,
  • The conductive layers 962a and 962b are over a substrate 960 provided, wherein a base layer 961 lies in between.
  • In addition, the conductive layer 962a in the peripheral circuit section 981 intended. The conductive layer 962a For example, it serves as the gate of a transistor in the gate driver.
  • The conductive layer 962b is in the pixel section 982 intended. The conductive layer 962b For example, it serves as the gate of a transistor in the pixel circuit. The transistor in the pixel circuit corresponds, for example, to the transistor 955 the pixel circuit in 22A ,
  • The conductive layers 962a and 962b are formed, for example, by partially etching the same conductive film.
  • The insulating layer 963 is above the base layer 961 provided, wherein the conductive layers 962a and 962b lie in between. The insulating layer 963 serves as a gate insulating layer of the transistor in the peripheral circuit section 981 and as the gate insulating layer of the transistor in the pixel portion 982 ,
  • The semiconductor layer 964a has an area that is in contact with the conductive layer 962a so overlapped that the insulating layer 963 lies in between. The semiconductor layer 964a serves as a channel formation layer of the transistor in the peripheral circuit section 981 ,
  • The semiconductor layer 964b has an area that is in contact with the conductive layer 962b so overlapped that the insulating layer 963 lies in between. The semiconductor layer 964b serves as a channel formation layer of the transistor in the pixel portion 982 ,
  • Each of the conductive layers 965a and 965b is electrically connected to the semiconductor layer 964a connected. The conductive layer 965a serves as one of source and drain of the transistor in the peripheral circuit section 981 , and the senior layer 965b serves as the other of the source and drain of the transistor in the peripheral circuit section 981 ,
  • Each of the conductive layers 965c and 965d is electrically connected to the semiconductor layer 964b connected. The conductive layer 965c serves as one of the source and drain of the transistor in the pixel portion 982 , and the senior layer 965d serves as the other of the source and drain of the transistor in the pixel portion 982 ,
  • The insulating layer 966 is above the semiconductor layers 964a and 964b provided such that the conductive layers 965a to 965d lie in between. The insulating layer 966 serves as a protective layer.
  • The insulating layer 967 is over the insulating layer 966 intended. The insulating layer 967 serves as a planarization layer.
  • The conductive layer 968a overlaps with the semiconductor layer in this way 964a in that the insulating layers 966 and 967 lie in between. The conductive layer 968a serves as the back gate electrode of the transistor in the peripheral circuit section 981 ,
  • The conductive layer 968b is electrically conductive with the conductive layer 965d connected by an opening containing the insulating layers 966 and 967 penetrates. The conductive layer 968b serves as Anode electrode of a light-emitting element in the pixel portion 982 ,
  • The conductive layers 968a and 968b are formed, for example, by partially etching the same conductive film.
  • The insulating layer 969 is over the insulating layer 967 provided, wherein the conductive layer 968a lies in between.
  • The light-emitting layer 970 is electrically conductive with the conductive layer 968b connected in an opening containing the insulating layer 969 penetrates.
  • The conductive layer 971 is electrically connected to the light-emitting layer 970 connected. The conductive layer 971 serves as a cathode electrode of the light-emitting element in the pixel portion 982 ,
  • The coloring layer 973 is on a part of a substrate 972 in the pixel section 982 intended.
  • The insulating layer 974 is on a flat surface of the substrate 972 provided such that the coloring layer 973 lies in between. The insulating layer 974 serves as a planarization layer.
  • The insulating layer 975 is on a flat surface of the insulating layer 974 intended. The insulating layer 975 serves as a protective layer.
  • The insulating layer 976 is a layer for attaching the substrate 972 on the substrate 960 which is provided with the elements.
  • Further, components of the semiconductor device used in 23 are shown described. It should be noted that each layer may be a stack of a variety of materials.
  • As each of the substrates 960 and 972 For example, a glass substrate or a plastic substrate may be used. It should be noted that the substrates 960 and 972 are not necessarily provided.
  • As the base layer 961 For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, a gallium oxide film or the like may be used. For example, a silicon oxide film, a silicon oxynitride film, or the like may be used as the base film 961 be used. The above insulating layer may contain halogen. It should be noted that the base layer 961 is not necessarily provided.
  • The conductive layers 962a and 962b For example, may be a layer containing a metal material such. As molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, ruthenium or scandium.