JP2006215086A - Active matrix substrate and display device equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate reducing capacitance formed in the intersection of a scanning line and a signal line without increasing wiring line resistance and decreasing driving capability of a switching element, and also to provide a display device equipped with the same. <P>SOLUTION: The active matrix substrate of the invention comprises; a substrate 10, the scanning line 11 which is formed on the substrate 10; the signal line 13 which intersects the scanning line 11; a thin film transistor 14 which operates in response to the signal applied to the scanning line 11; and a pixel electrode 15 which is electrically connected to the signal line 13 via the thin film transistor 14. The signal lines 13 is composed of a conductive layer different from a source electrode 14S and a drain electrode 14D on an inter-layer insulating film 12 covering the thin film transistor 14 and electrically connected to the source electrode 14S via a contact hole 12' which is provided in the inter-layer insulating film 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix substrate used for a liquid crystal television, a liquid crystal monitor, a notebook personal computer and the like. The present invention also relates to a display device including an active matrix substrate.

  A liquid crystal display device has a feature that it is thin and has low power consumption, and is widely used in various fields. In particular, an active matrix liquid crystal display device including a switching element such as a thin film transistor (referred to as a “TFT”) for each pixel has a high contrast ratio, excellent response characteristics, and high performance. In recent years, the market has expanded.

  On the active matrix substrate used in the active matrix liquid crystal display device, a plurality of scanning wirings and a plurality of signal wirings intersecting these scanning wirings through an insulating film are formed. A thin film transistor for switching a pixel is provided in the vicinity of the intersection with.

  The capacitance formed at the intersection of the scanning wiring and the signal wiring (referred to as “parasitic capacitance”) causes a reduction in display quality, and therefore it is preferable that the capacitance value of the parasitic capacitance is small.

Therefore, Patent Document 1 discloses a method for reducing the area of the intersection and reducing the parasitic capacitance formed at the intersection by narrowing the widths of the scanning wiring and the signal wiring at the intersection. Is disclosed.
JP-A-5-61069

  However, reducing the width of the wiring, albeit locally, increases the resistance value of the wiring and causes signal rounding. Also, reducing the width of the wiring increases the probability of disconnection, so generally it is necessary to ensure about 50% of the original width. For this reason, there is a limit in reducing the parasitic capacitance at the intersection by the method of Patent Document 1. In recent years, liquid crystal display devices have been increased in size and definition, and in large-sized and high-definition liquid crystal display devices, the width of wiring has been widened to reduce wiring resistance, and there are many intersections of wiring. Therefore, the parasitic capacitance formed at the intersection increases. Therefore, the above-mentioned signal rounding becomes significant.

  As another method for reducing the capacitance generated at the intersection between the scanning wiring and the signal wiring, it is conceivable to increase the thickness of the insulating film covering the scanning wiring, but the scanning wiring is covered like a bottom gate type TFT. When a part of the insulating film functions as a gate insulating film, increasing the thickness of the insulating film causes a decrease in the driving capability of the TFT.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a capacitance formed at the intersection of the scanning wiring and the signal wiring without increasing the wiring resistance or decreasing the driving capability of the switching element. An active matrix substrate and a display device including the same are provided.

  An active matrix substrate according to the present invention includes a substrate, a plurality of scanning wirings formed on the substrate, a plurality of signal wirings intersecting the plurality of scanning wirings, and the corresponding scanning wirings formed on the substrate. Each of the plurality of thin film transistors, and a plurality of pixel electrodes that can be electrically connected to the corresponding signal wirings via the plurality of thin film transistors. Includes a gate electrode electrically connected to the corresponding scanning line, a source electrode electrically connected to the corresponding signal line, and a drain electrode electrically connected to the corresponding pixel electrode. An active matrix substrate, further comprising an interlayer insulating film formed to cover the plurality of thin film transistors; The wiring is formed on the interlayer insulating film from a conductive layer different from the source electrode and the drain electrode, and is electrically connected to the source electrode through a contact hole provided in the interlayer insulating film. This achieves the above object.

  In a preferred embodiment, the interlayer insulating film is made of an insulating material containing an organic component.

  In a preferred embodiment, the active matrix substrate according to the present invention has a gate insulating film formed so as to cover the gate electrode, the interlayer insulating film is thicker than the gate insulating film, and the gate The relative dielectric constant is lower than that of the insulating film.

  In a preferred embodiment, the thickness of the interlayer insulating film is not less than 1.0 μm and not more than 4.0 μm.

  In a preferred embodiment, the interlayer dielectric film has a relative dielectric constant of 4.0 or less.

  In a preferred embodiment, the interlayer insulating film is made of a spin-on glass (SOG) material having a Si—O—C bond as a skeleton.

  In a preferred embodiment, the interlayer insulating film is made of a spin-on glass (SOG) material having a Si—C bond as a skeleton.

  In a preferred embodiment, the interlayer insulating film is made of a spin-on glass (SOG) material containing a filler made of silica.

  In a preferred embodiment, the active matrix substrate according to the present invention has a further interlayer insulating film formed so as to cover the plurality of signal wirings, and the plurality of pixel electrodes are provided on the further interlayer insulating film. ing.

  In a preferred embodiment, an active matrix substrate according to the present invention has a plurality of pixel regions arranged in a matrix, and each of the plurality of pixel electrodes is provided in each of the plurality of pixel regions.

  In a preferred embodiment, an active matrix substrate according to the present invention is arranged around a display area defined by the plurality of pixel areas and a signal for driving the plurality of pixel areas. A non-display area provided with a plurality of terminals, and the interlayer insulating film is not substantially formed in the non-display area.

  A display device according to the present invention includes an active matrix substrate having the above-described configuration and a display medium layer disposed on the active matrix substrate, thereby achieving the above object.

  In a preferred embodiment, the display device according to the present invention further includes a counter substrate facing the active matrix substrate via the display medium layer, and the display medium layer is a liquid crystal layer.

  In the active matrix substrate according to the present invention, the signal wiring is formed of a conductive layer different from the source electrode and the drain electrode on the interlayer insulating film formed so as to cover the thin film transistor, and is provided in the interlayer insulating film. It is electrically connected to the source electrode through a contact hole. Since the interlayer insulating film located between the signal wiring and the scanning wiring does not function as a gate insulating film, the thin film transistor can be formed even if the interlayer insulating film is formed thick or made of a material having a low relative dielectric constant. The driving ability is not reduced. Therefore, according to the present invention, it is possible to reduce the capacitance formed at the intersection between the scanning wiring and the signal wiring without increasing the wiring resistance or decreasing the driving capability of the switching element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following embodiment.

  1 and 2 show a liquid crystal display device 100 according to this embodiment. FIG. 1 is a top view schematically showing one pixel region of the liquid crystal display device 100, and FIG. 2 is a cross-sectional view taken along line 2A-2A 'in FIG.

  The liquid crystal display device 100 includes an active matrix substrate (hereinafter referred to as “TFT substrate”) 100a, a counter substrate (also referred to as “color filter substrate”) 100b facing the TFT substrate 100a, and a liquid crystal provided therebetween. Layer 60.

  The TFT substrate 100 a includes a transparent insulating substrate (for example, a glass substrate) 10, a plurality of scanning wirings 11 formed on the substrate 10, and a plurality of signal wirings 13 that intersect the scanning wirings 11.

  In each pixel region of the TFT substrate 100a, a thin film transistor (TFT) 14 that operates in response to a signal applied to the corresponding scanning line 11, and a pixel that can be electrically connected to the corresponding signal line 13 via the TFT 14. An electrode 15 is provided.

  The counter substrate 100 b includes a transparent insulating substrate (for example, a glass substrate) 50 and a counter electrode 51 that is formed on the substrate 50 and faces the pixel electrode 15. Typically, the counter substrate 100b further includes a color filter (not shown here).

  The liquid crystal layer 60 changes its orientation state in accordance with the voltage applied between the pixel electrode 15 and the counter electrode 51, and thereby displays light by modulating the light passing through the liquid crystal layer 60. As the liquid crystal layer 60, liquid crystal layers for various display modes can be widely used. For example, a TN (Twisted Nematic) mode liquid crystal layer utilizing optical rotation or an ECB (Electrically Controlled Birefringence) mode liquid crystal layer utilizing birefringence can be used. Among the ECB modes, the VA (Vertically Aligned) mode can realize a high contrast ratio. The VA mode liquid crystal layer is typically obtained by providing vertical alignment layers on both sides of a liquid crystal layer containing a liquid crystal material having negative dielectric anisotropy.

  Hereinafter, the configuration of the TFT substrate 100a will be described in more detail with reference to FIGS. 3 (a) to 3 (c). 3A to 3C are cross-sectional views taken along lines 3A-3A ', 3B-3B', and 3C-3C 'in FIG. 1, respectively.

  The TFT 14 included in the TFT substrate 100a in the present embodiment is a bottom gate type (also referred to as an inverted stagger type) amorphous silicon TFT. As shown in FIG. 3A, the TFT 14 includes a gate electrode 14G electrically connected to the scanning wiring 11, a gate insulating film 16 covering the gate electrode 14G, and the gate electrode 14G via the gate insulating film 16. It has a semiconductor layer (intrinsic semiconductor layer) 17 formed above, and a source electrode 14S and a drain electrode 14D formed on the semiconductor layer 17. The source region and the drain region of the semiconductor layer 17 are electrically connected to the source electrode 14S and the drain electrode 14D, respectively, via an impurity-added semiconductor layer 18 that functions as a contact layer.

  Further, as shown in FIG. 3B, the TFT substrate 100 a includes an auxiliary capacitance line 20 formed on the substrate 10 and an auxiliary capacitance electrode 21 that faces the auxiliary capacitance line 20 through the gate insulating film 16. Have. The auxiliary capacitance is constituted by the auxiliary capacitance line 20 and the auxiliary capacitance electrode 21 and the gate insulating film 16 located between them. The auxiliary capacitance line 20 is formed by patterning the same conductive film as the scanning line 13 and the gate electrode 14G. On the other hand, the auxiliary capacitance electrode 21 is formed by patterning the same conductive film as the source electrode 14S and the drain electrode 14D.

  An interlayer insulating film 12 is formed so as to cover the TFT 14 described above. The interlayer insulating film 12 also functions as a protective film for the channel portion of the TFT. As shown in FIG. 3C, the signal wiring 13 is provided on the interlayer insulating film 12, and is formed of a conductive layer different from the source electrode 14S and the drain electrode 14D. As shown in FIG. 3A, the signal wiring 13 is electrically connected to the source electrode 14 </ b> S through a contact hole 12 ′ provided in the interlayer insulating film 12.

  A further insulating film 19 is formed so as to cover the signal wiring 13, and the pixel electrode 15 is formed on the interlayer insulating film 19. The pixel electrode 15 is connected to the auxiliary capacitance electrode 21 in a contact hole 19 ′ provided in the interlayer insulating film 19, and is electrically connected to the drain electrode 14 </ b> D of the TFT 14 through the auxiliary capacitance electrode 21.

  Here, FIGS. 9 and 10A to 10C show the structure of a conventional TFT substrate 700a having a bottom gate type TFT. In the conventional TFT substrate 700a, the signal wiring 713 is formed by patterning the same conductive film as the source electrode 714S and the drain electrode 714D of the TFT 714, and the gate insulating film 716 is formed as shown in FIG. Via the scanning wiring 711. Therefore, if the gate insulating film 716 is formed thick in order to reduce the capacitance formed at the intersection between the scanning wiring 711 and the signal wiring 713, the driving capability of the TFT 14 is lowered. As shown in FIG. 10B, the gate insulating film 716 is located between the auxiliary capacitance line 720 and the auxiliary capacitance electrode 721, and also functions as a dielectric film for the auxiliary capacitance. Therefore, when the gate insulating film 716 is formed thick, the capacitance value of the auxiliary capacitor is also reduced.

  On the other hand, in the TFT substrate 100a in this embodiment, the signal wiring 13 is provided on the interlayer insulating film 12 covering the TFT 14, and is formed of a conductive layer different from the source electrode 14S and the drain electrode 14D. Since the interlayer insulating film 12 located between the signal wiring 13 and the scanning wiring 11 does not function as a gate insulating film or a dielectric film for an auxiliary capacitor, the interlayer insulating film 12 is formed thick or the interlayer insulating film 12 Even if it is made of a material having a low relative dielectric constant, the driving ability of the TFT 14 and the capacitance value of the auxiliary capacitor are not reduced. Therefore, in the TFT substrate 100a according to the present embodiment, the capacitance formed at the intersection of the scanning wiring 11 and the signal wiring 13 can be reduced without lowering the driving capability of the TFT 14 or lowering the capacitance value of the auxiliary capacitance. it can.

  In order to sufficiently reduce the capacitance at the intersection of the scanning wiring 11 and the signal wiring 13, the interlayer insulating film 12 is preferably thicker than the gate insulating film 16 and has a lower relative dielectric constant than the gate insulating film 16. It is preferable. The gate insulating film 16 typically has a thickness of about 0.2 μm to 0.4 μm and a relative dielectric constant of about 5.0 to 8.0. On the other hand, the thickness of the interlayer insulating film 12 is preferably 1.0 μm or more and 4.0 μm or less, and the relative dielectric constant of the interlayer insulating film 12 is preferably 4.0 or less.

The gate insulating film 16 is typically formed from an inorganic insulating material such as SiN _x or SiO _x . On the other hand, the interlayer insulating film 12 is preferably formed of an insulating material containing an organic component. As a material of the interlayer insulating film 12, a spin-on glass material containing an organic component (so-called organic SOG material) can be preferably used. In particular, an SOG material having a Si—O—C bond as a skeleton, or a Si—C bond. An SOG material having a skeleton can be preferably used.

  The SOG material is a material that can form a glass film (silica-based film) by a coating method such as a spin coating method. Since the organic SOG material has a low relative dielectric constant and it is easy to form a thick film, by using the organic SOG material, the relative dielectric constant of the interlayer insulating film 12 can be reduced and the interlayer insulating film 12 can be formed thick. Becomes easy.

  As the SOG material having a Si—O—C bond as a skeleton, for example, materials disclosed in JP-A-2001-98224 and JP-A-6-240455 can be used. In addition, as the SOG material having a Si—C bond as a skeleton, for example, a material disclosed in Japanese Patent Laid-Open No. 10-102003 can be used.

  Next, an example of a manufacturing method of the TFT substrate 100a will be described with reference to FIGS. 4 (a) to 4 (e) and FIGS. 5 (a) to 5 (d).

  First, as shown in FIG. 4A, a metal film is deposited on an insulating substrate 10 such as a glass substrate by a sputtering method, and this metal film is patterned to scan the wiring 11 (not shown here). Then, the gate electrode 14G and the auxiliary capacitance line 20 (not shown here) are formed. For example, Al or an Al alloy is used as the material of the scanning wiring 11. The scanning wiring 11 may be a laminated film such as TaN / Ta / TaN, Ti / Al / Ti, Mo / Al / Mo, and Mo / Al.

Next, as shown in FIG. 4B, after the SiN _x film, the amorphous silicon (a-Si) film, and the n ⁺ amorphous silicon (n ⁺ a-Si) film are successively deposited using the CVD method. By patterning the a-Si film and the n ⁺ a-Si film, the gate insulating film 16 and an island-shaped semiconductor structure (semiconductor active layer region) composed of the intrinsic semiconductor layer 17 and the impurity-added semiconductor layer 18 are formed. Form.

  Subsequently, as shown in FIG. 4C, after depositing a metal film using a sputtering method, the metal film is patterned to thereby form a source electrode 14S, a drain electrode 14D, and an auxiliary capacitance electrode 21 (not shown here). ). As a material of the source electrode 14S and the drain electrode 14D, for example, Ti, Mo, or Cr is used. Alternatively, a laminated film such as Mo / Al / Mo or Al / Ti may be used.

  Thereafter, as shown in FIG. 4D, using the source electrode 14S and the drain electrode 14D as a mask, a part of the impurity-added semiconductor layer 18 (portion located on the channel region) is removed by dry etching. Note that when the impurity-added semiconductor layer 18 is removed, the surface of the intrinsic semiconductor layer 17 is also thinly etched.

  Next, as shown in FIG. 4E, an organic SOG material is applied onto the substrate 10 using a spin coat method or a slit coat method, followed by baking to form an interlayer insulating layer 12. For example, an organic SOG material is applied to a thickness of about 3.0 μm and baked at 350 ° C. for 30 minutes.

  Subsequently, as shown in FIG. 5A, a contact hole 12 'is formed in a portion overlapping the source electrode 14S of the interlayer insulating layer 12 by photolithography and dry etching. In the case where the organic SOG material has photosensitivity, the contact hole 12 'can be formed only by photolithography, so that the etching process can be omitted.

  Next, as shown in FIG. 5B, a signal film 13 is formed by depositing a metal film by sputtering and then patterning the metal film. As a material of the signal wiring 13, for example, Al or an Al alloy is used. In addition, the signal wiring 13 may be a laminated film of Ta / TaN, Al / Mo, Mo / Al / Mo, or the like, without being limited thereto.

  Subsequently, as shown in FIG. 5C, a further interlayer insulating film 19 is formed so as to cover almost the entire surface of the substrate 10. As a material of the interlayer insulating film 19, for example, an acrylic resin can be used, and the thickness of the interlayer insulating film 19 is, for example, 1.0 μm to 4.0 μm. A contact hole 19 ′ is formed in a portion of the interlayer insulating film 19 that overlaps the auxiliary capacitance electrode 21 (see FIG. 3B).

  Finally, as shown in FIG. 5D, a pixel electrode 15 is formed by forming a film made of a transparent conductive material such as ITO by sputtering and patterning the transparent conductive film.

As described above, the TFT substrate 100a is completed. In the TFT substrate 100 a of this embodiment, a gate insulating film 16 and an interlayer insulating film 12 are interposed between the scanning wiring 11 and the signal wiring 13. Therefore, for example, when the gate insulating film 16 having a thickness of 0.5 μm and a relative dielectric constant of 6.9 and the interlayer insulating layer 12 having a thickness of 1.5 μm and a relative dielectric constant of 3.0 are formed, the scanning wiring 11 and the signal The capacitance value per unit area of the capacitance formed at the intersection with the wiring 13 is 1.5 × 10 ⁻⁵ pF / μm ² . On the other hand, in the conventional active matrix substrate shown in FIGS. 9 and 10, since only the gate insulating film 716 is located between the scanning wiring 711 and the signal wiring 713, for example, a thickness of 0.5 μm, When the gate insulating film 716 having a relative dielectric constant of 6.9 is formed, the capacitance value per unit area is 1.2 × 10 ⁻⁴ pF / μm ² . Therefore, by adopting the configuration of this embodiment, the value of the capacitance formed at the intersection is reduced to 1/8 or less of the conventional value.

Note that a film formed from an organic SOG material is generally less susceptible to mechanical stress and thermal stress and is likely to generate cracks than an inorganic insulating film formed from SiN _x or the like. Therefore, when the interlayer insulating film 12 is formed from an organic SOG material, the interlayer insulating film 12 may not be substantially formed in the non-display region 2 as shown in FIG. preferable.

  The non-display area 2 is arranged around the display area 1 defined by a plurality of pixel areas arranged in a matrix and is also called a frame area. The non-display area 2 is provided with a plurality of terminals to which signals for driving the pixel area are input, and a gate driver 30 and a source driver 40 are connected to these terminals. Since stress is easily applied to the non-display area 2 in the mounting process and the substrate cutting process, the generation of cracks can be suppressed by not forming the interlayer insulating film 12 in the non-display area 2.

  Further, the above-described cracks are more likely to occur as the interlayer insulating film 12 becomes thicker and the substrate becomes larger. The inventor of the present application has conducted a detailed study on the relationship between the generation of cracks and the material of the interlayer insulating film 12, and suppresses the generation of cracks by using an SOG material containing a filler (silica filler) formed from silica. It was found that it is easy to form the interlayer insulating film 12 thick on a large-sized active matrix substrate.

  FIG. 7 schematically shows a cross-sectional structure of the interlayer insulating film 12 formed from an organic SOG material containing a silica filler. As shown in FIG. 7, the interlayer insulating film 12 has a configuration in which a silica filler 12b is dispersed in a matrix (base material) 12a formed of an organic SOG material. When such a configuration is used, since the generation of cracks is suppressed by the silica filler 12b relieving stress, it is easy to increase the thickness of the interlayer insulating film 12 in a large substrate. The particle diameter of the silica filler 12b is typically 10 nm to 30 nm, and the mixing ratio of the silica filler 12b in the interlayer insulating film 12 is typically 20% by volume to 80% by volume.

  Table 1 shows the results of evaluating crack resistance of an organic SOG film containing a silica filler and an organic SOG film not containing a silica filler. Note that a glass substrate (Corning 1737) having a size of 360 mm × 465 mm was used as the sample substrate. The crack resistance evaluation was performed according to the procedure shown in FIG. Specifically, first, an SOG material is applied on the sample substrate, and then prebaking is performed at 180 ° C. for 4 minutes. Subsequently, an SOG film is formed by performing post-baking at 350 ° C. for 1 hour in a nitrogen atmosphere, and then the substrate on which the SOG film is formed is held at 350 ° C. for 1 hour in a nitrogen atmosphere and then rapidly cooled. A thermal cycle test was conducted.

  As shown in Table 1, when there is no filler, cracks may occur when the film thickness is 1.5 μm or more, whereas when there is a filler, the film thickness is 3.0 μm. The generation of cracks could be suppressed.

  According to the present invention, there is provided an active matrix substrate capable of reducing the capacitance formed at the intersection of the scanning wiring and the signal wiring without increasing the wiring resistance or decreasing the driving capability of the switching element. .

  The active matrix substrate according to the present invention is suitably used for various display devices such as liquid crystal display devices and organic EL display devices.

It is a top view which shows typically the liquid crystal display device 100 in suitable embodiment of this invention. It is sectional drawing which shows typically the liquid crystal display device 100 in suitable embodiment of this invention, and is a figure which shows the cross section along line 2A-2A 'in FIG. (A)-(c) is sectional drawing which shows typically the TFT substrate 100a with which the liquid crystal display device 100 is provided, 3A-3A 'line | wire, 3B-3B' line | wire, and 3C-3C 'line | wire in FIG. 1, respectively. It is a figure which shows the cross section along line. (A)-(e) is process sectional drawing which shows the manufacturing process of TFT substrate 100a typically. (A)-(d) is process sectional drawing which shows the manufacturing process of TFT substrate 100a typically. It is a top view which shows TFT substrate 100a typically. It is sectional drawing which shows typically the interlayer insulation film 12 formed from the organic SOG material containing a silica filler. It is a flowchart which shows the procedure of crack-proof evaluation. It is a top view which shows typically the conventional active matrix substrate 700a provided with the bottom gate type amorphous silicon TFT. (A)-(c) is sectional drawing which shows the conventional active matrix board | substrate 700a typically, and each followed the 10A-10A 'line | wire, 10B-10B' line | wire, and 10C-10C 'line | wire in FIG. It is a figure which shows a cross section.

Explanation of symbols

1 Display area 2 Non-display area (frame area)
10 Substrate (transparent insulating substrate)
11 Scanning wiring 12 Interlayer insulating film 12a Base material (matrix)
12b Silica filler 12 'Contact hole 13 Scanning wiring 14 Thin film transistor (TFT)
14G gate electrode 14S source electrode 14D drain electrode 15 pixel electrode 16 gate insulating film 17 semiconductor layer (intrinsic semiconductor layer)
DESCRIPTION OF SYMBOLS 18 Impurity-added semiconductor layer 19 Interlayer insulation film 19 'Contact hole 20 Auxiliary capacitance wiring 21 Auxiliary capacitance electrode 30 Gate driver 40 Source driver 60 Liquid crystal layer 100 Liquid crystal display device 100a Active matrix substrate (TFT substrate)
100b Counter substrate (color filter substrate)

Claims (13)

A substrate,
A plurality of scanning wirings formed on the substrate;
A plurality of signal lines crossing the plurality of scanning lines;
A plurality of thin film transistors formed on the substrate and operating in response to a signal applied to the corresponding scan wiring;
A plurality of pixel electrodes that can be electrically connected to the corresponding signal wirings via the plurality of thin film transistors;
Each of the plurality of thin film transistors is electrically connected to the corresponding gate electrode, the source electrode electrically connected to the corresponding signal line, and the corresponding pixel electrode. An active matrix substrate having a drain electrode formed thereon,
An interlayer insulating film formed to cover the plurality of thin film transistors;
The plurality of signal wirings are formed on the interlayer insulating film from a conductive layer different from the source electrode and the drain electrode, and are electrically connected to the source electrode through a contact hole provided in the interlayer insulating film. An active matrix substrate connected to the substrate.   The active matrix substrate according to claim 1, wherein the interlayer insulating film is formed of an insulating material containing an organic component. A gate insulating film formed to cover the gate electrode;
The active matrix substrate according to claim 1, wherein the interlayer insulating film is thicker than the gate insulating film and has a relative dielectric constant lower than that of the gate insulating film.   4. The active matrix substrate according to claim 1, wherein a thickness of the interlayer insulating film is not less than 1.0 μm and not more than 4.0 μm.   The active matrix substrate according to claim 1, wherein the interlayer dielectric film has a relative dielectric constant of 4.0 or less.   6. The active matrix substrate according to claim 1, wherein the interlayer insulating film is formed of a spin-on glass (SOG) material having a Si—O—C bond as a skeleton.   The active matrix substrate according to claim 1, wherein the interlayer insulating film is formed of a spin-on glass (SOG) material having a Si—C bond as a skeleton.   The active matrix substrate according to claim 1, wherein the interlayer insulating film is formed of a spin-on glass (SOG) material including a filler formed of silica. A further interlayer insulating film formed to cover the plurality of signal wirings;
The active matrix substrate according to claim 1, wherein the plurality of pixel electrodes are provided on the further interlayer insulating film.   10. The active matrix substrate according to claim 1, comprising a plurality of pixel regions arranged in a matrix, wherein each of the plurality of pixel electrodes is provided in each of the plurality of pixel regions. A display area defined by the plurality of pixel areas; and a non-display area provided around the display area and provided with a plurality of terminals to which signals for driving the plurality of pixel areas are input. ,
The active matrix substrate according to claim 10, wherein the interlayer insulating film is not substantially formed in the non-display region.   A display device comprising: the active matrix substrate according to claim 1; and a display medium layer disposed on the active matrix substrate.   The display device according to claim 12, further comprising a counter substrate facing the active matrix substrate via the display medium layer, wherein the display medium layer is a liquid crystal layer.

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