JP2007225860A - Active matrix substrate and liquid crystal display equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate in which the capacitance formed on intersections of scanning wires and signal wires is reduced and which has auxiliary capacitors with sufficiently large capacitance mounted thereon, without lowering the numerical aperture, and to provide a liquid crystal display device equipped with the same. <P>SOLUTION: The active matrix substrate is equipped with an insulating substrate 10; the scanning wires 11 and auxiliary capacitor wires 20 formed on the insulating substrate 10; an insulating film 12 for coating the scanning wires 11 and the auxiliary capacitor wires 20; and signal wires 13 intersecting the scanning wires 11 via the insulating film 12. The insulating film 12 is a multilayer insulating film, including a first insulating layer 12a formed of an insulating material containing an organic component, and a second insulating layer 12b formed of an inorganic insulating material. A region 12R, in which the number of laminated layers is reduced and on which the first insulating layer 12a is not formed, is located on at least one section of a region overlapping with a shield electrode 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix substrate used for a liquid crystal television, a liquid crystal monitor, a notebook personal computer and the like. The present invention also relates to a liquid crystal display device including an active matrix substrate.

  A liquid crystal display device has a feature that it is thin and has low power consumption, and is widely used in various fields. In particular, an active matrix liquid crystal display device including a switching element such as a thin film transistor (referred to as a “TFT”) for each pixel has a high contrast ratio, excellent response characteristics, and high performance. In recent years, the market has expanded.

  On the active matrix substrate used in the active matrix liquid crystal display device, a plurality of scanning wirings and a plurality of signal wirings intersecting these scanning wirings through an insulating film are formed. A thin film transistor for switching a pixel is provided in the vicinity of the intersection with.

  The capacitance formed at the intersection of the scanning wiring and the signal wiring (referred to as “parasitic capacitance”) causes a reduction in display quality, and therefore it is preferable that the capacitance value of the parasitic capacitance is small.

  Therefore, Patent Document 1 discloses a method for reducing the area of the intersection and reducing the parasitic capacitance formed at the intersection by narrowing the widths of the scanning wiring and the signal wiring at the intersection. Is disclosed.

  However, reducing the width of the wiring, albeit locally, increases the resistance value of the wiring and causes signal rounding. Also, reducing the width of the wiring increases the probability of disconnection, so generally it is necessary to ensure about 50% of the original width. For this reason, there is a limit in reducing the parasitic capacitance at the intersection by the method of Patent Document 1. In recent years, liquid crystal display devices have been increased in size and definition, and in large-sized and high-definition liquid crystal display devices, the width of wiring has been widened to reduce wiring resistance, and there are many intersections of wiring. Therefore, the parasitic capacitance formed at the intersection increases. Therefore, the above-mentioned signal rounding becomes significant.

  As another method for reducing the capacitance generated at the intersection between the scanning wiring and the signal wiring, it is conceivable to increase the thickness of the insulating film covering the scanning wiring. However, when a part of the insulating film covering the scanning wiring functions as a dielectric film constituting the auxiliary capacitance, increasing the thickness of the insulating film causes a reduction in the capacitance value of the auxiliary capacitance, thereby reducing the display quality. End up.

In Patent Document 2, two layers of silicon oxide films are stacked at the intersection of the scanning wiring and the signal wiring in order to prevent insulation failure at the intersection of the wiring without reducing the capacitance value of the auxiliary capacitor. In this part, an active matrix substrate in which a single-layer silicon oxide film is disposed is disclosed. By adopting such a configuration, it is possible to reduce the parasitic capacitance formed at the intersection between the scanning wiring and the signal wiring without reducing the capacitance value of the auxiliary capacitance.
JP-A-5-61069 Japanese Examined Patent Publication No. 6-56461

  However, even if the configuration disclosed in Patent Document 2 is used, it is difficult to realize a sufficiently large capacitance value, and it is necessary to provide a large-area auxiliary capacitor by increasing the width of the auxiliary capacitor line. . Since the auxiliary capacitor typically includes a light-shielding member, increasing the area of the auxiliary capacitor causes a decrease in the aperture ratio.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the capacitance formed at the intersection of the scanning wiring and the signal wiring, and sufficiently increase the capacitance without reducing the aperture ratio. An object of the present invention is to provide an active matrix substrate capable of providing an auxiliary capacitor having a value and a liquid crystal display device including the same.

  An active matrix substrate according to the present invention includes an insulating substrate, a plurality of scanning wires and a plurality of auxiliary capacitance wires formed on the insulating substrate, and an insulating film covering the plurality of scanning wires and the plurality of auxiliary capacitance wires. A plurality of signal wirings intersecting with the plurality of scanning wirings through the insulating film, and a plurality of shield electrodes formed from the same conductive film as the plurality of scanning wirings and extending substantially parallel to the plurality of signal wirings A plurality of switching elements which are provided on the insulating substrate and operate in response to a signal applied to the corresponding scanning wiring; and the corresponding signal wiring electrically through the plurality of switching elements. An active matrix substrate comprising a plurality of pixel electrodes that can be connected, wherein the insulating film comprises a first insulating layer formed of an insulating material containing an organic component, and an inorganic insulating material A multilayer insulating film including a second insulating layer formed of a material, wherein the multilayer insulating film has a low stacked region in which the first insulating layer is not formed in at least a part of the region overlapping the shield electrode. Thereby achieving the above objective.

  In a preferred embodiment, the multilayer insulating film has the low stacked region in a part of a region overlapping with the signal wiring.

  In a preferred embodiment, the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the storage capacitor wiring.

  In a preferred embodiment, the multilayer insulating film has the low lamination region in at least a part of a region overlapping with the switching element.

  In a preferred embodiment, each of the plurality of switching elements is electrically connected to a semiconductor layer including a channel region, a gate electrode electrically connected to the corresponding scan line, and a corresponding signal line. A thin film transistor having a source electrode and a drain electrode electrically connected to the corresponding pixel electrode.

  In a preferred embodiment, the multilayer insulating film has the low stacked region in a region overlapping at least the channel region.

  In a preferred embodiment, the first insulating layer is made of an SOG material.

  A liquid crystal display device according to the present invention includes an active matrix substrate having the above-described configuration, a counter substrate facing the active matrix substrate, and a liquid crystal layer provided between the active matrix substrate and the counter substrate. This achieves the above object.

  In a preferred embodiment, the counter substrate has alignment regulating means for controlling the alignment of the liquid crystal layer, and the auxiliary capacitance wiring of the active matrix substrate branches so as to overlap the alignment regulating means. The multi-layer insulating film has a branch portion, and the multilayer insulating film also has the low lamination region in at least a part of a region overlapping the branch portion.

  Alternatively, the liquid crystal display device according to the present invention includes an active matrix substrate having a plurality of switching elements, a counter substrate facing the active matrix substrate, and a liquid crystal layer provided between the active matrix substrate and the counter substrate. The active matrix substrate includes an insulating substrate, a plurality of scanning wirings and a plurality of auxiliary capacitance wirings formed on the insulating substrate, the plurality of scanning wirings and the plurality of scanning wirings. Electrically connected to the corresponding signal wiring via the plurality of switching elements, an insulating film covering the auxiliary capacitance wiring, a plurality of signal wirings intersecting the plurality of scanning wirings via the insulating film, and the plurality of switching elements. A plurality of pixel electrodes to be obtained, wherein the insulating film includes a first insulating layer formed of an insulating material containing an organic component, and an inorganic insulating material. And a second insulating layer formed from a material, wherein the counter substrate has alignment regulating means for controlling the alignment of the liquid crystal layer, and the auxiliary capacitance wiring is formed by the alignment regulating means. The multilayer insulating film has the low stacked region in which the first insulating layer is not formed in at least a part of the region overlapping with the branched portion, This achieves the above object.

  In a preferred embodiment, the multilayer insulating film has the low stacked region in a part of a region overlapping with the signal wiring.

  In a preferred embodiment, the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the storage capacitor wiring.

  In a preferred embodiment, the multilayer insulating film has the low lamination region in at least a part of a region overlapping with the switching element.

  In a preferred embodiment, the first insulating layer is made of an SOG material.

  According to the present invention, it is possible to reduce the capacitance formed at the intersection between the scanning wiring and the signal wiring, and to provide the auxiliary capacitance having a sufficiently large capacitance value without reducing the aperture ratio.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following embodiment.

(Embodiment 1)
1 and 2 show a liquid crystal display device 100 according to this embodiment. FIG. 1 is a top view schematically showing one pixel region of the liquid crystal display device 100, and FIG. 2 is a cross-sectional view taken along line 2A-2A ′ in FIG.

  The liquid crystal display device 100 includes an active matrix substrate (hereinafter referred to as “TFT substrate”) 100a, a counter substrate (also referred to as “color filter substrate”) 100b facing the TFT substrate 100a, and a liquid crystal provided therebetween. Layer 60.

  The TFT substrate 100 a includes a transparent insulating substrate (for example, a glass substrate) 10, a plurality of scanning wirings 11 formed on the substrate 10, an insulating film 12 covering these scanning wirings 11, and an insulating film 12. A plurality of signal wirings 13 intersecting the scanning wirings 11 are provided.

  Furthermore, the TFT substrate 100a is electrically connected to the corresponding thin film transistor (TFT) 14 that operates in response to a signal applied to the corresponding scanning line 11 and the corresponding signal line 13 via the switching element TFT 14 for each pixel region. And a pixel electrode 15 that can be connected to each other.

  The counter substrate 100 b includes a transparent insulating substrate (for example, a glass substrate) 50 and a counter electrode 51 that is formed on the substrate 50 and faces the pixel electrode 15. Typically, the counter substrate 100b further includes a color filter.

  The liquid crystal layer 60 changes its orientation state in accordance with the voltage applied between the pixel electrode 15 and the counter electrode 51, and thereby displays light by modulating the light passing through the liquid crystal layer 60. As the liquid crystal layer 60, liquid crystal layers for various display modes can be widely used. For example, a TN (Twisted Nematic) mode liquid crystal layer utilizing optical rotation or an ECB (Electrically Controlled Birefringence) mode liquid crystal layer utilizing birefringence can be used. Among the ECB modes, the VA (Vertically Aligned) mode can realize a high contrast ratio. The VA mode liquid crystal layer is typically obtained by providing vertical alignment layers on both sides of a liquid crystal layer containing a liquid crystal material having negative dielectric anisotropy.

  Hereinafter, the configuration of the TFT substrate 100a will be described in more detail with reference to FIGS. 3 (a) to 3 (d). 3 (a), (b), (c) and (d) are taken along lines 3A-3A ′, 3B-3B ′, 3C-3C ′ and 3D-3D ′ in FIG. 1, respectively. It is sectional drawing.

  As shown in FIG. 3A, the TFT 14 of the TFT substrate 100a includes a gate electrode 14G electrically connected to the scanning wiring 11, a source electrode 14S electrically connected to the signal wiring 13, and a pixel electrode 15. The drain electrode 14D is electrically connected to the drain electrode 14D. The TFT 14 has a stacked structure in which a gate electrode 14G, a gate insulating film 16, an intrinsic semiconductor layer (hereinafter also simply referred to as “semiconductor layer”) 17, and an impurity-added semiconductor layer 18 are sequentially stacked from the lower layer. The source region 17a and the drain region 17b of the semiconductor layer 17 are electrically connected to the source electrode 14S and the drain electrode 14D through the impurity-added semiconductor layer 18 that functions as a contact layer. Of the semiconductor layer 17, a region between the source region 17a and the drain region 17b functions as a channel region 17c, and the impurity-doped semiconductor layer 18 does not exist on the upper surface of the channel region 17c.

  As shown in FIG. 3B, the TFT substrate 100a includes a plurality of auxiliary capacitance lines 20 formed on the substrate 10 and a plurality of auxiliary capacitance lines 20 facing the plurality of auxiliary capacitance lines 20 with an insulating film 12 therebetween. The capacitor electrode 21 is further included. The auxiliary capacitance line 20 is formed by patterning the same conductive film as the scanning line 11 and the gate electrode 14G. The auxiliary capacitance electrode 21 is formed by patterning the same conductive film as the signal wiring 13, the source electrode 14S, and the drain electrode 14D. As shown in FIG. 1, a conductive member 22 extended from the drain electrode 14D is provided. And is electrically connected to the drain electrode 14D of the TFT 14.

  A protective insulating film 19 is formed so as to cover the TFT 14 and the signal wiring 13 described above, and the pixel electrode 15 is formed on the protective insulating film 19. As illustrated in FIG. 1, the pixel electrode 15 is electrically connected to the drain electrode 14 </ b> D of the TFT 14 in a contact hole 19 ′ formed in the protective insulating film 19.

In the TFT substrate 100a in this embodiment, as shown in FIG. 3C, the insulating film 12 covering the scanning wiring 11 is a multilayer insulating film including a first insulating layer 12a and a second insulating layer 12b. The first insulating layer 12a is formed below the second insulating layer 12b and is formed of an insulating material containing an organic component. On the other hand, the second insulating layer 12b is formed of an inorganic insulating material such as SiN _x or SiO _x .

  As shown in FIG. 3C, the first insulating layer 12a is formed on most of the substrate 10 including the intersection of the scanning wiring 11 and the signal wiring 13, but is shown in FIG. Thus, it is not formed in a part of the region where the insulating film 12 and the TFT 14 overlap. On the other hand, the second insulating layer 12b is formed on substantially the entire surface of the substrate 10, and is also formed in a portion where the insulating film 12 and the TFT 14 overlap. A portion of the second insulating layer 12b located between the gate electrode 14G and the semiconductor layer 17 functions as the gate insulating film 16.

  As described above, the multilayer insulating film 12 has a low stacked region 12R (shown as a region surrounded by a broken line in FIG. 1) in which the first insulating layer 12a is not formed. In the present embodiment, the multilayer insulating film 12 has a low stacked region 12R in a region overlapping the channel region 17c of the TFT 14.

  Further, as shown in FIG. 3B, the first insulating layer 12a is not formed between the auxiliary capacitance line 20 and the auxiliary capacitance electrode 21, and only the second insulating layer 12b is used for the auxiliary capacitance. It functions as a dielectric film. That is, the multilayer insulating film 12 also has the low stacked region 12R in a part of the region overlapping the auxiliary capacitance line 20 (specifically, between the auxiliary capacitance line 20 and the auxiliary capacitance electrode 21). The wiring 20 and the auxiliary capacitance electrode 21 and the second insulating layer 12b positioned therebetween constitute an auxiliary capacitance.

  In the TFT substrate 100a in the present embodiment, as described above, the insulating film 12 covering the scanning wiring 11 is a multilayer insulating film including the first insulating layer 12a and the second insulating layer 12b, and this multilayer insulating film 12 has a low lamination region 12R in which the first insulating layer 12a is not formed between the region overlapping the TFT 14 and between the auxiliary capacitance line 20 and the auxiliary capacitance electrode 21. Therefore, it is possible to reduce the capacitance formed at the intersection between the scanning wiring 11 and the signal wiring 13 without lowering the driving capability of the TFT 14 or lowering the capacitance value of the auxiliary capacitance.

  In order to sufficiently reduce the capacitance at the intersection of the scanning wiring 11 and the signal wiring 13, the first insulating layer 12a is preferably thicker than the second insulating layer 12b and has a relative dielectric constant than the second insulating layer 12b. A low rate is preferred.

  The second insulating layer 12b that also functions as the gate insulating film 16 typically has a thickness of about 0.2 μm to 0.4 μm and a relative dielectric constant of about 5.0 to 8.0. ing. On the other hand, the thickness of the first insulating layer 12a is preferably 0.5 μm or more and 4.0 μm or less, and the relative dielectric constant of the first insulating layer 12a is preferably 4.0 or less.

  As a material of the first insulating layer 12a, a spin-on glass material (SOG material) can be suitably used. The SOG material is a material that can form a glass film (silica-based film) by a coating method such as a spin coating method. In particular, an organic SOG material having a Si—O—C bond as a skeleton or an organic SOG material having a Si—C bond as a skeleton can be preferably used. Since the organic SOG material has a low relative dielectric constant and it is easy to form a thick film, by using the organic SOG material, the relative dielectric constant of the first insulating layer 12a is reduced and the first insulating layer 12a is formed thick. Easy to do. Examples of the SOG material having a Si—O—C bond as a skeleton include materials disclosed in Japanese Patent Application Laid-Open No. 2001-98224 and Japanese Patent Application Laid-Open No. Hei 6-240455, and disclosed in page 617 of IDW'03 Proceedings. DD1100 manufactured by Toray Dow Corning Silicone Co., Ltd. can be used. In addition, as the SOG material having a Si—C bond as a skeleton, for example, a material disclosed in Japanese Patent Laid-Open No. 10-102003 can be used.

  Furthermore, the TFT substrate 100a in this embodiment has a plurality of shield electrodes 23 extending substantially in parallel with the signal wirings 13, as shown in FIGS. The shield electrode 23 is formed by patterning the same conductive film as the scanning wiring 11. The shield electrode 23 is connected to the auxiliary capacitance line 20 and is given a constant potential. Here, problems that may occur when the shield electrode 23 is not provided and advantages obtained by providing the shield electrode 23 will be described.

  When the shield electrode 23 does not exist, an electrostatic capacity is formed between the pixel electrode 15 and the signal wiring 13. In other words, when focusing on the electric lines of force in the pixel region, the electric lines of force are not only formed so as to connect the pixel electrode 15 and the counter electrode 51 but also connect the pixel electrode 15 and the signal wiring 13. Also formed. Therefore, the potential of the pixel electrode 15 that should be kept constant within one frame varies due to the influence of the potential of the signal wiring 13.

  On the other hand, when the shield electrode 23 is provided, it is possible to guide the electric lines of force from the pixel electrode 15 toward the signal wiring 13 to the shield electrode 23, and the capacitance between the pixel electrode 15 and the signal wiring 13 is reduced. Can prevent formation. Therefore, it is possible to suppress the potential of the pixel electrode 15 from fluctuating due to the influence of the potential of the signal wiring 13. That is, the shield electrode 23 has a function of shielding the pixel electrode 15 from the electric field generated by the signal wiring 13.

  As shown in FIGS. 1 and 3D, the multilayer insulating film 12 in the present embodiment also has a low lamination region 12 </ b> R in a part of the region overlapping the shield electrode 23. As described above, when the multilayer insulating film 12 has the low stacked region 12R in a part of the region overlapping the shield electrode 23, the shield electrode 23 and the pixel electrode 15 and the second insulating layer positioned therebetween are provided. Since the auxiliary capacitance can be formed from 12b and the protective insulating film 19, the auxiliary capacitance value of each pixel can be increased. Therefore, it is not necessary to increase the area of the auxiliary capacitance formed by the auxiliary capacitance wiring 20, the auxiliary capacitance electrode 21, and the second insulating layer 12b (for example, the width of the auxiliary capacitance wiring 20 or the auxiliary capacitance electrode 22 is widened), and the opening A sufficiently high auxiliary capacitance value can be secured for each pixel without lowering the rate.

  1 and FIG. 3D show a configuration in which the low lamination region 12R is provided in a part of the region on the shield electrode 23. As shown in FIG. 4 and FIG. The low lamination region 12R may be provided in almost all of the regions. When such a configuration is used, the value of the auxiliary capacity can be further increased. On the other hand, as shown in FIGS. 1 and 3D, when the low lamination region 12R is provided only in a part of the region on the shield electrode 23, a part of the shield electrode 23 is covered with the first insulating film 12a. Therefore, it is possible to reduce the occurrence of a leak failure that occurs between the shield electrode 23 and the pixel electrode 15.

  In the configuration shown in FIGS. 1, 3 (d), 4, and 5, the low lamination region 12 </ b> R of the multilayer insulating film 12 is disposed so as to overlap with part of the signal wiring 13. When the low stacked region 12R is disposed so as to overlap a part of the signal wiring 13, the distance between the signal wiring 13 and the counter electrode 51 can be increased by the thickness of the first insulating layer 12a. For this reason, the capacitance formed between the signal wiring 13 and the counter electrode 51 can be reduced.

  Further, the first insulating layer 12a preferably covers the edge of the gate electrode 14G and the edge of the auxiliary capacitance wiring 20 as shown in FIGS.

  In a general active matrix substrate, an edge portion of a scanning wiring layer (a general term for elements formed from the same conductive film as the scanning wiring and the scanning wiring) and a signal wiring layer (from the same conductive film as the signal wiring and the signal wiring) Leakage of current is likely to occur between them and the generic name of the elements to be formed. Specifically, a leak between the edge portion of the gate electrode and the source electrode and the drain electrode and a leak between the edge portion of the auxiliary capacitance wiring and the auxiliary capacitance electrode are likely to occur.

  The cause of the leak described above is that a projection (called hillock) is likely to be formed at the edge when patterning the conductive film to be the scanning wiring layer, and a gate insulating film is formed on the scanning wiring layer by CVD or the like. In doing so, the covering property tends to deteriorate at the edge portion.

  Therefore, when patterning the conductive film to be the scanning wiring layer, it is necessary to perform patterning so that the edge portion is tapered, which causes a reduction in processing capability of the patterning process. Further, since it is necessary to form the edge portion in a tapered shape, it is difficult to increase the thickness of the scanning wiring layer itself.

  On the other hand, when the edge of the gate electrode 14G and the edge of the auxiliary capacitance wiring 20 are covered with the first insulating layer 12a, the edge portion of the scanning wiring layer (gate electrode 14G and auxiliary capacitance wiring 20) is formed in a tapered shape. Even without this, the occurrence of leakage can be suppressed. Therefore, the processing capability of the patterning process can be improved. In addition, since it is not necessary to form the edge portion in a tapered shape (the gate electrode 14G and the auxiliary capacitance wiring 20 may have a side surface substantially perpendicular to the substrate surface), the scanning wiring layer itself is also made thicker. Easy.

  Next, an example of a manufacturing method of the TFT substrate 100a will be described with reference to FIGS.

  First, a titanium (Ti) film, an aluminum (Al) film, and a titanium (Ti) film are laminated in this order on a transparent insulating substrate (for example, an alkali-free glass substrate) 10 using a sputtering method. By patterning by photolithography, a gate electrode 14G is formed as shown in FIG. At this time, the scanning wiring 11, auxiliary capacitance wiring 20, and shield electrode 23 (not shown) are also formed at the same time. Here, the thickness of the Ti / Al / Ti laminated film is 150 nm, 200 nm, and 50 nm in order from the upper layer. The laminated film is not limited to the Ti / Al / Ti film, and may be a Mo / Al / Mo film or a TaN / Ta / TaN film. Further, it may be a single layer film made of an Al alloy or the like.

  Next, the first insulating layer 12a is formed as shown in FIG. 6B by applying pre-baking and post-baking after applying an organic SOG material on the substrate 10 using a spin coating method or a slit coating method. . Pre-baking is performed at 120 ° C. for about 5 minutes, for example, and post-baking is performed at 350 ° C. for about 30 minutes, for example.

  Subsequently, as shown in FIG. 6C, a predetermined portion of the first insulating layer 12a, specifically, a portion overlapping the gate electrode 14G, a part of the portion overlapping the auxiliary capacitance wiring 20, and a signal wiring are overlapped. Part of the part and part (or all) of the part overlapping the shield electrode 23 are removed by etching (for example, dry etching).

Subsequently, a SiN _x film, an amorphous silicon (a-Si) film, and an n ⁺ amorphous silicon (n ⁺ a-Si) film are successively deposited by using a CVD method, and then an a-Si film and an n ⁺ a -Si film is patterned by photolithography (specifically, the n ⁺ a-Si film and a part of the a-Si film are removed by dry etching), whereby the second insulation is obtained as shown in FIG. A layer 12b (a part of which functions as the gate insulating film 16) and an island-shaped semiconductor structure (semiconductor active layer region) composed of the intrinsic semiconductor layer 17 and the impurity-added semiconductor layer 18 are formed.

  Thereafter, a Mo film, an Al film, and a Mo film are formed in this order by sputtering, and the stacked film is patterned by photolithography to form the source electrode 14S, the drain electrode 14D, the signal wiring 13 and the auxiliary capacitance electrode 21. To do.

  Next, as shown in FIG. 6E, the impurity-added semiconductor layer 18 is removed by dry etching using the source electrode 14S and the drain electrode 14D as a mask in the region 17c that becomes the channel of the island-shaped semiconductor structure. Note that when the impurity-added semiconductor layer 18 is removed, the surface of the intrinsic semiconductor layer 17 is also thinly etched.

Subsequently, as shown in FIG. 6F, a protective insulating film 19 having a thickness of about 250 nm to 300 nm is formed so as to cover almost the entire surface of the substrate 10 by depositing SiN _x using a CVD method. Thereafter, a contact hole 19 ′ is formed by photolithography.

  Finally, an ITO film having a thickness of 100 nm is formed by sputtering, and this ITO film is patterned by photolithography to form the pixel electrode 15. The material of the pixel electrode 15 is not limited to the ITO exemplified here, and a transparent conductive material can be widely used.

  A counter substrate 100b is manufactured separately from manufacturing the TFT substrate 100a as described above.

  Specifically, first, a resist material containing a photosensitive pigment is applied onto a transparent insulating substrate (for example, an alkali-free glass substrate) 50, and this resist material is patterned by photolithography to form a color filter. Next, the counter electrode 51 is formed by depositing ITO using a sputtering method.

  The counter substrate 100b and the TFT substrate 100a thus manufactured are bonded and sealed with a sealing resin, and a liquid crystal material is injected between both substrates to form the liquid crystal layer 60, whereby the liquid crystal display device 100 is completed. To do. Note that in the case where display is performed in the alignment-divided VA mode such as the MVA (Multi-domain Vertical Alignment) mode, at least one of the TFT substrate 100a and the counter substrate 100b is used to regulate the alignment direction of the liquid crystal molecules. An orientation regulating means is provided. For example, a slit is provided in the pixel electrode 15 of the TFT substrate 100a, or a rib (projection) is provided on the counter electrode 51 of the counter substrate 100b. The rib is formed, for example, by patterning an insulating film such as a photosensitive resist by photolithography.

(Embodiment 2)
The liquid crystal display device in this embodiment is an alignment division vertical alignment type LCD that performs display in an alignment division VA mode (for example, MVA mode). First, the basic configuration of an alignment-divided vertical alignment LCD will be described with reference to FIGS.

  The alignment-divided vertical alignment LCDs 1A, 1B, and 1C include a first electrode 1, a second electrode 2 facing the first electrode 1, and a vertical alignment liquid crystal provided between the first electrode 1 and the second electrode 2. A plurality of pixels having the layer 3 are provided. The vertical alignment type liquid crystal layer 3 aligns liquid crystal molecules having negative dielectric anisotropy substantially perpendicular to the surfaces of the first electrode 1 and the second electrode 2 (for example, 87 ° or more and 90 ° or less) when no voltage is applied. Is. Typically, it is obtained by providing a vertical alignment film (not shown) on the surface of each of the first electrode 1 and the second electrode 2 on the liquid crystal layer 3 side.

  First alignment regulating means (4, 6, 8) is provided on the first electrode 1 side of the liquid crystal layer 3, and second alignment regulating means (5, 7, 9) is provided. In the liquid crystal region defined between the first alignment regulating means and the second alignment regulating means, the liquid crystal molecules 3a receive the alignment regulating force from the first alignment regulating means and the second alignment regulating means, and receive the first electrode. When a voltage is applied between the first electrode 2 and the second electrode 2, it falls down (inclined) in the direction indicated by the arrow in the figure. That is, since the liquid crystal molecules 3a are tilted in a uniform direction in each liquid crystal region, each liquid crystal region can be regarded as a domain.

  The first alignment regulating means and the second alignment regulating means (these may be collectively referred to as “orientation regulating means”) are provided in a strip shape within each pixel, and FIG. c) is a cross-sectional view in a direction orthogonal to the extending direction of the strip-shaped orientation regulating means. Liquid crystal regions (domains) in which the directions in which the liquid crystal molecules 3a fall are different from each other by 180 ° are formed on both sides of each alignment regulating means.

  The LCD 1 </ b> A shown in FIG. 7A has ribs 4 as first alignment regulating means and slits (openings) 5 provided in the second electrode 2 as second alignment regulating means. Each of the ribs 4 and the slits 5 extends in a strip shape (strip shape). The ribs 4 orient the liquid crystal molecules 3 a substantially perpendicular to the side surfaces 4 a, thereby acting to align the liquid crystal molecules 3 a in a direction perpendicular to the extending direction of the ribs 4. When a potential difference is formed between the first electrode 1 and the second electrode 2, the slit 5 generates an oblique electric field in the liquid crystal layer 3 near the edge of the slit 5 and is orthogonal to the extending direction of the slit 5. It acts to align the liquid crystal molecules 3a in the direction in which they are directed. The ribs 4 and the slits 5 are arranged in parallel to each other with a certain distance therebetween, and a liquid crystal region (domain) is formed between the ribs 4 and the slits 5 adjacent to each other.

  The LCD 1B shown in FIG. 7B is different from the LCD 1A shown in FIG. 7A in that it has ribs 6 and ribs 7 as the first orientation regulating means and the second orientation regulating means, respectively. The rib 6 and the rib 7 are arranged in parallel with each other at a predetermined interval, and by acting to align the liquid crystal molecules 3a substantially vertically on the side surface 6a of the rib 6 and the side surface 7a of the rib 7, A liquid crystal region (domain) is formed between them.

  The LCD 1C shown in FIG. 7C is different from the LCD 1A shown in FIG. 7A in that each of the LCD 1C includes a slit 8 and a slit 9 as the first alignment regulating means and the second alignment regulating means. The slit 8 and the slit 9 generate an oblique electric field in the liquid crystal layer 3 in the vicinity of the end sides of the slits 8 and 9 when a potential difference is formed between the first electrode 1 and the second electrode 2. And the liquid crystal molecules 3a are aligned in a direction perpendicular to the extending direction of 9 and 9. The slit 8 and the slit 9 are arranged in parallel to each other with a certain interval, and a liquid crystal region (domain) is formed between them.

  As described above, ribs or slits can be used in any combination as the first orientation regulating means and the second orientation regulating means. The first electrode 1 and the second electrode 2 may be electrodes that face each other with the liquid crystal layer 3 interposed therebetween. Typically, one is a counter electrode and the other is a pixel electrode. Hereinafter, in the case where the first electrode 1 is a counter electrode and the second electrode 2 is a pixel electrode, a rib is provided as the first alignment regulating means, and a slit provided in the pixel electrode is provided as the second alignment regulating means. A specific embodiment will be described using an LCD having LCD (corresponding to the LCD 1A in FIG. 7A) as an example. Employing the configuration of the LCD 1A shown in FIG. 7A provides an advantage that an increase in manufacturing steps can be minimized. Even if a slit is provided in the pixel electrode, no additional process is required. On the other hand, for the counter electrode, the number of processes is less when the rib is provided than when the slit is provided. Of course, the present invention can be applied to a configuration in which only ribs are used as the orientation regulating means, or a configuration in which only slits are used, and a configuration in which the orientation regulating means is provided only on one substrate.

  Hereinafter, the structure of the TFT substrate 200a of the alignment-divided vertical alignment LCD according to this embodiment will be specifically described with reference to FIGS. 8 is a top view schematically showing the TFT substrate 200a, and FIG. 9 is a cross-sectional view taken along the line 9A-9A 'in FIG.

  Similar to the multilayer insulating film 12 of the TFT substrate 100a shown in FIG. 1, the multilayer insulating film 12 of the TFT substrate 200a is a low stacked region in a region overlapping the channel region of the TFT 14 and a part of the region overlapping the auxiliary capacitance wiring 20. 12R. Therefore, it is possible to reduce the capacitance formed at the intersection between the scanning wiring 11 and the signal wiring 13 without lowering the driving capability of the TFT 14 or lowering the capacitance value of the auxiliary capacitance. In addition, since the multilayer insulating film 12 has the low lamination region 12R in a part of the region overlapping the signal wiring 13, the capacitance formed between the signal wiring 13 and the counter electrode 51 can be reduced. it can.

  Further, in the TFT substrate 200a in the present embodiment, the auxiliary capacitance wiring 20 has a branching portion 20a branched so as to overlap a rib (alignment regulating means) provided on the counter substrate. The branch portion 20a extends from the auxiliary capacitance wiring 20 and is bent in a dogleg shape like the rib. In addition, although the slit is formed in the pixel electrode 15 as an orientation control means, the slit is omitted in FIG.

  As shown in FIG. 9, the multilayer insulating film 12 also has a low stacked region 12 </ b> R in a region overlapping the branch portion 20 a of the auxiliary capacitance line 20. The auxiliary capacitor is composed of the second insulating layer 12b and the protective insulating film 19 positioned between them.

  That is, in this embodiment, instead of forming an auxiliary capacitor including the shield electrode 23 as in the first embodiment, an auxiliary capacitor including the branch portion 20a of the auxiliary capacitor wiring 20 is formed. Even if such a configuration is adopted, the value of the auxiliary capacitance provided in each pixel can be increased. Since the region overlapping the rib (orientation restricting means) is a region that does not contribute to display originally, a sufficiently high auxiliary capacitance value can be secured for each pixel without reducing the aperture ratio.

  10 and 11 show another TFT substrate 200a in the present embodiment. In the TFT substrate 200a shown in FIG. 10, the auxiliary capacitance wiring 20 has a further branch portion 20b extending from the bent portion of the branch portion 20a. The branch portion 20b extends substantially parallel to the scanning wiring 11 and the auxiliary capacitance wiring 20, and is formed so as to divide the angle formed by the bent branch portion 20a into approximately two equal parts.

  As shown in FIG. 11, the multilayer insulating film 12 also has a low lamination region 12R in a region overlapping this further branching portion 20b, and the branching portion 20b, the pixel electrode 15, the second insulating layer 12b, and the protective insulation. An auxiliary capacitor is also formed by the film 19. Therefore, the auxiliary capacity value can be further increased. In addition, since the further branch part 20b is provided so that it may overlap with the boundary of liquid crystal domains, even if it provides the branch part 20b, substantial aperture ratio does not fall very much.

  12 and 13 show still another TFT substrate 200a in the present embodiment. In the TFT substrate 200a shown in FIGS. 12 and 13, the conductive member 22 formed of the same conductive film as the signal wiring 13 and the like and electrically connected to the drain electrode 14D of the TFT 14 is connected to the branch portion 20a of the auxiliary capacitance wiring 20. The auxiliary capacitance is formed by the branching portion 20a of the auxiliary capacitance wiring 20, the conductive member 22, and the second insulating layer 12b. Therefore, as shown in FIG. 9, a higher capacitance value can be realized as compared with the case where the auxiliary capacitance is formed by the branch portion 20 a and the pixel electrode 15, the second insulating layer 12 b and the protective insulating film 19.

  In the present embodiment, the low lamination region 12R of the multilayer insulating film 12 is not disposed on the shield electrode 23. Of course, the low lamination region 12R is also provided on the shield electrode 23. The auxiliary capacity value may be further increased.

  According to the present invention, it is possible to reduce the capacitance formed at the intersection between the scanning wiring and the signal wiring, and to provide the auxiliary capacitance having a sufficiently large capacitance value without reducing the aperture ratio. The present invention is suitably used for an active matrix substrate for a liquid crystal display device.

It is a top view which shows typically the liquid crystal display device 100 in suitable embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing the liquid crystal display device 100, showing a cross section taken along line 2A-2A ′ in FIG. 1. (A) to (d) are cross-sectional views schematically showing a TFT substrate 100a of the liquid crystal display device 100, respectively, 3A-3A ′ line, 3B-3B ′ line, 3C-3C ′ line in FIG. It is a figure which shows the cross section along 3D-3D 'line. 2 is a top view schematically showing a liquid crystal display device 100. FIG. FIG. 5 is a cross-sectional view schematically showing the liquid crystal display device 100, and is a view showing a cross section taken along line 5A-5A 'in FIG. (A) to (f) are process cross-sectional views schematically showing the manufacturing process of the TFT substrate 100a. (A) to (c) are cross-sectional views schematically showing a basic configuration of an alignment-divided vertical alignment LCD. It is a top view which shows typically the TFT substrate 200a of the alignment division | segmentation vertical alignment type LCD in suitable embodiment of this invention. It is sectional drawing which shows TFT substrate 200a typically, and is a figure which shows the cross section along the 9A-9A 'line | wire in FIG. It is a top view which shows typically the other TFT substrate 200a in suitable embodiment of this invention. It is sectional drawing which shows TFT substrate 200a typically, and is a figure which shows the cross section along the 11A-11A 'line in FIG. It is a top view which shows typically further another TFT substrate 200a in suitable embodiment of this invention. It is sectional drawing which shows TFT substrate 200a typically, and is a figure which shows the cross section along line 13A-13A 'in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st electrode 2 2nd electrode 3 Vertical alignment type liquid crystal layer 4, 6, 7 Rib (alignment control means)
5, 8, 9 Slit (Orientation regulating means)
10 Substrate (transparent insulating substrate)
11 Scanning wiring 12 Insulating film (Multilayer insulating film)
12a 1st insulating layer 12b 2nd insulating layer 12R Low lamination area 13 Signal wiring 14 Thin-film transistor (switching element)
14G gate electrode 14S source electrode 14D drain electrode 15 pixel electrode 16 gate insulating film 17 semiconductor layer (intrinsic semiconductor layer)
17a Source region 17b Drain region 17c Channel region 18 Impurity doped semiconductor layer 19 Protective insulating film 19 ′ Contact hole 20 Auxiliary capacitance wiring 20a Branching portion of auxiliary capacitance wiring 20b Further branching portion of auxiliary capacitance wiring 21 Auxiliary capacitance electrode 22 Conductive member 23 Shield Electrode 60 Liquid crystal layer 100 Liquid crystal display device 100a, 200a Active matrix substrate (TFT substrate)
100b Counter substrate

Claims (14)

An insulating substrate;
A plurality of scanning wirings and a plurality of auxiliary capacitance wirings formed on the insulating substrate;
An insulating film covering the plurality of scanning lines and the plurality of auxiliary capacitance lines;
A plurality of signal wirings crossing the plurality of scanning wirings through the insulating film;
A plurality of shield electrodes formed from the same conductive film as the plurality of scanning lines and extending substantially parallel to the plurality of signal lines;
A plurality of switching elements provided on the insulating substrate and operating in response to a signal applied to the corresponding scanning wiring;
An active matrix substrate comprising a plurality of pixel electrodes that can be electrically connected to the corresponding signal wirings via the plurality of switching elements,
The insulating film is a multilayer insulating film including a first insulating layer formed of an insulating material containing an organic component and a second insulating layer formed of an inorganic insulating material,
The multi-layer insulating film is an active matrix substrate having a low stacked region in which the first insulating layer is not formed in at least a part of a region overlapping with the shield electrode.   2. The active matrix substrate according to claim 1, wherein the multilayer insulating film has the low stacked region in a part of a region overlapping the signal wiring.   3. The active matrix substrate according to claim 1, wherein the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the storage capacitor wiring.   4. The active matrix substrate according to claim 1, wherein the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the switching element. 5.   Each of the plurality of switching elements corresponds to a semiconductor layer including a channel region, a gate electrode electrically connected to the corresponding scan wiring, a source electrode electrically connected to the corresponding signal wiring, 5. The active matrix substrate according to claim 1, wherein the active matrix substrate is a thin film transistor having a drain electrode electrically connected to the pixel electrode.   The active matrix substrate according to claim 5, wherein the multilayer insulating film has the low stacked region in a region overlapping at least the channel region.   The active matrix substrate according to claim 1, wherein the first insulating layer is made of an SOG material. An active matrix substrate according to any one of claims 1 to 7,
A counter substrate facing the active matrix substrate;
A liquid crystal display device comprising: a liquid crystal layer provided between the active matrix substrate and the counter substrate. The counter substrate has alignment regulating means for controlling the alignment of the liquid crystal layer,
The auxiliary capacitance wiring of the active matrix substrate has a branch portion branched so as to overlap the orientation regulating means,
The liquid crystal display device according to claim 8, wherein the multilayer insulating film has the low stacked region in at least a part of a region overlapping the branch portion. An active matrix substrate having a plurality of switching elements;
A counter substrate facing the active matrix substrate;
A liquid crystal display device comprising: a liquid crystal layer provided between the active matrix substrate and the counter substrate;
The active matrix substrate is
An insulating substrate;
A plurality of scanning wirings and a plurality of auxiliary capacitance wirings formed on the insulating substrate;
An insulating film covering the plurality of scanning lines and the plurality of auxiliary capacitance lines;
A plurality of signal wirings crossing the plurality of scanning wirings through the insulating film;
A plurality of pixel electrodes that can be electrically connected to the corresponding signal wirings via the plurality of switching elements;
The insulating film is a multilayer insulating film including a first insulating layer formed of an insulating material containing an organic component and a second insulating layer formed of an inorganic insulating material,
The counter substrate has alignment regulating means for controlling the alignment of the liquid crystal layer,
The auxiliary capacitance wiring has a branch portion branched so as to overlap the orientation regulating means,
The liquid crystal display device, wherein the multilayer insulating film has the low stacked region where the first insulating layer is not formed in at least a part of a region overlapping with the branch portion.   The liquid crystal display device according to claim 10, wherein the multilayer insulating film has the low stacked region in a part of a region overlapping with the signal wiring.   12. The liquid crystal display device according to claim 10, wherein the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the storage capacitor wiring.   13. The liquid crystal display device according to claim 10, wherein the multilayer insulating film has the low stacked region in at least a part of a region overlapping with the switching element.   The liquid crystal display device according to claim 10, wherein the first insulating layer is made of an SOG material.

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