KR20120003768A - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and method for fabricating the same is provided to improve a pixel transparent rate while reducing a common electrode and a pixel electrode. CONSTITUTION: A gate line and a data line define a pixel area on a substrate(100). A switching device is arranged in the cross area of the data line and gate line. A pixel electrode(129) is located in the pixel area which is parallel direction with the data line. The common electrode and common line are formed on the upper part of the data line between a protective film(119) and an organic insulating film(250). The thickness of the organic insulating film on the pixel electrode is smaller than the thickness of the organic insulating film of data line area.

Description

Thin Film Transistor Array Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device.

In general, a liquid crystal display (LCD) displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field. In the liquid crystal display, a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed are bonded to each other with a liquid crystal interposed therebetween.

Recently, in order to solve the narrow viewing angle problem of the liquid crystal display, a liquid crystal display adopting various new methods has been developed. Liquid crystal displays having a wide viewing angle include an in-plane switching mode (IPS), an optically compensated birefrigence mode (OCB), and a fringe field spooling (FFS).

The horizontal electric field type liquid crystal display device arranges the pixel electrode and the common electrode on the same substrate to generate a horizontal electric field between the electrodes. As a result, the long axes of the liquid crystal molecules are arranged in a horizontal direction with respect to the substrate, and thus have a wide viewing angle characteristic as compared with the conventional twisted nematic (TN) type liquid crystal display.

In addition, in the conventional transverse electric field type liquid crystal display, an organic insulating layer that is much thicker than the protective layer is formed to prevent an increase in parasitic capacitance between electrodes formed in the data line and the pixel region.

However, due to the high thickness of the organic insulating layer, the parasitic capacitance between the data line and the common line formed on the data line is reduced, but this causes the distance between the pixel electrode and the common electrode in the pixel region to increase, thereby increasing the pixel driving voltage. Occurred.

As such, when the pixel driving voltage rises, power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate having improved pixel transmittance while reducing a driving voltage applied between a pixel electrode and a common electrode, and a method of manufacturing the same.

In addition, the present invention provides a thin film transistor array substrate and a method of manufacturing the same, which may implement a high resolution and low power liquid crystal display device by reducing parasitic capacitance generated in the data line region by forming different thicknesses of the organic insulating layers of the data line region and the pixel region. There is another purpose.

The thin film transistor array substrate of the present invention for achieving the above object, the substrate; Gate lines and data lines cross-arranged to define pixel regions on the substrate; A switching element disposed in an intersection region of the gate line and the data line; A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And a common electrode and a common line respectively disposed on the pixel electrode and the data line, wherein a common electrode and a common line are formed on the pixel electrode and the data line, respectively, between the passivation layer and the organic insulating layer. The thickness of the organic insulating film formed on the substrate is characterized by having a thickness smaller than the thickness of the organic insulating film formed on the data line region.

In addition, the method of manufacturing a thin film transistor array substrate of the present invention includes providing a substrate divided into a display area and a non-display area; Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad in a non-display area; Sequentially forming a gate insulating film and a channel layer on the substrate on which the gate electrode and the like are formed; Forming a pixel electrode on the substrate on which the channel layer is formed, subsequently forming a source / drain metal film, and then forming a source / drain electrode, a data line, and a data pad; A protective film and an organic insulating film are formed on the substrate on which the source and drain electrodes are formed, and then, using a halftone mask or a diffraction mask, a region corresponding to the gate pad region and a region corresponding to the first contact hole and data pad region are formed. Forming a thickness of the organic insulating layer corresponding to the second contact hole and the pixel electrode to be thinner than other regions; Exposing the gate pad and the data pad using the organic insulating layers having the first and second contact holes as masks; And forming a transparent conductive material on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process.

The present invention has the effect of improving the pixel transmittance while reducing the driving voltage applied between the pixel electrode and the common electrode.

In addition, the present invention may implement a high resolution and low power liquid crystal display by reducing parasitic capacitance generated in the data line region by forming different thicknesses of the organic insulating layers of the data line region and the pixel region.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.
2A to 2J are diagrams illustrating a manufacturing process of a thin film transistor array substrate according to the present invention.
3A and 3B are diagrams comparing conventional organic insulating film thicknesses with organic insulating film thicknesses of the present invention.
4 is a graph illustrating a change in driving voltage according to the thickness of the organic insulating layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

In addition, in the description of the embodiments, each pattern, layer, film, region, or substrate is formed on or under the pattern of each pattern, layer, film, region, or substrate. In the case described, "on" and "under" include both those that are formed "directly" or "indirectly" through other components.

In addition, the criteria for the top, side or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.

Referring to FIG. 1, a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention is divided into a display area in which a plurality of pixel areas are formed and a non-display area in which a pad area is formed, and the gate line 101 and the data line 103 are separated from each other. Cross-aligned to define a sub-pixel region.

The thin film transistor TFT, which is a switching element, is disposed in an area where the gate line 101 and the data line 103 cross each other. The thin film transistor includes a gate electrode 101a, a source / drain electrode, and a channel layer (not shown), which are wider than the gate line 101 and drawn in the pixel area direction.

The pixel electrode 129 having a plate structure is disposed in the pixel area in a direction parallel to the data line 103. In addition, the common electrodes 150 having a plurality of slit structures are alternately disposed on the pixel electrode 129. In addition, a common line 151 integrally formed with the common electrode 150 is disposed around the pixel area. The common line 151 overlaps the gate line 101 and the data line 103 along the circumference of the pixel area.

In addition, the pixel electrode 129 and the common electrode 150 of the present invention are formed in a vertically symmetrical structure along the direction of the data line 103 around the pixel center line parallel to the gate line 101. In addition, the common electrode 150 and the pixel electrode 129 are formed to have a predetermined angle in the vertical direction with respect to the pixel center line.

In addition, the pixel electrode 129 is formed in the shape of a square plate, but this is not fixed. Therefore, the plurality of slits may be formed like the common electrode 150.

In the present invention, in order to reduce parasitic capacitance in the thin film transistor region, a part of the common line 151 overlapping the thin film transistor is removed to form an open (OP) region. Therefore, the common line 151 made of a transparent conductive material does not exist on the gate electrode 101 and the source / drain electrodes.

In addition, a gate pad 110 extending from the gate line 101 is formed in the gate pad region of the liquid crystal display, and gates electrically contacted with each other through the first contact hole 231 on the gate pad 110. The pad contact electrode 310 is formed.

In addition, a data pad 120 extending from the data line 103 is formed in the data pad area of the liquid crystal display, and data electrically contacted with each other through the second contact hole 233 on the data pad 120. The pad contact electrode 320 is formed.

2A to 2I are views illustrating a manufacturing process of a thin film transistor array substrate according to the present invention.

Referring to FIG. 2A, a metal film is deposited on a lower substrate 100 made of a transparent insulating material by sputtering, and then a gate electrode 101a is formed in a pixel area, which is a display area, according to a first mask process, and then is non-displayed. The gate pad 110 is formed in the pad region which is the region.

In the first mask process, a photoresist, which is a photosensitive material, is formed on the deposited metal film, and then a photoresist pattern is formed by an exposure and development process using a mask, and an etching process is performed using the photoresist pattern as a mask. .

As described above, in the first mask process, not only the gate electrode 101a and the gate pad 110 but also the gate line 101 (see FIG. 1) are formed together.

The metal film formed in the first mask process is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. It may be formed by laminating at least one of an alloy or a transparent conductive material ITO, IZO and ITZO.

In the drawing, the gate electrode 101a and the gate pad 110 are formed in a structure in which two metal layers are stacked. However, since the gate electrode 101a and the gate pad 110 are not fixed, they may be formed by stacking a single metal layer or three or more metal layers.

As described above, when the gate electrode 101a or the like is formed on the lower substrate 100, as shown in FIGS. 2B and 2C, the gate insulating film 102, the amorphous silicon film, and the doped amorphous silicon film n + or The semiconductor layer 124 formed of p + is sequentially formed, and then the channel layer 114 is formed on the gate insulating layer 102 on the gate electrode 101a according to the second mask process.

Next, as shown in FIG. 2D, a transparent conductive material is formed on the lower substrate 100 on which the channel layer 114 is formed, and the pixel electrode 129 is formed in the pixel region according to the third mask process. The transparent conductive material may use any one of ITO, IZO, and ITZO.

As described above, when the pixel electrode 129 is formed on the lower substrate 100, as shown in FIGS. 2E and 2F, the source / drain metal layer 217 is formed on the entire region of the lower substrate 100. do. Thereafter, a photoresist film is formed on the lower substrate 100 on which the source / drain metal film 217 is formed, and then a first photoresist film pattern 500 is formed according to a fourth mask process. Then, an etching process is performed using the first photoresist pattern 500 as a mask to form the source / drain electrodes 117a and 117b, the data line 103, and the data pad 120.

The drain electrode 117b is in direct contact with the pixel electrode 129 without a separate contact process.

The source / drain metal film 217 is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. Any of the alloys may be used. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the figure is formed of a single metal film, at least two or more metal films may be stacked in some cases.

Next, as shown in FIGS. 2G and 2H, the passivation layer 119 and the organic insulating layer 250 are sequentially formed in the entire area of the lower substrate 100 where the source / drain electrodes 117a and 117b are formed.

Thereafter, a first contact hole 231 and a second contact hole 233 are formed in the gate pad and the data pad area according to a fifth mask process using a halftone mask or a diffraction mask, and the pixel electrode 129 A portion of the organic insulating layer 250 corresponding to the substrate is removed. That is, the mask used in the fifth mask process has a non-transmissive region, a semi-transmissive region, and a non-transmissive region, wherein the transmissive region corresponds to the first and second contact holes 231 and 233, and the pixel region corresponds to the semi-transmissive region. Corresponding.

Therefore, the thickness of the organic insulating layer 250 in the region where the pixel electrode 129 is formed is thinner than the non-display region in which the data line 103 is formed.

The organic insulating layer 250 preferably has a lower dielectric constant than the passivation layer 119. The dielectric constant may be 3.0 to 4.0, and preferably, the dielectric constant of the organic insulating layer 250 may be 3.4 to 3.8. The organic insulating layer 119 may have a thickness of about 3 μm to about 6 μm. As such, when the organic insulating layer 250 having the low dielectric constant is used, the thickness of the passivation layer 119 may be about 1000 mW, thereby reducing losses in the deposition and etching processes.

In addition, the organic insulating layer 250 may be formed of an acrylic resin. The acrylic resin includes but is not limited to photo acryl. That is, the organic insulating layer 250 is not limited to the photo acrylic as long as the material has a low dielectric constant.

In addition, even when the first and second contact holes 231 and 233 are formed on the organic insulating layer 250, the gate pad 110 and the data pad 120 are covered by the passivation layer 119. Therefore, a dry etching process may be performed using the organic insulating layer 250 as a mask, and the gate pad 110 and the data pad 120 may be moved outwardly from the first contact hole 231 and the second contact hole 233, respectively. Expose

Then, as illustrated in FIGS. 2I and 2J, a transparent conductive film 140 is formed on the entire surface of the lower substrate 110 on which the organic insulating film 250 is formed, and then a photosensitive film is formed. The second photosensitive film pattern 600 is formed according to the sixth mask process. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

Portions of the second photoresist pattern 600 are filled in the first and second contact holes 231 and 233. This is to form the gate pad contact electrode 310 and the data pad contact electrode 320 by preventing the transparent conductive layer 140 from being removed by the etching process.

Thereafter, the transparent conductive film 140 is etched using the second photoresist pattern 600 as a mask. The common electrode 150 and the common line 151 are formed on the lower substrate 100. In addition, a gate pad contact electrode 310 is formed in an area of the first contact hole 231, and a data pad contact electrode 320 is formed in an area of the second contact hole 233.

The common line 151 has a structure surrounding the data line 103 and removes the transparent conductive film in the region where the gate electrode 101a is formed to form an open (OP) region. This open area is to reduce parasitic capacitance that may be generated between the thin film transistor and the common line 151.

In the present invention, since the thickness of the organic insulating layer 250 formed on the pixel electrode 129 is formed to be thinner than that of the data line 103 region, the vertical transmittance is improved and the pixel driving voltage can be lowered.

In the present invention, since the organic insulating film 250 having the low dielectric constant is formed on the data line 103, and the common line 151 is formed on the organic insulating film 250, the data line 103 and the common line are formed. The amount of parasitic capacitance that may be generated between 151 may be reduced.

3A and 3B are diagrams comparing the thickness of a conventional organic insulating film and the thickness of an organic insulating film of the present invention, and FIG. 4 is a graph showing a change in driving voltage according to the thickness of the organic insulating film.

First, referring to FIG. 4, a driving voltage when the thickness of the organic insulating layer is 5000 kV, 10000 kPa, or 15000 kPa is shown based on 1000 kPa of the protective film PAS.

It can be seen that the driving voltage increases to 5.5V, 6.5V, and 8V as the thickness of the organic insulating layer is gradually thickened under the condition of maintaining transmittance of 95% or more.

Although not shown in the drawing, as the thickness of the organic insulating layer increases, the driving voltage increases, but the parasitic capacitance Ccd decreases in the data line region.

However, if the thickness of the organic insulating layer is formed to simply reduce the parasitic capacitance, there is a problem that the transmittance and the driving voltage of the pixel region are gradually increased as shown in the graph.

3A and 3B, the data line DL is formed on the substrate S with the gate insulating layer GI interposed therebetween. On the data line DL, the passivation film PAS and the organic insulation film PA are formed to have a thickness of L, respectively. The common line CL is formed on the organic insulating layer corresponding to the data line DL, and the pixel electrode PE and the common electrode CE are disposed in the pixel region adjacent to the data line DL with the organic insulating layer interposed therebetween. Each is formed.

In FIG. 3A, since the organic insulating film PA is uniformly formed on the substrate S in the related art, the thickness of the organic insulating film PA in the pixel area is the same as the thickness L of the data line DL. .

However, in the present invention as shown in FIG. 3B, the organic insulating film PA thickness d2 in the pixel region and the organic insulating film PA thickness L in the data line region are differently formed using a halftone mask or a diffraction mask. It was. That is, the thickness d2 of the organic insulating film PA in the pixel region is formed to be much smaller than the thickness L of the organic insulating film PA in the data line region.

Therefore, in the present invention, the parasitic capacitance in the data line region is reduced as in the prior art while lowering the transmittance and pixel driving voltage of the pixel region.

Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

101: gate line 150: common electrode
151: common line 103: data line
129: pixel electrode 250: organic insulating film
119: shield OP: open area

Claims (6)

Board;
Gate lines and data lines cross-arranged to define pixel regions on the substrate;
A switching element disposed in an intersection region of the gate line and the data line;
A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And
A common electrode and a common line disposed on the pixel electrode and the data line, respectively;
A common electrode and a common line are formed between the passivation layer and the organic insulating layer on the pixel electrode and the data line, respectively, and the thickness of the organic insulating layer formed on the pixel electrode has a thickness smaller than that of the organic insulating layer formed in the data line region. Thin film transistor array substrate, characterized in that.
The thin film transistor array substrate of claim 1, wherein the pixel electrode and the data line are formed on a gate insulating layer. The thin film transistor array substrate of claim 1, wherein the drain electrode of the switching element is in direct contact with the pixel electrode. Providing a substrate divided into a display area and a non-display area;
Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad in a non-display area;
Sequentially forming a gate insulating film and a channel layer on the substrate on which the gate electrode and the like are formed;
Forming a pixel electrode on the substrate on which the channel layer is formed, subsequently forming a source / drain metal film, and then forming a source / drain electrode, a data line, and a data pad;
A protective film and an organic insulating film are formed on the substrate on which the source and drain electrodes are formed, and then, using a halftone mask or a diffraction mask, a region corresponding to the gate pad region and a region corresponding to the first contact hole and data pad region are formed. Forming a thickness of the organic insulating layer corresponding to the second contact hole and the pixel electrode to be thinner than other regions;
Exposing the gate pad and the data pad using the organic insulating layers having the first and second contact holes as masks; And
Forming a transparent conductive material on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process Substrate manufacturing method.
5. The method of claim 4, wherein the pixel electrode and the drain electrode are in direct contact.
The method of claim 4, wherein the passivation layer has a thickness of 1000 ns.

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