KR101997090B1 - Thin film transistor liquid crystal display device - Google Patents

Abstract

The present invention discloses a thin film transistor liquid crystal display device. The thin film transistor liquid crystal display of the present invention comprises: a lower substrate on which a plurality of pixel regions are partitioned; Wherein each of the pixel regions includes a plurality of gate lines and data lines arranged in an intersecting manner, a plurality of common lines parallel to the gate lines and arranged to intersect the data lines, A color filter layer including a switching element, pixel electrodes alternately arranged in the pixel region, and a common electrode, the color filter layer being disposed in the pixel region; A color filter pattern disposed adjacent to the pixel region and overlapping the gate line and the common line; An upper substrate bonded to the lower substrate; A cell gap column spacer disposed for maintaining a cell gap between the upper substrate and the lower substrate, and a column spacer disposed for suppression; And a blocking layer formed on the color filter pattern corresponding to the cell gap column spacer.
The thin film transistor liquid crystal display of the present invention has the effect of securing a space between the column spacer and the array substrate while forming the cell gap spacer and the column spacer with the same thickness using the step of the color filter layers.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor liquid crystal display device,

The present invention relates to a thin film transistor liquid crystal display device.

[0002] A liquid crystal display typically displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. The liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed.

In recent years, liquid crystal display devices employing various new methods have been developed to solve the narrow viewing angle problem of the liquid crystal display device. A liquid crystal display device having a wide viewing angle characteristic includes an in-plane switching mode (IPS), an optically compensated birefringence mode (OCB), and a fringe field swithching (FFS) mode.

In the transverse electric field type liquid crystal display device, a pixel electrode and a common electrode are disposed on the same substrate so that a horizontal electric field is generated between the electrodes. As a result, the long axes of the liquid crystal molecules are aligned in the horizontal direction with respect to the substrate, and thus the liquid crystal display device has a wide viewing angle characteristic as compared with a conventional TN (Twisted Nematic) type liquid crystal display device.

In addition, an array substrate of a color filter on TFT (COT) structure in which a color filter array is formed on a thin film transistor array substrate has been developed. This is because the adhesion margin considered in the process of attaching the upper and lower substrates is reduced, .

The array substrate of the COT structure is manufactured by forming a color filter and a black matrix on a substrate on which a thin film transistor array is formed. That is, a black matrix formed on a conventional color filter array substrate is formed in a region corresponding to a thin film transistor (TFT), a gate line, and a data line of a thin film transistor array substrate, and a red R), green (G), and blue (B) color filters.

As described above, since the thin film transistor array substrate of the COT structure uses the black matrix formed on the color filter substrate as it is, there is a limit to the improvement of the aperture ratio and the manufacturing process of the color filter substrate is directly applied to the manufacturing process of the thin film transistor array substrate The process is complicated.

An object of the present invention is to provide a thin film transistor liquid crystal display device in which an aperture ratio is improved by removing a black matrix on an array substrate having a COT structure.

The present invention also provides a thin film transistor liquid crystal display device capable of forming a cell gap column spacer and a pressed column spacer with the same thickness using the step of the color filter layers, but securing a space between the column spacer and the array substrate There is a purpose.

In addition, the present invention provides a thin film transistor liquid crystal display device capable of forming a cell gap spacer and a pressed column spacer using a material having a high optical density using a step of color filter layers, .

According to an aspect of the present invention, there is provided a thin film transistor liquid crystal display comprising: a lower substrate on which a plurality of pixel regions are partitioned; Wherein each of the pixel regions includes a plurality of gate lines and data lines arranged in an intersecting manner, a plurality of common lines parallel to the gate lines and arranged to intersect the data lines, A color filter layer including a switching element, pixel electrodes alternately arranged in the pixel region, and a common electrode, the color filter layer being disposed in the pixel region; A color filter pattern disposed adjacent to the pixel region and overlapping the gate line and the common line; An upper substrate bonded to the lower substrate; A cell gap column spacer disposed for maintaining a cell gap between the upper substrate and the lower substrate, and a column spacer disposed for suppression; And a blocking layer formed on the color filter pattern corresponding to the cell gap column spacer.

According to another aspect of the present invention, there is provided a thin film transistor liquid crystal display comprising: a lower substrate on which a plurality of pixel regions are partitioned; Wherein each of the pixel regions includes a plurality of gate lines and data lines arranged in an intersecting manner, a plurality of common lines parallel to the gate lines and arranged to intersect the data lines, A color filter layer including a switching element, pixel electrodes alternately arranged in the pixel region, and a common electrode, the color filter layer being disposed in the pixel region; A color filter pattern disposed adjacent to the pixel region and overlapping the gate line and the common line; An upper substrate bonded to the lower substrate; A cell gap column spacer disposed for maintaining a cell gap between the upper substrate and the lower substrate, and a column spacer disposed for suppression; And a barrier layer formed on the color filter pattern corresponding to the cell gap column spacer, wherein a metal barrier layer is formed under the color filter pattern.

The thin film transistor liquid crystal display device of the present invention has an effect of improving the aperture ratio by removing a black matrix on an array substrate having a COT structure.

In addition, the thin film transistor liquid crystal display of the present invention has the effect of securing a space between the column spacer and the array substrate while forming a cell gap column spacer and a pressed column spacer with the same thickness using the step of the color filter layers .

In addition, the thin film transistor liquid crystal display device of the present invention can form cell gap column spacers and pressed column spacers with a material having high optical density using the step of the color filter layers, thereby improving defects in light leakage.

1 is a diagram showing a pixel structure of a thin film transistor array substrate having a COT structure according to the present invention.
2 is a cross-sectional view taken along line I-I ', II-II', and III-III 'in FIG.
FIG. 3 is a view showing the arrangement structure of the cell gap spacer and the pressed spacer in the column spacer region of FIG. 1. FIG.
4A to 4C are diagrams showing the structures of color filter patterns formed in the thin film transistor liquid crystal display of the present invention.
5A and 5B are views showing structures of a blocking layer formed in a TFT liquid crystal display of the present invention.
FIG. 6 is a view showing an arrangement structure of a cell gap spacer and a pressed spacer in a column spacer region according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

FIG. 1 is a diagram showing a pixel structure of a thin film transistor array substrate having a COT structure according to the present invention, and FIG. 2 is a cross-sectional view taken along the line I-I ', II-II', and III-III 'of FIG.

Referring to FIGS. 1 and 2, a plurality of gate lines 101 and data lines 103 are arranged in a display area of a thin film transistor liquid crystal display device of the present invention to define a plurality of pixel regions. A thin film transistor (TFT), which is a switching element, is disposed in an intersecting region of the gate line 101 and the data line 103.

A first common line 111 is disposed in a region adjacent to the gate line 101 in parallel with the gate line 101. The first common line 111 intersects the data line 103 as well.

Since the gate electrode of the thin film transistor is formed on the gate line 101, the gate line 101 serves as a gate electrode. That is, the gate line 101 becomes the gate electrode 101 in the region where the thin film transistor is formed.

The first common line 111 includes a first common electrode 121 protruding in the direction of the pixel region. The first common electrode 121 is connected to the data line 103 adjacent to both edges of the pixel region, As shown in FIG.

The pixel region includes a first pixel electrode 109 electrically connected to the thin film transistor through the first contact hole C1 and a plurality of second pixel electrodes 109 formed integrally with the first pixel electrode 109, Two pixel electrodes 109a are arranged. A second common line (106) facing the first common line (111) is disposed between the pixel region and the second common line (106), and the second common line (106) And is formed integrally with the electrodes 106a.

The second pixel electrodes 109a and the second common electrodes 106a are alternately disposed at regular intervals in the pixel region, and the second common electrodes 106a disposed at both side edges of the pixel region 1 common electrode 121 and the predetermined portion. The first common electrode 121 is electrically connected to the second common line 106 formed integrally with the second common electrode 106a through the fourth contact hole C4.

The first pixel electrode 109 is parallel to the first common line 111 and partially overlaps with the first common line 111 to form a storage capacitor.

A gate pad 120 extending from the gate line 101 is formed in a pad region of the liquid crystal display device and a gate pad contact 120 electrically connected to the gate pad 120 through a second contact hole C2 is formed. An electrode 220 is formed.

A data pad 130 extending from the data line 103 is formed in the pad region and a data pad contact electrode 230 electrically contacted through the third contact hole C3 is formed on the data pad 130. [ .

1 and 2, a thin film transistor array substrate having a COT structure according to the present invention includes a lower substrate 100 made of a transparent insulating material, a gate electrode 101, a first common line 111, A first common electrode 121, a gate pad 120, and a data pad 130 are formed which are branched from the line 111.

The gate electrode 101, the first common line 111, the gate pad 120 and the data pad 130 may be formed of a metal such as molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W) ), Chromium (Cr), aluminum (Al), and alloys formed from combinations of these. In addition, although the metal film is formed of a single metal film, it may be formed by stacking at least two metal films.

As described above, the gate insulating film 102 is formed on the front surface of the lower substrate 100 on which the gate line (gate electrode) 101 is formed, and the channel insulating film 102 is formed on the gate electrode 101, The source electrode 104 and the source / drain electrodes 115a and 115b are formed to form a thin film transistor.

The source / drain electrodes 115a and 115b and the data line 103 may be formed of a metal such as molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr) ), Or an alloy formed from a combination of these. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the metal film is formed of a single metal film, it may be formed by stacking at least two metal films.

A first protective film 119 is formed on the lower substrate 100 on which the source / drain electrodes 115a and 115b and the data line 103 are formed. In the pixel region on the first protective film 119, The pixel electrode 109 and the second common electrode 106a are formed. Referring to FIG. 1, a second pixel electrode 109a and a second common electrode 106a are alternately arranged on a first protective layer 109 of the pixel region.

The first pixel electrode 109 is electrically connected to the drain electrode 115b of the thin film transistor through the first contact hole C1.

The first pixel electrode 109, the second common line 106, the second common electrode 106a, and the second pixel electrode 109a may be formed of any one of ITO, IZO and ITZO which are transparent conductive materials , The first pixel electrode 109 and the second pixel electrode 109a are formed of a transparent conductive material and the second common line 106 and the second common electrode 106a are formed using an opaque conductive material such as MoTi .

A gate pad 120 is formed in the gate pad region and extends from the gate line 101. A gate insulating layer 102 and a second contact hole 119 in which the first protective layer 119 is removed are formed on the gate pad 120. [ (C2) is formed. The gate pad contact electrode 220 is in electrical contact with the gate pad 120 through the second contact hole C2.

A data pad 130 is formed on the lower substrate 100 in the data pad region and the data pad 130 is formed through the third contact hole C3 in which the gate insulating film 102 and a part of the first protective film 119 are removed. The electrode 230 is in electrical contact with the data pad 130.

As described above, when a thin film transistor and pixel electrodes are formed on the lower substrate 100, a red (R) color filter layer 150 is formed in the pixel region. The color filter pattern 250 is formed to overlap the data line 103, the gate line 101, and the first common line 111 along the periphery of the pixel region.

The color filter pattern 250 includes at least two layers of red (R), green (G), and blue (B) color filter layers patterned with red (R), green (G), and blue Structure. This is not fixed but may be laminated with at least two of the red (R), green (G) and blue (B) color filter layers, as the case may be.

1, a pixel region in which a red (R) color filter layer 150 is formed is mainly described, but a pixel region in which adjacent green (G) and blue (B) color filter layers are formed also has the same structure.

In addition, if the color filter pattern 250 of the pixel region in which the red (R) color filter layer 150 is formed includes the red (R) color filter layer, it can be formed integrally with the red (R) color filter layer of the pixel region . This is true also in the pixel region where the green (G) and blue (B) color filter layers are formed.

2, the thin film transistor liquid crystal display device according to the present invention includes a color filter pattern (not shown) formed on the periphery of a pixel region, particularly, a column spacer region (CS region) with a red (R) color filter layer 150 formed in a pixel region as a center. (Not shown).

In addition, a blocking layer 222 is formed on the color filter pattern 250 corresponding to the CS region. The blocking layer 222 is formed in a region corresponding to the color filter pattern 250 and is formed in a region where the cell gap column spacer is located. In addition, the blocking layer 222 may be disposed to overlap the data line 103.

In addition, the blocking layer 222 is formed of the same material as the color resins forming the red (R), green (G), and blue (B) color filter layers. That is, a single layer of any one of red (R), green (G), and blue (B) color filter layers. However, in some cases, two or more color filter layers of red (R), green (G), and blue (B) color filter layers may be laminated. Reference is made to Figures 5A and 5B in this regard.

As described above, when the barrier layer 222 is formed, a second protective layer 129 is formed on the entire surface of the lower substrate 100.

FIG. 3 is a view showing the arrangement structure of the cell gap spacer and the pressed spacer in the column spacer region of FIG. 1. FIG.

1 to 3 together, a color filter pattern is disposed in a column spacer region (CS region) which is a non-display region of the pixel region of the present invention. That is, the CS region of the red (R) pixel region, the CS region of the green (G) pixel region and the CS region of the blue (B) pixel region are regions overlapping the gate line 101 and the first common line 111 .

 Cell gap column spacers CS1 and CS2 for maintaining the cell gap between the thin film transistor array substrate including the lower substrate 100 and the upper substrate 200 are disposed or the column spacers CS3 Can be located. In the drawings, the cell gap column spacers CS1 and CS2 are located in the red pixel region and the green pixel region, and the column spacer CS3 is located in the blue pixel region. However, The spacers and the pressed column spacers can be arranged regardless of the red (R), green (G), and blue (G) pixel regions.

That is, the cell gap column spacers C1 and C2 may be disposed in the column spacer region (CS region) of each pixel region, or the column spacer CS3 may be disposed. In the present invention, the blocking layer 222 is formed as a single layer or a plurality of layers of the color filter layer in the pixel region corresponding to the cell gap column spacers CS1 and CS2 and the blocking layer 222 is formed in the pixel region corresponding to the pressed column spacer CS3. 222 are not formed, so that a space can be formed between the pressed column spacer CS3 and the thin film transistor array substrate.

If the thickness of the cell gap column spacers CS1 and CS2 is greater than the thickness of the pressed column spacer CS3 without forming a step as described above, a gap is formed between the column spacer CS3 and the thin film transistor array substrate .

Further, in order to form the cell gap column spacer and the pressed column spacer having different thicknesses, two independent mask processes must be used, or a halftone mask process or a diffraction mask process must be used.

The addition of two masking processes complicates the process. When a halftone mask process or a diffractive mask process is used, a material having an optical density lower than that of a material capable of forming a column spacer in one mask process must be used There are drawbacks to vulnerability to light springs.

That is, in the structure in which the black matrix is removed like the thin film transistor array substrate having the COT structure of the present invention, when the optical density of the column spacer is low, defects of light are caused. Therefore, .

As described above, in the present invention, the cell gap column spacers CS1 and CS2 and the pressed column spacer CS3 are formed by a single mask process with a material having a high optical density. Therefore, their thicknesses have the same thickness. The blocking layer 222 is formed in the CS region corresponding to the cell gap column spacer CS1 and the blocking layer 222 is not formed in the CS region corresponding to the column spacer CS3, So that a pressed space can be formed in the pressed column spacer CS3 region.

Specifically, a thin film transistor array layer 160 is formed on the lower substrate 100, red (R), green (G), and blue (B) color filter layers are formed on the thin film transistor array layer 160 The color filter pattern 250 of the CS region is formed.

When the color filter pattern 250 formed by laminating at least two of the red (R), green (G), and blue (B) color filter layers is formed as described above, The blocking layer 222 is formed in the CS region of the red (R) and green (G) pixel regions corresponding to the spacers CS1 and CS2. The blocking layer 222 may be formed by laminating one or two or more color filter layers of red (R), green (G), and blue (B) color filter layers.

As described above, when the blocking layer 222 is formed on the lower substrate 100 on which the color filter pattern 250 is formed, the second protective layer 129 is formed on the lower substrate 100, Thereby completing the transistor array substrate.

When the thin film transistor array substrate and the upper substrate 200 are bonded together, the cell gap column spacers CS1 and CS2 among the column spacers formed on the upper substrate 200 are separated from the barrier layer 222 of the lower substrate 100 And maintains the cell gap between the lower substrate 100 (thin film transistor array substrate) and the upper substrate 200.

However, in the CS region of the blue (B) pixel region in which the blocking layer 222 is not formed in the pixel region, the pressed column spacer CS3 of the upper substrate 200 is located, and the pressed column spacer CS3 and the second A predetermined pressing space is formed between the protective films 129.

Therefore, unlike the cell gap column spacers CS1 and CS2, the pressed column spacer CS3, which is not in contact with the second protective film 129, and the thin film transistor array substrate are spaced apart by a predetermined distance? H.

That is, in the present invention, since the cell gap column spacers CS1 and CS2 and the pressed column spacers CS3 are formed to have the same thickness by one mask process, the column spacer formed by the halftone mask process or the diffraction mask process Excellent in characteristics. This is because, in order to form a column spacer by a halftone mask or a diffraction mask process, a material much lower than the optical density must be used.

Accordingly, the thin film transistor liquid crystal display device having the COT structure of the present invention from which the black matrix is removed has eliminated the light scattering defect that may occur in the region where the column spacers CS1, CS2, CS3 are formed.

FIGS. 4A to 4C are diagrams illustrating structures of a color filter pattern formed on a TFT LCD according to the present invention, and FIGS. 5A and 5B are views showing structures of a barrier layer formed on a TFT LCD according to an exemplary embodiment of the present invention. Fig.

4A to 5B, the color filter pattern 250 formed in the CS region of the red (R), green (G), and blue (B) pixel regions of the present invention includes red (R), green And blue (B) color filter layers.

Further, the red (R), green (G), and blue (B) color filter layers may be laminated in any order.

The blocking layer 222 formed on the color filter pattern 250 of the present invention may be formed of any one of color filter layers selected from red (R), green (G) and blue (B) color filter layers . However, it may be formed of two color filter layers arbitrarily selected from red (R), green (G) and blue (B) color filter layers as occasion demands, or may be formed of three color filter layers.

FIG. 6 is a view showing an arrangement structure of a cell gap spacer and a pressed spacer in a column spacer region according to another embodiment of the present invention.

The same reference numerals as those in FIG. 2 or 3 denote the same components, and the description will be centered on a portion different from FIG. 3 as follows.

Referring to FIGS. 1, 2 and 6 together, a color filter pattern 250 is disposed in a column spacer region (CS region) which is a non-display region of the pixel region of the present invention.

 In the present invention, a metal barrier layer 333 is formed between the thin film transistor array layer 160 and the color filter pattern 250. The metal barrier layer 333 may be formed not only in the non-display area of the pixel area, that is, the CS area, but also the area where the data line is formed.

A barrier layer 222 is formed on the color filter pattern 250 in the CS region of the red (R) and green (G) pixel regions corresponding to the cell gap column spacers CS1 and CS2 of the upper substrate 200 . The blocking layer 222 may be formed by laminating one or two or more color filter layers of red (R), green (G), and blue (B) color filter layers.

Although the metal barrier layer 333 is formed only in the region corresponding to the barrier layer 222 in FIG. 6, it may be formed in the CS region of each pixel region in some cases.

As described above, when the blocking layer 222 is formed on the lower substrate 100 on which the color filter pattern 250 is formed, the second protective layer 129 is formed on the lower substrate 100, Thereby completing the transistor array substrate.

When the thin film transistor array substrate and the upper substrate 200 are bonded together, the cell gap column spacers CS1 and CS2 among the column spacers formed on the upper substrate 200 are separated from the barrier layer 222 of the lower substrate 100 And maintains the cell gap between the lower substrate 100 (thin film transistor array substrate) and the upper substrate 200.

However, in the CS region of the blue (B) pixel region in which the blocking layer 222 is not formed in the pixel region, the pressed column spacer CS3 of the upper substrate 200 is located, and the pressed column spacer CS3 and the second A predetermined pressing space is formed between the protective films 129.

Therefore, unlike the cell gap column spacers CS1 and CS2, the pressed column spacer CS3, which is not in contact with the second protective film 129, and the thin film transistor array substrate are spaced apart by a predetermined distance? H.

In another embodiment of the present invention, the metal barrier layer 333 is formed in the non-display region (the CS region and the data line region in FIG. 1) around the red (R), green (G), and blue , The color filter pattern 250 and the blocking layer 222 are laminated on the metal barrier layer 333 to improve the light-blocking property.

101: gate line (gate electrode) 103: data line
104: channel layer 115a: source electrode
115b: drain electrode 119: first protective film
109: first pixel electrode 109a: second pixel electrode
222: blocking layer 250: color filter pattern
333: Metal barrier layer
CS1, CS2: cell gap column spacer CS3: pressed column spacer

Claims (14)

A lower substrate on which a plurality of gate lines and a plurality of data lines are arranged so as to define a plurality of pixel regions;
Wherein each of the pixel regions includes a plurality of common lines arranged in parallel with the gate lines and arranged to intersect with the data lines, switching elements arranged in an intersecting region of the gate lines and the data lines, A pixel electrode, and a common electrode,
A color filter layer disposed in the pixel region so as to cover the pixel electrode and the common electrode;
A color filter pattern disposed in an area overlapping the gate line and the common line along the periphery of the color filter layer;
An upper substrate bonded to the lower substrate;
A cell gap column spacer disposed for maintaining a cell gap between the upper substrate and the lower substrate, and a column spacer disposed for suppression; And
And a blocking layer formed on the color filter pattern corresponding to the cell gap column spacer,
The color filter pattern is formed by laminating at least two of red (R), green (G), and blue (B) color filter layers,
Wherein the cell gap column spacer and the pressed column spacer are disposed only on a region corresponding to the color filter pattern on the upper substrate,
Wherein the cell gap column spacer and the pressed column spacer are spaced apart from the pixel electrode and the common electrode.
The thin film transistor liquid crystal display of claim 1, wherein the thickness of the cell gap spacer is equal to the thickness of the column spacer.
The thin film transistor liquid crystal display of claim 1, wherein the color filter layer is formed of a single layer of any one of the red (R), green (G), and blue (B) color filter layers.
The organic electroluminescent device according to claim 1, wherein the barrier layer is formed by laminating a single layer of any one of the red (R), green (G) and blue (B) color filter layers or at least two or more thereof And the liquid crystal display device.
The thin film transistor liquid crystal display according to claim 1, wherein the color filter pattern is formed in a region overlapping with the data line.
delete A lower substrate on which a plurality of gate lines and a plurality of data lines are arranged so as to define a plurality of pixel regions;
Wherein each of the pixel regions includes a plurality of common lines arranged in parallel with the gate lines and arranged to intersect with the data lines, switching elements arranged in an intersecting region of the gate lines and the data lines, A pixel electrode, and a common electrode,
A color filter layer disposed in the pixel region so as to cover the pixel electrode and the common electrode;
A color filter pattern disposed in an area overlapping the gate line and the common line along the periphery of the color filter layer;
An upper substrate bonded to the lower substrate;
A cell gap column spacer disposed for maintaining a cell gap between the upper substrate and the lower substrate, and a column spacer disposed for suppression; And
And a blocking layer formed on the color filter pattern corresponding to the cell gap column spacer,
A metal barrier layer is formed under the color filter pattern,
The color filter pattern is formed by laminating at least two of red (R), green (G), and blue (B) color filter layers,
Wherein the cell gap column spacer and the pressed column spacer are disposed only on a region corresponding to the color filter pattern on the upper substrate,
Wherein the cell gap column spacer and the pressed column spacer are spaced apart from the pixel electrode and the common electrode.
The thin film transistor liquid crystal display of claim 7, wherein the thickness of the cell gap spacer is equal to the thickness of the column spacer.
The thin film transistor liquid crystal display of claim 7, wherein the color filter layer is formed of a single layer of any one of the red (R), green (G), and blue (B) color filter layers.
The organic light emitting display according to claim 7, wherein the barrier layer is formed by laminating a single layer of any one of the red (R), green (G), and blue (B) color filter layers or at least two or more thereof And the liquid crystal display device.
The thin film transistor liquid crystal display according to claim 7, wherein the color filter pattern is formed in a region overlapping the data line.
delete The thin film transistor liquid crystal display of claim 7, wherein the metal barrier layer is formed of the same metal as the pixel electrode and the common electrode.
8. The thin film transistor liquid crystal display of claim 7, wherein the metal barrier layer is disposed in an overlapping region with the data line.

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