KR101783581B1 - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention discloses a method of manufacturing a thin film transistor array substrate.
A method of manufacturing a thin film transistor array substrate according to the present invention includes the steps of providing a substrate divided into a display region and a non-display region, forming a metal film on the substrate, Forming a first storage electrode integrally formed with the first common line, the first common line, and the first common line, and forming a gate pad in a non-display region; forming a gate insulating film, And a source / drain metal film, forming a source / drain electrode, a second storage electrode formed integrally with the drain electrode, a channel layer, a data line, and a data pad according to a second mask process, A protective film and an organic insulating film are formed on the substrate on which the source / drain electrodes and the like are formed, and then, Forming a photoresist film, patterning the organic insulating film by performing exposure and development processes, and sequentially performing first and second etching processes with different oxygen content ratios of the etching gas using the patterned organic insulating film as an etching mask Exposing a protective film in each pixel region of the display region, forming a contact hole in the second storage electrode, the gate pad, and the data pad region, forming a metal layer on the organic insulating film on which the contact hole is formed, And forming a pixel electrode and a common electrode in the exposed pixel region.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. BACKGROUND ART [0002]

The present invention relates to a liquid crystal display device.

[0002] A liquid crystal display typically displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. The liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed.

In recent years, liquid crystal display devices employing various new methods have been developed to solve the narrow viewing angle problem of the liquid crystal display device. A liquid crystal display device having a wide viewing angle characteristic includes an in-plane switching mode (IPS), an optically compensated birefringence mode (OCB), and a fringe field swithching (FFS) mode.

In the transverse electric field type liquid crystal display device, a pixel electrode and a common electrode are disposed on the same substrate so that a horizontal electric field is generated between the electrodes. As a result, the long axes of the liquid crystal molecules are arranged in the horizontal direction with respect to the substrate, so that the liquid crystal molecules have a wide viewing angle characteristic as compared with a conventional TN (Twisted Nematic) type liquid crystal display device.

FIG. 1 is a view showing a pixel structure of a conventional transverse electric field type liquid crystal display device, and FIG. 2 is a sectional view taken along the line I-I 'of FIG.

Referring to FIGS. 1 and 2, a gate line 1 and a data line 5 intersect to define a pixel region, and a thin film transistor, which is a switching element, is disposed in the intersection region.

In the pixel region, a first common line (3) intersects the data line (5) so as to face the gate line (1). A first common electrode (3a) branched from the first common line (3) and parallel to the data line (3) is formed on both edge portions of the pixel region.

The gate line 1 has a gate electrode 1a having a larger width in the pixel region and a first storage electrode 6 is disposed in a region adjacent to the gate electrode 1a. The first storage electrode 6 is formed integrally with the first common electrode 3a.

A second common line 13 electrically connected to the first common line 3 is formed on the first common line 3. A third common electrode 13b overlapped with the first common electrode 3a and a second common electrode 13a formed in the pixel region are branched from the second common line 13. [

The pixel electrode 7a is connected to a second storage electrode 7 which overlaps with the first storage electrode 6 and is connected to the second common electrode 13a, do.

A gate insulating film 12 is formed on the lower substrate 10 and a data line 5 is formed on the gate insulating film 12 in the I-I 'cross section of the data line 5 region. On both sides of the data line 5, a first common electrode 3a formed on the lower substrate 10 is formed. A third common electrode 13b is formed on the first common electrode 3a with a protective film 19 therebetween.

The color filter substrate facing the data line 5 has a black matrix 21 formed on the upper substrate 20 and a red color filter layer 25a And a green (G) color filter layer 25b are formed. 29 is an overcoat layer.

In the conventional transverse electric field type liquid crystal display device, the width L1 of the black matrix 21 is enlarged in order to block the light leakage generated along the periphery of the pixel region by the light source generated from the backlight unit.

That is, in order to block light traveling in a predetermined oblique direction among the light passing between the data line 5 and the first common electrode 3a, the black matrix 21 is arranged outside the first common electrode 3a . As a result, the aperture ratio of the pixel region is decreased.

Further, in the prior art, the first common electrode 3a is disposed on both sides of the data line 5, which has limitations in improving the aperture ratio of the pixel region.

An object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same that improve the aperture ratio of a pixel region by disposing a common electrode over an organic insulating film over a data line.

Also, the present invention provides a thin film transistor array substrate which prevents a short defect of a channel layer pattern formed on a data line and a common electrode formed on a data line by using a halftone or diffraction mask, and a manufacturing method thereof There is another purpose.

According to an aspect of the present invention, there is provided a thin film transistor array substrate comprising: a substrate; A gate line and a data line cross-arrayed to define a pixel region on the substrate; A switching element disposed at an intersection of the gate line and the data line; A second pixel electrode and a first common electrode alternately arranged on an exposed protective layer of the pixel region; A second common electrode arranged to overlap the data line with a protective film and an organic insulating film interposed therebetween; A first storage electrode formed on the substrate; A second storage electrode formed integrally with the drain electrode of the switching element while overlapping the first story electrode with the gate insulating film therebetween; An organic insulating layer formed on the switching element, the second storage electrode, the gate pad, and the data pad; And a first pixel electrode connected to the second storage electrode through a contact hole, wherein the second common electrode surrounds the data line and the organic insulating layer, and a part of both edges of the second common electrode is formed on the protective layer of the pixel region .

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, comprising: providing a substrate divided into a display region and a non-display region; Forming a gate electrode, a gate line, and a first common line in a display region in accordance with a first mask process, and forming a gate pad in a non-display region, after forming a metal film on the substrate; Forming a source / drain electrode, a channel layer, a data line, and a data pad according to a second mask process after sequentially forming a gate insulating layer, a semiconductor layer, and a source / drain metal layer on the substrate having the gate electrode formed thereon; Forming a protective film and an organic insulating film on the substrate on which the source / drain electrodes and the like are formed, forming a photoresist according to a third mask process, and then performing an exposure and a development process to pattern the organic insulating film; The first and second etching processes are sequentially performed by using the patterned organic insulating film as an etching mask so that the oxygen content ratio of the etching gas is different to expose the protective film in each pixel region of the display region, Forming a contact hole in a storage electrode, a gate pad, and a data pad region; And forming a metal layer on the organic insulating film on which the contact hole is formed, and then forming a pixel electrode and a common electrode in a pixel region where the protective film is exposed.

As described above, according to the present invention, a common electrode for blocking the light leakage is disposed above the data line, thereby improving the defects of the light leakage and the pixel aperture ratio.

Further, the present invention has the effect of improving the transmissivity characteristic by exposing the pixel region to a protective film and alternately arranging the pixel electrode and the common electrode on the exposed protective film.

In addition, the present invention has an effect that a common electrode formed on a data line does not cause a data line or channel layer pattern and a shorting defect.

In addition, the present invention has an effect that a gap spacer holding the cell gap of the liquid crystal display device and a pressed spacer for preventing the pressing can be disposed to maintain a constant cell gap.

1 is a diagram showing a pixel structure of a transverse electric field type liquid crystal display device according to the related art.
2 is a sectional view taken along the line I-I 'of FIG. 1;
3 is a view showing a pixel region of a liquid crystal display device according to the first embodiment of the present invention.
FIGS. 4A and 8B are views showing a process of manufacturing a liquid crystal display device along the line II-II 'and III-III' of FIG.
FIGS. 9 to 11 are cross-sectional views taken along line IV-IV ', line V-V' and line VI-VI 'of FIG.
12A and 12B are diagrams showing the structure of a liquid crystal display device cut along line VII-VII 'in FIG.
FIGS. 13A and 13B are views for explaining problems occurring when a general etching process is applied in the contact hole forming process of the present invention.
FIGS. 14A to 14C are diagrams for explaining the etching process that proceeds when the contact hole of the present invention is formed. FIG.
15 to 17 are cross-sectional views taken along lines II-II 'and III-III' of FIG. 3 according to the second, third, and fourth embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Furthermore, in the description of the embodiments, it is to be understood that each pattern, layer, film, region, substrate, or the like is formed "on" or "under" each pattern, layer, film, The terms " on "and " under " all include being formed either" directly "or" indirectly "

In addition, reference to the top, side, or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

3 is a view showing a pixel region of a liquid crystal display device according to the first embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display of the present invention defines a pixel region by arranging gate lines 215 and data lines 315 in an intersecting manner. A thin film transistor (TFT) as a switching element is disposed in a region where the gate line 215 and the data line 315 intersect.

A first common line 225 is disposed in a region adjacent to the gate line 215 in parallel with the gate line 215. The first common line 225 also intersects the data line 315.

A gate electrode 250 is formed at a crossing region between the gate line 215 and the data line 315 so as to be wider than the gate line 215. The gate electrode 250 is used as a gate electrode of the thin film transistor. The gate electrode 250 and the gate line 215 are integrally formed. The thin film transistor (TFT) is composed of the gate electrode 250, the source electrode 440, the drain electrode 450, and a channel layer (not shown).

In addition, the first common line 225 is formed integrally with the first storage electrode 225a formed in the pixel region so as to be wider than the width of the first common line 225. The first storage electrode 225a forms a storage capacitor in the pixel region together with the second storage electrode 260 formed to overlap the upper portion. The second storage electrode 260 is formed integrally with the drain electrode 450.

A first pixel electrode 240 is formed in the pixel region so as to overlap the first common line 225 and a plurality of second pixel electrodes 730 are formed in the pixel region direction parallel to the data line 315, And is branched from the electrode 240. The second pixel electrode 730 is formed in the pixel region at a predetermined interval in a slit shape. Here, the second storage electrode 260 and the first pixel electrode 240 are connected to each other through the first contact hole 610.

A second common line 245 is formed so as to face the first common line 225 and the first storage electrode 225a with the pixel region therebetween. The first common electrode 740 is branched from the second common line 245 in the direction of the pixel region parallel to the data line 315. The first common electrode 740 is formed in a plurality of slit shapes and alternately arranged with the second pixel electrode in the pixel region.

The second common electrode 235 is branched at the edge of the second common line 245 so as to overlap the data line 315. The second common electrode 235 functions to block the light leakage generated in the data line 315 region by the backlight light source.

The second common electrode 235 is electrically connected to the first storage electrode 225a through a third contact hole 630. Therefore, a common voltage is supplied to the second common electrode 235, the first common electrode 740, and the second common line 245 via the first common line 225 and the first storage electrode 225a.

An organic insulating layer 600 is disposed between the two common electrodes 235 and the data line 315. Although not shown in the drawing, since the present invention is performed in a 4-mask process, the data line 315 and the semiconductor layer are simultaneously patterned to form a channel layer pattern (see FIG. 5A) under the data line 315.

Accordingly, in the present invention, in order to prevent short-circuiting between the second common electrode 235 and the channel layer pattern formed under the data line 315, a halftone or a diffraction mask is used in the contact hole forming step, (315).

A gate pad 210 extending from the gate line 215 is formed in a pad region of the liquid crystal display device and a gate pad contact 210 electrically connected to the gate pad 210 through a second contact hole 620 is formed. An electrode 710 is formed.

FIGS. 4A and 8B are views showing a process of manufacturing a liquid crystal display device along the line II-II 'and III-III' of FIG.

4A and 4B, a metal film is deposited on the lower substrate 100 made of a transparent insulating material by a sputtering method, and then the etching process is performed according to the first mask process.

In the first mask process, a photoresist, which is a photosensitive material, is formed on the deposited metal film, and then a photoresist pattern is formed by exposing and developing using a mask having a transmissive region and a non-transmissive region.

Then, the metal film is etched using the photoresist pattern as a mask to form the gate electrode 250, the first storage electrode 225a, and the gate pad 210. Next, as shown in FIG. A gate line 215 formed integrally with the gate electrode 250 and a first common line 225 integrally formed with the first storage electrode 225a are formed at the same time.

The metal film may use any one of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al) . In addition, although the metal film is formed of a single metal film, it may be formed by stacking at least two metal films.

5A and 5B, when the gate electrode 250 and the like are formed on the lower substrate 100 as described above, the gate insulating film 200, the amorphous silicon film, and the doped amorphous silicon film (n + p +) and the source / drain metal film are continuously formed.

The source / drain metal film may be formed of any one of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al) One can be used. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the metal film is formed of a single metal film, it may be formed by stacking at least two metal films.

When the source / drain metal layer is formed on the lower substrate 100, a second mask process using a halftone mask or a diffraction mask is performed to form the source / drain electrodes 440 and 450 and the second storage electrode 260 ), A data line 315, and a channel layer 340 are formed. Although not shown in the figure, a data pad is also formed at this time.

Depending on the use of a halftone mask or a diffraction mask, a channel layer pattern 320 is present below the data line 315. 5B, a storage capacitance is formed between the first storage electrode 225a and the second storage electrode 260. As shown in FIG. Thereafter, a protective film 500 is formed on the entire region of the lower substrate 100.

6A to 7, an organic insulating layer 600 is formed on a lower substrate 100 on which a protective layer 500 is formed. Then, the third mask process is carried out using the mask 850 composed of the completely transparent area P1, the non-transparent area P3 and the semi-transparent area P2. The completely transparent region P1 of the mask corresponds to the contact hole formation region and the semi-transparent region P2 corresponds to the pixel region.

In the third mask process, a contact hole is formed on the organic insulating film 600.

The organic insulating layer 600 has a lower dielectric constant than the protective layer 500. The dielectric constant may be 3.0 to 4.0, and preferably, the dielectric constant of the organic insulating film 600 may be 3.4 to 3.8. The thickness of the organic insulating layer 600 may be 3 to 6 占 퐉. The thickness of the organic insulating layer 600 may be designed to vary according to the driving frequency of the liquid crystal display device.

Particularly, when the driving frequency is high, a signal delay occurs due to the coupling effect between the data line 315 and the second common electrode (reference numeral 235 in FIG. 3) to be formed on the organic insulating film 600. In the present invention, the parasitic capacitance generated between the data line 315 and the second common electrode 235 is reduced by using the low dielectric constant organic insulating film 600 to prevent signal delay.

Because the parasitic capacitance is in inverse proportion to the distance between the data line 315 and the second common electrode 235, the parasitic capacitance value becomes small when the thickness of the organic insulating film 600 is increased. Accordingly, the signal delay due to the coupling effect generated between the data line 315 and the second common electrode 235 can be reduced.

For example, when the driving frequency of the liquid crystal display device of the present invention is 120 Hz, the thickness of the organic insulating film 600 is set to 2.5 to 3.5 μm, and when the driving frequency is 240 Hz, the organic insulating film 600 has a thickness of 5.5 to 6.5 μm. However, this is not a fixed design value and can be changed. In particular, when it is necessary to change the position of the second common electrode 235 in order to shield the pixel aperture ratio and the light leakage, the thickness of the organic insulating film 600 determined according to the driving frequency can be made smaller or larger.

The organic insulating layer 600 may be formed of an acrylic resin. The acrylic resin includes, but is not limited to, photo acryl. That is, the organic insulating layer 600 is not limited to the photoacrylic layer if it has a low dielectric constant.

The second storage electrode 260, the gate pad 210, and the data pad (not shown) corresponding to the completely transparent region P1 of the mask 850 The upper protective film 500 is exposed.

An organic insulating film pattern 600a having a smaller thickness than the organic insulating film 600 is formed in the pixel region corresponding to the transflective region P2 of the mask 850. [ That is, the protective film 500 is not exposed in the pixel region, and the organic insulating film pattern 600a exists.

After the exposure and development processes are completed as described above, the etching process is performed using the patterned organic insulating film 600 and the organic insulating film pattern 600a as masks.

The first contact hole 610 in which a part of the second storage electrode 260 is exposed and the second contact hole 620 in which a part of the gate pad 210 is exposed are formed in the etching process as described above . At this time, since the organic insulating film pattern 600a exists in the region corresponding to the pixel region, only the organic insulating film pattern 600a is removed by the etching process, and the protective film 500 is exposed.

Particularly, in the third mask process of the present invention, since the etching process is performed in a two-step etching process with different oxygen content ratios, the inclination of the side surfaces in the contact holes becomes gentle. The two-step etching process is described in detail below.

As shown in FIG. 7, in the third mask process, a third contact hole 630 is also formed on the first storage electrode 225a.

The organic insulating film 600, the lower protective film 500, and the gate insulating film 200 must be etched in the regions of the second and third contact holes 620 and 630 of the present invention. At this time, if the contact hole is formed only in the dry etching process as in the related art, a part of the organic insulating film 600 to be removed by the exposure and development processes remains, and the inclined inner surface of the contact hole is not uniform.

However, as described above, in the third mask process of the present invention, since the etching process proceeds to the two-stage etching process while changing the oxygen content ratio of the etching gas, such defects do not occur.

8A and 8B, a metal film 700 is formed on a lower substrate 100 on which contact holes are formed, and then a photoresist 770 is formed. Thereafter, the first pixel electrode 240, the first common electrode 740, the second pixel electrode 730, the second common electrode 235, and the gate Thereby forming a pad contact electrode 710.

The metal film may use any one of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al) . It may also be a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). I In addition, although it is formed of a single metal film in the drawing, in some cases, it may be formed by laminating at least two or more metal films.

However, the first common electrode 740, the second common electrode 235 and the gate pad contact electrode 710 are formed of opaque metal, and the first pixel electrode 240 and the second pixel electrode 730 are made of opaque metal. And the like. In this case, proceed to the second masking step.

In the present invention, it is preferable that the second common electrode 235 is formed of opaque metal so that the black matrix formed on the color filter substrate can be removed or the width thereof can be reduced.

The first pixel electrode 240, the first common electrode 740, the second pixel electrode 730, the second common electrode 235, and the gate pad contact electrode 710 are formed of a transparent conductive material. . In this case, a black matrix is formed on the color filter substrate corresponding to the data line 315.

The first pixel electrode 240 is connected to the second storage electrode 260 through the first contact hole 610. The second pixel electrode 730 and the first common electrode 740 are alternately formed on the lower substrate 100 in the form of slits in the pixel region. In particular, since the gate insulating layer 200 and the passivation layer 500 are present in the pixel region, the second pixel electrode 730 and the first common electrode 740 are formed on the passivation layer 500.

 In addition, the second common electrode 235 is formed so as to surround the data line 315 region. Specifically, a portion is formed on the protective film 500 along the side inclined surface, while being formed on the organic insulating film 600 on the data line 315. This is because when the protective film 500 is removed, the side surface of the channel layer pattern 320 existing under the data line 315 and the second common electrode 235 can be electrically shorted during the process. The data line 315 or the channel layer pattern 320 may be generated between the second common electrode 235 and the data line 315 without removing the protective layer 500 existing on the pixel region and the data line 315 in the present invention. Thereby preventing a shorting defect.

The second common electrode 235 functions to shield an electric field formed between the data line 315 and the second pixel electrode 730. Thus, defects in the light leakage occurring along the data line 315 can be removed. Since the dielectric constant of the organic insulating film 600 in the present invention is smaller than the dielectric constant of the protective film 500, the parasitic capacitance generated between the second common electrode 235 and the data line 315 is Can be reduced.

As described above, when the parasitic capacitance between the second common electrode 235 and the data line 315 is reduced, the signal delay that may be caused by the coupling effect is reduced.

The gate pad contact electrode 710 is electrically connected to the gate pad 210 through the second contact hole 620. Although not shown in the figure, the data pad contact electrode is electrically connected to the data pad in the data pad region.

FIGS. 9 to 11 are cross-sectional views taken along line IV-IV ', line V-V' and line VI-VI 'of FIG.

In the liquid crystal display device of the present invention, two kinds of spacers are formed. A gap spacer for keeping the cell gap of the color filter substrate and the thin film transistor array substrate constant, and a pressing spacer for preventing the gap spacer from being damaged by external pressing. The gap spacers are generally applied to liquid crystal display devices. Therefore, here, the pressing spacer formed together with the gap spacer will be mainly described.

Figs. 9-11 illustrate the pressed spacer 400. Fig. Since the position of the pressing spacer 400 is not fixed, the positions of the gap spacer (not shown) and the pressing spacer 400 can be variously changed.

The pressed spacer of the present invention serves to disperse the force that the gap spacer can sustain when the display area of the liquid crystal display device is pressed. In the case of forming only the gap spacer in the liquid crystal display device, the gap spacer may be broken or the restoring force may be lost by the external pressing force. Therefore, in the present invention, when the display area of the liquid crystal display device is pressed with a certain force, the pressed spacers and the gap spacers together keep the cell gap of the liquid crystal display device.

Fig. 9 shows a pressed spacer disposed in the storage capacitor forming region. Referring to FIGS. 3 and 9, a first storage electrode 225a formed integrally with the first common line 225 is formed on the lower substrate 100. Referring to FIG. A gate insulating layer 200, a passivation layer 500, an organic insulating layer 600, and a second storage electrode 260 are formed on the first storage electrode 225a.

Correspondingly, a black matrix 350 and an overcoat layer 371 are formed on the upper substrate 300 of the color filter substrate. On the overcoat layer 371, a pressed spacer 400 is formed.

A predetermined groove (G) is formed in the organic insulating film 600 corresponding to the pressing spacers 400. The grooves G may be formed by completely removing the organic insulating film 600 or by removing only a part of the organic insulating film 600.

Referring to FIGS. 3, 10 and 11, a pressed spacer 400 is formed over the gate line 215 and the data line 315, respectively. A groove G from which the organic insulating layer 600 is removed is formed on the gate line 315 corresponding to the pressed spacer 400. The protective film 500 is exposed in the groove (G) region. However, it is possible to leave the organic insulating film in the groove G region with a thickness smaller than the thickness of the organic insulating film 600.

In addition, a groove G is formed in a region corresponding to the pressed spacer 400 on the data line 315. A second common electrode 235 is formed on the organic insulating film 600. The second common electrode 235 is formed on the organic insulating layer 600, the side surface of the groove G, and the protective layer 500 exposed. However, a part of the organic insulating film smaller than the thickness of the organic insulating film 600 may be left in the groove (G) region.

This is because when the display area of the liquid crystal display device is pressed, the cell gap is maintained by the gap spacer until the pressed spacer 400 touches the bottom surface (organic insulating film or protective film) of the groove G, and the pressed spacer 400 So that the gap spacer (not shown) and the pressed spacer 400 together maintain the cell gap from the moment when they touch the bottom surface of the groove (G).

In other words, according to the present invention, only the gap spacer maintains the cell gap according to the force that is pushed in the display region of the liquid crystal display device, or the gap spacer and the pressed spacer maintain the cell gap together.

12A and 12B are diagrams showing the structure of a liquid crystal display device cut along line VII-VII 'in FIG.

Referring to Figs. 12A and 12B, the structure of the color filter substrate corresponding to the data line 315 region of the present invention is shown.

A data line 315 and a channel layer pattern 320 are formed on the lower substrate 100 with a gate insulating layer 200 interposed therebetween. A protective layer 500 and an organic insulating layer 600 are formed on the data line 315, Respectively.

A second common electrode 235 is formed on the organic insulating layer 600 on the data line 315. The second common electrode 235 has a structure in which both portions of the second common electrode 235 are formed on the passivation layer 500 while covering the organic insulating layer 600 and the passivation layer 500 formed on the data line 315.

Since the second common electrode 235 is formed of an opaque metal capable of blocking light, light incident from the back surface of the lower substrate 100 is blocked by the second common electrode 235. The second common electrode 235 may be formed of a metal such as molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al) Or an alloy thereof. In addition, the second common electrode 235 may be formed of at least one metal layer.

Therefore, the width (L2) of the black matrix 350 formed on the color filter substrate corresponding to the second common electrode 235 can be reduced as compared with the related art. The width of the black matrix 350 may be formed in the width of the second common electrode 235 and the width of the data line 315 (6 to 16 μm).

As described above, when the width of the black matrix 350 is reduced, the area of the adjacent red (R) color filter layer 303a, the green (G) color filter layer, and the blue (G) color filter layer (not shown) can be increased. Thus, the pixel aperture ratio of the liquid crystal display device can be improved.

In Fig. 12B, the color filter substrate on which the black matrix is completely removed is shown. That is, the second common electrode 235 formed on the thin film transistor array substrate serves as a black matrix. When the black matrix is removed, the pixel aperture ratio can be made larger than that of FIG. 12A.

FIGS. 13A and 13B are diagrams for explaining problems occurring when a general etching process is applied in the contact hole forming process of the present invention.

13A and 13B, a gate pad 210 is formed on the lower substrate 100 in the gate pad region of the present invention and a gate insulating film 200 and a protective film 500 And an organic insulating film 600 are formed.

If a dry etch process commonly used to expose the gate pad 210 is used, the taper of the inner surface of the hole becomes poor due to the organic insulating film 600 remaining in the hole region during the exposure and development processes .

An undercut structure is formed under the organic insulating film 600 due to the organic insulating film 600 remaining in the hole region, as shown in FIG. 13A. That is, a step is generated between the organic insulating film 600, the protective film 500, and the gate insulating film 200.

As shown in Fig. 13B, the stepped portion generated in the hole region causes a break of the metal film 470 to be formed later. The gate pad contact electrode formed in the gate pad region of the present invention is electrically disconnected by a step formed inside the contact hole. The metal film 470 may have a structure in which at least one metal film is stacked.

In order to solve such a problem, the present invention proceeds to two etching processes while changing the content ratio of the etching gas in forming the contact holes.

FIGS. 14A to 14C are diagrams for explaining the etching process that proceeds when the contact hole of the present invention is formed. FIG. This process can be directly applied to the third mask process of FIGS. 6A to 7.

 14A to 14C, a gate pad 210 is formed on the lower substrate 100. A gate insulating layer 200, a protective layer 500, and an organic insulating layer 600 are formed on the gate pad 210, Are sequentially formed.

When the organic insulating layer 600 is patterned by a mask process, the first etching process is performed using the organic insulating layer 600 as an etching mask. The flow ratio of SF ₆ : O ₂ in the etching gas used in the first etching step may be 1: 2.0 to 1: 3.0, preferably 1: 2.5. For example, in the case of SF ₆ : 4000, O ₂ has 10000 to 12000.

Thereafter, the second etching process is performed by changing the flow ratio of SF ₆ : O _{2 in} the etching gas. At this time, the flow ratio of SF ₆ : O ₂ is 1: 2.4 to 1: 3.0, preferably 1: 2.9.

That is, the oxygen (O ₂ ) content is increased during the first etching process and the second etching process, thereby improving the taper of the inner inclined surface of the contact hole region. It is preferable that the first etching time and the second etching time are the same or the second etching time is shorter than the first etching time.

As shown in FIG. 14B, it can be seen that the first inclined plane S1 and the second inclined plane S2 of the contact hole formed in the gate pad 210 region are formed in the same plane. That is, it can be seen that no step is generated between the organic insulating film 600, the protective film 500, and the gate insulating film 200. . Specifically, as shown in FIG. 14B, the inner surface of the organic insulating film 600, the inner surface of the protective film 500, and the inner surface of the gate insulating film 200 are disposed on the same plane.

Thereafter, as shown in FIG. 14C, a metal film 470 is formed on the lower substrate 100 on which the organic insulating film 600, the passivation film 500, and the gate insulating film 200 are formed, The metal film disconnection does not occur in the contact hole on the gate pad 210.

As described above, in the present invention, the step of two-step etching is performed in the third mask process to remove the step on the side surface inside the contact hole.

15 to 17 are cross-sectional views taken along lines II-II 'and III-III' of FIG. 3 according to the second, third, and fourth embodiments of the present invention.

The fabrication process of the second, third, and fourth embodiments of the present invention can be performed according to the fabrication process of the first embodiment of the present invention described above with reference to FIGS. 4A to 8B. Therefore, the description will be focused on the portion different from FIG. 8B. The same reference numerals as those in Fig. 8B designate the same components.

In the second and third embodiments of the present invention, the structure of the non-display region where the data pad and the gate pad are formed is changed, unlike the first embodiment of the present invention.

3 and 15, in the second embodiment of the present invention, the organic insulating film pattern 600a in the region where the gate pad 210 is formed and the organic insulating film 600 formed on the data line 315 So that they have different thicknesses.

Although not shown in the figure, an organic insulating film pattern is similarly formed in the data pad region. That is, the thickness of the organic insulating film pattern 600a in the non-display area where the gate pad and the data pad are formed is smaller than the thickness of the organic insulating film 600 overlapping the data line 315. This can be achieved by using a halftone mask or a diffraction mask in a third mask process to form the contact holes.

The reason why the organic insulating film 600 is formed at a low height in the pad region is that the thickness of the organic insulating film 600 is thicker than the protective film 500 and the gate insulating film 200, The contact failure of the electrodes 710 occurs.

Therefore, by lowering the stepped portion of the pad region, electrical contact with the external circuit terminals can be facilitated.

In the third embodiment shown in FIG. 16, the organic insulating layer 600 between the gate pad region and the data pad region is completely removed. The gate pad contact electrode 710 electrically connected to the gate pad 210 is formed on the protection layer 500 and is electrically connected to the gate pad 210. [ Similarly, a data pad contact electrode (not shown) is formed on the protective layer 500 and is electrically connected to a data pad (not shown).

In the fourth embodiment of FIG. 17, the organic insulating layer 600, the protective layer 500, and the gate insulating layer 200 are all removed in the gate pad region in the third mask process of the present invention. In the data pad region, only the organic insulating film 600 and the protective film 500 are structurally removed, and the gate insulating film 200 existing under the data pad remains.

However, the organic insulating layer 600, the protective layer 500, and the gate insulating layer 200 are all removed between the gate pads and the data pads to expose the lower substrate 100.

Accordingly, the gate pad contact electrode 710 is formed directly on the gate pad 210 and the lower substrate 100. It can be seen that the gate pad contact electrode 710 completely covers the gate pad 210.

As described above, in the present invention, the pad region of the liquid crystal display device can be formed in various structures without an additional mask process.

In the above description, the common electrode and the pixel electrode are formed on the protective film. However, the pixel electrode may be disposed between the protective film and the gate insulating film or disposed on the substrate. In addition, the pixel electrode may be formed in a slit structure, but may be formed in a pixel region in a plate shape. When the pixel electrode is in the form of a plate, a transparent conductive material is used.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

215: gate line 225: first common line
225a: first storage electrode 240: first pixel electrode
730: second pixel electrode 245: second common line
740: first common electrode 235: second common electrode

Claims (6)

Providing a substrate separated into a display area and a non-display area;
Forming a metal film on the substrate, forming a gate electrode, a gate line, a first common line and a first storage electrode integrally with the first common line in a display region according to a first mask process, Forming a gate pad;
A source electrode and a drain electrode are sequentially formed on a substrate on which the gate electrode and the like are formed, and then a source electrode and a drain electrode are formed in accordance with a second mask process, a second storage electrode integral with the drain electrode, Forming a data line and a data pad;
Forming a protective film and an organic insulating film on the substrate on which the source / drain electrodes and the like are formed, and then performing an exposure and a development process according to a third mask process to pattern the organic insulating film;
The protective layer is exposed in each pixel region of the display region by sequentially performing first and second etching processes with different oxygen content ratios of the etching gas using the patterned organic insulating layer as an etching mask, Forming a contact hole exposing each of the gate pad and the data pad; And
Forming a metal layer on the organic insulating film on which the contact hole is formed and then forming a pixel electrode and a common electrode in a pixel region in which the protective film is exposed,
Wherein the inner inclined surfaces of the contact holes are formed in the same plane so that the inner surface of the organic insulating film, the inner surface of the protective film, and the inner surface of the gate insulating film are disposed in the same plane.

The method according to claim 1, wherein in the third mask process, the organic insulating film is patterned using a halftone mask or a diffraction mask to form a third organic insulating film having a thickness smaller than that of the organic insulating film in the pixel region, ≪ / RTI >
The method according to claim 1, wherein in the third mask process, the thickness of the organic insulating film formed in the non-display region is made thinner than the thickness of the organic insulating film formed in the display region by using a halftone mask or a diffraction mask. Lt; / RTI >
The method according to claim 1, wherein the flow rate ratio of SF ₆ and O ₂ in the first etching gas is 1: 2.0 to 1: 3.0 in the third mask process.
2. The method of claim 1, wherein a flow rate ratio of SF ₆ and O ₂ of the second etching gas is 1: 2.4 to 1: 3.0 in the third mask process.
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