JP2000155335A - Manufacture of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a liquid crystal display device, capable of reducing the connection resistance of a pixel electrode and a drain electrode through a interlayer insulating film, and also, capable of satisfactorily patterning an ITO film free from a short circuit between mounted terminals on a single etching processing stage at the time of forming the pixel electrode, as for the liquid crystal display device having a pixel uppermost layer structure. SOLUTION: As for a process of forming a contact hole 12 in the interlayer insulating film 11 and a passivation film 10 in order to connect the pixel electrode 13 and the drain electrode 8, and as a dry etching condition, an etching processing with fluoro-gas and O2 gas, etc., is executed so as to reduce the unevenness on the surface of the interlayer insulating film 11 after executing an ashing process with O2 gas for removing the residual material in the bottom part of the contact hole 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing an active matrix type liquid crystal display device having a thin film transistor (hereinafter referred to as a TFT) as a switching element.

[0002]

2. Description of the Related Art A liquid crystal display device has a driving method as follows.
From the viewpoint of high display quality, an active matrix type TFT array using a TFT as a switching element is mainly used. To reduce the power consumption of the liquid crystal display device, it is effective to increase the effective display area of the pixel portion of the liquid crystal display panel, that is, to increase the aperture ratio of the pixel. As a TFT array effective for obtaining a liquid crystal display panel, after forming a TFT composed of a scanning electrode, a signal electrode and a semiconductor layer, an interlayer insulating film made of a transparent resin is provided so as to cover these, and a pixel electrode is formed on the uppermost layer. The structure to be formed is described, for example, in Japanese Patent No. 252
No. 1,752, Japanese Patent No. 2,598,420, and Japanese Patent Application Laid-Open No. 4-163528.

As a method of manufacturing a high aperture ratio TFT array having a structure in which a pixel electrode is formed on the uppermost layer, first, a gate electrode wiring and a gate electrode, a gate insulating film, a semiconductor layer are formed on a transparent insulating substrate such as a glass substrate. The TFT is formed by sequentially forming the source electrode wiring and the source / drain electrodes. Next, a passivation film made of a silicon nitride film is formed to protect the TFT. Next, an interlayer insulating film made of a transparent resin is formed, and contact holes are formed in the passivation film and the interlayer insulating film. Finally, a pixel electrode is formed on the interlayer insulating film, and a TFT array is formed. Note that the pixel electrode is electrically connected to the drain electrode via a contact hole formed in the passivation film and the interlayer insulating film. Terminals for electrically connecting each electrode wiring to an external substrate are formed outside the display area on the TFT array substrate on which the above-mentioned TFT array is formed. In a TFT array having such a structure, a pixel electrode can overlap a gate electrode wiring or a source electrode wiring, and the aperture ratio of a pixel can be improved.

However, since the interlayer insulating film is not formed in the mounting area where the terminals outside the display area of the TFT array substrate are formed, the following problems occur. In the step of forming the pixel electrode on the interlayer insulating film, after the ITO film forming the pixel electrode is formed on the interlayer insulating film, the etching region becomes the mounting region where the interlayer insulating film and the interlayer insulating film have been removed. The etching rate of the ITO film is significantly different from that on the transparent insulating substrate, and the etching rate of the ITO film on the interlayer insulating film is about 5 times or more higher than that of the ITO film on the transparent insulating substrate. Cannot be etched at once with the ITO film on the transparent insulating substrate. That is, when the etching time is adjusted to the etching of the ITO film on the interlayer insulating film at the time of forming the pixel electrode,
The ITO film on the transparent insulating substrate is not completely etched, and the remaining ITO film causes a short circuit between terminals.

Conventionally, in order to prevent a short circuit between the terminals, first, a first etching process is performed for an etching time corresponding to the etching of the ITO film on the interlayer insulating film serving as a display region. After protecting the ITO pattern on the film with the resist formed by the photoengraving process, a second etching process is performed with the etching time corresponding to the etching of the ITO film on the transparent insulating substrate, which is the mounting area, to form pixel electrodes Was. Also, JP-A-9-90
Japanese Patent No. 397 discloses a method in which a short circuit between terminals can be prevented by leaving an interlayer insulating film between terminals in a mounting region, and the ITO film is etched by a single etching process.

[0006]

SUMMARY OF THE INVENTION Conventional high aperture ratio TFT
The liquid crystal display device for realizing the array is configured as described above, and the mounting region for electrical connection between the external substrate provided outside the display region of the TFT array substrate and each electrode wiring is provided with an interlayer. Since the insulating film is not formed, two photoengraving steps and two etching steps are required in the pixel electrode forming step on the interlayer insulating film,
The manufacturing process becomes complicated, and there are problems such as a decrease in throughput and an increase in cost. Further, in the method in which the interlayer insulating film is left between the terminals, there is a problem in that when the terminals are connected to the external substrate, unevenness due to the interlayer insulating film increases the connection resistance.

In general, electrical connection between a pixel electrode and a drain electrode of a TFT in a TFT array having the above structure is made through a contact hole formed in an interlayer insulating film. CF ₄ + O ₂ or SF ₆ + O ₂ ,
Alternatively, after forming a contact hole by a dry etching method using another fluorine-based gas + O ₂ gas, an ashing process is performed with an O ₂ gas to remove the residue in the contact hole. However, the surface of the interlayer insulating film is also etched by the ashing process using the O ₂ gas,
Irregularities are formed on the surface of the interlayer insulating film. It has been found that the surface condition of the interlayer insulating film affects the etching property of the ITO film formed on the interlayer insulating film.

For example, CF ₄ + O ₂ or SF ₆ + O
₂ or after etching using a fluorine-based gas + O ₂ gas, the surface of the interlayer insulating film is smooth, and when the ITO film is formed on the interlayer insulating film in this state, the ITO film on the interlayer insulating film And the etching rate of the ITO film on the transparent insulating substrate becomes substantially the same, and the ITO film can be patterned by one etching process. Actually, when the etching process is performed for the optimum etching time of the ITO film on the transparent insulating substrate, the side etching amount of the ITO pattern on the interlayer insulating film is 1 μm or less on one side, and a good I
A TO pattern is obtained. However, if ashing is performed with O ₂ gas after etching using CF ₄ + O ₂ , SF ₆ + O ₂ , or fluorine-based gas + O ₂ gas, unevenness occurs on the surface of the interlayer insulating film. When an ITO film is formed on the film, the I
The etching rate of the TO film is about five times faster than that of the ITO film on the transparent insulating substrate, and the ITO film cannot be patterned by one etching process. Actually, when the etching process is performed for the optimal etching time of the ITO film on the transparent insulating substrate, the ITO film on the interlayer insulating film is
The side etch amount of the pattern is 3 μm or more on one side, and I
The TO pattern has an extremely tapered shape.

As described above, when an ashing process using O ₂ gas is performed to reduce the connection resistance between the pixel electrode and the drain electrode, the ITO film on the interlayer insulating film and the ITO film on the transparent insulating substrate are removed. If patterning cannot be performed in one etching process and ashing using O ₂ gas is not performed, the ITO film on the interlayer insulating film and the ITO film on the transparent insulating substrate are subjected to one etching process. However, there is a problem that the connection resistance between the pixel electrode and the drain electrode increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can reduce and stabilize the connection resistance between a pixel electrode and a drain electrode. Without causing a short circuit,
It is an object of the present invention to provide a method of manufacturing a liquid crystal display device that can pattern a TO film in one etching process.

[0011]

According to a method of manufacturing a liquid crystal display device according to the present invention, two transparent insulating substrates having electrodes formed on at least one of them are opposed to each other and bonded together. In a method of manufacturing a liquid crystal display device having a liquid crystal material sandwiched between transparent insulating substrates, a step of forming a scanning electrode, a scanning electrode wiring and a scanning electrode wiring terminal on one of two transparent insulating substrates, A scan electrode, a step of forming an insulating film on the scan electrode wiring and the scan electrode wiring terminal, a step of forming a semiconductor layer on the scan electrode via the insulating film, and a first electrode and a first electrode on the semiconductor layer. Forming an electrode wiring, a first electrode wiring terminal and a second electrode,
Forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode, applying a photosensitive transparent resin on the passivation film, exposing and developing Forming a contact hole on the second electrode, and an interlayer insulating film having an opening in a mounting region where the scanning electrode wiring terminal and the first electrode wiring terminal are formed, and using the interlayer insulating film as a mask to form a contact. A step of etching the passivation film and the insulating film exposed by the holes and the opening by a dry etching method; and a step of etching the interlayer insulating film and the inside of the contact hole, and the transparent insulating substrate exposed by the opening and the scanning electrode wiring terminal. A transparent conductive film is formed on the electrode wiring terminals of
Patterning is performed by one etching process to form a transparent conductive film pattern on the pixel electrode electrically connected to the second electrode through the contact hole, and on the scanning electrode wiring terminal and the first electrode wiring terminal. Including the steps, the surface of the interlayer insulating film after the etching process by the dry etching method is in a smooth state.

In addition, at least one of the two transparent insulating substrates having electrodes formed thereon is opposed to and bonded to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. In a method for manufacturing a display device, a step of forming a scan electrode, a scan electrode wiring and a scan electrode wiring terminal on one of two transparent insulating substrates, and forming an insulating film on the scan electrode, the scan electrode wiring and the scan electrode wiring terminal Forming, forming a semiconductor layer on the scan electrode via an insulating film, removing the insulating film in a mounting area where the scan electrode wiring terminal and the first electrode wiring terminal are formed, Forming a first electrode, a first electrode wiring, a first electrode wiring terminal and a second electrode on the first electrode, a first electrode wiring, a first electrode wiring terminal and a second electrode; Passivation on electrodes Forming a transparent resin having photosensitivity on the passivation film, exposing and developing a contact hole on the second electrode, and a scanning electrode wiring terminal and a first electrode wiring terminal were formed. A step of forming an interlayer insulating film having an opening in the mounting region, a step of etching the passivation film exposed by the contact hole and the opening by a dry etching method using the interlayer insulating film as a mask, and a step of forming a contact hole on the interlayer insulating film. Inside, and on the transparent insulating substrate exposed by the opening and the scanning electrode wiring terminal, a transparent conductive film is formed on the first electrode wiring terminal, patterned by a single etching process, and the second electrode Transparent conductive on the pixel electrode electrically connected through the contact hole, and on the scanning electrode wiring terminal and the first electrode wiring terminal Includes forming a pattern, the interlayer insulation film surface after etching with a dry etching method is smooth state.

A liquid crystal comprising two transparent insulating substrates having electrodes formed on at least one of them, which are opposed to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. In a method for manufacturing a display device, a step of forming a scan electrode, a scan electrode wiring and a scan electrode wiring terminal on one of two transparent insulating substrates, and forming an insulating film on the scan electrode, the scan electrode wiring and the scan electrode wiring terminal Forming, forming a semiconductor layer on the scanning electrode via an insulating film, forming a first electrode, a first electrode wiring, a first electrode wiring terminal and a second electrode on the semiconductor layer And a step of forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode,
A transparent resin having photosensitivity is coated on the passivation film, and a contact hole is formed on the second electrode by exposure and development, and an opening is formed in a mounting area where the scanning electrode wiring terminal and the first electrode wiring terminal are formed. Forming an interlayer insulating film having, and applying a photoresist, forming a resist by patterning the same shape as the interlayer insulating film,
Using the resist as a mask, etching the passivation film and the insulating film exposed by the contact hole and the opening by a dry etching method, and then removing the resist;
And a transparent conductive film is formed on the transparent insulating substrate, the scanning electrode wiring terminal, and the first electrode wiring terminal exposed by the opening, and is patterned by a single etching process to form a second electrode and a contact hole. And a step of forming a transparent conductive film pattern on the pixel electrode and the scanning electrode wiring terminal and the first electrode wiring terminal which are electrically connected to each other.

Further, at least one of the transparent insulating substrates having electrodes formed thereon is opposed to and bonded to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. In a method for manufacturing a display device, a step of forming a scan electrode, a scan electrode wiring and a scan electrode wiring terminal on one of two transparent insulating substrates, and forming an insulating film on the scan electrode, the scan electrode wiring and the scan electrode wiring terminal Forming, forming a semiconductor layer on the scanning electrode via an insulating film, forming a first electrode, a first electrode wiring, a first electrode wiring terminal and a second electrode on the semiconductor layer And a step of forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode,
A step of applying a transparent resin having no photosensitivity on the passivation film, forming an interlayer insulating film, forming a resist, etching the interlayer insulating film, the passivation film and the insulating film by a dry etching method, Forming a contact hole on the electrode, and an opening in the mounting region where the scanning electrode wiring terminal and the first electrode wiring terminal are formed, and then removing the resist; and forming an opening on the interlayer insulating film, in the contact hole, and in the opening. A transparent conductive film is formed on the transparent insulating substrate, the scanning electrode wiring terminal, and the first electrode wiring terminal, which are exposed by the portion, and is patterned by a single etching process. Forming a transparent conductive film pattern on the pixel electrode and the scanning electrode wiring terminal and the first electrode wiring terminal which are electrically connected to each other. .

Further, after forming the semiconductor layer, the insulating film in the mounting region where the scanning electrode wiring terminal and the first electrode wiring terminal are to be formed is first electrode, first electrode wiring, first electrode wiring terminal and The method includes a step of removing before forming the second electrode. The etching condition by the dry etching method using the interlayer insulating film as a mask is the first CF ₄ +
O ₂ , or SF ₆ + O ₂ , or other fluorine-based gas +
After etching with O ₂ gas, the ashing treatment with O ₂ gas, further second time CF ₄ + O ₂ or SF _6,
+ O _2, or in which the etching process is performed by another fluorine-based gas + O ₂ gas. Furthermore, the second CF ₄
+ O ₂ , or SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas is subjected to the first CF processing.
₄ + O ₂ , or SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas It is performed in a shorter time than the etching process.
Alternatively, the flow rate ratio of the O ₂ gas is increased, the power is reduced, or at least any two of the above processing conditions are combined.

In addition, after the resist is formed on the interlayer insulating film,
The etching condition by the lye etching method is CF_Four
+ O_Two, Or SF₆+ O_TwoOr other fluorine-based gas
+ O _TwoAfter etching with gas, O_TwoA by gas
This is to perform a washing process. In addition, there is an interlayer insulating film.
Dry etching using a resist as a mask.
Etching condition is the first CF_Four+ O_Two,Also
Is SF₆+ O_TwoOr other fluorine-based gas + O_TwoTo gas
After the etching process, the second CF_Four+ O_TwoOr
SF₆+ O_TwoOr other fluorine-based gas + O_TwoBy gas
Etching process_TwoGas flow ratio higher than the first time
That is what you do.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a method for manufacturing a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a TF of a liquid crystal display device equipped with a TFT as a switching element according to a first embodiment of the present invention.
2 is a schematic plan view of the periphery of the TFT array substrate shown in FIG. 1, and FIG. 3 is a cross-sectional view showing a state during the manufacturing process of the TFT array substrate shown in FIG. In the figure, reference numeral 1 denotes a transparent insulating substrate such as a glass substrate, 2 denotes a scanning electrode (gate electrode in the present embodiment) formed on the transparent insulating substrate 1, and 2a denotes a scanning electrode wiring (scanning electrode) having the scanning electrode 2. In the embodiment, gate electrode wirings), 2b are scanning electrode wiring terminals (gate terminals in this embodiment) formed extending from the scanning electrode wirings 2a, and 3 are common electrodes formed on the transparent insulating substrate 1. Reference numeral 4 denotes a gate insulating film formed on the gate electrode 2, the gate electrode wiring 2a and the common wiring 3, reference numeral 5 denotes a semiconductor layer formed on the gate electrode 2 via the gate insulating film 4, and reference numeral 6 denotes a semiconductor layer. Contact layers 7 and 8 have a first electrode and a second electrode (a source electrode and a drain electrode in the present embodiment) formed on the contact layer 6, and 7a has a first electrode 7. First electrode wiring (this embodiment 7b, a first electrode wiring terminal (source terminal in this embodiment) formed by extending from the first electrode wiring 7a, 9 a channel portion, 10 a passivation film, and 11 a An interlayer insulating film formed on the passivation film 10, 12 is a contact hole formed in the passivation film 10 and the interlayer insulating film 11, and 13 is a pixel electrode formed on the interlayer insulating film 11, and is a pixel electrode formed on the interlayer insulating film 11. Membrane 11
Is electrically connected to the drain electrode 8 through the contact hole 12 formed at the bottom. Reference numeral 13a denotes an ITO film on the terminals 2b and 7b formed simultaneously with the pixel electrode 13. Reference numeral 14 denotes a mounting region in which the terminals 2b and 7b are provided. In the mounting region 14, the gate insulating film 4, the passivation film 10, and the interlayer insulating film. 11 is removed, and the transparent insulating substrate 1 is exposed between the terminals 2b and 7b.

Next, the T of the liquid crystal display device according to the present embodiment will be described.
The manufacturing process of the FT array substrate will be described. First, a Cr film is formed on the surface of the transparent insulating substrate 1 by a sputtering method or the like, and a resist is formed by a photoengraving method and patterning is performed by a wet etching method to form a gate electrode 2, a gate electrode wiring 2a, and a gate terminal 2b. And the common wiring 3 is formed. Next, a silicon nitride film, an amorphous silicon film, and an impurity-doped low-resistance amorphous silicon film forming the gate insulating film 4 are sequentially formed by using a plasma CVD method. The semiconductor layer 5 and the contact layer 6 are formed by patterning by an etching method. Next, a Cr film is formed by a sputtering method, a resist is formed by a photoengraving method, and patterning is performed by a wet etching method.
a, after forming the source terminal 7 b and the drain electrode 8, the low-resistance amorphous silicon film (contact layer 6) which is not covered by the source electrode 7 and the drain electrode 8 is etched by dry etching, Is formed to form a TFT.

Next, in order to protect the TFT, a silicon nitride film serving as a passivation film 10 is formed by a plasma CVD method. Next, an acrylic transparent resin having photosensitivity is applied by a spin coating method or the like, and is exposed and developed so that the surface is flattened by absorbing a step due to the TFT and the electrode wiring. Is formed, bleaching exposure and baking are performed to form an interlayer insulating film 11. At this time, as shown in FIG. 2, the gate electrode wiring 2a or the source electrode wiring 7a is connected to an external substrate (not shown).
In the mounting region 14 in which the gate terminal 2b and the source terminal 7b for electrically connecting with the terminal 2b, the interlayer insulating film 1 is provided on the terminals 2b, 7b and between the terminals 2b, 7b.
1 has been removed to be absent. Each terminal 2b, 7b
The reason why the interlayer insulating film 11 is removed is to prevent the connection resistance between the terminals 2b and 7b and the external substrate from increasing due to the unevenness of the interlayer insulating film 11. Next, using the interlayer insulating film 11 as a mask, the passivation film 10 exposed by the contact hole formed in the interlayer insulating film 11 is etched by dry etching to form the contact hole 12 and to form the passivation film in the mounting region 14. 10 and the gate insulating film 4 are etched.
At this time, in the mounting area 14, the transparent insulating substrate 1 is exposed between the terminals 2b and 7b.

FIG. 3 shows an etching process of the passivation film 10 and the gate insulating film 4 using the interlayer insulating film 11 as a mask by a dry etching method. The dry etching conditions for the passivation film 10 and the gate insulating film 4 are such that the silicon nitride forming the passivation film 10 and the gate insulating film 4 is etched with CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas. After that, an ashing process using O ₂ gas is performed to reduce the connection resistance between the pixel electrode 13 and the drain electrode 8 formed in the next step, and the residue on the drain electrode 8 at the bottom of the contact hole 12 is removed. At this time, CF ₄ + O ₂ or SF ₆ +
Because O ₂ or ashing treatment by etching and O ₂ gas by another fluorine-based gas + O ₂ gas, is performed, unevenness is formed on the surface of the interlayer insulating film 11. Next, CF ₄ + O is again formed for the purpose of reducing irregularities on the surface of the interlayer insulating film 11 formed by the ashing treatment of the O ₂ gas.
₂ , or SF ₆ + O ₂ , or other fluorine-based gas + O
Perform an etching process using _two gases.

The second CF ₄ + O ₂ or SF
Etching with ₆ + O ₂ or another fluorine-based gas + O ₂ gas is performed for a second time shorter than the first etching time in order to prevent reattachment of the residue of the interlayer insulating film 11 into the contact hole 12. Is performed. Alternatively, the second etching process is performed by increasing the flow rate ratio of CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas to O ₂ gas. Alternatively, a second etching process is performed with a lower power than the first etching process. Alternatively, the short-time treatment described above, O ₂
The etching process is performed by combining at least any two conditions of increasing the flow rate ratio and decreasing the power.

Next, an ITO film is formed by a sputtering method, and a pixel electrode 13 and each terminal 2 are formed on the interlayer insulating film 11 by forming and etching a resist by a photoengraving method.
An ITO film 13a is formed on b and 7b. At this time, the pixel electrode 13 is electrically connected to the drain electrode 8 via the contact hole 12. The etching of the ITO film, before the step, subjected to O ₂ again CF ₄ + O ₂ after ashing gases or SF ₆ + O ₂ etching process or by another fluorine-based gas + O ₂ gas,
By reducing irregularities on the surface of the interlayer insulating film 11, the etching rate of the ITO film on the interlayer insulating film 11 and the etching rate of the ITO film on the transparent insulating substrate 1 between the terminals 2b and 7b in the mounting region 14 become substantially the same. The pixel electrode 13 and the ITO film 13a in the mounting region 14 can be simultaneously patterned by one etching process.

An alignment film is formed on the surface of the TFT array substrate formed by the above process and the surface of a counter substrate on which a counter electrode and the like are formed on another transparent insulating substrate, and then the liquid crystal material is injected therebetween. Thus, a liquid crystal display element is formed.

In the etching of the ITO film forming the pixel electrode 13, if the etching process is performed for the optimum etching time of the ITO film on the transparent insulating substrate 1,
The side etch amount of the ITO pattern (pixel electrode 13) on the interlayer insulating film 11 was 1 μm or less on one side, and a pattern having a good shape was obtained. The connection resistance between the pixel electrode 13 and the drain electrode 8 was 35 μm □ and was several hundred Ω or less.

According to the present invention, in the step of forming contact hole 12 for connecting pixel electrode 13 and drain electrode 8 formed on interlayer insulating film 11, passivation film 10 using interlayer insulating film 11 as a mask is formed. And CF ₄ + O ₂ or SF ₆ + of the gate insulating film 4
O ₂ or an etching treatment with other fluorine-based gas + O ₂ gas, and the residue was removed with the contact hole 12 after the ashing treatment with O ₂ gas for the purpose, or again CF ₄ + O ₂ or SF ₆ + O _2, By performing the etching process using another fluorine-based gas + O ₂ gas, the unevenness of the surface of the interlayer insulating film 11 formed by the ashing process of the O ₂ gas can be reduced, and the contact hole 12
The connection resistance between the pixel electrode 13 and the drain electrode 8 can be reduced via the TFT. In addition, when the pixel electrode 13 is formed, the ITO film on the interlayer insulating film 11 and each terminal 2 in the mounting region 14 are removed.
The ITO film on the transparent insulating substrate 1 between b and 7b can be patterned by a single etching process.

Embodiment 2 FIG. In the first embodiment, etching of the passivation film 10 and the gate insulating film 4 using the interlayer insulating film 11 as a mask is performed by first using CF ₄ +
O ₂ , or SF ₆ + O ₂ , or other fluorine-based gas +
O ₂ gas etching the passivation film 10 and the gate insulating film 4 by, then ashing treatment with O ₂ gas for the purpose of residue removal of the contact hole 12 bottom, and then the purpose of unevenness reduction of the interlayer insulating film 11 surface The second etching was performed by using CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas. First, CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas was used. + O ₂ gas with was etched passivation film 10 and the gate insulating film 4, then O ₂ flow rate ratio of the gas increased to a second time CF ₄
By performing an etching process using + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, the residue at the bottom of the contact hole 12 is removed, and the pixel electrode 13 and the drain electrode via the contact hole 12 are removed. 8 and the roughness of the surface of the interlayer insulating film 11 can be reduced as compared with the ashing process using O ₂ gas.
The etching property of the ITO film on the transparent insulating substrate 1 between the film and each of the terminals 2b and 7b in the mounting region 14 can be improved.

Embodiment 3 FIG. 4 is a cross-sectional view showing a state during the manufacturing process of the TFT array substrate of the liquid crystal display device according to Embodiment 3 of the present invention. In the figure, reference numeral 15 denotes a resist formed on the interlayer insulating film 11. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

Next, a process of manufacturing the TFT array substrate of the liquid crystal display according to the present embodiment will be described. In the same manner as in the first embodiment, a gate electrode 2, a gate electrode wiring (not shown), a gate terminal 2
b, common electrode 3, gate insulating film 4, semiconductor layer 5, contact layer 6, source electrode 7, drain electrode 8, source electrode wiring (not shown), source terminal (not shown), channel 9, and passivation film 10 are sequentially formed. Next, an acrylic transparent resin having photosensitivity is applied by spin coating or the like, exposed and developed to form a contact hole, and then bleaching exposure and baking are performed to form an interlayer insulating film 11. At this time, as shown in FIG.
Gate terminal 2 for electrically connecting gate electrode wiring 2a or source electrode wiring 7a to an external substrate (not shown)
In the mounting region 14 where the b and source terminals 7b are provided, the interlayer insulating film 11 is removed so as not to exist on the terminals 2b, 7b and between the terminals 2b, 7b.

Next, a photoresist is applied on the interlayer insulating film 11, the photoresist is exposed using a mask used for exposing the acrylic transparent resin, and a developing process is performed. Resist 1 with the same pattern as 11
5 is formed. Next, using the resist 15 as a mask, the passivation film 10 is etched by a dry etching method to form a contact hole 12, and the passivation film 10 and the gate insulating film 4 in the mounting region 14 are etched. The dry etching condition of the passivation film 10 and the gate insulating film 4 is CF ₄ + O
₂ , or SF ₆ + O ₂ , or other fluorine-based gas + O
_{After the} passivation film 10 and the silicon nitride forming the gate insulating film 4 are etched by the _two gases, the residue at the bottom of the contact hole 12 is removed to reduce the connection resistance between the pixel electrode and the drain electrode 8 formed in the next step. An ashing process using O ₂ gas is performed for the purpose. After that, the resist 15 is removed. During the ashing process using the O ₂ gas, since the surface of the interlayer insulating film 11 is protected by the resist 15, no irregularities are formed on the surface of the interlayer insulating film 11.

Thereafter, an ITO film is formed on the pixel electrodes and the terminals 2b and 7b in the same manner as in the first embodiment, and a TFT array substrate is formed. The dry etching of the passivation film 10 and the gate insulating film 4 is performed by first etching silicon nitride with CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, and then etching the bottom of the contact hole 12. CF ₄ with a high flow rate of O ₂ gas for the purpose of removing residue
Similar effects can be obtained by performing an etching process using + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas.

According to the present embodiment, ashing treatment of O ₂ gas for the purpose of removing the residue at the bottom of the contact hole 12 or CF ₄ having a high flow rate of O ₂ gas is performed.
By performing etching with + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas while the surface of the interlayer insulating film 11 is protected by the resist 15,
No irregularities are formed on the surface of the interlayer insulating film 11, so that the connection resistance between the pixel electrode and the drain electrode 8 through the contact hole 12 can be reduced. The etching rate of the ITO film on the transparent insulating substrate 1 between the terminals 2b and 7b in the mounting area 14 is substantially the same, and the pixel electrode and the ITO film in the mounting area 14 can be patterned by one etching process.

Embodiment 4 FIG. FIG. 5 is a cross-sectional view showing a state during the manufacturing process of the TFT array substrate of the liquid crystal display device according to Embodiment 4 of the present invention. Note that the reference numerals in the figure are the same as those in FIG.

Next, a process of manufacturing the TFT array substrate of the liquid crystal display according to the present embodiment will be described. In the same manner as in the first embodiment, a gate electrode 2, a gate electrode wiring (not shown), a gate terminal 2
b, common electrode 3, gate insulating film 4, semiconductor layer 5, contact layer 6, source electrode 7, drain electrode 8, source electrode wiring (not shown), source terminal (not shown), channel 9, and passivation film 10 are sequentially formed. Next, an acrylic transparent resin having no photosensitivity is applied by using a spin coating method or the like, followed by baking to form an interlayer insulating film 11. Next, a photoresist is applied on the interlayer insulating film 11, exposed and developed to form a resist 15 having an opening pattern at a predetermined position.

Next, using the resist 15 as a mask, the interlayer insulating film 11 and the passivation film 10 are etched by dry etching to form a contact hole 12, and the interlayer insulating film 11, the passivation film 10 and the gate insulating film in the mounting region 14 are formed. The film 4 is etched. The dry etching condition of the interlayer insulating film 11, the passivation film 10, and the gate insulating film 4 is CF ₄ +
O ₂ , or SF ₆ + O ₂ , or other fluorine-based gas +
After etching the interlayer insulating film 11, the passivation film 10 and the silicon nitride forming the gate insulating film 4 with O ₂ gas, the residue at the bottom of the contact hole 12 is removed, and the pixel electrode and the drain electrode formed in the next step are formed. 8
An ashing process using O ₂ gas is performed for the purpose of reducing the connection resistance with the O2 gas. After that, the resist 15 is removed.
During the ashing process using the O ₂ gas, since the surface of the interlayer insulating film 11 is protected by the resist 15, no irregularities are formed on the surface of the interlayer insulating film 11. Thereafter, an ITO film is formed on the pixel electrode, the gate terminal 2b, and the source terminal by the same method as in Embodiment 1, and a TFT array substrate is formed.

The dry etching of the interlayer insulating film 11, the passivation film 10, and the gate insulating film 4 is first performed by using CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas. After the etching of the silicon nitride 11 and the silicon nitride, CF ₄ + O ₂ or SF ₆ + O ₂ with a high flow rate of O ₂ gas, or another fluorine-based gas + O ₂ gas for the purpose of removing the residue at the bottom of the contact hole 12 The same effect can be obtained by performing the etching process by using.

According to the present embodiment, the interlayer insulating film 11 is made of an inexpensive acrylic transparent resin having no photosensitivity, and the interlayer insulating film 11 is patterned by the interlayer insulating film 1.
Since the etching of the passivation film 10 can be performed collectively using the resist 15 formed for the purpose of protecting one surface as a mask, the material cost can be reduced and the third embodiment can be implemented without increasing the number of manufacturing steps. Similar effects can be obtained.

Embodiment 5 In the first, second, third, and fourth embodiments, the gate insulating film 4 on the gate terminal 2b in the mounting region 14 is etched using the interlayer insulating film 11 or the resist 15 as a mask after forming the interlayer insulating film 11. The same effect can be obtained by applying the present invention to a liquid crystal display device having a structure in which the gate insulating film 4 on the gate terminal 2b is removed by etching after the formation of the layer 5 and the contact layer 6, and a manufacturing process.

FIG. 6 is a sectional view showing a TFT array substrate of a liquid crystal display according to a fifth embodiment of the present invention, and FIG.
FIG. 7 is a cross-sectional view showing a state during the manufacturing process of the TFT array substrate of FIG. Note that the reference numerals in the figure are the same as those in FIG. Next, a manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described. In the same manner as in the first embodiment, a gate electrode 2, a gate electrode wiring (not shown), a gate terminal 2
b, a common electrode 3, a gate insulating film 4, a semiconductor layer 5, and a contact layer 6 are sequentially formed. Next, after forming a resist having an opening pattern at a predetermined position by a photoengraving method,
The gate insulating film 4 in the mounting region 14 is etched by a dry etching method. Next, a Cr film is formed by a sputtering method, a resist is formed by a photoengraving method, and patterning is performed by a wet etching method, and a source electrode 7, a source electrode wiring (not shown), and a source terminal (not shown) are formed. After the formation of the Cr film 7c on the drain electrode 8 and the gate terminal 2b, the low-resistance amorphous silicon film (contact layer 6) not covered by the source electrode 7 and the drain electrode 8 is etched by dry etching. Then, a channel portion 9 is formed to form a TFT.

Next, in order to protect the TFT, a silicon nitride film serving as a passivation film 10 is formed by a plasma CVD method. Next, an acrylic transparent resin having photosensitivity is applied by a spin coating method or the like, and is exposed and developed so that the surface is flattened by absorbing a step due to the TFT and the electrode wiring. Is formed, bleaching exposure and baking are performed to form an interlayer insulating film 11. At this time, as shown in FIG. 2, the gate electrode wiring 2a or the source electrode wiring 7a is connected to an external substrate (not shown).
In the mounting region 14 where the gate terminal 2b and the source terminal 7b for electrically connecting the terminal 2b are provided. 7b and between the terminals 2b, 7b.
1 has been removed to be absent. Next, using the interlayer insulating film 11 as a mask, the passivation film 10 exposed by the contact hole formed in the interlayer insulating film 11 is etched by dry etching to form the contact hole 12 and to form the passivation film in the mounting region 14. 10 is etched. At this time, in the mounting area 14, the transparent insulating substrate 1 is placed between the terminals 2b and 7b.
Is exposed.

FIG. 7 shows an etching step of the passivation film 10 by a dry etching method using the interlayer insulating film 11 as a mask. The dry etching condition of the passivation film 10 is CF ₄ + O ₂ or SF ₆ +
After etching the silicon nitride forming the passivation film 10 with O ₂ or another fluorine-based gas + O ₂ gas, an O ₂ gas is used to reduce the connection resistance between the pixel electrode 13 and the drain electrode 8 formed in the next step. Is performed to remove the residue on the drain electrode 8 at the bottom of the contact hole 12. At this time, the interlayer insulating film 11
Is also subjected to an etching process using CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, and an ashing process using O ₂ gas. It is formed. Then, the unevenness reduction in formed by ashing of the O ₂ gas interlayer insulating film 11 surface as a purpose, again CF ₄ + O _2, or SF ₆ + O _2, or other etching with fluorine-based gas + O ₂ gas Do.

The second CF ₄ + O ₂ or SF
Etching with ₆ + O ₂ or another fluorine-based gas + O ₂ gas is performed for a second time shorter than the first etching time in order to prevent reattachment of the residue of the interlayer insulating film 11 into the contact hole 12. Is performed. Alternatively, the second etching process is performed by increasing the flow rate ratio of CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas to O ₂ gas. Alternatively, a second etching process is performed with a lower power than the first etching process. Alternatively, the short-time treatment described above, O ₂
The etching process is performed by combining at least any two conditions of increasing the flow rate ratio and decreasing the power.

Next, an ITO film is formed by a sputtering method, and a pixel electrode 13 and each terminal 2 are formed on the interlayer insulating film 11 by forming a resist by photolithography and etching.
An ITO film 13a is formed on b and 7b. At this time, the pixel electrode 13 is electrically connected to the drain electrode 8 via the contact hole 12. The etching of the ITO film, before the step, subjected to O ₂ again CF ₄ + O ₂ after ashing gases or SF ₆ + O ₂ etching process or by another fluorine-based gas + O ₂ gas,
By reducing irregularities on the surface of the interlayer insulating film 11, the etching rate of the ITO film on the interlayer insulating film 11 and the etching rate of the ITO film on the transparent insulating substrate 1 between the terminals 2b and 7b in the mounting region 14 become substantially the same. The pixel electrode 13 and the ITO film 13a in the mounting region 14 can be simultaneously patterned by one etching process.

An alignment film is formed on the surface of the TFT array substrate formed by the above process and the surface of the opposite substrate on which an opposite electrode and the like are formed on another transparent insulating substrate, and then, the liquid crystal material is injected therebetween. Thus, a liquid crystal display element is formed.

In the etching of the ITO film forming the pixel electrode 13, when the etching process is performed for the optimum etching time of the ITO film on the transparent insulating substrate 1,
The side etch amount of the ITO pattern (pixel electrode 13) on the interlayer insulating film 11 was 1 μm or less on one side, and a pattern having a good shape was obtained. The connection resistance between the pixel electrode 13 and the drain electrode 8 was 35 μm □ and was several hundred Ω or less.

According to the present embodiment, * (see question)

Embodiment 6 FIG. In the fifth embodiment, the etching of the passivation film 10 using the interlayer insulating film 11 as a mask is performed by first using CF ₄ + O ₂ or SF ₆ +
Etching of the passivation film 10 and the gate insulating film 4 with O ₂ or another fluorine-based gas + O ₂ gas, then ashing with O ₂ gas for the purpose of removing the residue at the bottom of the contact hole 12, and then interlayer insulation Second CF ₄ + for the purpose of reducing unevenness of the surface of the film 11
O ₂ , or SF ₆ + O ₂ , or other fluorine-based gas +
The etching was performed using O ₂ gas.
The passivation film 10 is etched with F ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, and then the flow rate of the O ₂ gas is increased to increase the second CF ₄ + O ₂ , Alternatively, by performing an etching process using SF ₆ + O ₂ or another fluorine-based gas + O ₂ gas, the residue at the bottom of the contact hole 12 is removed, and the pixel electrode 13 and the drain electrode 8 are connected through the contact hole 12. The connection resistance can be reduced, and the unevenness on the surface of the interlayer insulating film 11 can be reduced as compared with the ashing process using O ₂ gas.
The upper ITO film and each terminal 2b, 7 in the mounting area 14
The etching property of the ITO film on the transparent insulating substrate 1 between b can be improved.

Embodiment 7 FIG. FIG. 8 is a sectional view showing a state during the manufacturing process of the TFT array substrate of the liquid crystal display device according to Embodiment 7 of the present invention. The reference numerals in the figure are the same as those in FIG.

Next, a process of manufacturing the TFT array substrate of the liquid crystal display according to the present embodiment will be described. The gate electrode 2, the gate electrode wiring (not shown) and the gate terminal 2 are formed on the transparent insulating substrate 1 in the same manner as in the fifth embodiment.
b, common electrode 3, gate insulating film 4, semiconductor layer 5, contact layer 6, source electrode 7, drain electrode 8, source electrode wiring (not shown), source terminal (not shown), channel 9, and passivation film 10 are sequentially formed. Next, an acrylic transparent resin having photosensitivity is applied by spin coating or the like, exposed and developed to form a contact hole, and then bleaching exposure and baking are performed to form an interlayer insulating film 11. At this time, as shown in FIG.
Gate terminal 2 for electrically connecting gate electrode wiring 2a or source electrode wiring 7a to an external substrate (not shown)
In the mounting region 14 where the b and source terminals 7b are provided, the interlayer insulating film 11 is removed so as not to exist on the terminals 2b, 7b and between the terminals 2b, 7b.

Next, a photoresist is applied on the interlayer insulating film 11, and the photoresist is exposed using the mask used for exposing the acrylic transparent resin, followed by development processing. Resist 1 with the same pattern as 11
5 is formed. Next, using the resist 15 as a mask, the passivation film 10 is etched by a dry etching method to form the contact hole 12 and to etch the passivation film 10 in the mounting region 14. The dry etching conditions for the passivation film 10 are as follows: after etching the silicon nitride forming the passivation film 10 with CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, the residue at the bottom of the contact hole 12 Is removed, and an ashing process using O ₂ gas is performed for the purpose of reducing the connection resistance between the pixel electrode formed in the next step and the drain electrode 8. After that, the resist 15 is removed. During the ashing process using the O ₂ gas, since the surface of the interlayer insulating film 11 is protected by the resist 15, no irregularities are formed on the surface of the interlayer insulating film 11.

Thereafter, an ITO film is formed on the pixel electrodes and the terminals 2b and 7b in the same manner as in the fifth embodiment, and a TFT array substrate is formed. The dry etching of the passivation film 10 and the gate insulating film 4 is performed by first etching silicon nitride with CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, and then etching the bottom of the contact hole 12. CF ₄ with a high flow rate of O ₂ gas for the purpose of removing residue
Similar effects can be obtained by performing an etching process using + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas.

According to the present embodiment, ashing treatment of O ₂ gas for the purpose of removing the residue at the bottom of contact hole 12 or CF _{4 in} which the flow ratio of O ₂ gas is increased.
By performing etching with + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas while the surface of the interlayer insulating film 11 is protected by the resist 15,
No irregularities are formed on the surface of the interlayer insulating film 11, so that the connection resistance between the pixel electrode and the drain electrode 8 through the contact hole 12 can be reduced. The etching rate of the ITO film on the transparent insulating substrate 1 between the terminals 2b and 7b in the mounting area 14 is substantially the same, and the pixel electrode and the ITO film 13a in the mounting area can be patterned by one etching process.

Embodiment 8 FIG. FIG. 9 is a cross-sectional view showing a state during the manufacturing process of the TFT array substrate of the liquid crystal display device according to Embodiment 8 of the present invention. Note that the reference numerals in the figure are the same as those in FIG.

Next, the steps of manufacturing the TFT array substrate of the liquid crystal display according to the present embodiment will be described. The gate electrode 2, the gate electrode wiring (not shown) and the gate terminal 2 are formed on the transparent insulating substrate 1 in the same manner as in the fifth embodiment.
b, common electrode 3, gate insulating film 4, semiconductor layer 5, contact layer 6, source electrode 7, drain electrode 8, source electrode wiring (not shown), source terminal (not shown), channel 9, and passivation film 10 are sequentially formed. Next, an acrylic transparent resin having no photosensitivity is applied by using a spin coating method or the like, followed by baking to form an interlayer insulating film 11. Next, a photoresist is applied on the interlayer insulating film 11, exposed and developed to form a resist 15 having an opening pattern at a predetermined position.

Next, using the resist 15 as a mask, the interlayer insulating film 11 and the passivation film 10 are etched by dry etching to form a contact hole 12 and to etch the interlayer insulating film 11 and the passivation film 10 in the mounting region 14. Do. The dry etching conditions for the interlayer insulating film 11 and the passivation film 10 are such that the silicon nitride forming the interlayer insulating film 11 and the passivation film 10 is made of CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas. After the etching, the residue at the bottom of the contact hole 12 is removed, and an ashing process using O ₂ gas is performed for the purpose of reducing the connection resistance between the pixel electrode and the drain electrode 8 formed in the next step. After that, the resist 15 is removed.
During the ashing process using the O ₂ gas, since the surface of the interlayer insulating film 11 is protected by the resist 15, no irregularities are formed on the surface of the interlayer insulating film 11. Thereafter, an ITO film is formed on the pixel electrode, the gate terminal 2b, and the source terminal by the same method as in Embodiment 5, and a TFT array substrate is formed.

The dry etching of the interlayer insulating film 11 and the passivation film 10 is first performed by CF ₄ +
O ₂ , or SF ₆ + O ₂ , or other fluorine-based gas +
After etching the interlayer insulating film 11 and silicon nitride by O ₂ gas, the purpose of residue removal of the contact hole 12 bottom, CF ₄ was higher flow rate ratio of O ₂ gas
Similar effects can be obtained by performing an etching process using + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas.

According to the present embodiment, the interlayer insulating film 11 is formed by using an inexpensive acrylic transparent resin having no photosensitivity, and the interlayer insulating film 11 is patterned by the interlayer insulating film 1.
Since the etching of the passivation film 10 can be performed at a time using the resist 15 formed for the purpose of protecting one surface as a mask, the material cost can be reduced and the seventh embodiment can be performed without increasing the number of manufacturing steps. Similar effects can be obtained.

Embodiment 9 FIG. In the first to eighth embodiments, the interlayer insulating film 11 is removed so that the interlayer insulating film 11 does not exist between the terminals 2b and 7b in the mounting region 14, but the interlayer insulating film 11 outside the display region is removed. May be removed.

In the first to eighth embodiments, the structure having the passivation film 10 is used. However, the structure may be such that the interlayer insulating film 11 is formed directly on the TFT without the passivation film 10. In the case where no passivation film is provided, the method of manufacturing the TFT array substrate according to the fifth to seventh embodiments does not require the step of etching the passivation film 10 using the interlayer insulating film 11 or the resist 15 as a mask. Ashing of O ₂ gas for the purpose of removing the residue at the bottom of the contact hole 12, or CF ₄ + O ₂ or SF ₆ + O ₂ with a higher flow rate of O ₂ gas, or other fluorine-based gas + O ₂ gas It is only necessary to perform the etching process by

In the first to eighth embodiments, a transparent resin other than an acrylic resin may be used as a material for forming the interlayer insulating film 11. Embodiment 1
According to the eighth embodiment, in the contact hole 12 forming step, CF ₄ + O used for dry etching is used.
₂ , or SF ₆ + O ₂ , or other fluorine-based gas + O
₍₂₎ Ar or H is added to the gas for the purpose of improving in-plane uniformity.
e may be added and used. In the first to eighth embodiments, amorphous silicon is used as the semiconductor layer 5. However, the present invention may be applied to a device having a pixel uppermost layer structure using polycrystalline silicon.

[0060]

As described above, according to the present invention, an interlayer insulating film made of a transparent resin is formed on an electrode wiring and a TFT, the surface thereof is flattened, and a pixel electrode is formed on the uppermost layer. In the method of manufacturing a liquid crystal display device that realizes an improvement in aperture ratio by optimizing dry etching conditions for forming a contact hole that electrically connects a pixel electrode and a drain electrode formed on an interlayer insulating film, In addition to the reliable removal of the residue at the bottom of the contact hole, the IT forming the pixel electrode after the formation of the contact hole
When the O film is formed, the connection resistance between the pixel electrode and the drain electrode can be reduced by keeping the surface of the interlayer insulating film free from unevenness, and the ITO film on the interlayer insulating film and the A high performance and high aperture ratio liquid crystal display device in which an ITO film on a transparent insulating substrate exposed between terminals can be patterned into a good shape without short circuit between terminals in a single etching process. Can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a TFT array substrate of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view of a periphery of a TFT array substrate of the liquid crystal display according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of manufacturing the TFT array substrate of the liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 4 is a cross-sectional view showing a step of manufacturing a TFT array substrate of a liquid crystal display device according to Embodiment 3 of the present invention.

FIG. 5 is a cross-sectional view showing a step of manufacturing a TFT array substrate of a liquid crystal display device according to Embodiment 4 of the present invention.

FIG. 6 is a sectional view showing a TFT array substrate of a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of manufacturing a TFT array substrate of a liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 8 is a sectional view illustrating a manufacturing process of a TFT array substrate of a liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view illustrating a manufacturing process of a TFT array substrate of a liquid crystal display device according to an eighth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 transparent insulating substrate, 2 gate electrode, 2a gate electrode wiring, 2b gate terminal, 3 common electrode, 4 gate insulating film, 5 semiconductor layer, 6 contact layer, 7 source electrode, 7a source electrode wiring, 7b source terminal, 8
Drain electrode, 9 channel section, 10 passivation film, 11 interlayer insulating film, 12 contact hole, 1
3 pixel electrode, 13a ITO film, 14 mounting area, 1
5 Resist.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627Z F-term (Reference) 2H092 GA17 GA25 JA05 JA24 JA28 JA37 JA46 JB12 JB13 JB22 JB31 KA05 KB24 MA10 MA12 MA15 MA16 MA18 MA19 MA29 MA31 NA16 NA19 NA27 NA28 4K057 DA19 DB06 DB11 DB15 DE06 DE08 DE20 DN01 5F110 AA16 AA18 BB01 CC07 EE04 EE23 EE44 FF03 FF30 GG02 GG13 GG15 GG45 HK09 HK16 NN03 NN24 Q19

Claims (9)

[Claims] At least one of two transparent insulating substrates on which electrodes are formed is opposed to and bonded to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. Forming a scan electrode, a scan electrode wiring, and a scan electrode wiring terminal on one of the two transparent insulating substrates; and forming the scan electrode, the scan electrode wiring, and the scan electrode wiring terminal on one of the two transparent insulating substrates. A step of forming an insulating film, a step of forming a semiconductor layer on the scan electrode via the insulating film, and a first electrode, a first electrode wiring, a first electrode wiring terminal on the semiconductor layer, and Forming a second electrode; forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode; and forming a photosensitive film on the passivation film. Having A transparent resin is applied, and a contact hole is formed on the second electrode by exposure and development to form an interlayer insulating film having an opening in a mounting area where the scanning electrode wiring terminal and the first electrode wiring terminal are formed. Using the interlayer insulating film as a mask, etching the passivation film and the insulating film exposed through the contact hole and the opening by a dry etching method; and forming the interlayer insulating film on the interlayer insulating film, in the contact hole, and A transparent conductive film is formed on the transparent insulating substrate and the scanning electrode wiring terminal exposed by the opening, and on the first electrode wiring terminal, and is patterned by a single etching process to form the second electrode. A pixel electrode electrically connected through the contact hole, and the scan electrode wiring terminal and the first electrode wiring terminal Includes the step of forming a transparent conductive film pattern, a method of manufacturing a liquid crystal display device in which the interlayer insulating film surface after the etching processing by the dry etching method is characterized by a smooth state. 2. A liquid crystal material sandwiched between at least one of two transparent insulating substrates on which electrodes are formed, and two transparent insulating substrates having electrodes formed thereon are opposed to and bonded to each other. Forming a scan electrode, a scan electrode wiring, and a scan electrode wiring terminal on one of the two transparent insulating substrates; and forming the scan electrode, the scan electrode wiring, and the scan electrode wiring terminal on one of the two transparent insulating substrates. Forming an insulating film, forming a semiconductor layer on the scanning electrode via the insulating film, and forming the insulating film in a mounting region where the scanning electrode wiring terminal and the first electrode wiring terminal are formed. A step of removing; a step of forming a first electrode, a first electrode wiring, a first electrode wiring terminal and a second electrode on the semiconductor layer; and the first electrode, the first electrode wiring, First electrode wiring terminal And a step of forming a passivation film on the second electrode, applying a transparent resin having photosensitivity on the passivation film, exposing and developing a contact hole on the second electrode, and the scanning electrode wiring Forming an interlayer insulating film having an opening in the mounting region where the terminal and the first electrode wiring terminal are formed; and drying the passivation film exposed through the contact hole and the opening using the interlayer insulating film as a mask. Etching by an etching method, and a transparent conductive film on the interlayer insulating film, in the contact hole, and on the transparent insulating substrate, the scan electrode wiring terminal, and the first electrode wiring terminal exposed through the opening. Is formed and patterned by a single etching process to form the second electrode and the contact hole. Forming a transparent conductive film pattern on the pixel electrode and the scanning electrode wiring terminal and the first electrode wiring terminal, the interlayer insulating film after the etching process by the dry etching method. A method for manufacturing a liquid crystal display device, characterized in that the surface is smooth. 3. At least one of two transparent insulating substrates having electrodes formed thereon is opposed to and bonded to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. Forming a scan electrode, a scan electrode wiring, and a scan electrode wiring terminal on one of the two transparent insulating substrates; and forming the scan electrode, the scan electrode wiring, and the scan electrode wiring terminal on one of the two transparent insulating substrates. A step of forming an insulating film, a step of forming a semiconductor layer on the scan electrode via the insulating film, and a first electrode, a first electrode wiring, a first electrode wiring terminal on the semiconductor layer, and Forming a second electrode; forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode; and forming a photosensitive film on the passivation film. Having A transparent resin is applied, and a contact hole is formed on the second electrode by exposure and development to form an interlayer insulating film having an opening in a mounting area where the scanning electrode wiring terminal and the first electrode wiring terminal are formed. Applying a photoresist, patterning the photoresist into the same shape as the interlayer insulating film to form a resist, and using the resist as a mask, removing the passivation film and the insulating film exposed through the contact hole and the opening. A step of removing the resist after etching by a dry etching method; and a step of removing the resist on the interlayer insulating film and in the contact hole, and on the transparent insulating substrate exposed by the opening and the scan electrode wiring terminal, A transparent conductive film is formed on the electrode wiring terminal, and is patterned by one etching process. A liquid crystal comprising: a pixel electrode electrically connected to the second electrode via the contact hole; and a transparent conductive film pattern on the scan electrode wiring terminal and the first electrode wiring terminal. A method for manufacturing a display device. 4. At least one of two transparent insulating substrates having electrodes formed thereon is opposed to and bonded to each other, and a liquid crystal material is sandwiched between the two transparent insulating substrates. Forming a scan electrode, a scan electrode wiring, and a scan electrode wiring terminal on one of the two transparent insulating substrates; and forming the scan electrode, the scan electrode wiring, and the scan electrode wiring terminal on one of the two transparent insulating substrates. A step of forming an insulating film, a step of forming a semiconductor layer on the scan electrode via the insulating film, and a first electrode, a first electrode wiring, a first electrode wiring terminal on the semiconductor layer, and Forming a second electrode; forming a passivation film on the first electrode, the first electrode wiring, the first electrode wiring terminal and the second electrode; and forming a photosensitive film on the passivation film. Have Applying a transparent resin, forming an interlayer insulating film, forming a resist, etching the interlayer insulating film, the passivation film and the insulating film by a dry etching method, forming a contact hole on the second electrode, And after forming an opening in the mounting region where the scanning electrode wiring terminal and the first electrode wiring terminal are formed, removing the resist, and on the interlayer insulating film and in the contact hole, and by the opening A transparent conductive film is formed on the exposed transparent insulating substrate, the scanning electrode wiring terminal, and the first electrode wiring terminal, and is patterned by a single etching process to form the second electrode and the contact hole. Forming a transparent conductive film pattern on the pixel electrode electrically connected via the first electrode wiring terminal and the scanning electrode wiring terminal and the first electrode wiring terminal. Method of manufacturing a liquid crystal display device, characterized in that. 5. An insulating film in a mounting area where a scanning electrode wiring terminal and a first electrode wiring terminal are formed, after forming a semiconductor layer, forming a first electrode, a first electrode wiring, and the first electrode wiring terminal. 5. The method for manufacturing a liquid crystal display device according to claim 3, further comprising a step of removing before forming the second electrode. 6. An etching condition by a dry etching method using an interlayer insulating film as a mask is the first CF ₄ etching process.
+ O ₂ , or SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas, followed by an ashing treatment with an O ₂ gas, and a second CF ₄ + O ₂ or SF treatment
₆ + O _2, or other method for producing a fluorine-based gas + O ₂ gas liquid crystal display device according to claim 1 or claim 2, wherein the etching is performed by,. 7. The second CF ₄ + O ₂ or SF ₆ +
O ₂ or etching conditions by another fluorine-based gas + O ₂ gas, the first-time CF ₄ + O _2, or SF _6,
+ O ₂ or another fluorine-based gas + O ₂ gas in a shorter time than the etching process, increase the flow rate of the O ₂ gas, reduce the power, or combine at least any two of the above processing conditions 7. The method for manufacturing a liquid crystal display device according to claim 6, wherein: 8. An etching condition by dry etching after forming a resist on an interlayer insulating film is CF ₄ + O
₂ , or SF ₆ + O ₂ , or other fluorine-based gas + O
After etching with ₂ gas, a method of manufacturing a liquid crystal display device of any one of claims 3-5, characterized in that ashing treatment with O ₂ gas. 9. An etching condition by a dry etching method using an interlayer insulating film or a resist as a mask is that after the first etching process using CF ₄ + O ₂ , SF ₆ + O ₂ , or another fluorine-based gas + O ₂ gas , claim 1, wherein the performing second-time CF ₄ + O _2, or SF ₆ + O _2, or other etching process with a fluorine gas + O ₂ gas is higher than the first time the flow ratio of O ₂ gas, A method for manufacturing a liquid crystal display device according to any one of claims 1 to 5.