USRE40028E1 - Liquid crystal display device and method of manufacturing the same - Google Patents

Liquid crystal display device and method of manufacturing the same Download PDF

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Publication number
USRE40028E1
USRE40028E1 US10/752,486 US75248604A USRE40028E US RE40028 E1 USRE40028 E1 US RE40028E1 US 75248604 A US75248604 A US 75248604A US RE40028 E USRE40028 E US RE40028E
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metal layer
semiconductor layer
photoresist pattern
photoresist
forming
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US10/752,486
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Kwangjo Hwang
Changwook Han
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LG Display Co Ltd
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LG Philips LCD Co Ltd
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Priority to US11/984,431 priority patent/USRE41632E1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device fabricated through four photolithography processes and a method of fabricating the same.
  • a typical liquid crystal display (LCD) device has a gate bus line 60 arranged in a transverse direction and a data bus line 70 arranged in a longitudinal direction, a thin film transistor (TFT) formed near a cross point of the gate bus line 60 and the data bus line 70 .
  • the TFT has a source electrode 70 a, a drain electrode 70 b, a gate electrode 60 a, and a semiconductor layer 80 .
  • the drain electrode 70 b is connected to a pixel electrode 40 .
  • the LCD device described above is completed through five photolithography processes.
  • FIGS. 2A to 2 E show a process of manufacturing the conventional LCD device
  • FIGS. 3A and 3B show a photolithography process to form a gate insulating layer 50 , the amorphous silicon (a-Si) layer 80 a, and an n-type impurity doped silicon (n + a-Si) layer 80 b.
  • FIGS. 4A-4C show a photolithography process to form source and drain electrode 70 a and 70 b.
  • a gate electrode 60 a shown in FIG. 2A is formed on a transparent substrate 10 during a first photolithography process.
  • a metal layer (not shown) of Mo or Cr is deposited on the transparent substrate 10 and then a photoresist is applied on the metal layer. Then, a first photo-mask (not shown) is located over the substrate 10 , and light exposure and developing processes are performed to etch the metal layer so that the gate electrode 60 a is formed. Finally, the photoresist remaining on the metal layer is removed, leaving the gate electrode 60 a on transparent substrate 10 as shown in FIG. 2 A.
  • a gate insulting layer 50 , the a-Si layer 80 a, and a n + a-Si layer 80 b shown in FIG. 2B are sequentially formed during a second photolithography process, detailed as shown in FIGS. 3A and 3B .
  • a photoresist 88 is applied on the n + a-Si layer 80 b.
  • light exposure and developing processes are performed using a second photo-mask 100 , thereby forming a photoresist pattern 88 a as shown in FIG. 3 B.
  • the a-Si layer 80 a and the n + a-Si layer 80 b are simultaneously etched according to the photoresist pattern 88 a so that the gate insulating layer 50 , the a-Si layer 80 a, and the n + a-Si layer 80 b are formed.
  • the photoresist remaining on the n + a-Si layer 80 b is removed.
  • the source electrode 70 a and the drain electrode 70 b shown in FIG. 2C are formed during a third photolithography process, detailed as shown in FIGS. 4A-4C .
  • a metal layer 170 such as Cr is deposited over the whole surface of the substrate 10 while covering a-Si layer 80 a and n + a-Si layer 80 b.
  • the positive type photoresist 88 is applied, and then light exposure and developing processes are performed using a third photo-mask 200 , thereby forming a photoresist pattern 88 a as shown in FIG. 4 B.
  • a lower metal layer 170 is etched to form the source electrode 70 a and the drain electrode 70 b as shown in FIG. 4 C.
  • the n + a-Si layer 80 b is etched using the metal layer (source and drain electrodes) as a mask. Finally, the photoresist pattern 88 a remaining on the source electrode 70 a and the drain electrode 70 b is removed.
  • the passivation layer 55 having the contact hole 30 shown in FIG. 2D is formed during a fourth photolithography process.
  • An inorganic material such as a nitride or oxide of silicon (SiNx or SiOx, respectively) or an organic material such as bis-benzocyclobutene (BCB) is deposited on the source electrode 70 a and the drain electrode 70 b.
  • the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fourth photo-mask (not shown) to form a photoresist pattern.
  • the passivation layer 55 is formed through an etching process. After the etching process, the photoresist pattern remaining on the passivation layer 55 is removed.
  • the pixel electrode 40 to be connected to the drain electrode 70 b shown in FIG. 2E is formed during a fifth photolithography process.
  • a metal layer such as indium tin oxide (ITO) is deposited on the passivation layer 55 .
  • the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fifth photo-mask (not shown), thereby forming a photoresist pattern.
  • the metal layer is etched so that the pixel electrode 40 is formed. After the etching process, the photoresist pattern remaining on the pixel electrode 40 is removed.
  • the photolithography process described above includes the steps of: cleaning a substrate; applying a photoresist; soft-baking the photoresist; aligning a photo-mask; light-exposing the photoresist; developing the photoresist; inspecting the array substrate; hard-baking the photoresist; etching a portion that the photoresist does not cover; inspecting the array substrate; and removing the photoresist.
  • the photolithography process includes the complex steps described above, as the number of photolithography processes increases, the inferiority rate become greater, leading to a low yield. In other words, reliability of the manufacturing process varies inversely proportional to the number of photolithography processes performed.
  • An object of the present invention is to provide a liquid crystal display device fabricated through four photolithography processes.
  • Another object of the present invention is to increase yield and to reduce the production cost of TFT fabrication.
  • the present invention provides a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first enchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an
  • the first etchant contains Cl 2 /O 2 gas and the second etchant contains SF 6 /HCl or SF 6 /H 2 /Cl 2 gas.
  • the source and drain electrodes are made of a metal selected form a group consisting of Cr, Mo, Al, and Al alloy, and the first semiconductor layer comprises an amorphous silicon and the second semiconductor layer comprises an amorphous silicon doped with n-type impurity.
  • FIG. 1 is a plan view of a conventional liquid crystal display device
  • FIGS. 2A to 2 E are cross sectional views taken along line I-I of FIG. 1 showing a process of fabricating the conventional liquid crystal display device;
  • FIGS. 3A and 3B are cross-sectional views illustrating a photolithography process corresponding to FIG. 2B ;
  • FIGS. 4A to 4 C are cross-sectional views illustrating a photolithography process corresponding to FIG. 2C ;
  • FIGS. 5A and 5B , 6 A to 6 E, 7 A and 7 B, and 8 A to 8 C are cross sectional views showing a process of fabricating a liquid crystal display device according to a preferred embodiment of the present invention.
  • FIG. 9 is a plan view illustrating the liquid crystal display device according to the preferred embodiment of the present invention.
  • a metal layer 160 of Mo or Cr is deposited on a transparent substrate 10 .
  • a positive type photoresist (photosensitive layer) 88 is applied on the metal layer 160 , and then a first photo-mask 15 is aligned.
  • a region 15 a represents a light shielding area and a region 15 b represents a light transmitting area.
  • a gate electrode 60 a is formed by etching the metal layer 160 according to a photoresist pattern 88 a produced after light exposure and development of the photoresist 88 . After that, the photoresist 88 a remaining on the gate electrode 60 a is removed.
  • a gate insulating layer 50 comprising an inorganic material such as SiNx and SiOx, an a-Si layer 80 a, an n + a-Si layer 80 b, and a single or multi-layered metal layer 170 made of a metal such as Cr, Mo, Al, and Al alloy are sequentially formed on the gate electrode 60 a.
  • a positive type photoresist 88 is applied on the metal layer 170 and then a second photo-mask 25 partially executing a diffraction light exposure is aligned.
  • a region 25 a represents a light shielding area
  • a region 25 b represents a light transmitting area
  • a region 25 c represents a diffraction light exposing area.
  • a photoresist pattern 88 a is formed by the second photo-mask 25 .
  • the region 25 a is relatively thick and the region 25 c is relatively thin in thickness. Further, the region 25 b is completely removed so that a surface of the metal layer 170 is exposed. Specifically, the thickness of the photoresist pattern depends on a pattern shape of the second photo-mask 25 .
  • the metal layer 170 is etched by subjecting the array substrate 10 having the photoresist pattern 88 a to a first etchant containing Cl 2 /O 2 gas.
  • a central portion of the photoresist pattern 88 a is removed by O 2 gas ashing, thereby exposing a central portion of the metal layer 170 corresponding to the central portion of the photoresist pattern 88 a.
  • the a-Si layer 80 a and the n + a-Si layer 80 b are etched by a second etchant preferably containing either SF 6 /HCl or SF 6 /H 2 /Cl 2 gas.
  • the metal layer 170 functions as a mask.
  • the exposed portion of the metal layer 170 and the central portion of the n + a-Si layer 80 b corresponding to the exposed portion of the metal layer 170 are etched by a third etchant preferably containing Cl 2 /O 2 gas, thereby forming an ohmic contact layer, and source and drain electrodes 70 a and 70 b.
  • the photoresist pattern 88 a functions as a mask.
  • the line edge of the source and drain electrodes 70 a and 70 b and the line edge of the semiconductor layer 80 are formed in the shape of curved lines.
  • the dimension “d” represents a distance between the data bus line 70 and the semiconductor layer 80 or the drain electrode 70 b and the semiconductor layer 80 . Since the distance ‘d’ is maintained equally throughout, it is possible to prevent the distance difference due to misalignment during the photolithography process.
  • a third photolithography process as shown in FIG. 7A , an inorganic material such as SiNx and SiOx or an organic material such as BCB is deposited on the source and drain electrodes 70 a and 70 b to form a passivation layer 55 .
  • the positive type photoresist 88 is applied on the passivation layer 55 , and then light exposure and developing processes are executed using a third photo-mask 35 , thereby forming a photoresist pattern 88 a.
  • a region 35 a represents a light shielding area and a region 35 b represents a light transmitting area.
  • the passivation layer 55 is etched to form a contact hole 30 and then the photoresist pattern remaining on the passivation 55 is removed.
  • a metal layer 140 made of ITO is deposited on the passivation layer 55 having the contact hole 30 .
  • the positive type photoresist 88 is applied on the metal layer 140 , and then the light exposure and developing processes are executed using a fourth photo-mask 45 , thereby forming a photoresist pattern 88 a.
  • a region 45 a represents a light shielding area and a region 45 b represents a light transmitting area.
  • the metal layer 140 is etched so that the pixel electrode 40 is formed. After etching process, the photoresist pattern 88 a remaining on the pixel electrode 40 is removed as shown in FIG. 8 C.
  • liquid crystal display device Accordingly, the substantially important components of liquid crystal display device according to the preferred embodiment of the present invention are completed by four photolithography processes described above.
  • the a-Si layer 80 a, the n + a-Si layer 80 b and the source and drain electrodes are simultaneously formed through the same photolithography process, that is, by the diffraction light exposure using the second photo-mask, it is possible to manufacture the LCD device through the four lithography processes, thereby increasing the yield and reducing the production cost by decreasing the inferiority rate due to many photolithography processes.

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Abstract

The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode connecting with the drain electrode through the contact hole.

Description

CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-19145, filed on May 27, 1999, under 35U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device fabricated through four photolithography processes and a method of fabricating the same.
2. Description of the Related Art
As shown in FIG. 1, a typical liquid crystal display (LCD) device has a gate bus line 60 arranged in a transverse direction and a data bus line 70 arranged in a longitudinal direction, a thin film transistor (TFT) formed near a cross point of the gate bus line 60 and the data bus line 70. The TFT has a source electrode 70a, a drain electrode 70b, a gate electrode 60a, and a semiconductor layer 80. The drain electrode 70b is connected to a pixel electrode 40.
The LCD device described above is completed through five photolithography processes.
Hereinafter, a method of fabricating the conventional LCD device will be explained in detail. FIGS. 2A to 2E show a process of manufacturing the conventional LCD device, and FIGS. 3A and 3B show a photolithography process to form a gate insulating layer 50, the amorphous silicon (a-Si) layer 80a, and an n-type impurity doped silicon (n+ a-Si) layer 80b. Further, FIGS. 4A-4C show a photolithography process to form source and drain electrode 70a and 70b.
First, a gate electrode 60a shown in FIG. 2A is formed on a transparent substrate 10 during a first photolithography process.
In the first photolithography process, a metal layer (not shown) of Mo or Cr is deposited on the transparent substrate 10 and then a photoresist is applied on the metal layer. Then, a first photo-mask (not shown) is located over the substrate 10, and light exposure and developing processes are performed to etch the metal layer so that the gate electrode 60a is formed. Finally, the photoresist remaining on the metal layer is removed, leaving the gate electrode 60a on transparent substrate 10 as shown in FIG. 2A.
Second, a gate insulting layer 50, the a-Si layer 80a, and a n+ a-Si layer 80b shown in FIG. 2B are sequentially formed during a second photolithography process, detailed as shown in FIGS. 3A and 3B.
As shown in FIG. 3A, a photoresist 88 is applied on the n+ a-Si layer 80b. After that, light exposure and developing processes are performed using a second photo-mask 100, thereby forming a photoresist pattern 88a as shown in FIG. 3B. The a-Si layer 80a and the n+ a-Si layer 80b are simultaneously etched according to the photoresist pattern 88a so that the gate insulating layer 50, the a-Si layer 80a, and the n+ a-Si layer 80b are formed. Finally, the photoresist remaining on the n+ a-Si layer 80b is removed.
Third, the source electrode 70a and the drain electrode 70b shown in FIG. 2C are formed during a third photolithography process, detailed as shown in FIGS. 4A-4C.
As shown in FIG. 4A, a metal layer 170 such as Cr is deposited over the whole surface of the substrate 10 while covering a-Si layer 80a and n+ a-Si layer 80b. After that, the positive type photoresist 88 is applied, and then light exposure and developing processes are performed using a third photo-mask 200, thereby forming a photoresist pattern 88a as shown in FIG. 4B. In accordance with the photoresist pattern 88a, a lower metal layer 170 is etched to form the source electrode 70a and the drain electrode 70b as shown in FIG. 4C. Continually, the n+ a-Si layer 80b is etched using the metal layer (source and drain electrodes) as a mask. Finally, the photoresist pattern 88a remaining on the source electrode 70a and the drain electrode 70b is removed.
Fourth, the passivation layer 55 having the contact hole 30 shown in FIG. 2D is formed during a fourth photolithography process.
An inorganic material such as a nitride or oxide of silicon (SiNx or SiOx, respectively) or an organic material such as bis-benzocyclobutene (BCB) is deposited on the source electrode 70a and the drain electrode 70b. After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fourth photo-mask (not shown) to form a photoresist pattern. Then, the passivation layer 55 is formed through an etching process. After the etching process, the photoresist pattern remaining on the passivation layer 55 is removed.
Fifth, the pixel electrode 40 to be connected to the drain electrode 70b shown in FIG. 2E is formed during a fifth photolithography process.
A metal layer such as indium tin oxide (ITO) is deposited on the passivation layer 55. After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fifth photo-mask (not shown), thereby forming a photoresist pattern. In accordance with the photoresist pattern, the metal layer is etched so that the pixel electrode 40 is formed. After the etching process, the photoresist pattern remaining on the pixel electrode 40 is removed.
The photolithography process described above includes the steps of: cleaning a substrate; applying a photoresist; soft-baking the photoresist; aligning a photo-mask; light-exposing the photoresist; developing the photoresist; inspecting the array substrate; hard-baking the photoresist; etching a portion that the photoresist does not cover; inspecting the array substrate; and removing the photoresist.
Since the photolithography process includes the complex steps described above, as the number of photolithography processes increases, the inferiority rate become greater, leading to a low yield. In other words, reliability of the manufacturing process varies inversely proportional to the number of photolithography processes performed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a liquid crystal display device fabricated through four photolithography processes.
Another object of the present invention is to increase yield and to reduce the production cost of TFT fabrication.
To achieve the above objects, the present invention provides a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first enchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode contacting with the drain electrode through the contact hole.
The first etchant contains Cl2/O2 gas and the second etchant contains SF6/HCl or SF6/H2/Cl2 gas. The source and drain electrodes are made of a metal selected form a group consisting of Cr, Mo, Al, and Al alloy, and the first semiconductor layer comprises an amorphous silicon and the second semiconductor layer comprises an amorphous silicon doped with n-type impurity.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which:
FIG. 1 is a plan view of a conventional liquid crystal display device;
FIGS. 2A to 2E are cross sectional views taken along line I-I of FIG. 1 showing a process of fabricating the conventional liquid crystal display device;
FIGS. 3A and 3B are cross-sectional views illustrating a photolithography process corresponding to FIG. 2B;
FIGS. 4A to 4C are cross-sectional views illustrating a photolithography process corresponding to FIG. 2C;
FIGS. 5A and 5B, 6A to 6E, 7A and 7B, and 8A to 8C are cross sectional views showing a process of fabricating a liquid crystal display device according to a preferred embodiment of the present invention; and
FIG. 9 is a plan view illustrating the liquid crystal display device according to the preferred embodiment of the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the preferred embodiment of the present invention, example of which is illustrated in the accompanying drawings.
As shown in FIG. 5A, in a first photolithography process, first, a metal layer 160 of Mo or Cr is deposited on a transparent substrate 10. After that, a positive type photoresist (photosensitive layer) 88 is applied on the metal layer 160, and then a first photo-mask 15 is aligned. In the first photo-mask, a region 15a represents a light shielding area and a region 15b represents a light transmitting area.
Referring to FIG. 5B, a gate electrode 60a is formed by etching the metal layer 160 according to a photoresist pattern 88a produced after light exposure and development of the photoresist 88. After that, the photoresist 88a remaining on the gate electrode 60a is removed.
In a second photolithography process, as shown in FIG. 6A, a gate insulating layer 50 comprising an inorganic material such as SiNx and SiOx, an a-Si layer 80a, an n+ a-Si layer 80b, and a single or multi-layered metal layer 170 made of a metal such as Cr, Mo, Al, and Al alloy are sequentially formed on the gate electrode 60a. After that, a positive type photoresist 88 is applied on the metal layer 170 and then a second photo-mask 25 partially executing a diffraction light exposure is aligned. At this time, a region 25a represents a light shielding area, a region 25b represents a light transmitting area, and a region 25c represents a diffraction light exposing area.
Further, as shown in FIG. 6B, a photoresist pattern 88a is formed by the second photo-mask 25. The region 25a is relatively thick and the region 25c is relatively thin in thickness. Further, the region 25b is completely removed so that a surface of the metal layer 170 is exposed. Specifically, the thickness of the photoresist pattern depends on a pattern shape of the second photo-mask 25.
Continually, as shown in FIG. 6C, the metal layer 170 is etched by subjecting the array substrate 10 having the photoresist pattern 88a to a first etchant containing Cl2/O2 gas. When an etching process for the metal layer is completed, a central portion of the photoresist pattern 88a is removed by O2 gas ashing, thereby exposing a central portion of the metal layer 170 corresponding to the central portion of the photoresist pattern 88a.
And then, as shown in FIG. 6D, the a-Si layer 80a and the n+ a-Si layer 80b are etched by a second etchant preferably containing either SF6/HCl or SF6/H2/Cl2 gas. At this time, the metal layer 170 functions as a mask.
Further, the exposed portion of the metal layer 170 and the central portion of the n+ a-Si layer 80b corresponding to the exposed portion of the metal layer 170 are etched by a third etchant preferably containing Cl2/O2 gas, thereby forming an ohmic contact layer, and source and drain electrodes 70a and 70b. At this time, the photoresist pattern 88a functions as a mask.
Subsequently, as shown in FIG. 9, by the diffraction light exposure as the inventive second photolithography process, the line edge of the source and drain electrodes 70a and 70b and the line edge of the semiconductor layer 80 are formed in the shape of curved lines. The dimension “d” represents a distance between the data bus line 70 and the semiconductor layer 80 or the drain electrode 70b and the semiconductor layer 80. Since the distance ‘d’ is maintained equally throughout, it is possible to prevent the distance difference due to misalignment during the photolithography process.
In a third photolithography process, as shown in FIG. 7A, an inorganic material such as SiNx and SiOx or an organic material such as BCB is deposited on the source and drain electrodes 70a and 70b to form a passivation layer 55. After that, the positive type photoresist 88 is applied on the passivation layer 55, and then light exposure and developing processes are executed using a third photo-mask 35, thereby forming a photoresist pattern 88a. In the third photo-mask 35, a region 35a represents a light shielding area and a region 35b represents a light transmitting area. Further, in accordance with the photoresist pattern 88a, as shown in FIG. 7B, the passivation layer 55 is etched to form a contact hole 30 and then the photoresist pattern remaining on the passivation 55 is removed.
In a fourth photolithography process, as shown in FIG. 8A, a metal layer 140 made of ITO is deposited on the passivation layer 55 having the contact hole 30. After that, the positive type photoresist 88 is applied on the metal layer 140, and then the light exposure and developing processes are executed using a fourth photo-mask 45, thereby forming a photoresist pattern 88a. In the fourth photo-mask 45, a region 45a represents a light shielding area and a region 45b represents a light transmitting area. Further, in accordance with the photoresist pattern 88a, as shown in FIG. 8B, the metal layer 140 is etched so that the pixel electrode 40 is formed. After etching process, the photoresist pattern 88a remaining on the pixel electrode 40 is removed as shown in FIG. 8C.
Accordingly, the substantially important components of liquid crystal display device according to the preferred embodiment of the present invention are completed by four photolithography processes described above.
In the present invention, since the a-Si layer 80a, the n+ a-Si layer 80b and the source and drain electrodes are simultaneously formed through the same photolithography process, that is, by the diffraction light exposure using the second photo-mask, it is possible to manufacture the LCD device through the four lithography processes, thereby increasing the yield and reducing the production cost by decreasing the inferiority rate due to many photolithography processes.
It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of the disclosed device and that various changes and modification may be made in the invention without departing from the spirit and scope thereof.

Claims (50)

1. A method of manufacturing a liquid crystal display device, comprising:
a first photolithography process forming a gate electrode on a substrate;
a second photolithography process including:
a) depositing sequentially a gate insulating layer, a semiconductor layer, and a metal layer;
b) applying a first photoresist on the metal layer;
c) aligning a first photo mask with the substrate;
d) light exposing and developing the first photoresist to produce a first photoresist pattern;
e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a portion of the metal layer to produce a second photoresist pattern, thereby exposing the portion of the metal layer; and
f) etching the gate insulating layer, the semiconductor layer, and the portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area;
a third photolithography process forming a passivation film and a contact hole; and
a fourth photolithography process forming a pixel electrode connecting with the drain electrode through the contact hole.
2. The method of claim 1, wherein the first etchant includes Cl2/O2 gas.
3. The method of claim 2, wherein the second etchant includes SF6/HCl gas.
4. The method of claim 2, wherein the second etchant includes SF6/H2/Cl2 gas.
5. The method of claim 1, wherein the semiconductor layer includes first and second semiconductor layers.
6. The method of claim 5, wherein the first semiconductor layer includes amorphous silicon.
7. The method of claim 5, wherein the second semiconductor layer includes doped amorphous silicon.
8. The method of claim 1, wherein the source and drain electrodes are made of a metal selected from a group consisting of Cr, Mo, Al, and Al alloy.
9. The method of claim 8, wherein the semiconductor layer includes first and second semiconductor layers.
10. The method of claim 9, wherein the first semiconductor layer includes amorphous silicon.
11. The method of claim 9, wherein the second semiconductor layer includes doped amorphous silicon.
12. The method of claim 1, wherein the pixel electrode includes indium tin oxide.
13. The method of claim 12, wherein the semiconductor layer includes first and second semiconductor layers.
14. The method of claim 13, first semiconductor layer includes amorphous silicon.
15. The method of claim 13, wherein the second semiconductor layer includes doped amorphous silicon.
16. A method of manufacturing a thin film transistor of a liquid crystal display device, comprising:
forming a gate electrode on substrate; and
forming a gate insulating layer, a semiconductor layer and source and drain electrodes using a photolithography process including:
forming a gate insulating layer a semiconductor layer, and a metal layer;
forming a photoresist on the metal layer;
light exposing and developing the photoresist to produce a first photoresist pattern, wherein the first photoresist pattern includes a central portion having a first thickness and adjacent side portions having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the first photoresist pattern;
removing the central portion of the first photoresist pattern to form a second photoresist pattern;
selectively removing the semiconductor layer using the second photoresist pattern;
selectively removing the metal layer corresponding to the central portion of the photoresist pattern; and
selectively removing the semiconductor layer corresponding to the central portion of the photoresist pattern.
17. The method of claim 16, wherein light exposing and developing the photoresist to produce the photoresist first pattern includes using a diffraction light exposure technique.
18. The method of claim 16, wherein the metal layer is selectively removed using a dry etch technique.
19. The method of claim 18, wherein the dry etch technique uses a gas including Cl2 /O 2 gas.
20. The method of claim 16, wherein the semiconductor layer is selectively removed using a dry etch technique.
21. The method of claim 20, wherein the dry etch technique uses a gas including fluorine and chlorine.
22. The method of claim 21, wherein the gas includes SF6 /HCl.
23. The method of claim 21 wherein the gas includes SF6 /H 2 /Cl 2.
24. The method of claim 16, wherein the semiconductor layer includes first and second semiconductor layers.
25. The method of claim 24, wherein the first semiconductor layer includes amorphous silicon.
26. The method of claim 24, wherein the second semiconductor layer includes doped amorphous silicon.
27. The method of claim 16, wherein the source and drain electrodes are made of a metal selected from the group consisting of Cr, Mo, Al, and Al alloy.
28. The method of claim 16, wherein removing the central portion of the first photoresist pattern exposes the metal layer.
29. A method of manufacturing a thin film transistor of a liquid crystal display device, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer, a first semiconductor layer, a second semiconductor layer and source and drain electrodes using a photolithography process including:
forming a gate insulating layer, a first semiconductor layer, a second semiconductor layer and a metal layer;
forming a photoresist on the metal layer;
positioning a photo mask above the substrate;
light exposing and developing the photoresist to produce a photoresist pattern, wherein the photoresist pattern includes a central portion having a first thickness and adjacent side portions having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the photoresist pattern;
selectively removing the first and second semiconductor layers;
selectively removing the metal layer beneath the central portion of the photoresist pattern having the first thickness to separate the metal layer into a first part spaced from a second part, the first part corresponding to the source electrode and the second part corresponding to the drain electrode; and
selectively removing the first semiconductor layer corresponding to the space between the first and second parts of the metal layer.
30. The method of claim 29, wherein the central portion of the photoresist is removed prior to selectively removing the first and second semiconductor layers.
31. A method of manufacturing a liquid crystal display device, comprising:
forming a thin film transistor and a pixel electrode coupled to the thin film transistor; and
forming the thin film transistor including:
forming a gate electrode on a substrate;
forming a gate insulating layer, a semiconductor layer and source and drain electrodes using a photolithography process including:
forming a gate insulating layer, a semiconductor layer, and a metal layer;
forming a photoresist on the metal layer;
positioning a photo mask above the substrate;
light exposing and developing the photoresist to produce a photoresist pattern, wherein the photoresist pattern includes a central portion having a first thickness and a side portion having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the photoresist pattern;
removing the central portion of the photoresist pattern having a first thickness;
selectively removing the semiconductor layer;
selectively removing the metal layer corresponding to the central portion of the photoresist pattern; and
selectively removing the semiconductor layer corresponding to the central portion of the photoresist pattern.
32. The method of claim 31, further comprising forming a passivation film having a contact hole over the source and drain electrodes, wherein the pixel electrode is formed on the passivation layer and contacting the drain electrode through the contact hole.
33. The method of claim 31, wherein the pixel electrode directly contacts the drain electrode.
34. The method of claim 31, wherein the pixel electrode includes indium tin oxide.
35. A method of manufacturing a liquid crystal display device, comprising:
forming a thin film transistor and a pixel electrode coupled to the thin film transistor;
forming the thin film transistor including:
forming a gate electrode on a substrate;
forming a gate insulating layer, a first semiconductor layer, a second semiconductor layer and a metal layer;
forming a photoresist on the metal layer;
positioning a photo mask above the substrate;
light exposing and developing the photoresist to produce a photoresist pattern, wherein the photoresist pattern includes a central portion having a first thickness and a side portion having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the photoresist pattern;
selectively removing the first and second semiconductor layers;
selectively removing the metal layer beneath the central portion of the photoresist pattern having the first thickness to separate the metal layer into a first part spaced from a second part, the first part corresponding to the source electrode and the second part corresponding to the drain electrode; and
selectively removing the first semiconductor layer corresponding to the space between the first and second parts of the metal layer.
36. The method of claim 35, wherein the central portion of the photoresist is removed prior to selectively removing the first and second semiconductor layers.
37. A method of manufacturing a liquid crystal display device, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer, a semiconductor layer and source and drain electrodes using a photolithography process including:
forming a gate insulating layer, a semiconductor layer, and a metal layer;
forming a photoresist on the metal layer;
positioning a photo mask above the substrate;
light exposing and developing the photoresist to produce a photoresist pattern, wherein the photoresist pattern includes a central portion having a first thickness and adjacent side portions having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the photoresist pattern;
removing the central portion of the photoresist pattern having the first thickness to expose the metal layer;
selectively removing the semiconductor layer;
selectively removing the metal layer corresponding to the central portion of the photoresist pattern;
selectively removing the semiconductor layer corresponding to the central portion of the photoresist pattern;
forming a passivation film having a contact hole over the source and drain electrodes; and
forming a pixel electrode contacting the drain electrode through the contact hole.
38. A method of manufacturing a thin film transistor of a liquid crystal display device, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer, a semiconductor layer, and a metal layer over the gate electrode;
forming a photoresist over the metal layer, the photoresist including a central portion having a first thickness and a side portion having a second thickness, the first thickness being smaller than the second thickness; and
selectively removing the metal layer and the semiconductor layer including portions of the metal layer below the central portion of the photoresist to form source and drain electrodes and a channel.
39. The method of claim 38, wherein the semiconductor layer includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.
40. The method of claim 39, further comprising selectively removing the second semiconductor layer corresponding to the central portion of the photoresist.
41. The method of claim 39, wherein the first semiconductor layer includes amorphous silicon and the second semiconductor layer includes doped amorphous silicon.
42. The method of claim 38, wherein the metal layer is selectively removed using a dry etch technique.
43. The method of claim 42, wherein the dry etch technique uses a gas including Cl2 /O 2 gas.
44. The method of claim 38, wherein the semiconductor layer is selectively removed using a dry etch technique.
45. The method of claim 44, wherein the dry etch technique uses a gas including fluorine and chlorine.
46. The method of claim 45, wherein the gas includes SF6 /HCl.
47. The method of claim 45, wherein the gas includes SF6 /H 2 /Cl 2.
48. The method of claim 38, wherein the source and drain electrodes are made of a metal selected from the group consisting of Cr, Mo, Al, and Al alloy.
49. A method of manufacturing a thin film transistor of a liquid crystal display device, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer, a first semiconductor layer, a second semiconductor layer and source and drain electrodes using a photolithography process including:
sequentially forming the gate insulating layer, the first semiconductor layer, the second semiconductor layer and the metal layer;
forming a photoresist on the metal layer;
positioning a photo mask above the substrate;
light exposing and developing the photoresist to produce a photoresist pattern, wherein the photoresist pattern includes a central portion having a first thickness and adjacent side portions having a second thickness, the first thickness being smaller than the second thickness;
selectively removing the metal layer using the photoresist pattern;
selectively removing the first and second semiconductor layers;
selectively removing a portion of the metal layer beneath the central portion of the photoresist pattern to separate the metal layer into a first part spaced from a second part, the first part corresponding to the source electrode and the second part corresponding to the drain electrode; and
selectively removing the first semiconductor layer corresponding to the space between the first and second parts of the metal layer.
50. The method of claim 49, wherein the central portion of the photoresist is removed prior to selectively removing the first and second semiconductor layers.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283769A1 (en) * 1998-11-26 2009-11-19 Woon-Yong Park Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100740927B1 (en) * 1999-12-07 2007-07-19 삼성전자주식회사 Thin film transistor panels for liquid crystal display and methods for manufacturing the same
JP2001324725A (en) * 2000-05-12 2001-11-22 Hitachi Ltd Liquid crystal display device and method of manufacture
US6451705B1 (en) * 2000-08-31 2002-09-17 Micron Technology, Inc. Self-aligned PECVD etch mask
JP2002141512A (en) * 2000-11-06 2002-05-17 Advanced Display Inc Patterning method of thin film, tft array substrate using the patterning method, and manufacturing method of the tft array substrate
KR100755563B1 (en) * 2000-12-01 2007-09-06 비오이 하이디스 테크놀로지 주식회사 Method for manufacturing pixel electrode of fringe field switching lcd
JP4776813B2 (en) * 2001-06-12 2011-09-21 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6940142B2 (en) * 2001-07-02 2005-09-06 Xerox Corporation Low data line capacitance image sensor array using air-gap metal crossover
KR100480333B1 (en) * 2002-04-08 2005-04-06 엘지.필립스 엘시디 주식회사 Array substrate for a liquid crystal display device and Method for fabricating of the same
EP1361619A3 (en) * 2002-05-09 2007-08-15 Konica Corporation Organic thin-film transistor, organic thin-film transistor sheet and manufacturing method thereof
KR100493381B1 (en) * 2002-08-16 2005-06-07 엘지.필립스 엘시디 주식회사 Liquid crystal display panel
KR100915864B1 (en) * 2002-12-26 2009-09-07 엘지디스플레이 주식회사 Method for Fabricating of Array Panel used for a Liquid Crystal Display Device
CN1324359C (en) * 2003-05-28 2007-07-04 友达光电股份有限公司 Planar displaying device and producing method thereof
KR101006475B1 (en) * 2003-12-26 2011-01-06 엘지디스플레이 주식회사 array substrate for liquid crystal display device and manufacturing method of the same
WO2006015510A1 (en) * 2004-08-09 2006-02-16 Quanta Display Inc. Pixel structure of a liquid crystal display and the manufacturing method thereof
TWI290771B (en) * 2006-01-02 2007-12-01 Wintek Corp TFT substrate, liquid crystal display panel, transflective liquid crystal display device, and methods for the same
KR101056429B1 (en) * 2010-03-16 2011-08-11 삼성모바일디스플레이주식회사 Display device and method of manufacturing the same
KR20120044745A (en) * 2010-10-28 2012-05-08 삼성모바일디스플레이주식회사 Liquid crystal display device and manufacturing method thereof
KR101813719B1 (en) * 2011-07-19 2017-12-29 엘지디스플레이 주식회사 Manufacturing method of thin film transisotr array substrate
US8329518B1 (en) * 2011-08-11 2012-12-11 Shenzhen China Star Optoelectronics Technology Co., Ltd. Methods for manufacturing thin film transistor array substrate and display panel
CN102629576A (en) 2011-09-26 2012-08-08 京东方科技集团股份有限公司 Array substrate and method for manufacturing the same
TWI459477B (en) 2011-11-16 2014-11-01 Chunghwa Picture Tubes Ltd Pixel structure and method of fabricating the same
CN102629586B (en) * 2011-11-24 2013-12-25 北京京东方光电科技有限公司 Array substrate and manufacturing method thereof and display device
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US9786997B2 (en) 2013-08-01 2017-10-10 Centurylink Intellectual Property Llc Wireless access point in pedestal or hand hole
US9312276B2 (en) * 2014-03-28 2016-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd Method for manufacturing array substrate
CN103887245B (en) * 2014-03-28 2017-03-08 深圳市华星光电技术有限公司 A kind of manufacture method of array base palte
CN109859624B (en) * 2017-11-30 2021-04-20 昆山国显光电有限公司 Array substrate, preparation method thereof and display screen
CN109087953A (en) * 2018-08-16 2018-12-25 南京中电熊猫液晶显示科技有限公司 A kind of thin film transistor (TFT) and its manufacturing method
CN109786321B (en) * 2018-12-25 2022-07-22 惠科股份有限公司 Preparation method and device of array substrate and display panel

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
JPH0728074A (en) 1993-07-09 1995-01-31 Sharp Corp Display device and its production
US5427962A (en) * 1991-11-15 1995-06-27 Casio Computer Co., Ltd. Method of making a thin film transistor
KR970059801A (en) 1996-01-18 1997-08-12 구자홍 Structure and manufacturing method of TFT-LCD (LCD)
US5943559A (en) * 1997-06-23 1999-08-24 Nec Corporation Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process
US5985766A (en) 1997-02-27 1999-11-16 Micron Technology, Inc. Semiconductor processing methods of forming a contact opening
US5998229A (en) * 1998-01-30 1999-12-07 Samsung Electronics Co., Ltd. Methods of manufacturing thin film transistors and liquid crystal displays by plasma treatment of undoped amorphous silicon
US6043511A (en) * 1995-12-29 2000-03-28 Samsung Electronics Co., Ltd. Thin film transistor array panel used for a liquid crystal display having patterned data line components
US6255668B1 (en) * 1998-06-05 2001-07-03 Hyundai Electronics Industries Co., Ltd. Thin film transistor with inclined eletrode side surfaces
US6255130B1 (en) 1998-11-19 2001-07-03 Samsung Electronics Co., Ltd. Thin film transistor array panel and a method for manufacturing the same
US6287899B1 (en) 1998-12-31 2001-09-11 Samsung Electronics Co., Ltd. Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
US6335276B1 (en) 1998-11-26 2002-01-01 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US6410211B1 (en) 1997-11-27 2002-06-25 Lg Electronics, Inc. Method for manufacturing a liquid crystal display device
US6441399B1 (en) * 1994-04-22 2002-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated system
US6774969B2 (en) * 2001-10-22 2004-08-10 Samsung Electronics Co. Ltd. Liquid crystal display device and method for manufacturing the same
KR100978662B1 (en) 2008-09-02 2010-08-30 삼성전기주식회사 Key scanning circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2771820B2 (en) * 1988-07-08 1998-07-02 株式会社日立製作所 Active matrix panel and manufacturing method thereof
KR100360873B1 (en) * 1995-07-07 2003-03-03 엘지전자 주식회사 Method for manufacturing thin film transistor
KR100750922B1 (en) * 2001-04-13 2007-08-22 삼성전자주식회사 A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same
KR20090080786A (en) * 2008-01-22 2009-07-27 삼성전자주식회사 Method of manufacturing array substrate and array substrate

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
US5427962A (en) * 1991-11-15 1995-06-27 Casio Computer Co., Ltd. Method of making a thin film transistor
JPH0728074A (en) 1993-07-09 1995-01-31 Sharp Corp Display device and its production
US6441399B1 (en) * 1994-04-22 2002-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated system
US6043511A (en) * 1995-12-29 2000-03-28 Samsung Electronics Co., Ltd. Thin film transistor array panel used for a liquid crystal display having patterned data line components
KR970059801A (en) 1996-01-18 1997-08-12 구자홍 Structure and manufacturing method of TFT-LCD (LCD)
US5985766A (en) 1997-02-27 1999-11-16 Micron Technology, Inc. Semiconductor processing methods of forming a contact opening
US5943559A (en) * 1997-06-23 1999-08-24 Nec Corporation Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process
US6410211B1 (en) 1997-11-27 2002-06-25 Lg Electronics, Inc. Method for manufacturing a liquid crystal display device
US5998229A (en) * 1998-01-30 1999-12-07 Samsung Electronics Co., Ltd. Methods of manufacturing thin film transistors and liquid crystal displays by plasma treatment of undoped amorphous silicon
US6255668B1 (en) * 1998-06-05 2001-07-03 Hyundai Electronics Industries Co., Ltd. Thin film transistor with inclined eletrode side surfaces
US6255130B1 (en) 1998-11-19 2001-07-03 Samsung Electronics Co., Ltd. Thin film transistor array panel and a method for manufacturing the same
US6335276B1 (en) 1998-11-26 2002-01-01 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US6287899B1 (en) 1998-12-31 2001-09-11 Samsung Electronics Co., Ltd. Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
US6774969B2 (en) * 2001-10-22 2004-08-10 Samsung Electronics Co. Ltd. Liquid crystal display device and method for manufacturing the same
KR100978662B1 (en) 2008-09-02 2010-08-30 삼성전기주식회사 Key scanning circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
C.W. Kim et al., "A Novel Four-Mask-Count Process Architecture for TFT-LCDs," Society for Information Display International Symposium Digest of Technical Papers, vol. XXXI, Long Beach Convention Center, Long Beach, California, May 16-18, 2000, pp. 1006-1009.
Chang Wook Han et al., "A TFT Manufactured by 4 Masks Process with New Photolithography," SID KPS, Proceedings of the 18<SUP>th </SUP>International Display Research Conference, Asia Display '98, Sep. 28-Oct. 1, 1998, Seoul, Korea.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283769A1 (en) * 1998-11-26 2009-11-19 Woon-Yong Park Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US7888677B2 (en) * 1998-11-26 2011-02-15 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films

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