CN102629586B - Array substrate and manufacturing method thereof and display device - Google Patents

Array substrate and manufacturing method thereof and display device Download PDF

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Publication number
CN102629586B
CN102629586B CN 201110378273 CN201110378273A CN102629586B CN 102629586 B CN102629586 B CN 102629586B CN 201110378273 CN201110378273 CN 201110378273 CN 201110378273 A CN201110378273 A CN 201110378273A CN 102629586 B CN102629586 B CN 102629586B
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Prior art keywords
photoresist
drain electrode
source
zone
etch
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CN102629586A (en
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史大为
郭建
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BOE Technology Group Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention relates to the liquid crystal display technology field, especially to an array substrate and a manufacturing method thereof and a display device. The manufacturing method comprises the following steps: forming a graph containing a gate electrode on a substrate; forming a gate insulator layer, an active layer, an ohmic contact layer, and a source/drain electrode layer, coating a photoresist, forming a graph containing a source/drain electrode etching region, a channel etching region and a via hole etching region on the photoresist by utilizing a composition process, and forming a graph containing a source electrode, a drain electrode and a channel by utilizing an etching process; carrying out photoresist ashing to remove the photoresist outside the via hole etching region; forming an organic resin layer and carrying out photoresist strippling to form a graph containing a via hole; and forming a graph containing a pixel electrode. The array substrate is manufactured by employing the above-mentioned method; and the display device uses the array substrate. According to the method and the display device provided by the embodiments of the invention, the photoetching number is reduced, manufacturing time is shortened and manufacturing cost is saved.

Description

A kind of array base palte and preparation method thereof and display unit
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to a kind of array base palte and preparation method thereof and display unit.
Background technology
LCD (Liquid Crystal Display, liquid crystal display) be current flat-panel monitor commonly used, its technology had development by leaps and bounds in nearly ten years, from screen size, to the display frame quality, had all obtained very much progress, and the competition between each production firm also is growing more intense.Particularly along with LCD, the impact in life is increasing, and market demand share is increased sharply, and each producer also is being the supply of guarantee client product, improve the coefficient of safety of process of producing product, reduce production costs and effort, thereby improve occupation rate of market, Win Clients satisfaction.
As shown in Figure 1, for TFT (Thin Film Transistor, Thin Film Transistor (TFT)) structural representation, prior art is when making this TFT substrate, usually adopt 4 photoetching processes, comprise the grid photoetching process, source-drain electrode and raceway groove photoetching process, via hole photoetching process, and pixel electrode photoetching process.In order to enhance productivity, save production cost, prior art also requires further improvement.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof and display unit, can shorten the fabrication processing of array base palte, improves make efficiency, saves cost of manufacture.
The embodiment of the present invention provides a kind of manufacture method of array base palte, comprising:
Form the figure that comprises grid on substrate;
Form gate insulator, active layer, ohmic contact layer and source-drain electrode layer, the coating photoresist, form the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone by composition technique on photoresist, form the figure that comprises source electrode, drain electrode and raceway groove by etching technics;
Carry out photoresist ashing, remove described via etch zone photoresist in addition;
Form organic resin layer, form the figure that comprises via hole by photoresist lift off;
Formation comprises the figure of pixel electrode.
Preferably, the described figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone that forms on photoresist by composition technique comprises:
Described preset mask plate is placed on to the substrate top of coating photoresist, after being exposed, developing, forms the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone on described photoresist.
Preferably, the photoresist thickness of described via area is greater than described source-drain electrode zone photoresist thickness; Described source-drain electrode zone photoresist thickness is greater than the photoresist thickness of described channel region.
Preferably, described preset mask plate is gray mask plate or half-tone mask plate.
Preferably, the thickness of described photoresist is greater than 2.1 microns.
Preferably, the described figure that comprises source electrode, drain electrode and raceway groove that forms by etching technics comprises:
Adopt the wet etching mode, etch away the source-drain electrode layer of described photoresist with exterior domain, form the source-drain electrode layer that meets predetermined pattern;
Adopt and do the mode at quarter, etch away active layer and the ohmic contact layer of described photoresist with exterior domain;
Carry out ashing for the first time, remove and be positioned at the photoresist on described channel etching zone;
Carry out etching in described channel etching zone, form the raceway groove of desired depth.
Preferably, described formation organic resin layer, form the figure that comprises via hole by photoresist lift off, comprising:
Apply organic resin layer on substrate, the photoresist in the via etch zone that retains after ashing is carried out to liftoff peeling off, form the figure that comprises via hole.
Accordingly, the embodiment of the present invention also provides a kind of array base palte, adopts said method to make.
Accordingly, the embodiment of the present invention also provides a kind of display unit, comprises the array base palte that said method is made.
The embodiment of the present invention provides a kind of array base palte and preparation method thereof and display unit.This manufacture method comprises: form the figure that comprises grid on substrate; Form gate insulator, active layer, ohmic contact layer and source-drain electrode layer, the coating photoresist, form the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone by composition technique on photoresist, form the figure that comprises source electrode, drain electrode and raceway groove by etching technics; Carry out photoresist ashing, remove described via etch zone photoresist in addition; Form organic resin layer, form the figure that comprises via hole by photoresist lift off; Formation comprises the figure of pixel electrode.Array base palte that uses the embodiment of the present invention to provide and preparation method thereof and display unit, by form source-drain electrode layer etch areas, channel etching zone and via etch zone simultaneously, reduced the photoetching number of times, shortened Production Time, saved cost of manufacture.Simultaneously, determine the position of via hole by the method, avoided in the prior art making the registration problems in the via hole process, improved the precision of making via hole.
The accompanying drawing explanation
The structural representation that Fig. 1 is the TFT substrate;
The manufacture method schematic flow sheet that Fig. 2 is array base palte in the embodiment of the present invention;
The structural representation that Fig. 3 is preset mask plate in the embodiment of the present invention;
Fig. 4 is the structural representation that uses photoresist after preset mask plate exposure imaging in the embodiment of the present invention;
The manufacture method schematic flow sheet that Fig. 5 is array base palte in another embodiment of the present invention;
Fig. 6 a-Fig. 6 m makes the process schematic diagram of array base palte in another embodiment of the present invention.
Embodiment
Embodiment of the present invention technical scheme main realized to principle, embodiment and the beneficial effect that should be able to reach is at length set forth below in conjunction with each accompanying drawing.
The problem existed in order to solve prior art, the embodiment of the present invention provides a kind of manufacture method of array base palte, as shown in Figure 2, comprises the following steps:
Step 201, form the figure comprise grid on substrate;
Step 202, formation gate insulator, active layer, ohmic contact layer and source-drain electrode layer, the coating photoresist, form the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone by composition technique on photoresist, form the figure that comprises source electrode, drain electrode and raceway groove by etching technics;
Step 203, carry out photoresist ashing, remove the photoresist beyond described via etch zone;
Step 204, formation organic resin layer, form the figure that comprises via hole by photoresist lift off;
Step 205, formation comprise the figure of pixel electrode.
Concrete, while making Thin Film Transistor (TFT), first on the ratio base material, cover one deck ITO (Indium Tin Oxide, tin indium oxide), form grid layer by photoetching for the first time, continue cover gate insulating barrier, active layer and ohmic contact layer, and then cover one deck ITO as the source-drain electrode layer.
Be coated with photoresist on the source-drain electrode layer, preset mask plate be placed on to the substrate top of coating photoresist, after being exposed, developing, form the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone on photoresist.This preset mask plate is gray mask plate or half-tone mask plate, as shown in Figure 3, above-mentioned preset mask plate can comprise: mask plate base material 31 and lay respectively at source-drain electrode shielding layer 32, raceway groove shielding layer 33 and the via hole shielding layer 34 on mask plate base material 31.The transmitance of source-drain electrode shielding layer 32 is less than the transmitance of raceway groove shielding layer 33; The transmitance of via hole shielding layer 34 is zero, covers fully.Regional transmitance on this preset mask substrate 31 except source-drain electrode shielding layer 32, raceway groove shielding layer 33 and via hole shielding layer 34 is 100%, sees through fully.
While using above-mentioned preset mask plate to carry out photoetching for the second time, the photoresist of smearing on the source-drain electrode layer need to be thicker than conventional photoresist, and for example the thickness of above-mentioned photoresist is greater than 2.1 microns.
As shown in Figure 4, after using above-mentioned preset mask board to explosure, development, form source-drain electrode etch areas 41, channel etching zone 42 and via etch zone 43 on photoresist.Wherein, the photoresist thickness in this via etch zone 43 is greater than the regional photoresist thickness of source-drain electrode etching 41; Source-drain electrode etch areas 41 photoresist thickness are greater than the photoresist thickness in channel etching zone 42.
Then, adopt the wet etching mode, etch away the source-drain electrode layer of photoresist with exterior domain, form the source-drain electrode layer that meets predetermined pattern; Adopt and do the mode at quarter, etch away active layer and the ohmic contact layer of photoresist with exterior domain; Then carry out ashing for the first time, remove and be positioned at the photoresist on the channel etching zone; Carry out etching in the channel etching zone, form the raceway groove of desired depth.The concrete depth value of this raceway groove can be set according to actual needs.
In podzolic process, whole removing gradually is except photoresist, due to the photoresist thickness in via etch zone, so, after the photoresist beyond the etch areas of hole removes fully, the via etch zone still has photoresist, can determine accurately like this position of via hole.
Apply organic resin layer on substrate, the photoresist in the via etch zone that retains after ashing is carried out to liftoff peeling off, form the figure that comprises via hole.Can also continue this via hole is carried out to etching, in order to reach, be scheduled to hole depth.Simultaneously, in the embodiment of the present invention, use organic resin to replace silicon nitride of the prior art, can produce the effect that reduces power consumption, improves aperture opening ratio.
Finally, cover pixel electrode layer, by photoetching for the third time, form the pixel electrode layer that meets the predetermined pattern requirement on organic resin layer and via hole.
By foregoing description, can find out the manufacture method of the array base palte that uses the embodiment of the present invention to provide, by form source-drain electrode layer etch areas, channel etching zone and via etch zone simultaneously, reduce the photoetching number of times, shortened Production Time, saved cost of manufacture.Simultaneously, determine the position of via hole by the method, avoided in the prior art making the registration problems in the via hole process, improved the precision of making via hole.
The manufacture method of the Thin Film Transistor (TFT) below embodiment of the present invention provided is described in detail, and as shown in Figure 5, comprises the following steps:
Step 501, cover ITO on transparency carrier, by photoetching for the first time, form grid layer; As shown in Figure 6 a, on transparency carrier 1, cover ITO, adopt the mask plate of design in advance, by photoetching for the first time, form grid layer 2;
Step 502, cover gate insulating barrier, active layer and ohmic contact layer; As shown in Figure 6 b, cover one deck gate insulator 3 on transparency carrier 1 and grid layer 2, cover again active layer 4 and ohmic contact layer 5 on gate insulator 3;
Step 503, covering ITO are as the source-drain electrode layer; As shown in Fig. 6 c, cover again one deck ITO as source-drain electrode layer 6 on ohmic contact layer 5;
Step 504, on the source-drain electrode layer, smear photoresist, preset mask plate is placed on to source-drain electrode layer top and carries out exposure imaging; As shown in Fig. 6 d, smear one deck photoresist 7 on source-drain electrode layer 6, then preset mask plate 8 is placed on to source-drain electrode layer 6 top and carries out exposure imaging.This preset mask plate 8 comprises: mask plate base material 81 and lay respectively at source-drain electrode shielding layer 82, raceway groove shielding layer 83 and the via hole shielding layer 84 on mask plate base material 81.The transmitance of source-drain electrode shielding layer 82 is less than the transmitance of raceway groove shielding layer 83; The transmitance of via hole shielding layer 84 is zero, covers fully.Regional transmitance on this preset mask substrate 81 except source-drain electrode shielding layer 82, raceway groove shielding layer 83 and via hole shielding layer 84 is 100%, sees through fully.In addition, the one-tenth-value thickness 1/10 of above-mentioned photoresist is larger, generally should be greater than 2.1 microns.
Step 505, by the exposure imaging process, form source-drain electrode etch areas, channel etching zone and via etch zone on photoresist; Concrete, as shown in Fig. 6 e, by the exposure imaging process, transmitance difference according to diverse location on preset mask plate, make and form the different a plurality of zones of photoresist residual thickness on photoresist, wherein, source-drain electrode shielding layer corresponding zone on photoresist forms source-drain electrode etch areas 9; Raceway groove shielding layer corresponding zone on photoresist forms channel etching zone 10; Via hole shielding layer corresponding zone on photoresist forms via etch zone 11.
Step 506, employing wet etching mode, etch away the source-drain electrode layer of photoresist with exterior domain, forms the source-drain electrode layer that meets predetermined pattern; As shown in Figure 6 f, because source-drain electrode etch areas 9, channel etching zone 10 and via etch zone 11 all have photoresist, so the source-drain electrode layer of the below in these zones is not etched, all the other source-drain electrode layers that do not have the zone of photoresist all are etched away.
Step 507, employing mode at dry quarter, etch away active layer and the ohmic contact layer of photoresist with exterior domain; As shown in Fig. 6 g, continue to etch away active layer 4 and the ohmic contact layer 5 of photoresist with exterior domain, manifest gate insulator 3.
Step 508, carry out ashing for the first time, remove and be positioned at the photoresist on the channel etching zone; As shown in Fig. 6 h, photoresist is carried out to ashing for the first time, owing in podzolic process, can removing gradually photoresist, cut down the thickness of photoresist, and the photoresist on channel etching zone 10 is thinner, so, when the photoresist on can channel etching zone 10 is removed, all the other places still have photoresist, as on source-drain electrode etch areas 9 and via etch zone 11, still had photoresist, just its photoresist one-tenth-value thickness 1/10 had diminishes.
Step 509, in the channel etching zone, carry out etching, form the raceway groove of desired depth; As shown in Fig. 6 i, on the basis of Fig. 6 h, by etching technics, form the raceway groove 12 of desired depth in the channel etching zone;
Step 510, carry out ashing for the second time, remove the photoresist beyond the via etch zone; As shown in Fig. 6 j, because the photoresist one-tenth-value thickness 1/10 in via etch zone 11 is larger, therefore, after carrying out ashing for the second time, the photoresist of source-drain electrode etch areas 9 is melted by complete ash, via etch zone 11 still has photoresist, can determine accurately like this position of via hole, and while having avoided making via hole in the prior art, development and etching alignment precision deficiency caused the problem of hole site skew.
Step 511, covering organic resin layer; As shown in Fig. 6 k, cover one deck organic resin layer 13 on the basis of Fig. 6 j, cover silicon nitride in traditional handicraft herein, the embodiment of the present invention is used organic resin to replace silicon nitride, can effectively reduce power consumption and improve aperture opening ratio.
Step 512, carry out photoresist lift off and form via hole; As shown in Fig. 6 l, stripping photoresist makes the via etch zone form via hole 14, and wherein, this process of peeling off can directly be removed whole photoresists.
Step 513, covering pixel electrode layer by photoetching for the third time, form the pixel electrode layer that meets the predetermined pattern requirement on organic resin layer and via hole.As shown in Fig. 6 m, on the basis of Fig. 6 l, after covering layer of transparent conducting film (such as ITO), by photoetching for the third time, form the pixel electrode layer 15 that meets the predetermined pattern requirement.
By foregoing description, can find out the manufacture method of the array base palte that uses the embodiment of the present invention to provide, by form source-drain electrode layer etch areas, channel etching zone and via etch zone simultaneously, reduce the photoetching number of times, shortened Production Time, saved cost of manufacture.Simultaneously, determine the position of via hole by the method, avoided in the prior art making the registration problems in the via hole process, improved the precision of making via hole.
Accordingly, the embodiment of the present invention also provides a kind of array base palte, adopts said method to make.
Accordingly, the embodiment of the present invention also provides a kind of display unit, comprises the array base palte that said method is made.This display unit can be liquid crystal panel, OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) panel, electronic paper panel, mobile phone, TV, notebook, panel computer etc.
Pass through foregoing description, can find out, array base palte that uses the embodiment of the present invention to provide and preparation method thereof and display unit, by form source-drain electrode layer etch areas, channel etching zone and via etch zone simultaneously, reduced the photoetching number of times, shorten Production Time, saved cost of manufacture.Simultaneously, determine the position of via hole by the method, avoided in the prior art making the registration problems in the via hole process, improved the precision of making via hole.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.

Claims (9)

1. the manufacture method of an array base palte, is characterized in that, comprising:
Form the figure that comprises grid on substrate;
Form gate insulator, active layer, ohmic contact layer and source-drain electrode layer, the coating photoresist, form the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone by composition technique on photoresist, form the figure that comprises source electrode, drain electrode and raceway groove by etching technics;
Carry out photoresist ashing, remove described via etch zone photoresist in addition;
Form organic resin layer, form the figure that comprises via hole by photoresist lift off;
Formation comprises the figure of pixel electrode.
2. manufacture method as claimed in claim 1, is characterized in that, the described figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone that forms on photoresist by composition technique comprises:
Preset mask plate is placed on to the substrate top of coating photoresist, after being exposed, developing, forms the figure that comprises source-drain electrode etch areas, channel etching zone and via etch zone on described photoresist.
3. manufacture method as claimed in claim 2, is characterized in that, the photoresist thickness in described via etch zone is greater than described source-drain electrode etch areas photoresist thickness; Described source-drain electrode etch areas photoresist thickness is greater than the photoresist thickness in described channel etching zone.
4. manufacture method as claimed in claim 2 or claim 3, is characterized in that, described preset mask plate is gray mask plate or half-tone mask plate.
5. manufacture method as claimed in claim 2, is characterized in that, the thickness of described photoresist is greater than 2.1 microns.
6. manufacture method as claimed in claim 1, is characterized in that, the described figure that comprises source electrode, drain electrode and raceway groove that forms by etching technics comprises:
Adopt the wet etching mode, etch away the source-drain electrode layer of described photoresist with exterior domain, form the source-drain electrode layer that meets predetermined pattern;
Adopt and do the mode at quarter, etch away active layer and the ohmic contact layer of described photoresist with exterior domain;
Carry out ashing for the first time, remove and be positioned at the photoresist on described channel etching zone;
Carry out etching in described channel etching zone, form the raceway groove of desired depth.
7. manufacture method as claimed in claim 1, is characterized in that, described formation organic resin layer forms the figure that comprises via hole by photoresist lift off, comprising:
Apply organic resin layer on substrate, the photoresist in the via etch zone that retains after ashing is carried out to liftoff peeling off, form the figure that comprises via hole.
8. an array base palte, is characterized in that, adopts as arbitrary described manufacture method making in claim 1-7.
9. a display unit, is characterized in that, comprises array base palte as claimed in claim 8.
CN 201110378273 2011-11-24 2011-11-24 Array substrate and manufacturing method thereof and display device Expired - Fee Related CN102629586B (en)

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Publication number Priority date Publication date Assignee Title
CN103560088B (en) * 2013-11-05 2016-01-06 京东方科技集团股份有限公司 The manufacture method of array base palte
CN109037151B (en) * 2018-07-25 2020-02-07 深圳市华星光电半导体显示技术有限公司 Preparation method of array substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337284B1 (en) * 1999-05-27 2002-01-08 Lg. Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing the same
CN1591144A (en) * 2003-08-28 2005-03-09 三星电子株式会社 Film transistor array panel and its mfg method
CN101752361A (en) * 2008-12-18 2010-06-23 乐金显示有限公司 Array substrate for display device and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337284B1 (en) * 1999-05-27 2002-01-08 Lg. Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing the same
CN1591144A (en) * 2003-08-28 2005-03-09 三星电子株式会社 Film transistor array panel and its mfg method
CN101752361A (en) * 2008-12-18 2010-06-23 乐金显示有限公司 Array substrate for display device and method for fabricating the same

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